A transistor and semiconductor device

Abstract

The application discloses a transistor and a semiconductor device, relates to the technical field of semiconductors, and aims to solve the problem of poor compatibility between a ring-gate transistor and another transistor with a relatively thick gate dielectric layer and / or gate in a semiconductor device and to reduce the integration difficulty of the two transistors. The transistor comprises an active structure, an isolation layer and a gate stack structure. The active structure comprises a source region, a drain region and at least two channel layers between the source region and the drain region. The at least two channel layers are in contact with the source region and the drain region respectively. The first gap is between the adjacent two channel layers. The isolation layer comprises at least a first isolation layer. The first isolation layer at least fills the first gap. The at least two channel layers and the isolation layer form a first fin structure. The gate stack structure is across the first fin structure. The transistor is applied to the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a transistor and a semiconductor device. Background Technology

[0002] Gate-around transistors (GMT-A) have advantages over planar transistors and fin field-effect transistors, such as higher gate control capability. Therefore, when individual transistors in a semiconductor device are GMT-A, the operating performance of the semiconductor device can be improved.

[0003] However, existing semiconductor devices include gate-ring transistors with poor compatibility with other transistors having a thicker gate dielectric layer and / or gate, making it difficult to integrate the two types of transistors using existing manufacturing methods. Summary of the Invention

[0004] The purpose of this invention is to provide a transistor and semiconductor device that solves the problem of poor compatibility between a gate-around transistor and another transistor with a thicker gate dielectric layer and / or gate in a semiconductor device, thereby reducing the integration difficulty of the two types of transistors.

[0005] In a first aspect, the present invention provides a transistor comprising: an active structure, an isolation layer, and a gate stack structure. Wherein,

[0006] The aforementioned active structure includes a source region, a drain region, and at least two channel layers located between the source region and the drain region. The at least two channel layers are in contact with the source region and the drain region, respectively. A first gap exists between adjacent channel layers. An isolation layer includes at least a first isolation layer. The first isolation layer at least fills the first gap. The at least two channel layers and the isolation layer constitute a first fin structure. The aforementioned gate stack structure spans the first fin structure.

[0007] Compared with the prior art, the transistor provided by the present invention includes an active structure comprising at least two channel layers located between the source and drain regions. Furthermore, a first gap exists between adjacent channel layers. In this case, the arrangement of at least one of the aforementioned at least two channel layers between the source and drain regions is similar to the arrangement of nanowires or sheets included in the channel of a gate-around transistor between the source and drain regions. In addition, the transistor provided by the present invention also includes an isolation layer, and this isolation layer includes at least a first isolation layer. The first isolation layer can at least fill the aforementioned first gap. In this case, in practical applications, the transistor provided by the present invention can be manufactured using the manufacturing method of a gate-around transistor, and the space released by removing the sacrificial layer (this space includes the first gap) is filled by the aforementioned isolation layer, so that the gate stack structure included in the transistor provided by the present invention only spans across the first fin structure composed of at least two channel layers and an isolation layer; that is, the arrangement of the gate stack structure included in the transistor provided by the present invention is similar to the arrangement of the gate stack structure included in a fin field-effect transistor. In the above-described case, when the transistor provided by the present invention replaces the transistor in the semiconductor device that has a thicker gate dielectric layer and / or gate, the transistor provided by the present invention is compatible with the manufacturing process of conventional gate-around transistors, and the gate stack structure included in the transistor provided by the present invention does not need to be formed in the space freed up by removing the sacrificial layer. This solves the problem of poor compatibility between gate-around transistors and other transistors with different gate dielectric layers and / or gates in the prior art, and reduces the integration difficulty of gate-around transistors with other transistors with different absolute values ​​of threshold voltage.

[0008] In a second aspect, the present invention also provides a semiconductor device comprising the transistors provided in the first aspect and various implementations thereof.

[0009] The beneficial effects of the second aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0010] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0011] Figure 1 This is a schematic diagram of the structure of a first transistor and a second transistor integrated in the prior art, where the device structure is a ring-gate transistor and the gate dielectric layer and / or gate thickness are different.

[0012] Figure 2 Parts (1) and (2) are cross-sectional schematic diagrams of the two active structures along the length of the channel layer in the embodiments of the present invention;

[0013] Figure 3 A schematic cross-sectional view of the first transistor structure provided in an embodiment of the present invention along the length of the channel layer;

[0014] Figure 4 A schematic cross-sectional view of the first transistor structure provided in an embodiment of the present invention along the width direction of the channel layer;

[0015] Figure 5 A cross-sectional schematic diagram of the second transistor structure provided in an embodiment of the present invention along the length of the channel layer;

[0016] Figure 6 A cross-sectional schematic diagram of the second transistor structure provided in an embodiment of the present invention along the width direction of the channel layer;

[0017] Figure 7 A schematic cross-sectional view of the third transistor structure provided in an embodiment of the present invention along the width direction of the channel layer;

[0018] Figure 8 A cross-sectional schematic diagram along the length of the channel layer for a fourth transistor structure provided in an embodiment of the present invention;

[0019] Figure 9 This is a cross-sectional schematic diagram of the fourth transistor structure provided in an embodiment of the present invention, along the width direction of the channel layer and at the second isolation portion.

[0020] Figure 10 This is a cross-sectional schematic diagram of the fourth transistor structure provided in an embodiment of the present invention, along the width direction of the channel layer and at the first isolation portion.

[0021] Figure 11 A cross-sectional schematic diagram along the length of the channel layer for the fifth transistor structure provided in an embodiment of the present invention;

[0022] Figure 12 A cross-sectional schematic diagram along the width direction of the channel layer for the fifth transistor structure provided in an embodiment of the present invention;

[0023] Figure 13 This is a cross-sectional schematic diagram of the sixth transistor structure provided in an embodiment of the present invention, along the length of the channel layer and at the second isolation portion.

[0024] Figure 14 This is a cross-sectional schematic diagram of the sixth transistor structure provided in an embodiment of the present invention, along the length of the channel layer and at the first isolation portion.

[0025] Figure 15 A cross-sectional schematic diagram along the width direction of the channel layer for the sixth transistor structure provided in an embodiment of the present invention;

[0026] Figure 16 A cross-sectional schematic diagram along the width direction of the channel layer for the seventh transistor structure provided in an embodiment of the present invention;

[0027] Figure 17 A schematic cross-sectional view of the seventh transistor structure provided in an embodiment of the present invention along the length of the channel layer and at the second and third isolation portions;

[0028] Figure 18 A cross-sectional schematic diagram along the length of the channel layer for the eighth transistor structure provided in this embodiment of the invention;

[0029] Figure 19 A schematic cross-sectional view of the eighth transistor structure provided in this embodiment of the invention along the width direction of the channel layer;

[0030] Figure 20 A cross-sectional schematic diagram along the length of the channel layer for the ninth transistor structure provided in this embodiment of the invention;

[0031] Figure 21 A cross-sectional schematic diagram along the width direction of the channel layer for the ninth transistor structure provided in an embodiment of the present invention;

[0032] Figure 22 This is a cross-sectional schematic diagram of the tenth transistor structure provided in an embodiment of the present invention, along the length of the channel layer and at the second isolation portion.

[0033] Figure 23 This is a cross-sectional schematic diagram of the tenth transistor structure provided in an embodiment of the present invention, along the length of the channel layer and at the first isolation portion.

[0034] Figure 24 A cross-sectional schematic diagram along the width direction of the channel layer for the tenth transistor structure provided in an embodiment of the present invention;

[0035] Figure 25 This is a cross-sectional schematic diagram of the eleventh transistor structure provided in an embodiment of the present invention along the width direction of the channel layer.

[0036] Reference numerals: 1 is semiconductor substrate, 2 is active structure, 21 is source region, 22 is drain region, 23 is channel layer, 3 is first gap, 4 is isolation layer, 41 is first isolation layer, 411 is first isolation section, 412 is second isolation section, 413 is third isolation section, 42 is second isolation layer, 421 is fourth isolation section, 422 is fifth isolation section, 5 is gate stack structure, 51 is gate dielectric layer, 52 is gate, 6 is second gap, 7 is shallow trench isolation, 8 is sidewall, 9 is dielectric layer. Detailed Implementation

[0037] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0038] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0039] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0040] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0041] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0042] Gate-around transistors (GMT-A) offer advantages over planar transistors and fin field-effect transistors, such as higher gate control capability. Therefore, when individual transistors in a semiconductor device are GMT-A, the device's performance can be improved. Furthermore, in existing semiconductor devices, the absolute values ​​of the threshold voltages of two GMT-A transistors are often achieved by using gate dielectric layers and / or gates of different thicknesses (here, for ease of description, the GMT-A transistor with a thinner gate dielectric layer and / or gate is referred to as the first GMT-A transistor, and the GMT-A transistor with a thicker gate dielectric layer and / or gate is referred to as the second GMT-A transistor). However, in the above-described case, it is difficult to manufacture the first and second GMT-A transistors using existing manufacturing methods.

[0043] Specifically, in practical applications, to improve the manufacturing efficiency and reduce the manufacturing cost of semiconductor devices, manufacturing processes with the same structural type are typically used to fabricate different transistors within the semiconductor device on the same semiconductor substrate. Based on this, in the actual manufacturing process, such as... Figure 1 As shown, when fabricating the two gate ring transistors on the same semiconductor substrate, the distance between adjacent nanowires or sheets only meets the structural requirements of the first gate ring transistor with a thinner gate dielectric layer 51 and / or gate 52. Therefore, the thicker gate dielectric layer 51 and / or gate 52 of the second gate ring transistor cannot be filled between adjacent nanowires or sheets with a small spacing. This makes it difficult for the threshold voltage of the second gate ring transistor to meet the requirements of the preset scheme, reducing the yield and performance of the semiconductor device.

[0044] To address the aforementioned technical problems, embodiments of the present invention provide a transistor and a semiconductor device. The transistor provided by these embodiments is compatible with the manufacturing process of conventional gate-around transistors, and the gate stack structure included in the transistor does not need to be formed within the space freed up by removing the sacrificial layer. Therefore, when the transistor provided by these embodiments replaces a transistor in a semiconductor device with a thicker gate dielectric layer and / or gate, the integration difficulty of the gate-around transistor with another transistor having a different absolute value of the threshold voltage can be reduced.

[0045] like Figure 5 and Figure 6As shown, an embodiment of the present invention provides a transistor. The transistor includes an active structure 2, an isolation layer, and a gate stack structure 5. The active structure 2 includes a source region 21, a drain region 22, and at least two channel layers 23 located between the source region 21 and the drain region 22. The at least two channel layers 23 are in contact with the source region 21 and the drain region 22, respectively. A first gap exists between adjacent channel layers 23. The isolation layer 4 includes at least a first isolation layer 41. The first isolation layer 41 at least fills the first gap. The at least two channel layers 23 and the isolation layer 4 constitute a first fin structure. The gate stack structure 5 spans the first fin structure.

[0046] In practical applications, the transistor provided in this embodiment of the invention may include a semiconductor substrate to facilitate the fabrication of the active structure, isolation layer, and gate stack structure included in the transistor on the semiconductor substrate. The specific structure of the semiconductor substrate can be set according to the actual application scenario. For example, the semiconductor substrate may be a silicon substrate, a germanium-silicon substrate, a germanium substrate, a silicon-on-insulator substrate, or other semiconductor substrates on which no other structures are formed. As another example, if the transistor provided in this embodiment of the invention is applied to a second or higher layer transistor in a semiconductor device, the semiconductor substrate may include a semiconductor substrate, a first layer device structure formed on the semiconductor substrate, and a dielectric layer covering the first layer device structure. In this case, the materials of each part of the semiconductor substrate can be set according to actual needs, as long as they can be applied to the transistor provided in this embodiment of the invention.

[0047] For the aforementioned active structure, the source region, drain region, and at least two channel layers can be made of semiconductor materials such as silicon, germanium-silicon, germanium, or group III-V compound semiconductors. Specifically, the source and drain regions can be made of the same or different materials. When the source and drain regions are made of the same material, they can be formed simultaneously in a unified operation, simplifying the transistor manufacturing process. Furthermore, the material of the at least two channel layers can be at least the same as or different from the material of one of the source and drain regions. For example, the source and drain regions can be made of germanium-silicon, and the at least two channel layers can be made of germanium-silicon or silicon. Moreover, the materials of channel layers located in different layers can be the same or different. When the materials of channel layers located in different layers are the same, the difficulty of selectively etching the sacrificial layer can be reduced, which is beneficial to improving the compatibility between the transistor provided in this embodiment and the manufacturing process of conventional gate-around transistors.

[0048] The number of channel layers included in the active structure can be set according to the actual application scenario, and no specific limit is made here. Additionally, as... Figure 2 Part (1), and Figure 3 and Figure 4As shown, in the active structure 2, the bottom channel layer 23 of all channel layers 23 can have a second gap 6 between itself and the semiconductor substrate 1, and the first isolation layer 41 further fills the second gap 6. In this case, when manufacturing the transistor provided in this embodiment of the invention using a conventional gate-around transistor manufacturing process, this can be achieved by depositing a corresponding sacrificial layer before forming each semiconductor material layer used to manufacture the corresponding channel layer 23. Alternatively, as... Figure 2 Part (2) and Figure 5 and Figure 6 As shown, the bottom channel layer 23 of all the channel layers 23 included in the active structure 2 can be in contact with the semiconductor substrate 1. At this time, in the process of manufacturing the transistor provided in this embodiment of the invention using the conventional gate-around transistor manufacturing process, this can be achieved by directly depositing a semiconductor material layer for manufacturing the bottom channel layer 23 on the semiconductor substrate 1.

[0049] Specifically, the heights of the first and second gaps can be set according to the actual application scenario, and are not specifically limited here. For example, the height of the first or second gap can be 4nm to 12nm. Furthermore, when the active structure includes at least three channel layers, the heights of the first gaps located on different layers can be equal or unequal. When the heights of the first gaps located on different layers are equal, during the manufacturing process of the transistor provided in this embodiment of the invention using conventional gate-around transistor manufacturing processes, the heights of the sacrificial layers located between adjacent channel layers are also equal. This prevents the time required for different sacrificial layers to be completely etched (or completely insulated) due to height differences between them. It ensures that the channel layers on both sides of the sacrificial layer requiring a shorter time to be completely etched (or completely insulated) are not over-processed, improving the yield of the transistor provided in this embodiment of the invention using conventional gate-around transistor manufacturing processes, and thus improving the electrical performance of the transistor provided in this embodiment of the invention.

[0050] The specifications of each channel layer in the active structure can be set according to the conductivity type of the transistor and the actual application scenario, and no specific limitations are made here.

[0051] For example: Figure 4 As shown, the aspect ratio A of each channel layer 23 ranges from 1:10 to 1:1. In this case, the height of each channel layer 23 is less than or equal to its width, making the structure of the channel layer 23 similar to the nanowire or sheet structure included in a gate-around-the-ring transistor. Based on this, since the crystal orientation of the channel including the nanosheet is usually

[100] , and the

[100] crystal orientation is favorable for electron transport but unfavorable for hole transport, when the transistor is an NMOS transistor, the carrier mobility of the NMOS transistor can be improved by appropriately reducing the aspect ratio of each channel layer 23.

[0052] For example: Figure 7 As shown, the aspect ratio A of each channel layer 23 ranges from 1:1 to 10:1. In this case, the height of each channel layer 23 is greater than its width, making the structure of the channel layer 23 similar to the fin-shaped channel structure of a fin field-effect transistor. Based on this, since the crystal orientation of the fin-shaped channel in a fin field-effect transistor is usually

[110] , and the

[110] crystal orientation is conducive to hole transport but not to electron transport, when the transistor is a PMOS transistor, the carrier mobility of the PMOS transistor can be improved by appropriately increasing the aspect ratio of each channel layer 23.

[0053] Furthermore, the height of trench layers located on different levels can be the same. Alternatively, at least one trench layer can have a different height from another trench layer. Specifically, the height of each trench layer can be set according to actual needs.

[0054] For the aforementioned isolation layer, the material of the isolation layer is a dielectric material. This dielectric material can be a low dielectric constant such as silicon dioxide or silicon nitride, or a high dielectric constant such as hafnium dioxide, zirconium dioxide, titanium dioxide, or aluminum oxide. Furthermore, the isolation layer can be formed from only one dielectric material, or it can be formed from at least two dielectric materials. For example, the material of the isolation layer can include one or more of silicon dioxide, silicon nitride, hafnium dioxide, zirconium dioxide, titanium dioxide, and aluminum oxide.

[0055] The specifications of the first isolation layer, which is included in the isolation layer, can be set according to actual needs. For example... Figure 3 and Figure 4 As shown, since the first isolation layer 41 at least fills the first gap, the height of the first isolation layer 41 located between adjacent channel layers 23 is equal to the height of the first gap in the corresponding layer. Furthermore, as... Figure 5 and Figure 6 As shown, when there is a second gap between the bottom channel layer 23 and the semiconductor substrate 1, the height of the bottom first isolation layer 41 is equal to the height of the second gap. For example, the height of each first isolation layer 41 can be from 4 nm to 12 nm. In this case, the thickness of each first isolation layer 41 is moderate, preventing waste of material in manufacturing the first isolation layer 41 due to its large thickness, thus reducing manufacturing costs. It can also prevent the gate 52 of the gate-ring transistor in the semiconductor device including the transistor provided in the embodiment of the present invention from not being completely filled due to the small thickness of the first isolation layer 41, thereby improving the yield of the semiconductor device.

[0056] Furthermore, when the isolation layer includes at least two first isolation layers, the heights of the first isolation layers located in different layers can be the same or different. The beneficial effects of having the same height for the first isolation layers in different layers can be found in the analysis of the beneficial effects of having equal heights for the first gaps in different layers described above, and will not be repeated here.

[0057] For gate stacking structures, such as Figures 3 to 6 As shown, the gate stack structure 5 may include a gate dielectric layer 51 and a gate 52 located on the gate dielectric layer 51. The gate dielectric layer 51 covers the top of the first fin structure and the sidewalls of the first fin structure along its width direction. Alternatively, the gate dielectric layer 51 may also be formed on the portion of the semiconductor substrate 1 exposed to the gate formation region. The gate formation region is the region corresponding to the gate stack structure 5. The gate dielectric layer 51 may be made of an insulating material with a low dielectric constant, such as silicon oxide or silicon nitride, or an insulating material with a high dielectric constant, such as HfO2, ZrO2, TiO2, or Al2O3. The gate 52 may be made of a conductive material such as polysilicon, TiN, TaN, or TiSiN.

[0058] In some cases, such as Figures 3 to 6 As shown, the transistor may further include at least one of a shallow trench isolation 7, a sidewall 8, and a dielectric layer 9. The shallow trench isolation 7 is formed on the semiconductor substrate 1 to isolate different active regions 21 of the semiconductor substrate 1, preventing leakage. The thickness of the shallow trench isolation 7 can be set according to actual conditions. The material of the shallow trench isolation 7 can be an insulating material such as SiN, Si3N4, SiO2, or SiCO. The sidewall 8 is formed at least on both sides of the gate stack structure 5 along its length direction (parallel to the length direction of the channel layer 23) to isolate the gate 52 included in the gate stack structure 5 from other subsequently formed conductive structures, improving the electrical stability of the transistor. The material of the sidewall 8 can be an insulating material such as silicon oxide or silicon nitride. The dielectric layer 9 covers the semiconductor substrate 1, and its top is flush with the top of the gate stack structure 5. In actual manufacturing, the presence of the dielectric layer 9 can protect the source region 21 and drain region 22 from the effects of subsequent operations such as manufacturing the isolation layer 4, improving the yield of the semiconductor device. The dielectric layer 9 can be made of insulating materials such as silicon oxide or silicon nitride.

[0059] As can be seen from the above, such as Figures 3 to 6As shown, in the transistor provided in this embodiment of the invention, the active structure 2 includes at least two channel layers 23 located between the source region 21 and the drain region 22. Furthermore, a first gap exists between adjacent channel layers 23. In this case, the arrangement of at least one of the at least two channel layers 23 between the source region 21 and the drain region 22 is similar to the arrangement of nanowires or sheets included in the channel of a gate-around transistor between the source region 21 and the drain region 22. In addition, the transistor provided in this embodiment of the invention also includes an isolation layer 4, and the isolation layer 4 includes at least a first isolation layer 41. The first isolation layer 41 can at least fill the first gap. In this case, in practical applications, the transistor provided in this embodiment of the invention can be manufactured using the manufacturing method of a gate-around transistor. The space released by removing the sacrificial layer (including the first gap 3) is filled by the aforementioned isolation layer 4, so that the gate stack structure 5 included in the transistor provided in this embodiment of the invention only spans across the first fin structure composed of at least two channel layers 23 and the isolation layer 4. That is, the configuration of the gate stack structure 5 included in the transistor provided in this embodiment of the invention is similar to the configuration of the gate stack structure 5 included in a fin field-effect transistor. In the above case, when the transistor provided in this embodiment of the invention replaces the transistor in the semiconductor device that has a thicker gate dielectric layer 51 and / or gate 52, since the transistor provided in this embodiment of the invention is compatible with the manufacturing process of conventional gate-around transistors, and the gate stack structure 5 included in the transistor provided in this embodiment of the invention does not need to be formed in the space released by removing the sacrificial layer, the problem of poor compatibility between the gate-around transistor and another transistor with a gate dielectric layer 51 and / or gate 52 of different thicknesses in the prior art can be solved, and the integration difficulty of the gate-around transistor and another transistor with a different absolute value of threshold voltage can be reduced.

[0060] In practical applications, the first isolation layer can be formed from only one material, or it can be formed from at least two materials. Specifically, when the first isolation layer is formed from at least two materials, its structure can be classified into at least the following three types based on the relative positional relationship between the isolation portions of different materials:

[0061] The first type: such as Figures 8 to 10 As shown, along the length direction parallel to the channel layer 23, the first isolation layer 41 includes a first isolation portion 411 and second isolation portions 412 located on both sides of the first isolation portion 411. The material of the first isolation portion 411 is different from that of the second isolation portion 412.

[0062] In this case, the transistor provided in the embodiment of the present invention will be described as an example manufactured using a conventional gate-around transistor manufacturing process. In the actual manufacturing process, a fin structure for manufacturing at least two channel layers needs to be formed on a semiconductor substrate. This fin structure includes alternately stacked sacrificial layers and channel material layers. The top layer of the fin structure is the channel material layer. The bottom layer can be either a channel material layer or a sacrificial layer. Furthermore, along the length of the fin structure, it includes a source formation region, a drain formation region, and a transition region between the source and drain formation regions. After forming the sacrificial gate and sidewalls across the transition region, the portions of the fin structure located in the source and drain formation regions need to be removed. At this time, along the length of the fin structure, the portion of the sacrificial layer located within the transition region is exposed. Then, an inner sidewall process is used to form a second isolation portion at least between adjacent channel layers. After forming the source and drain regions and removing the sacrificial gate, the remaining portion of the sacrificial layer is exposed. Finally, a first isolation portion is formed at the location of the remaining portion of the sacrificial layer through etching and deposition processes, or through insulating treatment processes such as oxidation. Since the second isolation portion and the first isolation portion are formed in different operations, their materials can be different.

[0063] Specifically, along the length direction parallel to the channel layer, the lengths of the first isolation portion and each of the second isolation portions can be set according to the actual application scenario, and are not specifically limited here. As can be seen from the formation process of the first and second isolation portions described above, the lengths of the first and second isolation portions are related to the length of the formed notch and the length of the transition region. With a fixed gate length for the transistor, the length of the transition region is also a fixed value. The length of the notch can be set according to requirements; therefore, the length of the first isolation portion can be greater than, less than, or equal to the length of each of the second isolation portions. The material of the first isolation portion can be set according to the actual application scenario. For example, when the first isolation portion is formed using etching and deposition processes, the material of the first isolation portion can be any dielectric material different from that of the second isolation portion. However, when the remaining portion of the sacrificial layer is directly insulated using an oxidation or other insulating process to form the first isolation portion, the material of the first isolation portion is related to the material of the sacrificial layer and the insulating process. For example, when the sacrificial layer is made of silicon and the first isolation portion is formed using an oxidation process, the material of the first isolation portion is silicon oxide.

[0064] The material of the second isolation part can be any dielectric material that is different from the material of the first isolation part.

[0065] The second type: such as Figure 11 and Figure 12As shown, along the height direction parallel to the channel layer 23, the first isolation layer 41 includes a first isolation portion 411 and a second isolation portion 412 located on both sides of the first isolation portion 411. The material of the first isolation portion 411 is different from that of the second isolation portion 412.

[0066] In the actual manufacturing process, the transistor provided in this embodiment of the invention will be described as an example manufactured using a conventional gate-around transistor manufacturing process. After removing the sacrificial gate, the sacrificial layer located in the gate formation region is exposed. Next, as... Figure 2 As shown in parts (1) and (2), the sacrificial layer located in the gate formation region can be removed using a dry or wet etching process to obtain at least the first gap 3. Then, a first isolation material layer surrounding the outer periphery of each channel layer can be formed using a process such as atomic layer deposition. A second isolation material layer of a different material is deposited around the outer periphery of the first isolation material layer. Finally, under the masking effect of the channel layer, the first and second isolation material layers are selectively etched, so that the remaining portion of the first isolation material layer forms the second isolation portion, and the remaining portion of the second isolation material layer forms the first isolation portion.

[0067] In the second scenario described above, as can be seen from the formation process of the first and second isolation portions, the material layers used to manufacture the first and second isolation portions are formed using a deposition process. Therefore, the materials of the first and second isolation portions can be any two different dielectric materials, and their materials are not directly related to the materials of the channel layer and the sacrificial layer. For example, the material of the first isolation portion could be silicon oxide, and the material of the second isolation portion could be titanium oxide. Furthermore, the heights of the first and second isolation portions can be set according to actual needs. Specifically, the height of the first isolation portion can be greater than, less than, or equal to the height of the second isolation portion.

[0068] The third type: such as Figures 13 to 15 As shown, along the width direction parallel to the channel layer 23, the first isolation layer 41 includes at least a first isolation portion 411 and a second isolation portion 412 located on both sides of the first isolation portion 411. The material of the first isolation portion 411 is different from that of the second isolation portion 412.

[0069] Specifically, in this third case, such as Figures 13 to 15 As shown, the height of the second isolation section 412 can be equal to the height of the first isolation section 411. Or, as... Figure 16 and Figure 17As shown, the height of the second isolation portion 412 can be less than the height of the first isolation portion 411. When the height of the second isolation portion 412 is less than the height of the first isolation portion 411, the first isolation layer 41 further includes a third isolation portion 413. Furthermore, along a height direction parallel to the channel layer 23, the third isolation portion 413 is located on both sides of the second isolation portion 412. The material of the third isolation portion 413 is different from the material of the second isolation portion 412.

[0070] In the actual manufacturing process, the formation process of the first isolation layer corresponding to the third case can be subdivided into the following three types:

[0071] 1. In the case of using a conventional gate-around transistor manufacturing process, and the height of the second isolation section is equal to the height of the first isolation section, such as Figure 2 As shown in sections (1) and (2), after obtaining at least the first gap 3, a first isolation material layer can be formed around the periphery of each channel layer using processes such as atomic layer deposition. The portion of this first isolation material layer located between adjacent channel layers fills the first gap. If there is a second gap between the bottom channel layer and the semiconductor substrate, the first isolation material layer also fills the second gap. Next, under the masking effect of the channel layer, the first isolation material layer is selectively etched so that the remaining portion of the first isolation material layer is located only in the first gap. Alternatively, if there is a second gap between the bottom channel layer and the semiconductor substrate, the remaining portion of the first isolation material layer also fills the second gap. Finally, along the width direction parallel to the channel layer, the remaining portion of the first isolation material layer is recessed inward relative to the sidewall of the channel layer to form a notch. A second isolation portion is formed within the notch. The portion of the first isolation material layer located between the two second isolation portions along the width direction parallel to the channel layer is the first isolation portion.

[0072] In this manufacturing process, the material of the first isolation portion is related to the material of the sacrificial layer and the insulation treatment process. For example, if the sacrificial layer is germanium-silicon and the first isolation portion is formed by oxidation, the material of the first isolation portion includes silicon oxide and germanium oxide. The material of the second isolation portion can be any dielectric material different from that of the first isolation portion.

[0073] 2. During the removal of the sacrificial layer in the gate formation region along the width direction parallel to the channel layer, a portion of the sacrificial layer is retained. Then, an insulating process, such as oxidation, is used to directly process the remaining portion of the sacrificial layer to form the first isolation portion. During the formation of the first isolation portion, the exposed portion of the channel layer may also be insulatingly treated, thereby forming an isolation material layer on the exposed portion of the channel layer. After forming this isolation material layer, if the first gap (or, in the case of a second gap, both the first and second gaps) is filled, the portion of the isolation material layer outside the first gap (or, in the case of a second gap, both the first and second gaps) needs to be removed. The portion of the isolation material layer remaining within the first gap constitutes the second isolation portion. Because the channel layer and the sacrificial layer are made of different materials, the first and second isolation portions obtained after the above insulating processes are made of different materials.

[0074] Third, after forming the isolation material layer using the second manufacturing method described above, if the first gap (in the case of a second gap, here it is the first gap and the second gap) is not completely filled, another isolation material layer can be deposited using processes such as atomic layer deposition to fill the first gap (in the case of a second gap, here it is the first gap and the second gap). Finally, the portions of these two isolation material layers outside the first gap (in the case of a second gap, here it is the first gap and the second gap) are removed. Wherein, if the two isolation material layers are made of the same material, the first isolation layer only includes the first isolation portion and the second isolation portion. If the two isolation material layers are made of different materials, the portion of the subsequently deposited isolation material layer located within the first gap (in the case of a second gap, here it is the first gap and the second gap) forms a third isolation portion.

[0075] In the second and third cases described above, the first and second isolation portions can be made of any two different dielectric materials. Furthermore, the third isolation portion can be made of any dielectric material different from the second isolation portion. The material of the third isolation portion can be the same as or different from the material of the first isolation portion.

[0076] As described above, the first isolation layer includes at least a first isolation portion and a second isolation portion made of different materials, and the first isolation portion and the second isolation portion have multiple possible relative positional relationships. Furthermore, the manufacturing processes of the first isolation portion and the second isolation portion corresponding to each positional relationship are not entirely the same. Based on this, a suitable structure and manufacturing process of the first isolation layer can be selected according to the needs of different application scenarios to improve the applicability of the transistor provided in the embodiments of the present invention in different application scenarios.

[0077] Furthermore, during the formation of the aforementioned first isolation layer, the portion of the corresponding dielectric material located outside the first gap (or, in the case of a second gap, both the first and second gaps) is removed to ensure that the transistor meets the threshold voltage requirement of a relatively small absolute value in practical applications. For example, this applies to core transistors in semiconductor devices with low operating voltages. Conversely, if a larger absolute threshold voltage is required in practical applications (e.g., to input / output transistors in semiconductor devices with higher operating voltages), the portion of the dielectric material located outside the first gap (or, in the case of a second gap, both the first and second gaps) can be retained. Based on this, as... Figure 18 and Figure 19 As shown, at least two channel layers 23 and a first isolation layer 41 constitute the second fin structure. The isolation layer also includes a second isolation layer 42 covering the outer periphery of the second fin structure. A gate stack structure 5 is formed on the second isolation layer 42.

[0078] The aforementioned second isolation layer is the portion of the dielectric material located outside the first gap (or, in the case of a second gap, both the first and second gaps). As described above regarding the various structures and manufacturing processes of the first and second isolation portions, the material of the second isolation layer 42 included in the isolation layer 4 can be formed from only one material. See [link to relevant documentation]. Figure 18 and Figure 19 Or, as Figures 20 to 25 As shown, the second isolation layer 42 can also be made of at least two materials.

[0079] Specifically, when the second isolation section is formed of at least two materials, such as Figures 20 to 25 As shown, the second isolation layer 42 includes a fourth isolation portion 421 and a fifth isolation portion 422. The materials of the fourth isolation portion 421 and the fifth isolation portion 422 are different. The fourth isolation portion 421 covers the outer periphery of the second fin structure, and the contact area between the fourth isolation portion 421 and the first isolation layer 41 has a hollow area. The fifth isolation layer is formed on the fourth isolation layer and fills the hollow area.

[0080] Specifically, the materials of the fourth and fifth isolation sections mentioned above can be referenced from the materials of the first and second isolation sections (or the third isolation section) mentioned earlier, and will not be repeated here.

[0081] This invention also provides a semiconductor device, which includes the transistor provided in the above embodiments.

[0082] Specifically, the semiconductor device can be any semiconductor device including transistors. The semiconductor device may include only one transistor or multiple transistors. Where the semiconductor device includes multiple transistors, the multiple transistors may have the same conductivity type, or at least one transistor may have a conductivity type opposite to the others. Furthermore, the absolute values ​​of the threshold voltages of the multiple transistors may be the same or different.

[0083] In one example, the semiconductor device described above may include a first transistor and a second transistor. One of the first transistor and the second transistor is the transistor provided in the above embodiments, and the other is a gate-around transistor.

[0084] Specifically, the number of first and second transistors in the semiconductor device can be set according to the actual application scenario. Furthermore, the absolute values ​​of the threshold voltages of the first and second transistors can be the same or different. When the absolute values ​​of the threshold voltages of the first and second transistors are different, the transistor with the larger absolute value of its threshold voltage has a thicker gate dielectric layer and / or gate. Based on this, when the transistor provided in this embodiment is applied to a transistor with a thicker gate dielectric layer and / or gate, because the transistor provided in this embodiment is compatible with the manufacturing process of conventional gate-around transistors, and the gate stack structure included in the transistor provided in this embodiment does not need to be formed in the space freed up by removing the sacrificial layer, the problem of poor compatibility between gate-around transistors and other transistors with different thicknesses of gate dielectric layers and / or gates in the prior art can be solved, reducing the integration difficulty of gate-around transistors with other transistors with different absolute values ​​of threshold voltages.

[0085] Furthermore, the first transistor and the second transistor can have the same or opposite conductivity types. The channel layers of the first transistor and the second transistor can be made of the same or different materials. In cases where the first transistor and the second transistor have opposite conductivity types and different channel layer materials, in practical applications, the channel materials used to manufacture the channel layer of the first transistor and the channel material used to manufacture the channel layer of the second transistor can serve as sacrificial layers for each other. Based on this, if the transistor provided in this embodiment is applied to either the first transistor or the second transistor, and the thickness of the channel layer in the transistor provided in this embodiment is determined by the dimensions of the gate stack structure of the other transistor, it can be ensured that both the gate stack structures of the first transistor and the second transistor meet the operational requirements, thereby improving the electrical performance of the semiconductor device.

[0086] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0087] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A transistor, characterized in that, include: Active structure, isolation layer and gate stack structure; among which, The active structure includes a source region, a drain region, and at least two channel layers located between the source region and the drain region; the at least two channel layers are in contact with the source region and the drain region respectively; a first gap exists between adjacent channel layers; The isolation layer includes at least a first isolation layer; the first isolation layer at least fills the first gap; the at least two channel layers and the isolation layer constitute a first fin structure; there is an interface between the isolation layer and the gate stack structure; The gate stack structure spans across the first fin structure; The transistor further includes a semiconductor substrate; the channel layer located at the bottom layer is in contact with the semiconductor substrate; or, the channel layer located at the bottom layer and the semiconductor substrate have a second gap, and the first isolation layer further fills the second gap; Along the length, width, or height direction parallel to the channel layer, the first isolation layer includes a first isolation portion and a second isolation portion located on both sides of the first isolation portion; the material of the first isolation portion is different from the material of the second isolation portion.

2. The transistor according to claim 1, characterized in that, When the second isolation portion is located on both sides of the first isolation portion along the direction parallel to the width of the channel layer, the height of the second isolation portion is less than the height of the first isolation portion; The first isolation layer further includes a third isolation portion; the third isolation portion is located on both sides of the second isolation portion along the height direction parallel to the channel layer; the material of the third isolation portion is different from the material of the second isolation portion.

3. The transistor according to claim 1, characterized in that, The height of each of the first isolation layers is 4 nm to 12 nm; and / or, In the case where the isolation layer includes at least two first isolation layers, the height of the first isolation layers located on different layers is the same.

4. The transistor according to claim 1, characterized in that, The at least two channel layers and the first isolation layer constitute the second fin structure; The isolation layer also includes a second isolation layer covering the outer periphery of the second fin structure; The gate stack structure is formed on the second isolation layer.

5. The transistor according to claim 4, characterized in that, The second isolation layer includes a fourth isolation portion and a fifth isolation portion; the fourth isolation portion and the fifth isolation portion are made of different materials; The fourth isolation portion covers the outer periphery of the second fin structure, and the contact area between the fourth isolation portion and the first isolation layer has a hollow area; the fifth isolation portion is formed on the fourth isolation portion and fills the hollow area.

6. The transistor according to claim 1, characterized in that, The material of the isolation layer includes one or more of silicon dioxide, silicon nitride, hafnium dioxide, zirconium dioxide, titanium dioxide, and aluminum oxide.

7. The transistor according to claim 1, characterized in that, The aspect ratio A of each channel layer is in the range of: 1:10 ≤ A ≤ 1:1; or, The aspect ratio A of each channel layer is in the range of 1:1 < A ≤ 10:

1.

8. The transistor according to claim 1, characterized in that, The channel layers located in different layers have the same height.

9. The transistor according to claim 1, characterized in that, At least one of the trench layers has a different height from the other trench layer.

10. A semiconductor device, characterized in that, Includes the transistor as described in any one of claims 1 to 9.

11. The semiconductor device according to claim 10, characterized in that, The semiconductor device includes a first transistor and a second transistor; one of the first transistor and the second transistor is the transistor according to any one of claims 1 to 9, and the other is a gate-around transistor.

12. The semiconductor device according to claim 11, characterized in that, The first transistor has the opposite conductivity type to the second transistor.

13. The semiconductor device according to claim 11, characterized in that, The first transistor and the second transistor have different materials for their channel layers.

Images