A harmonic-like noise ring voltage controlled oscillator
By designing a harmonic noise-cycled voltage-controlled oscillator and combining noise cycling with a Class-F23 oscillator, the phase noise performance of the oscillator was optimized, solving the problem of phase noise degradation at high frequencies and achieving excellent results in high-quality factor and frequency regulation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-09-06
- Publication Date
- 2026-04-07
AI Technical Summary
Existing oscillators suffer from deteriorating phase noise at high frequencies, and existing noise-cycle oscillators and harmonic oscillators only optimize phase noise from the perspective of noise generation or noise transmission, failing to achieve comprehensive optimization.
Design a harmonic noise-cycle voltage-controlled oscillator. Use an NMOS transistor, a PMOS transistor, a gate capacitor, a drain capacitor, and an inductor that are coupled together to form a transformer. Combine the noise cycle with a Class-F23 oscillator and connect the transistors through cross-coupling. Design a high-order resonant cavity to resonate at the fundamental and third harmonic frequencies to achieve the Class-F23 oscillation state.
It effectively reduces the phase noise of the oscillator, improves the quality factor, occupies a smaller area, and achieves frequency regulation and excellent phase noise performance.
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Figure CN115425926B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to microwave monolithic integrated circuits and microelectronics technology, and particularly to a harmonic noise cyclic voltage-controlled oscillator. Background Technology
[0002] In recent years, with the development of wireless communication systems, higher frequencies, smaller sizes, and lower power consumption have been required for radio frequency (RF) front-end transceiver systems. Simultaneously, as frequencies continue to rise, wireless communication relies on more complex modulation schemes, thus demanding higher purity from the local oscillator signal. However, as frequencies increase, the phase noise of the oscillator gradually deteriorates. This is mainly because the performance of both passive and active components in the oscillator deteriorates to some extent with increasing operating frequencies. For passive components, this manifests primarily as a significant decrease in the quality factor; for active components, it manifests primarily as a significant decrease in gain and switching characteristics.
[0003] To address this issue, noisy cyclic oscillators have been proposed by researchers. By designing a stacked topology of NMOS and PMOS transistors and simultaneously turning on or off transistors on the same side, transistor-generated noise can be effectively reduced. Additionally, harmonic oscillators have been extensively studied in recent years. These oscillators utilize a resonant cavity composed of a transformer with coupled inductors and a capacitor, giving the cavity high-order resonance characteristics. By designing the resonant point of the cavity to be located at the fundamental frequency and the third resonance of the oscillator, the oscillator is placed in a Class-F oscillation state, effectively reducing the conversion of transistor noise into phase noise. However, the aforementioned noisy cyclic oscillators only reduce the overall phase noise of the oscillator from the perspective of noise generation, while harmonic oscillators only optimize phase noise performance from the perspective of noise propagation to phase noise. To further reduce phase noise, it is necessary to consider both noise generation and phase noise propagation factors in the oscillator design and optimize the phase noise accordingly. Summary of the Invention
[0004] The purpose of this invention is to propose a harmonic noise cyclic voltage-controlled oscillator.
[0005] The technical solution to achieve the purpose of this invention is: a harmonic noise cyclic voltage-controlled oscillator, comprising NMOS transistor N1, NMOS transistor N2, PMOS transistor P1, PMOS transistor P2, and gate capacitor C. G Drain capacitance C D and three mutually coupled inductors L P L S L T The transformer is composed of [various components].
[0006] The aforementioned harmonic noise cyclic oscillator is characterized in that the source of NMOS transistor N1 is connected to the source of PMOS transistor P1, and the drain of NMOS transistor N1 is connected to inductor L. P The positive and drain capacitance C D One end is connected, and the gate of NMOS transistor N1 is connected to inductor L. S negative electrode, gate capacitance C G Connected; the gate of PMOS transistor P1 is connected to inductor L T The positive terminal of P1 is connected to the positive terminal of P2, and the drain of P1 is grounded; the source of N2 is connected to the source of P2, and the drain of N2 is connected to the inductor L. P The negative and drain capacitance C D The other end is connected, and the gate of NMOS transistor N2 is connected to inductor L. S The positive electrode and gate capacitance C G The other end is connected; the gate of PMOS transistor P2 is connected to inductor L. T The negative terminal of P2 is connected to the ground, and the drain of P2 is grounded; inductor L P Center tap connected to V DD Potential, providing energy to the entire voltage-controlled oscillator, inductor L S Center tap connected to V BIASN Potential, providing DC gate voltage bias for NMOS transistors N1 and N2, L T Center tap connected to V BIASP The potential provides a DC gate voltage bias for PMOS transistors P1 and P2.
[0007] Three mutually coupled inductors L P L S L T This forms transformer T1 and inductor L. P With inductor L S The coupling coefficient between them is K PS Inductor L P With inductor L T The coupling coefficient between them is K PT Inductor L S With inductor L T The coupling coefficient between them is K ST Furthermore, transformer T1 occupies only the layout area of one inductor.
[0008] The resonant cavity of the oscillator is composed of the gate capacitance C G Drain capacitance C D and three mutually coupled inductors L P L S L TThe transformer is composed of NMOS transistors N1, NMOS transistor N2, PMOS transistor P1, and PMOS transistor P2 of the oscillator are connected in a cross-coupled manner to provide negative resistance to the resonant cavity and maintain the oscillation of the oscillator.
[0009] The gate input voltages of PMOS transistors P1 and P2 are achieved through magnetic coupling via transformer T1; within one oscillation cycle, when inductor L... P When the positive electrode is at a high potential, due to the coupling effect of transformer T1, the inductor L... T The positive electrode is at a high potential, thereby obtaining the gate voltages of PMOS transistors P1 and P2.
[0010] During the first half of the oscillation cycle, the gate voltage of NMOS transistor N1 is high, and since the drain voltage of NMOS transistor N2 is low and the gate voltage of PMOS transistor P1 is low, both NMOS transistor N1 and PMOS transistor P1 are turned on simultaneously. During the second half of the oscillation cycle, the gate voltage of NMOS transistor N1 is low, and since the drain voltage of NMOS transistor N2 is high and the gate voltage of PMOS transistor P1 is high, both NMOS transistor N1 and PMOS transistor P1 are turned off simultaneously.
[0011] During the first half of the oscillation cycle, the gate voltage of NMOS transistor N2 is low. Since the drain voltage of NMOS transistor N2 is high and the gate voltage of PMOS transistor P2 is high, both NMOS transistor N2 and PMOS transistor P2 are turned off simultaneously. During the second half of the oscillation cycle, the gate voltage of NMOS transistor N2 is high. Since the drain voltage of NMOS transistor N2 is low and the gate voltage of PMOS transistor P2 is low, both NMOS transistor N2 and PMOS transistor P2 are turned on simultaneously.
[0012] A resonant cavity composed of a transformer and a capacitor exhibits high-order oscillation characteristics. In the design of a differential-mode resonant cavity, the first resonant point is designed at the fundamental frequency of the oscillator, and the second resonant point is designed at the third harmonic frequency of the oscillator. In the design of a common-mode resonant cavity, the resonant point is designed at the second harmonic frequency of the oscillator, so that the entire oscillator operates at Class-F. 23 Under the oscillation state.
[0013] Compared with the prior art, the significant advantages of this invention are: (1) combining a noisy cyclic oscillator with Class-F 23 (1) The oscillator is combined to optimize the phase noise performance of the oscillator from two aspects: noise generation and noise transmission to phase noise; (2) The transformer composed of three mutually coupled inductors realizes Class-F through the high-order resonant cavity composed of the transformer. 23The working state of the oscillator also realizes the design of noise cycling, while occupying only the area of an inductor; (3) The transformer-based resonant cavity has a higher quality factor at the fundamental frequency than the inductor-based resonant cavity, and can be optimized based solely on the phase noise performance of the oscillator. Attached Figure Description
[0014] Figure 1 This is a schematic diagram of the topology of the harmonic noise cyclic voltage-controlled oscillator provided in an embodiment of the present invention;
[0015] Figure 2 This is a schematic diagram of the transformer structure provided in an embodiment of the present invention;
[0016] Figure 3 The simulation results of the time-domain signal of the harmonic noise cyclic voltage-controlled oscillator within one oscillation cycle provided in the embodiments of the present invention are as follows:
[0017] Figure 4 This is the equivalent circuit of the resonant cavity of the harmonic noise cyclic voltage-controlled oscillator provided in the embodiment of the present invention;
[0018] Figure 5 These are the simulation results of the resonant cavity input impedance provided in the embodiments of the present invention;
[0019] Figure 6 This is a complete schematic diagram of the harmonic noise cyclic voltage-controlled oscillator provided in the embodiment of the present invention;
[0020] Figure 7 This is the frequency adjustment range curve of the harmonic noise cyclic voltage-controlled oscillator provided in the embodiments of the present invention;
[0021] Figure 8 This is the phase noise curve of the harmonic noise cyclic voltage-controlled oscillator provided in the embodiment of the present invention.
[0022] Figure 9 The layout of a harmonic noise cyclic oscillator provided in an embodiment of the present invention. Detailed Implementation
[0023] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0024] Figure 1 This is a topology of a harmonic noise cyclic voltage-controlled oscillator provided in an embodiment of this disclosure. Please refer to [link to relevant documentation]. Figure 1 The oscillator consists of NMOS transistors N1 and N2, PMOS transistors P1 and PMOS transistors P2, and a gate capacitor C. G Drain capacitance C Dand three mutually coupled inductors L P L S L T The transformer T1 is composed of transistors; the source of NMOS transistor N1 is connected to the source of PMOS transistor P1, and the drain of NMOS transistor N1 is connected to the inductor L. P The positive and drain capacitance C D One end is connected, and the gate of NMOS transistor N1 is connected to inductor L. S negative electrode, gate capacitance C G Connected; the gate of PMOS transistor P1 is connected to inductor L T The positive terminal of P1 is connected to the positive terminal of P2, and the drain of P1 is grounded; the source of N2 is connected to the source of P2, and the drain of N2 is connected to the inductor L. P The negative and drain capacitance C D The other end is connected, and the gate of NMOS transistor N2 is connected to inductor L. S The positive electrode and gate capacitance C G The other end is connected; the gate of PMOS transistor P2 is connected to inductor L. T The negative terminal of P2 is connected to the ground, and the drain of P2 is grounded; inductor L P Center tap connected to V DD Potential, providing energy to the entire voltage-controlled oscillator, inductor L S Center tap connected to V BIASN Potential, providing DC gate voltage bias for NMOS transistors N1 and N2, L T Center tap connected to V BIASP The potential provides a DC gate voltage bias for PMOS transistors P1 and P2.
[0025] Furthermore, in the aforementioned harmonic noise cyclic oscillator, the resonant cavity of the oscillator is composed of a gate capacitor C. G Drain capacitance C D and three mutually coupled inductors L P L S L T The transformer is composed of components; the NMOS transistors N1, NMOS transistor N2, PMOS transistor P1, and PMOS transistor P2 of the oscillator are connected in a cross-coupled manner to provide negative resistance to the resonant cavity and maintain the oscillation of the oscillator.
[0026] Figure 2 This is a schematic diagram of a transformer structure provided in an embodiment of the present invention, showing three mutually coupled inductors L. P L S L T This forms transformer T1 and inductor L. P With inductor L S The coupling coefficient between them is K PSInductor L P With inductor L T The coupling coefficient between them is K PT Inductor L S With inductor L T The coupling coefficient between them is K ST Furthermore, the three transformers occupy the layout area of only one inductor.
[0027] In the aforementioned harmonic noise cyclic oscillator, the gate input voltages of PMOS transistors P1 and P2 are achieved through magnetic coupling via transformer T1; within one oscillation cycle, when inductor L... P When the positive electrode is at a high potential, due to the coupling effect of transformer T1, the inductor L... T The positive electrode is at a high potential, thereby obtaining the gate voltages of PMOS transistors P1 and P2.
[0028] Figure 3 This is a simulation result of the time-domain signal of the harmonic noise cyclic voltage-controlled oscillator provided in this embodiment of the invention within one oscillation cycle. In the first half of the oscillation cycle, the gate voltage of NMOS transistor N1 is high, and since the drain voltage of NMOS transistor N2 is low, the gate voltage of PMOS transistor P1 is also low; therefore, NMOS transistor N1 and PMOS transistor P1 are simultaneously turned on. In the second half of the oscillation cycle, the gate voltage of NMOS transistor N1 is low, and since the drain voltage of NMOS transistor N2 is high, the gate voltage of PMOS transistor P1 is also high; therefore, NMOS transistor N1... The NMOS transistor N2 is turned off simultaneously with PMOS transistor P1. During the first half of the oscillation cycle, the gate voltage of NMOS transistor N2 is low. Since the drain voltage of NMOS transistor N2 is high and the gate voltage of PMOS transistor P2 is high, both NMOS transistor N2 and PMOS transistor P2 are turned off simultaneously. During the second half of the oscillation cycle, the gate voltage of NMOS transistor N2 is high. Since the drain voltage of NMOS transistor N2 is low and the gate voltage of PMOS transistor P2 is low, both NMOS transistor N2 and PMOS transistor P2 are turned on simultaneously. Therefore, the oscillator has noise cycling characteristics.
[0029] Figure 4 This is the equivalent circuit of the resonant cavity of the harmonic noise cyclic voltage-controlled oscillator provided in the embodiments of the present invention, such as... Figure 4 As shown, r P For inductor L P The equivalent loss resistance, L Pe For inductor L P The equivalent sense value can be expressed as r S For inductor L S The equivalent loss resistance, L Se For inductor L S The equivalent sense value can be expressed as r T For inductor L T The equivalent loss resistance, L Te For inductor L T The equivalent sense value can be expressed as L P With L S The equivalent coil ratio N S It can be represented as L P With L T The equivalent coil ratio N T It can be represented as Mutual inductance M can be represented as C T Let P be the gate parasitic capacitance of PMOS transistor P1. Therefore, the differential-mode input impedance of the resonant cavity can be expressed as:
[0030]
[0031] Figure 5 The simulation results of the resonant cavity input impedance provided in the embodiments of the present invention can be found in [link to relevant documentation]. Figure 5 The resonant cavity composed of a transformer and a capacitor exhibits high-order oscillation characteristics. In the design of the differential-mode resonant cavity, the first resonant point is designed at the fundamental frequency of the oscillator, and the second resonant point is designed at the third harmonic frequency. In the design of the common-mode resonant cavity, the resonant point is designed at the second harmonic frequency of the oscillator, ensuring the entire oscillator operates at Class-F. 23 Under the oscillation state.
[0032] Figure 6 This is a complete schematic diagram of the harmonic noise cyclic voltage-controlled oscillator provided in the embodiment of the present invention. In order to expand the frequency adjustment bandwidth, the gate capacitor C... G The design consists of a switched capacitor array C composed of four differential switched capacitors. G,diff _Bank, Fixed Capacitor C G,diff and the differential connection type of the variable capacitance tube C Var It also allows for continuous frequency adjustment; drain capacitance C D The design consists of a switched capacitor array C composed of three differential switched capacitors. D,diff A switched capacitor array C consisting of a bank and three single-ended switched capacitors. D,se _Bank and fixed capacitor C D,diff .
[0033] Figure 7The figure shows the frequency adjustment range curve of the harmonic noise cyclic voltage-controlled oscillator provided in the embodiment of the present invention. By designing a switched capacitor array and a varactor tube, continuous frequency adjustment from 5.29 GHz to 6.38 GHz can be achieved.
[0034] Figure 8 The figure shows the phase noise curve of the harmonic noise cyclic oscillator provided in the embodiment of the present invention. By combining the noise cyclic oscillator with the Class-F23 oscillator, the phase noise performance of the oscillator is optimized from two aspects: noise generation and noise transmission to phase noise. At a frequency offset of 100kHz, the phase noise is -105.95dBc / Hz; at a frequency offset of 1MHz, the phase noise is -126.18dBc / Hz; and at a frequency offset of 10MHz, the phase noise is -145.973dBc / Hz.
[0035] Figure 9 The layout of the harmonic noise cyclic oscillator provided in this embodiment of the invention has a core layout area of only 0.216 mm². 2 A voltage-controlled oscillator with excellent phase noise performance was designed in a relatively small area.
[0036] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0037] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A harmonic noise cyclic voltage-controlled oscillator, characterized in that, Composed of NMOS transistors N1 and N2, PMOS transistors P1 and PMOS transistors P2, and gate capacitor C G Drain capacitance C D Three mutually coupled inductors L P L S L T Composed of three mutually coupled inductors L P L S L T This forms transformer T1, with gate capacitance C. G Drain capacitance C D The resonant cavity of the oscillator is composed of transformer T1, wherein: The source of NMOS transistor N1 is connected to the source of PMOS transistor P1, and the drain of NMOS transistor N1 is connected to inductor L. P The positive and drain capacitance C D One end is connected, and the gate of NMOS transistor N1 is connected to inductor L. S negative electrode, gate capacitance C G Connected; the gate of PMOS transistor P1 is connected to inductor L T The positive terminal of P1 is connected to the positive terminal of P2, and the drain of P1 is grounded; the source of N2 is connected to the source of P2, and the drain of N2 is connected to the inductor L. P The negative and drain capacitance C D The other end is connected, and the gate of NMOS transistor N2 is connected to inductor L. S The positive electrode and gate capacitance C G The other end is connected; the gate of PMOS transistor P2 is connected to inductor L. T The negative terminal of P2 is connected to the ground, and the drain of P2 is grounded; inductor L P Center tap connected to V DD Potential, providing energy to the entire voltage-controlled oscillator, inductor L S Center tap connected to V BIASN Potential, providing DC gate voltage bias for NMOS transistors N1 and N2, L T Center tap connected to V BIASP The potential provides a DC gate voltage bias for PMOS transistors P1 and P2.
2. The harmonic noise cyclic oscillator according to claim 1, characterized in that, The NMOS transistors N1, NMOS transistor N2, PMOS transistor P1, and PMOS transistor P2 of the oscillator are connected in a cross-coupled manner to provide negative resistance to the resonant cavity and maintain the oscillation of the oscillator.
3. The harmonic noise cyclic oscillator according to claim 1, characterized in that, The gate input voltages of PMOS transistors P1 and P2 are achieved through the magnetic coupling of transformer T1. Within one oscillation cycle, when the inductor L... P When the positive electrode is at a high potential, due to the coupling effect of transformer T1, the inductor L... T The positive electrode is at a high potential, thereby obtaining the gate voltages of PMOS transistors P1 and P2.
4. The harmonic noise cyclic oscillator according to claim 1, characterized in that, During the first half of the oscillation cycle, the gate voltage of NMOS transistor N1 is high, and since the drain voltage of NMOS transistor N2 is low, the gate voltage of PMOS transistor P1 is also low, so both NMOS transistor N1 and PMOS transistor P1 are turned on simultaneously. During the second half of the oscillation cycle, the gate voltage of NMOS transistor N1 is low, and since the drain voltage of NMOS transistor N2 is high, the gate voltage of PMOS transistor P1 is also high, so both NMOS transistor N1 and PMOS transistor P1 are turned off simultaneously. During the first half of the oscillation cycle, the gate voltage of NMOS transistor N2 is low. Since the drain voltage of NMOS transistor N2 is high, the gate voltage of PMOS transistor P2 is also high, and both NMOS transistor N2 and PMOS transistor P2 are turned off simultaneously. During the second half of the oscillation cycle, the gate voltage of NMOS transistor N2 is high. Since the drain voltage of NMOS transistor N2 is low, the gate voltage of PMOS transistor P2 is also low, and both NMOS transistor N2 and PMOS transistor P2 are turned on simultaneously.
5. The harmonic noise cyclic oscillator according to claim 1, characterized in that, In the design of differential-mode resonant cavities, the first resonant point is designed at the fundamental frequency of the oscillator, and the second resonant point is designed at the third harmonic frequency of the oscillator. In the design of common-mode resonant cavities, the resonant point is designed at the second harmonic frequency of the oscillator, so that the entire oscillator operates in Class-F. 23 Under the oscillation state.