A universal multi-segment binary capacitive array and its design method

Abstract

The application relates to a universal multi-section binary capacitance array and application thereof, and belongs to the technical field of integrated circuits. The application comprises a capacitance array, a bridging capacitance, a redundant capacitance, an input stage and an output stage, wherein the capacitance array comprises n sections, each section comprises S n bit capacitances arranged in parallel, the n-section capacitance array is provided with a redundant capacitance on one side, the n-section capacitance array is provided with a bridging capacitance, all the lower plates of the capacitances of the capacitance array and the lower plate of the redundant capacitance are connected with the input stage, and the n-section capacitance array is connected with the output stage. The application reduces the area of a high-precision analog-to-digital converter or digital-to-analog converter capacitance array, alleviates the contradiction between the precision and the area of the analog-to-digital converter and the digital-to-analog converter, all the capacitances are integer multiples of unit capacitances, and the influence of capacitance mismatch on the overall precision is reduced.

Description

Technical Field

[0001] This invention relates to a general-purpose multi-segment binary capacitor array and its applications, belonging to the field of integrated circuit technology. Background Technology

[0002] Capacitor arrays are widely used in analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), utilizing the different weights of each capacitor in the array to convert digital signals into corresponding analog signals. A traditional N-bit binary capacitor array requires 2... N Composed of a single unit capacitor, high-precision analog-to-digital converters (ADCs) or digital-to-analog converters (DACs) (12-24 bits) cannot accommodate large capacitors due to limitations in integrated circuit technology and area. Therefore, segmented capacitor arrays are necessary. Traditional segmented structures are mostly two- or three-segmented. However, for even higher-precision ADCs or DACs (12 bits and above), two- or three-segmented structures cannot meet the circuit design area requirements.

[0003] Currently, designing structures with three or more segments requires first designing them in two segments, then designing the higher segments in two segments, and so on, to achieve a multi-segment capacitor structure. However, this method involves cumbersome calculations. Therefore, this invention is proposed. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a universal multi-segment binary capacitor array and its application, which reduces the area of ​​capacitor arrays in high-precision analog-to-digital converters or digital-to-analog converters, alleviates the contradiction between accuracy and area in analog-to-digital converters and digital-to-analog converters, and ensures that all capacitors are integer multiples of the unit capacitance, reducing the impact of capacitor mismatch on overall accuracy.

[0005] The technical solution of the present invention is as follows:

[0006] A general-purpose multi-segment binary capacitor array includes a capacitor array, bridging capacitors, redundant capacitors, an input stage, and an output stage, wherein:

[0007] The capacitor array consists of n segments, each segment including S capacitors connected in parallel. n The n-segment capacitor array has redundant capacitors on one side and bridging capacitors between the n segments. The lower plates of all capacitors in the capacitor array and the lower plates of the redundant capacitors are connected to the input stage, and the nth segment of the capacitor array is connected to the output stage.

[0008] The above n represents the number of segments in the capacitor array, S n This represents the number of bits of capacitors in each segment of the capacitor array.

[0009] Preferably, the capacitance value of the lowest bit of each segment of the capacitor array, except for the first segment, is... is the unit capacitance of the above paragraph k i-1 times, k i-1 Any positive integer can be taken, in order to ensure that the overall capacitance array weight is a binary relationship, each segment of the capacitance array from the lowest bit to the highest bit capacitance meets the binary weight relationship.

[0010] Wherein, C0 i represents the unit capacitance of the i-th segment of the capacitance array, and i represents any segment of the capacitance array.

[0011] Preferably, in order to ensure that the number of adjacent bits between the segments of the capacitance array meets the binary weight relationship, the bridge capacitance calculation formula is derived as

[0012] In the formula, C ai is the bridge capacitance of the segmented capacitance array, C (i―1)t is the total capacitance value of the first i-1 segments of the capacitance, including the sum of the redundant capacitance of the segment and the equivalent capacitance value of the remaining low segment capacitance in series; C ai―1 is the value of the i-1th bridge capacitance, S i―1 is the number of bits of the i-1th segment of the capacitance, k i―1 represents the multiple of the value of the lowest bit capacitance of the i-th segment of the capacitance array relative to the unit capacitance of the i-1th segment.

[0013] Preferably, the redundant capacitance of each segment of the multi-segmented capacitance array is any positive integer multiple of the unit capacitance of the first segment of the capacitance array, that is, C d1 =q i C0 1 , q i is any positive integer, and C d1 is the redundant capacitance of the i-th segmented capacitance array, and in order to ensure that the value of the bridge capacitance is a positive integer multiple of the unit capacitance of the first segment of the capacitance array, q i starts from 1 and is calculated, that is, p i is a positive integer.

[0014] Preferably, the sum of the capacitance bit numbers of the n segments of the capacitance array is the total bit number M, that is, M=S1+S2+S3+S4+……+S n .

[0015] Preferably, the input stage is a sampling circuit or a switching circuit, and the output stage is a comparator input end circuit or a digital-to-analog converter output end circuit.

[0016] The application of the above general multi-segment binary capacitance array is as follows:

[0017] ​​(1) Determine the total number of bits M of the multi-segment capacitor array based on the accuracy of the designed analog-to-digital converter or digital-to-analog converter;

[0018] (2) Determine the number of segments n and the number of bits S in each segment of the capacitor array based on the required area of ​​the designed capacitor array. n The sum of the bits in the n-segment capacitor array equals the total number of bits M;

[0019] (3) Determine the capacitance value: the capacitance value of the lowest bit of each segment of the capacitor array except the first segment. It is the unit capacitance of the segment above it. k i-1 The capacitors in each segment of the capacitor array satisfy a binary weighting relationship from the least significant bit to the most significant bit.

[0020] (4) According to the calculation formula of bridging capacitance Calculate the value of each bridging capacitor;

[0021] Then, based on the fact that the redundant capacitance of each segment of the multi-segment capacitor array is an arbitrary positive integer multiple of the unit capacitance of the first segment of the capacitor array, i.e., C... di =q i C0 1 , q i Starting from 1, substitute values ​​into the calculation to ensure the bridging capacitor satisfies the equation. p i It is a positive integer;

[0022] (5) S of each segment of the multi-segment capacitor array n The capacitors are connected in parallel. The upper plate of the first capacitor array and the first redundant capacitor is connected to the lower plate of the first bridging capacitor. The upper plates of the second capacitor array and the second redundant capacitor are both connected to the upper plate of the first bridging capacitor and the lower plate of the second bridging capacitor. The upper plates of the third capacitor array and the third redundant capacitor are both connected to the upper plate of the second bridging capacitor and the lower plate of the third bridging capacitor. And so on. The upper plate of the nth capacitor array and the nth redundant capacitor is connected to the upper plate of the (n-1)th bridging capacitor and the output stage. The lower plates of the M capacitors and n redundant capacitors in the capacitor array are all connected to the input stage.

[0023] In this invention, the upper end of a vertical capacitor is designated as the upper plate and the lower end as the lower plate; the right end of a horizontal capacitor is designated as the upper plate and the left end as the lower plate.

[0024] The beneficial effects of this invention are as follows:

[0025] 1. Compared with traditional binary capacitor array technology, this invention can reduce the area of ​​the capacitor array in high-precision analog-to-digital converters or digital-to-analog converters, alleviate the contradiction between the accuracy and area of ​​analog-to-digital converters and digital-to-analog converters, and all capacitors are integer multiples of unit capacitance, reducing the impact of capacitor mismatch on overall accuracy.

[0026] 2. Compared to traditional segmented capacitors, this invention can be applied to analog-to-digital converters (ADCs) or digital-to-analog converters (DACs) with precision of 12 bits or higher, as well as low-area, high-integration ADCs or DACs. Furthermore, the method proposed in this invention makes segmented capacitor array design more flexible, allowing for better matching of integrated circuit processes and area according to design needs, thus reducing the design complexity of capacitor arrays for high-precision ADCs and DACs. By rationally setting the capacitance values ​​of redundant capacitors, each capacitor value can be an integer multiple of the unit capacitance, which can be achieved through cell replication during layout design, making layout design easier and ensuring high capacitor array matching accuracy. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the M-bit n-segmented capacitor array of the present invention;

[0028] Figure 2 This is a schematic diagram of a 16-bit 4-segment capacitor array according to Embodiment 1 of the present invention;

[0029] Figure 3 This is a schematic diagram of a 20-bit 5-segment capacitor array according to Embodiment 2 of the present invention. Detailed Implementation

[0030] The present invention will be further described below with reference to the embodiments and accompanying drawings, but is not limited thereto.

[0031] Example 1:

[0032] like Figure 2 As shown, this embodiment provides a 4-segment 16-bit multi-segment binary capacitor array for analog-to-digital converters, including 4 capacitor arrays, 3 bridging capacitors and 4 redundant capacitors. Each segment includes 4-bit capacitors connected in parallel. A switching circuit serves as the input stage, and a comparator input circuit serves as the output stage.

[0033] The 4-bit capacitors of each segment of the capacitor array are connected in parallel, the upper plates of the first segment capacitor array and the first redundant capacitor are connected to the lower plate of the first bridging capacitor, the upper plates of the second segment capacitor array and the second redundant capacitor are connected to the upper plate of the first bridging capacitor and the lower plate of the second bridging capacitor, the upper plates of the third segment capacitor array and the third redundant capacitor are connected to the upper plate of the second bridging capacitor and the lower plate of the third bridging capacitor, the upper plates of the fourth segment capacitor array and the fourth redundant capacitor are connected to the upper plate of the third bridging capacitor and the input of the comparator, the lower plates of the 16-bit capacitors of the 4-segment capacitor array are connected to the switch array, and the lower plates of the four redundant capacitors are connected to the ground.

[0034] In the figure, S0 is a reset switch, Comp is a comparator, the first segment, the second segment, the third segment and the fourth segment respectively represent four segmented arrays of the 16-bit capacitor array, GND represents the ground, S1, S2, S3, S4, S5, S6, S7, S8, S9, S 10 , S 11 , S 12 , S 13 , S 14 , S 15 and S 16 respectively represent the control switches of the first capacitor to the sixteenth capacitor, which are responsible for signal sampling and conversion in the working process of the analog-to-digital converter.

[0035] The capacitance value of the lowest capacitor of each segment capacitor array of the multi-segment capacitor array except the first segment is k i-1 times the unit capacitance of the previous segment. k i-1 is any positive integer. In order to ensure that the overall capacitor array weight is in binary relationship, the capacitors of each segment capacitor array from the lowest bit to the highest bit satisfy the binary weight relationship.

[0036] In order to ensure that the number of adjacent bits between the segments of the multi-segment capacitor array satisfies the binary weight relationship, the calculation formula of the bridging capacitor is In the formula, C (i―1)t represents the total capacitance value of the first i-1 segments of capacitors, including the redundant capacitor of the segment and the equivalent capacitance value of the remaining low segment capacitors in series; C ai―1 represents the value of the i-1th bridging capacitor, S i―1 represents the number of bits of the i-1th segment capacitor, k i―1 represents the value of the lowest capacitor of the i-th segment capacitor array relative to the unit capacitance of the i-1th segment .

[0037] The redundant capacitance of each segment of the multi-segment capacitance array is any positive integer multiple of the unit capacitance of the first segment capacitance array, i.e. C di = q i C0 1 (i = 1, 2, 3, 4), q i is any positive integer. To ensure that the value of the bridging capacitance is a positive integer multiple of the unit capacitance of the first segment capacitance array, q i is taken from 1 and brought into the calculation, i.e. p i is a positive integer.

[0038] The sum of the bit numbers of the n segment capacitance arrays of the multi-segment capacitance array is the total bit number 16, i.e. 16 = 4 + 4 + 4 + 4.

[0039] The application of the above multi-segment binary capacitance array is as follows:

[0040] (1) According to the 16-bit conversion accuracy of the designed analog-to-digital converter or digital-to-analog converter, the total bit number 16 of the multi-segment capacitance array is determined;

[0041] (2) According to the area of the designed capacitance array, the number of segments required for the capacitance array is determined to be 4 and the bit number of each segment capacitance array is determined to be 4, and it is ensured that the bit numbers of the 4 segment capacitance arrays add up to the total bit number 16;

[0042] (3) The capacitance values are determined. The lowest bit capacitance value of each segment capacitance array of the multi-segment capacitance array except the first segment is satisfying k i-1 times the unit capacitance of the previous segment k i-1 can be any positive integer, and the value of the capacitance is determined. To ensure that the weight of the overall capacitance array is in a binary relationship, the capacitances of each segment capacitance array from the lowest bit to the highest bit satisfy the binary weight relationship;

[0043] Therefore, take k1, k2, k3 as 1, and take The calculation can obtain that the values of the first bit capacitance to the fourth bit capacitance in the first segment capacitance array are C0, 2C0, 4C0, 8C0, the values of the fifth bit capacitance to the eighth bit capacitance in the second segment capacitance array are C0, 2C0, 4C0, 8C0, the values of the ninth bit capacitance to the twelfth bit capacitance in the third segment capacitance array are C0, 2C0, 4C0, 8C0, and the values of the thirteenth bit capacitance to the sixteenth bit capacitance in the fourth segment capacitance array are C0, 2C0, 4C0, 8C0;

[0044] (4) According to the calculation formula of the bridging capacitance the value of each bridging capacitance is calculated, wherein, C (i―1)tCi-1 represents the total capacitance of the i-1th segment capacitor, including the sum of the redundant capacitance of the segment and the series equivalent capacitance of the remaining low segment capacitors; C ai―1 Ci-1 represents the value of the i-1th bridge capacitor, S i―1 Ci-1 represents the number of bits of the i-1th segment capacitor, k i―1 Ci-1 represents the lowest bit capacitor of the i-1th segment capacitor array Ci-1 represents the value of the i-1th segment capacitor, S Ci-1 represents the value of the i-1th segment capacitor, S

[0045] Then, according to the redundant capacitance of each segment of the multi-segment capacitor array, the unit capacitance of the first segment capacitor array can be any positive integer multiple, that is, C di = q i C0 1 , q i is any positive integer, and q i is taken from 1 to calculate, so that the bridge capacitor satisfies the equation p i is a positive integer;

[0046] Therefore, the value of C d1 is 225C0, the value of C d2 is 210C0, the value of C d3 is 210C0, the value of C d4 is C0, and according to the formula, the value of C a1 is 16C0, the value of C a2 is 16C0, and the value of C a3 is 16C0.

[0047] (5) The 4-bit capacitors of each segment of the multi-segment capacitor array are connected in parallel to each other, the upper plate of the first segment capacitor array and the first segment redundant capacitor is connected to the lower plate of the first bridge capacitor, the upper plate of the second segment capacitor array and the second segment redundant capacitor is connected to the upper plate of the first bridge capacitor and the lower plate of the second bridge capacitor, the upper plate of the third segment capacitor array and the third segment redundant capacitor is connected to the upper plate of the second bridge capacitor and the lower plate of the third bridge capacitor, the upper plate of the fourth segment capacitor array and the fourth segment redundant capacitor is connected to the upper plate of the third bridge capacitor and the output stage, the 16-bit capacitors of the multi-segment capacitor array are connected to the switch circuit, the lower plate of the redundant capacitor is connected to the ground, and the 4-bit capacitors of the fourth segment of the multi-segment capacitor array and the upper plate of the third bridge capacitor are both connected to the output end of the comparator through the switch.

[0048] In this embodiment, the upper end of the vertical capacitor is set as the upper plate, and the lower end is the lower plate; the right end of the horizontal capacitor is set as the upper plate, and the left end is the lower plate. In the shown figure, from right to left are 1-bit redundant capacitors to 16-bit capacitors.

[0049] The total capacitance value required by the 4-segment 16-bit capacitor array proposed in this embodiment is 754C0, and the total capacitance value required by the conventional 16-bit binary capacitor array is 131072C0, so the area is only 0.575% of the conventional binary capacitor array structure. Moreover, all the capacitors of the capacitor array proposed in this embodiment are integer multiples of unit capacitors, making it easier to match the capacitors.

[0050] Embodiment 2:

[0051] As shown in Figure 2 , this embodiment provides a 5-segment 20-bit multi-segment binary capacitor array applied to an analog-to-digital converter, which is a 20-bit capacitor array composed of a first 2-bit capacitor array, a second 2-bit capacitor array, a third 3-bit capacitor array, a fourth 5-bit capacitor array, a fifth 8-bit capacitor array, 4 bridge capacitors and 4 redundant capacitors, with switch power as the input stage and comparator input circuit as the output stage.

[0052] Among them, the 2-bit capacitors of the first segment of the segmented capacitor array are connected in parallel with each other, the 2-bit capacitors of the second segment are connected in parallel with each other, the 3-bit capacitors of the third segment are connected in parallel with each other, the 5-bit capacitors of the fourth segment are connected in parallel with each other, the 8-bit capacitors of the fifth segment are connected in parallel with each other, the upper plate of the first segment capacitor array and the first redundant capacitor is connected with the lower plate of the first bridge capacitor, the upper plate of the second segment capacitor array and the second redundant capacitor is connected with the upper plate of the first bridge capacitor and the lower plate of the second bridge capacitor, the upper plate of the third segment capacitor array and the third redundant capacitor is connected with the upper plate of the second bridge capacitor and the lower plate of the third bridge capacitor, the upper plate of the fourth segment capacitor array and the fourth redundant capacitor is connected with the upper plate of the third bridge capacitor and the lower plate of the fourth bridge capacitor, the upper plate of the fifth segment capacitor array and the fifth redundant capacitor is connected with the upper plate of the fourth bridge capacitor and the comparator input circuit, the lower plates of the 20-bit capacitors of the 5-segment capacitor array are all connected with the switch circuit, and the lower plates of the 5 redundant capacitors are all connected with the ground.

[0053] In the figure, S0 is a reset switch, Comp is a comparator, the 1st segment, the 2nd segment, the 3rd segment, the 4th segment and the 5th segment respectively represent the 5 segmented arrays of the 20-bit capacitor array, GND represents the ground, S1, S2, S3, S4, S5, S6, S7, S8, S9, S 10 , S 11 , S 12 , S 13 , S 14 , S 15 , S 16 , S 17 , S 18 , S 19 , and S 20Control switches for the first to the twentieth capacitors, responsible for signal sampling and conversion in the working process of the analog-digital converter.

[0054] The capacitance value of the lowest capacitor in each segment of the multi-segment capacitive array except the first segment Satisfies k i-1 Times the unit capacitance of the previous segment k i-1 Can be any positive integer. To ensure that the overall capacitive array weight is in binary relationship, each segment of the capacitive array from the lowest to the highest capacitor satisfies the binary weight relationship.

[0055] To ensure that the number of adjacent bits between the segments of the multi-segment capacitive array satisfies the binary weight relationship, the bridging capacitor calculation formula is In the formula, C (i―1)t represents the total capacitance of the first i-1 segments of capacitors, including the sum of the capacitance of the redundant capacitors of the segment and the equivalent capacitance of the remaining low segment capacitors in series; C ai―1 represents the value of the i-1th bridging capacitor, S i―1 represents the number of bits of the i-1th segment of capacitors, k i―1 represents the lowest capacitor of the i-th segment of capacitive array The value is a multiple of the unit capacitance of the i-1th segment .

[0056] The redundant capacitors of each segment of the multi-segment capacitive array are any positive integer times the unit capacitance of the first segment of capacitive array, i.e. di C i 0 1 (i = 1, 2, 3, 4, 5), q i is any positive integer. To ensure that the value of the bridging capacitor is a positive integer multiple of the unit capacitance of the first segment of capacitive array, q i should be taken from 1 and brought into the calculation, i.e. p i is a positive integer.

[0057] The sum of the capacitance bits of the n segments of the multi-segment capacitive array is 20, i.e. 16 = 2 + 2 + 3 + 5 + 8.

[0058] The application of the above multi-segment binary capacitive array is as follows:

[0059] (1) According to the 20-bit conversion accuracy of the designed analog-digital converter or digital-analog converter, determine the total number of bits of the multi-segment capacitive array as 20 bits;

[0060] (2) According to the designed capacitor array area, the number of segments of the capacitor array is determined to be 5, and the bit number of each segment of the capacitor array is respectively 2, 2, 3, 5, and 8, and it is ensured that the bit number of the 5 segments of the capacitor array is added to equal the total bit number 20;

[0061] (3) The capacitor capacitance is determined, and the lowest bit capacitor capacitance of each segment of the multi-segment capacitor array except the first segment is satisfies k i-1 times the unit capacitance of the previous segment k i-1 is any positive integer. To ensure that the overall capacitor array weight is in a binary relationship, each segment of the capacitor array from the lowest bit to the highest bit capacitor satisfies the binary weight relationship;

[0062] Therefore, k1, k2, k3, and k4 are respectively taken as 2, 4, 8, and 8, and The calculation can obtain that the first bit capacitor to the second bit capacitor value in the first segment of the capacitor array are respectively C0 and 2C0, the third bit capacitor to the fourth bit capacitor value in the second segment of the capacitor array are respectively 2C0 and 4C0, the fifth bit capacitor to the seventh bit capacitor value in the third segment of the capacitor array are respectively 4C0, 8C0, and 16C0, the eighth bit capacitor to the twelfth bit capacitor value in the fourth segment of the capacitor array are respectively 8C0, 16C0, 32C0, 64C0, and 128C0, and the thirteenth bit capacitor to the twentieth bit capacitor value in the fifth segment of the capacitor array are respectively 8C0, 16C0, 32C0, 64C0, 128C0, 256C0, 512C0, and 1024C0;

[0063] (4) According to the calculation formula of the bridge capacitor The value of each bridge capacitor is calculated, wherein C (i―1)t represents the total capacitance of the first i-1 segments of the capacitor, including the redundant capacitor of the segment and the equivalent capacitance sum of the remaining low segment capacitors in series; C ai―1 represents the value of the i-1th bridge capacitor, S i―1 represents the bit number of the i-1th segment of the capacitor, k i―1 represents the lowest bit capacitor of the i-th segment of the capacitor array value relative to the unit capacitance of the i-1th segment ;

[0064] Then, according to the redundant capacitor of each segment of the multi-segment capacitor array, the unit capacitance of the first segment of the capacitor array can be any positive integer times, that is, C d i = q i C0 1 , q i is any positive integer. Taking q i from 1, the bridge capacitor satisfies the equation p i is a positive integer.

[0065] Therefore, the value of C d1 is C d2 is 0, the value of C d3 is 4C d4 is 22C d5 is 8C a1 is 4C a2 is 8C a3 is 12C a4 is 9C

[0066] (5) The 2-bit capacitors of the first section, the 2-bit capacitors of the second section, the 3-bit capacitors of the third section, the 5-bit capacitors of the fourth section, the 8-bit capacitors of the fifth section are connected in parallel with each other, the upper plate of the first section capacitor array and the first redundant capacitor are connected to the lower plate of the first bridge capacitor, the upper plate of the second section capacitor array and the second redundant capacitor are connected to the upper plate of the first bridge capacitor and the lower plate of the second bridge capacitor, the upper plate of the third section capacitor array and the third redundant capacitor are connected to the upper plate of the second bridge capacitor and the lower plate of the third bridge capacitor, the upper plate of the fourth section capacitor array and the fourth redundant capacitor are connected to the upper plate of the third bridge capacitor and the lower plate of the fourth bridge capacitor, the upper plate of the fifth section capacitor array and the fifth redundant capacitor are connected to the upper plate of the fourth bridge capacitor and the comparator input circuit, the lower plate of the 20-bit capacitors of the fifth section capacitor array are connected to the switch circuit, and the lower plate of the five redundant capacitors are connected to the ground.

[0067] In this embodiment, the upper end of the vertical capacitor is set as the upper plate, and the lower end is set as the lower plate; the right end of the horizontal capacitor is set as the upper plate, and the left end is set as the lower plate. In the shown figure, from right to left are the 1-bit redundant capacitor to the 20-bit capacitor.

[0068] The total capacitance value required by the 5-section 20-bit capacitor array proposed in this embodiment is 2393C i , and the total capacitance value required by the traditional 20-bit binary capacitor array is 2097152C i , so the area is only 0.114% of the traditional binary capacitor array structure. Moreover, all the capacitors of the capacitor array proposed in this embodiment are integer multiples of unit capacitors, making it easier to match capacitors.

[0069] The above merely provides preferred embodiments of the present application, but is not intended to limit the present application. Based on the above teachings, one skilled in the art will be able to implement various modifications and variations without departing from the scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall fall within the scope of the present application.

[0070] The above merely provides preferred embodiments of the present application, but is not intended to limit the present application. Based on the above teachings, one skilled in the art will be able to implement various modifications and variations without departing from the scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall fall within the scope of the present application.

Claims

1. A universal multi-segment binary capacitor array, characterized in that, It includes a capacitor array, bridging capacitors, redundant capacitors, an input stage, and an output stage, among which, The capacitor array consists of n segments, each segment including S capacitors connected in parallel. n The n-segment capacitor array has redundant capacitors on one side and bridging capacitors between the n segments. The lower plates of all capacitors in the capacitor array and the lower plates of the redundant capacitors are connected to the input stage, and the nth segment of the capacitor array is connected to the output stage.

2. The universal multi-segment binary capacitor array as described in claim 1, characterized in that, The capacitance value of the least significant bit in each segment of the capacitor array, except for the first segment. It is the unit capacitance of the segment above it. k i-1 times, k i-1 The values ​​can be any positive integers, and each segment of the capacitor array, from the least significant bit to the most significant bit, satisfies a binary weighting relationship. Among them, C0 i Let represent the unit capacitance of the i-th segment of the capacitor array, where i represents any segment of the capacitor array.

3. The universal multi-segment binary capacitor array as described in claim 2, characterized in that, The formula for calculating bridging capacitance is: In the formula, C ai C is the bridge capacitor for the segmented capacitor array. (i-1)t C represents the total capacitance of the first i-1 segments, including the redundant capacitance of this segment and the sum of the equivalent capacitance of the remaining lower segments connected in series; ai-1 S is the value of the (i-1)th bridging capacitor. i-1 k represents the number of bits in the (i-1)th capacitor segment. i-1 Represents the least significant bit capacitance of the i-th segment of the capacitor array. The value is relative to the unit capacitance of the (i-1)th segment. Multiples of.

4. The universal multi-segment binary capacitor array as described in claim 3, characterized in that, The redundant capacitance of each segment of the capacitor array is any positive integer multiple of the unit capacitance of the first segment of the capacitor array, i.e., C. d1 =q i C0 1 q i Let C be any positive integer. d1 Let q be the redundant capacitor of the i-th segment of the capacitor array. i The calculation starts from 1, that is... p i It is a positive integer.

5. The universal multi-segment binary capacitor array as described in claim 4, characterized in that, The sum of the number of bits in the n-segment capacitor array is the total number of bits M, i.e., M = S1 + S2 + S3 + S4 + ... + S n .

6. The universal multi-segment binary capacitor array as described in claim 1, characterized in that, The input stage is a sampling circuit or a switching circuit, and the output stage is a comparator input circuit or a digital-to-analog converter output circuit.

7. A design method for a general multi-segment binary capacitor array as described in claim 6, characterized in that, The steps are as follows: (1) Determine the total number of bits M of the multi-segment capacitor array based on the accuracy of the designed analog-to-digital converter or digital-to-analog converter; (2) Determine the number of segments n and the number of bits S in each segment of the capacitor array based on the required area of ​​the designed capacitor array. n The sum of the bits in the n-segment capacitor array equals the total number of bits M; (3) Determine the capacitance value: the capacitance value of the lowest bit of each segment of the capacitor array except the first segment. It is the unit capacitance of the segment above it. k i-1 The capacitors in each segment of the capacitor array satisfy a binary weighting relationship from the least significant bit to the most significant bit. (4) According to the calculation formula of bridging capacitance Calculate the value of each bridging capacitor; Then, based on the fact that the redundant capacitance of each segment of the multi-segment capacitor array is an arbitrary positive integer multiple of the unit capacitance of the first segment of the capacitor array, i.e., C... di =q i C0 1 , q i Starting from 1, substitute values ​​into the calculation to ensure the bridging capacitor satisfies the equation. p i It is a positive integer; (5) S of each segment of the multi-segment capacitor array n The capacitors are connected in parallel. The upper plate of the first capacitor array and the first redundant capacitor is connected to the lower plate of the first bridging capacitor. The upper plates of the second capacitor array and the second redundant capacitor are both connected to the upper plate of the first bridging capacitor and the lower plate of the second bridging capacitor. The upper plates of the third capacitor array and the third redundant capacitor are both connected to the upper plate of the second bridging capacitor and the lower plate of the third bridging capacitor. And so on. The upper plate of the nth capacitor array and the nth redundant capacitor is connected to the upper plate of the (n-1)th bridging capacitor and the output stage. The lower plates of the M capacitors and n redundant capacitors in the capacitor array are all connected to the input stage.

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