A UDP real-time network transmission method and system based on FPGA

Abstract

The present invention discloses a UDP real-time network transmission method and system based on FPGA, the method comprises receiving network packets transmitted by two-way switching networks, and filtering out UDP packets from front-end sensing devices from the network packets; extracting UDP payload data through UDP protocol unloading for UDP packets, and performing seamless dual-redundancy processing on UDP packets according to the packet sequence number field in the UDP payload data; aggregating multiple UDP payload data retained after seamless dual-redundancy processing into a data block, and storing the data block in an external DDR cache, which is then forwarded to the back-end processor by the external DDR cache. The present invention can simultaneously meet the use requirements of large bandwidth, high reliability and real-time performance of data transmission.

Description

Technical Field

[0001] The invention belongs to the technical field of data transmission, and in particular relates to a UDP real-time network transmission method and system based on FPGA. Background Art

[0002] In view of the wide and mature application of Ethernet technology in the field of informatization, as well as the rich expansion capabilities of the upper layer of the network protocol, many vehicle-mounted, airborne, and ship-mounted platforms have adopted Ethernet as the main bus for data and command communication. Among them, some special sensors on the platform (such as optoelectronic cameras, SAR radars, microwave radio frequency antenna arrays, sonar arrays, etc.) real-time acquisition / preprocessing data needs to be sent to the signal processor for further analysis. Sensors and computers are deployed in different locations, and the transmission network should be guaranteed in terms of bandwidth, real-time performance, and reliability.

[0003] The bandwidth and switching capacity of Ethernet have developed from 10 / 100 / 1000Mbps and 10Gbps to 40Gbps and 100Gbps, and have been continuously upgraded with the improvement of bus technology. At the same time, Ethernet can ensure real-time and reliable transmission through redundant design and some upper-layer QoS services. With the continuous increase in data processing bandwidth, a trade-off needs to be made between real-time and high reliability. For example, the TCP protocol uses a retransmission mechanism to ensure that there is no packet loss, but the cost may be further aggravation of network congestion, and the transmission performance and real-time performance will be reduced accordingly; the UDP protocol is generally used for real-time data stream transmission such as sensors, and a certain amount of packet loss is allowed without affecting the user experience. However, in some special equipment, the data stream sent by the sensor has more stringent requirements on the packet loss rate, so it is necessary to provide a large-bandwidth, highly reliable real-time data stream transmission technology based on Ethernet.

[0004] There are two existing Ethernet-based real-time data stream transmission technology solutions, namely dual-redundant network transmission technology based on UDP protocol and dual-redundant network transmission technology based on DDS protocol, but both transmission technologies have their own defects. DDS, Data Distribution Service, is a distributed real-time communication middleware protocol that adopts a publish / subscribe architecture, emphasizes data-centricity, and provides a wealth of QoS service quality strategies to ensure real-time, efficient, and flexible data distribution.

[0005] Among them, the dual redundant network transmission technology based on UDP protocol has the following problems:

[0006] Performance issues: When processing network packets based on CPU or DSP, the network protocol stack implementation is limited, and data needs to be copied from the kernel to the application. In addition, each network packet needs to be parsed and processed in turn. The processor capacity and DDR main memory access bandwidth may become performance bottlenecks on the entire data path, resulting in packet loss at the network card level or kernel level. If there is a burst of network traffic in the network, the packet loss rate will increase instantly.

[0007] Network packet loss problem: Although the solution adopts a dual-redundant Ethernet bus architecture and a two-choice mode, when it detects that the link of the network port in use is abnormally disconnected, that is, it switches to another network port, there will be a window period, and the processor cannot receive any network packets during the switching period. After testing, the switching time of the two network ports of the 10G network card is on the order of 30ms. In addition, the solution cannot handle packet loss caused by occasional bit errors. When a sudden bit error occurs in the network in use, it will not immediately switch to another network, resulting in packet loss. As mentioned above, when the data sent by the sensor reaches a certain bandwidth, it will be affected by the processor performance bottleneck and packet loss will occur in the network card or operating system kernel.

[0008] Among them, the dual redundant network transmission technology based on the DDS protocol has the following problems:

[0009] Performance issues: Based on the dual-redundant Ethernet transceiver technology of the DDS protocol, dual-redundant hot backup is implemented in the DDS protocol layer. The network packets from the two network ports will be received by the processor at the same time, and the two network packets will be compared through the specific fields of the DDS protocol layer to eliminate redundant packets, avoiding the packet loss caused by the switching of the primary and standby network ports and sudden bit errors in the physical link in the above solution. However, at the same time, the DDS protocol has relatively high requirements on processor performance.

[0010] Network packet loss problem: The DDS protocol belongs to the protocol above the transport layer (such as UDP, TCP). Real-time data stream processing generally adopts the best-effort transmission mode based on UDP. Because two copies of the same data need to be processed at the same time, one of them is discarded after comparison. The processing complexity is relatively high, and generally requires a high-performance processor to implement. A domestic high-performance processor is used for testing under a 10Gbps network. When the UDP sending rate reaches 300MB / s, packet loss occurs, and the bandwidth utilization rate is low. Therefore, the DDS protocol is suitable for small-bandwidth data communication. With the QoS service that comes with DDS, it can ensure the high-reliability real-time distribution of some important instructions. As mentioned above, when the data sent by the sensor reaches a certain bandwidth, it will be affected by the processor's reception of double networks and the complexity of DDS protocol parsing, and packets will be lost in the network card or operating system kernel. Summary of the invention

[0011] One of the purposes of the present invention is to provide a UDP real-time network transmission method based on FPGA, which can simultaneously meet the use requirements of large bandwidth, high reliability and real-time performance of data transmission.

[0012] To achieve the above object, the technical solution adopted by the present invention is:

[0013] A UDP real-time network transmission method based on FPGA is used for data transmission between a front-end sensing device and a back-end processor, wherein the front-end sensing device and the back-end processor are connected via FPGA, and the front-end sensing device and the FPGA are connected via two hot standby switching networks, and the two switching networks belong to different IP network segments. The UDP real-time network transmission method based on FPGA is implemented in FPGA, and comprises:

[0014] Receive network packets transmitted by two switching networks, and filter out UDP packets from front-end sensing devices;

[0015] Extract UDP payload data from UDP packets through UDP protocol unloading, and perform seamless dual-redundancy processing on UDP packets according to the packet sequence number field in the UDP payload data; the packet sequence number field is added by the front-end sensing device at a fixed offset position of the UDP payload data, and the value of the packet sequence number field is assigned in a step-by-step manner for each UDP packet sent, and the same UDP packet is sent to a hot standby two-way switching network through different IP network segments;

[0016] A plurality of UDP payload data retained after seamless dual-redundancy processing is aggregated into a data block, and the data block is stored in an external DDR cache, which is then forwarded to the back-end processor by the external DDR cache.

[0017] Several optional methods are also provided below, but they are not intended to be additional limitations on the above-mentioned overall solution, but are merely further supplements or preferences. Under the premise that there are no technical or logical contradictions, each optional method can be combined with the above-mentioned overall solution separately, and multiple optional methods can also be combined.

[0018] Preferably, the value of the packet sequence number field is assigned in a step-by-step manner for each UDP packet sent, including:

[0019] The value of the packet sequence number field is initialized to 0, and is assigned a value in the form of increment by 1 each time a UDP packet is sent.

[0020] Preferably, the data packets in the network packets, except for the UDP packets from the front-end sensing device, are directly transmitted to the back-end processor in a transparent manner after dual redundant processing.

[0021] Preferably, the forwarding from the external DDR cache to the back-end processor comprises:

[0022] The data in the external DDR cache is transmitted to the back-end processor via DMA.

[0023] Preferably, the seamless dual-redundancy processing of the UDP packet according to the packet sequence number field in the UDP payload data comprises:

[0024] Compare the value of the packet sequence number field in the UDP payload data received and parsed from the two-way switching network with the expected correct packet sequence number;

[0025] If there is only one UDP payload data whose packet sequence number field value is the same as the expected correct packet sequence number, then this UDP payload data is taken as the UDP payload data retained after seamless dual redundancy processing;

[0026] If the values ​​of the packet sequence number fields in two UDP payload data are the same as the expected correct packet sequence number, the UDP payload data with the earlier UDP packet receiving time is taken as the UDP payload data retained after seamless dual redundancy processing;

[0027] The expected correct packet sequence number is the value of the next packet sequence number field calculated based on the value of the packet sequence number field in the last UDP payload data retained after seamless dual redundancy processing according to the value assignment method of the packet sequence number field.

[0028] The FPGA-based UDP real-time network transmission method provided by the present invention adds a packet sequence number field to the UDP payload data at the front-end sensing device sending end; adds an FPGA chip to the back-end processor receiving front end to realize network preprocessing, and the functions include network packet classification and filtering, UDP protocol unloading, data seamless dual-redundancy processing, etc. After the designated UDP packet undergoes data seamless dual-redundancy processing, multiple UDP packet payload data are aggregated into a large data block, first stored in the DDR cache, and then transmitted to the processor through DMA for further analysis. In this way, on the one hand, processor interrupts are reduced through the aggregation method, and on the other hand, the packet loss caused by the multi-threaded scheduling of the processor can be effectively reduced through the DDR cache. Other network packets are directly transparently transmitted to the processor, which realizes high-reliability real-time processing of large-bandwidth data streams while being compatible with the processing capabilities of upper-layer protocols such as DDS in the original network.

[0029] The second purpose of the present invention is to provide a UDP real-time network transmission system based on FPGA, which can simultaneously meet the requirements of large bandwidth, high reliability and real-time performance of data transmission.

[0030] To achieve the above object, the technical solution adopted by the present invention is:

[0031] A UDP real-time network transmission system based on FPGA, the UDP real-time network transmission system based on FPGA includes a front-end sensing device, an FPGA and a back-end processor, the front-end sensing device and the FPGA are connected through two switching networks in hot standby, the two switching networks belong to different IP network segments, wherein:

[0032] The front-end sensing device is used to pack the collected sensing signals into UDP packets, and add a packet sequence number field at a fixed offset position of the UDP payload data. The value of the packet sequence number field is assigned in a step-by-step manner for each UDP packet sent, and the same UDP packet is sent to the hot standby two-way switching network through different IP network segments;

[0033] The FPGA is used to receive network packets transmitted by two switching networks, and filter out UDP packets from front-end sensing devices from the network packets; extract UDP payload data from UDP packets through UDP protocol unloading, and perform seamless dual-redundancy processing on UDP packets according to the packet sequence number field in the UDP payload data; aggregate multiple UDP payload data retained after seamless dual-redundancy processing into a data block, and store the data block in an external DDR cache, which is then forwarded to the back-end processor by the external DDR cache;

[0034] The back-end processor is used to receive and process the data blocks sent by the FPGA.

[0035] Preferably, the value of the packet sequence number field is assigned in a step-by-step manner for each UDP packet sent, including:

[0036] The value of the packet sequence number field is initialized to 0, and is assigned a value in the form of increment by 1 each time a UDP packet is sent.

[0037] Preferably, the data packets in the network packets, except for the UDP packets from the front-end sensing device, are directly transmitted to the back-end processor in a transparent manner after dual redundant processing.

[0038] Preferably, the forwarding from the external DDR cache to the back-end processor comprises:

[0039] The data in the external DDR cache is transmitted to the back-end processor via DMA.

[0040] Preferably, the seamless dual-redundancy processing of the UDP packet according to the packet sequence number field in the UDP payload data comprises:

[0041] Compare the value of the packet sequence number field in the UDP payload data received and parsed from the two-way switching network with the expected correct packet sequence number;

[0042] If there is only one UDP payload data whose packet sequence number field value is the same as the expected correct packet sequence number, then this UDP payload data is taken as the UDP payload data retained after seamless dual redundancy processing;

[0043] If the values ​​of the packet sequence number fields in two UDP payload data are the same as the expected correct packet sequence number, the UDP payload data with the earlier UDP packet receiving time is taken as the UDP payload data retained after seamless dual redundancy processing;

[0044] The expected correct packet sequence number is the value of the next packet sequence number field calculated based on the value of the packet sequence number field in the last UDP payload data retained after seamless dual redundancy processing according to the value assignment method of the packet sequence number field. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A schematic diagram of the connection between the front-end sensing device, FPGA and back-end processor of the present invention;

[0046] Figure 2 A schematic diagram showing the location of the packet sequence number field of the present invention;

[0047] Figure 3 The figure is a flow chart of the UDP real-time network transmission method based on FPGA of the present invention. DETAILED DESCRIPTION

[0048] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0050] In order to overcome the defects of the dual redundant network transmission technology in the prior art, this embodiment provides a UDP real-time network transmission method based on FPGA for data transmission between a front-end sensing device and a back-end processor.

[0051] In this embodiment, the front-end sensing device is used to obtain the sensing signal, such as a sensor. The back-end processor is used to analyze and process the sensing signal, such as a computer system or a signal processor. It can be applied to various practical scenarios, such as vehicle-mounted, airborne, and ship-mounted platforms.

[0052] like Figure 1 As shown, in this embodiment, the front-end sensing device and the back-end processor are connected via FPGA, and the front-end sensing device and the FPGA are connected via two switching networks in hot backup, and the two switching networks belong to different IP network segments.

[0053] The two network ports of the front-end sensing device are connected to different switching networks. The sensor packages the real-time collected and pre-processed data stream into UDP packets. In the existing dual-redundant switching network environment, in order to achieve seamless switching between the two networks, a field is added to the fixed offset position of the UDP payload data when sending. Here it is defined as the packet sequence number field. The value of the packet sequence number field is assigned in a step-by-step manner for each UDP packet sent.

[0054] In addition, the same UDP packet is sent to the two-way hot standby switching network through different IP network segments at the same time. The receiving end implements dual-port hot standby based on this field, avoiding packet loss caused by active-standby switching or sudden bit errors, effectively improving the reliability of UDP transmission and seamlessly switching between network ports. Therefore, high-reliability UDP transmission is achieved on the basis of simplified upper-layer protocols.

[0055] like Figure 2 As shown in FIG. 1 , it is a schematic diagram of the location of the packet sequence number field. In actual applications, the offset position in the UDP payload data can be customized. The value of the packet sequence number field can be assigned in a step-by-step decreasing or step-by-step increasing manner, and can be a number or an alphabetical symbol. The specific assignment form is not limited on the basis that the assignment method has a certain regularity. This embodiment adopts the most conventional assignment method, that is, the value of the packet sequence number field is initialized to 0, and the value is increased by 1 for each UDP packet sent.

[0056] It should be noted that, except for the packet sequence number field added to the UDP payload data, the rest of the structure of the UDP packet in this embodiment is consistent with the original UDP packet, so the rest of the UDP packet will not be described in detail in this embodiment.

[0057] like Figure 3 As shown, the UDP real-time network transmission method based on FPGA in this embodiment is implemented in FPGA, that is, the receiving part of the network pre-processing logic in FPGA includes the following steps:

[0058] S1. Receive network packets transmitted by two switching networks, and filter out UDP packets from front-end sensing devices.

[0059] In this embodiment, the FPGA is used as the pre-receiving and processing end of the data flow, and the two network ports are in hot standby state, each belonging to a different IP network segment, and receiving data from the two network ports at the same time. The UDP packets sent by the front-end sensing device through the two IP network segments are routed to the FPGA through their respective switching networks.

[0060] Of course, since the network segment is not necessarily dedicated to connecting to the front-end sensing device, that is, while the FPGA receives the UDP packets sent by the front-end sensing device, it may also receive other similar network packets. Therefore, this embodiment first classifies and filters the received network packets to filter out the UDP packets from the front-end sensing device.

[0061] In this embodiment, source IP, destination IP and port number are used as classification and filtering basis. In other embodiments, distinction can also be made based on setting special characters, etc. This embodiment does not impose strict restrictions.

[0062] S2. Extract UDP payload data from UDP packets through UDP protocol unloading, and perform seamless dual-redundancy processing on the UDP packets according to the packet sequence number field in the UDP payload data.

[0063] The FPGA simultaneously receives all network packets from two IP segments, and after classification and filtering, separates the UDP packet of a certain sensor and extracts the UDP payload through UDP protocol unloading. The two UDP payload data streams are processed by seamless dual redundancy to remove redundant data. The seamless dual redundancy processing logic for UDP packets in this embodiment is as follows:

[0064] The value of the packet sequence number field in the UDP payload data received and parsed from the two-way switching network is compared with the expected correct packet sequence number.

[0065] If only one path of UDP payload data has a packet sequence number field value that is the same as the expected correct packet sequence number, then this path of UDP payload data is taken as the UDP payload data retained after seamless dual redundancy processing; if two paths of UDP payload data have packet sequence number fields values ​​that are the same as the expected correct packet sequence number, then the path of UDP payload data with the earlier UDP packet reception time is taken as the UDP payload data retained after seamless dual redundancy processing.

[0066] In this embodiment, the FPGA is always in the state of receiving the UDP network packets of the two sensors, that is, in the hot standby state. When one of the two channels has a link disconnection or a sudden bit error, the other channel can still receive normally. Therefore, the next correct packet can be predicted by the incremental attribute of the packet sequence number field.

[0067] That is, this embodiment calculates the expected correct packet sequence number of the next UDP packet in advance after receiving the correct UDP packet each time, and performs seamless dual-redundancy processing based on the expected correct packet sequence number. The expected correct packet sequence number is the value of the next packet sequence number field calculated based on the value of the packet sequence number field in the UDP payload data retained after the previous seamless dual-redundancy processing according to the value assignment method of the packet sequence number field. Taking the value of the packet sequence number field plus 1 for each UDP packet sent as an example, if the value of the packet sequence number field last time is 3, the expected correct packet sequence number is 4.

[0068] After the two UDP network packets pass through their respective switching networks, the delays to reach the FPGA are different. During processing, only the payload data stream of the expected correct packet sequence number that was input first is retained. If one of the network ports suddenly loses packets and causes the packet sequence number to jump, the other network port automatically fills in the payload data stream of the next correct packet sequence number, and the two network ports switch seamlessly.

[0069] In this embodiment, data packets other than UDP packets from front-end sensing devices in network packets are directly transmitted to the back-end processor in a transparent manner after dual redundancy processing. For other types of data packets, existing conventional dual redundancy processing methods can be used, such as dual-homing technology, IuFlex technology, etc.

[0070] S3, aggregating multiple UDP payload data retained after seamless dual redundancy processing into a data block, and storing the data block in a DDR cache, which is then forwarded by the DDR cache to the back-end processor, thereby reducing processor interrupts and improving processing bandwidth.

[0071] In order to reduce the number of interruptions when the back-end processor receives UDP packets, and avoid packet loss caused by the failure to timely schedule the UDP receiving process during multi-threaded scheduling of the back-end processor, in the dual redundant preprocessing, after the redundant data is eliminated, multiple UDP payload data are aggregated into a large data block. The data block is first stored in the DDR cache and then transmitted to the back-end processor via DMA for further analysis, effectively reducing the processor load and greatly improving the overall performance.

[0072] This embodiment adopts a simpler custom UDP protocol, that is, at the sending end of the front-end sensing device, a packet sequence number field is added to the UDP payload data; an FPGA chip is added to the receiving front end of the back-end processor to implement network preprocessing, and the functions include network packet classification and filtering, UDP protocol unloading, and seamless data dual-redundancy processing. After the designated UDP packet undergoes seamless data dual-redundancy processing, multiple UDP packet payload data are aggregated into a large data block, first stored in the DDR cache, and then transmitted to the processor through DMA for further analysis. In this way, on the one hand, processor interrupts are reduced through aggregation, and on the other hand, the DDR cache can effectively reduce the packet loss caused by multi-threaded scheduling of the processor. Other network packets are directly transparently transmitted to the processor, which realizes high-reliability real-time processing of large-bandwidth data streams while being compatible with the processing capabilities of upper-layer protocols such as DDS in the original network.

[0073] After testing, this embodiment can still achieve high-reliability real-time receiving and processing by the back-end processor in equipment that requires the network data stream emitted by the sensor to have a bandwidth of more than 800MB / s Ethernet transmission bus, thus overcoming the defect that the prior art cannot simultaneously meet the requirements of large bandwidth, high reliability, and real-time performance.

[0074] In another embodiment, a UDP real-time network transmission system based on FPGA is provided, comprising a front-end sensing device, an FPGA and a back-end processor, wherein the front-end sensing device and the FPGA are connected via two switching networks in hot standby, and the two switching networks belong to different IP network segments, wherein:

[0075] The front-end sensing device is used to pack the collected sensing signals into UDP packets, and add a packet sequence number field at a fixed offset position of the UDP payload data. The value of the packet sequence number field is assigned in a step-by-step manner for each UDP packet sent, and the same UDP packet is sent to the hot standby two-way switching network through different IP network segments;

[0076] The FPGA is used to receive network packets transmitted by two switching networks, and filter out UDP packets from front-end sensing devices from the network packets; extract UDP payload data from UDP packets through UDP protocol unloading, and perform seamless dual-redundancy processing on UDP packets according to the packet sequence number field in the UDP payload data; aggregate multiple UDP payload data retained after seamless dual-redundancy processing into a data block, and store the data block in an external DDR cache, which is then forwarded to the back-end processor by the external DDR cache;

[0077] The back-end processor is used to receive and process the data blocks sent by the FPGA.

[0078] In a specific embodiment, the value of the packet sequence number field is assigned in a step-by-step manner for each UDP packet sent, including:

[0079] The value of the packet sequence number field is initialized to 0, and is assigned a value in the form of increment by 1 each time a UDP packet is sent.

[0080] In a specific embodiment, the data packets in the network packets, except for the UDP packets from the front-end sensing device, are directly transmitted to the back-end processor in a transparent manner after dual redundant processing.

[0081] In a specific embodiment, the forwarding from the external DDR cache to the back-end processor includes:

[0082] The data in the external DDR cache is transmitted to the back-end processor via DMA.

[0083] In a specific embodiment, the seamless dual-redundancy processing of the UDP packet according to the packet sequence number field in the UDP payload data includes:

[0084] Compare the value of the packet sequence number field in the UDP payload data received and parsed from the two-way switching network with the expected correct packet sequence number;

[0085] If there is only one UDP payload data whose packet sequence number field value is the same as the expected correct packet sequence number, then this UDP payload data is taken as the UDP payload data retained after seamless dual redundancy processing;

[0086] If the values ​​of the packet sequence number fields in two UDP payload data are the same as the expected correct packet sequence number, the UDP payload data with the earlier UDP packet receiving time is taken as the UDP payload data retained after seamless dual redundancy processing;

[0087] The expected correct packet sequence number is the value of the next packet sequence number field calculated based on the value of the packet sequence number field in the last UDP payload data retained after seamless dual redundancy processing according to the value assignment method of the packet sequence number field.

[0088] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0089] The above-mentioned embodiments only express several implementation modes of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the invention. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the attached claims.

Claims

1. A UDP real-time network transmission method based on FPGA, used for data transmission between a front-end sensing device and a back-end processor, characterized in that: The front-end sensing device is connected to the back-end processor via an FPGA, and the front-end sensing device is connected to the FPGA via two hot standby switching networks, the two switching networks belong to different IP network segments, and the FPGA-based UDP real-time network transmission method is implemented in the FPGA, including: Receive network packets transmitted by two switching networks, and filter out UDP packets from front-end sensing devices; UDP payload data is extracted from UDP packets through the UDP protocol, and seamless dual-redundancy processing is performed on the UDP packets according to the packet sequence number field in the UDP payload data; the packet sequence number field is added by the front-end sensing device at a fixed offset position of the UDP payload data, and the value of the packet sequence number field is assigned in a step-by-step manner for each UDP packet sent, and the same UDP packet is sent to the hot standby two-way switching network through different IP network segments; Aggregate multiple UDP payload data retained after seamless dual-redundancy processing into a data block, store the data block in an external DDR cache, and then forward it to the back-end processor by the external DDR cache. The data packets in the network packets, except for the UDP packets from the front-end sensing device, are directly transmitted to the back-end processor in a transparent manner after dual-redundancy processing; wherein, forwarding from the external DDR cache to the back-end processor includes: transmitting the data in the external DDR cache to the back-end processor by DMA; The step of performing seamless dual-redundancy processing on the UDP packet according to the packet sequence number field in the UDP payload data includes: Compare the value of the packet sequence number field in the UDP payload data received and parsed from the two-way switching network with the expected correct packet sequence number; If there is only one UDP payload data whose packet sequence number field value is the same as the expected correct packet sequence number, then this UDP payload data is taken as the UDP payload data retained after seamless dual redundancy processing; If the values ​​of the packet sequence number fields in two UDP payload data are the same as the expected correct packet sequence number, the UDP payload data with the earlier UDP packet receiving time is taken as the UDP payload data retained after seamless dual redundancy processing; The expected correct packet sequence number is the value of the next packet sequence number field calculated based on the value of the packet sequence number field in the last UDP payload data retained after seamless dual redundancy processing according to the value assignment method of the packet sequence number field.

2. The UDP real-time network transmission method based on FPGA as claimed in claim 1, characterized in that: The value of the packet sequence number field is assigned in a step-by-step manner for each UDP packet sent, including: The value of the packet sequence number field is initialized to 0, and is assigned a value in the form of increment by 1 each time a UDP packet is sent.

3. A UDP real-time network transmission system based on FPGA, characterized in that: The FPGA-based UDP real-time network transmission system includes a front-end sensing device, an FPGA, and a back-end processor. The front-end sensing device and the FPGA are connected via two hot-backup switching networks, and the two switching networks belong to different IP network segments, wherein: The front-end sensing device is used to pack the collected sensing signals into UDP packets, and add a packet sequence number field at a fixed offset position of the UDP payload data. The value of the packet sequence number field is assigned in a step-by-step manner for each UDP packet sent, and the same UDP packet is sent to the hot standby two-way switching network through different IP network segments; The FPGA is used to receive network packets transmitted by two-way switching networks, and filter out UDP packets from front-end sensing devices from the network packets; extract UDP payload data from the UDP packets through the UDP protocol, and perform seamless dual-redundancy processing on the UDP packets according to the packet sequence number field in the UDP payload data; aggregate multiple UDP payload data retained after seamless dual-redundancy processing into a data block, and store the data block in an external DDR cache, which is then forwarded to the back-end processor by the external DDR cache; data packets in the network packets except the UDP packets from the front-end sensing devices are directly transmitted to the back-end processor in a transparent transmission manner after dual-redundancy processing; wherein, forwarding from the external DDR cache to the back-end processor includes: transmitting the data in the external DDR cache to the back-end processor in a DMA manner; The back-end processor is used to receive and process the data blocks sent by the FPGA; The step of performing seamless dual-redundancy processing on the UDP packet according to the packet sequence number field in the UDP payload data includes: Compare the value of the packet sequence number field in the UDP payload data received and parsed from the two-way switching network with the expected correct packet sequence number; If there is only one UDP payload data whose packet sequence number field value is the same as the expected correct packet sequence number, then this UDP payload data is taken as the UDP payload data retained after seamless dual redundancy processing; If the values ​​of the packet sequence number fields in two UDP payload data are the same as the expected correct packet sequence number, the UDP payload data with the earlier UDP packet receiving time is taken as the UDP payload data retained after seamless dual redundancy processing; The expected correct packet sequence number is the value of the next packet sequence number field calculated based on the value of the packet sequence number field in the last UDP payload data retained after seamless dual redundancy processing according to the value assignment method of the packet sequence number field.

4. The UDP real-time network transmission system based on FPGA as claimed in claim 3, characterized in that: The value of the packet sequence number field is assigned in a step-by-step manner for each UDP packet sent, including: The value of the packet sequence number field is initialized to 0, and is assigned a value in the form of increment by 1 each time a UDP packet is sent.

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