Display panel and display device

Abstract

A display panel (10) and a display device (40), wherein the display panel (10) comprises a substrate (101) and sub-pixels (100) on the substrate, wherein each sub-pixel (100) comprises a light-emitting element (120) and a pixel circuit for driving the light-emitting element. The pixel circuit comprises a data writing sub-circuit (111), a storage sub-circuit (113), a driving sub-circuit (112), and a shunt noise reduction sub-circuit (114), wherein the data writing sub-circuit (111) is configured to transmit a data signal (Vd) to a first end of the storage sub-circuit (113) in response to a control signal, wherein the driving sub-circuit (112) comprises a control electrode (150), a first electrode (151), and a second electrode (152), wherein the control electrode (150) of the driving sub-circuit (112) is coupled to the storage sub-circuit (113), and the driving sub-circuit (114) is configured to transmit a data signal (Vd) to a first end of the storage sub-circuit (113) in response to a control signal. The first electrode (151) of (112) is configured to receive a first power supply voltage (VDD), the second electrode (152) of the driving subcircuit (112) is coupled to the first electrode (121) of the light-emitting element (120), the driving subcircuit (112) is configured to drive the light-emitting element (120) to emit light in response to the voltage of the control electrode (150), the shunt noise reduction subcircuit (114) includes a noise reduction transistor (N4), and the gate (N4G) and the first electrode (N4D) of the noise reduction transistor (N4) are both coupled to the same electrode of the driving subcircuit (112).

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Micro OLED displays involve the combination of organic light-emitting diode (OLED) technology and CMOS technology, and are related to the cross-integration of the optoelectronics industry and the microelectronics industry. They have promoted the development of a new generation of micro-display technology and also advanced the research and development of organic electronics on silicon and even molecular electronics on silicon.

[0003] Micro OLED displays have excellent display characteristics, such as high resolution, high brightness, rich colors, low driving voltage, fast response speed, low power consumption, etc., and have broad development prospects.

[0004] Public Content

[0005] Some embodiments of the present disclosure provide a display panel, the display panel comprising a substrate and sub-pixels on the substrate, wherein the pixel circuit comprises a data writing sub-circuit, a storage sub-circuit, a driving sub-circuit, and a first sub-circuit:

[0006] The data writing sub-circuit is configured to transmit a data signal to the first terminal of the storage sub-circuit in response to a control signal,

[0007] The driving subcircuit comprises a control electrode, a first electrode and a second electrode, the control electrode of the driving subcircuit is coupled to the storage subcircuit, the first electrode of the driving subcircuit is configured to receive a first power supply voltage, the second electrode of the driving subcircuit is coupled to the first electrode of the light-emitting element, and the driving subcircuit is configured to drive the light-emitting element to emit light in response to the voltage of the control electrode,

[0008] The first sub-circuit includes a first transistor, and a gate and a first electrode of the first transistor are coupled to the same electrode of the driving sub-circuit.

[0009] In some embodiments, the first transistor is a noise reduction transistor, and the driving circuit further includes a bias transistor, the noise reduction transistor and the bias transistor are connected in series, and the noise reduction transistor and the bias transistor each include a gate, a first electrode, and a second electrode, the gate and the first electrode of the noise reduction transistor are both coupled to the second electrode of the driving subcircuit, the second electrode of the noise reduction transistor is coupled to the first electrode of the bias transistor, the gate of the bias transistor receives a bias voltage, and the second electrode of the bias transistor receives a predetermined voltage.

[0010] In some embodiments, the pixel circuit also includes a resistor, which is connected in series between the second electrode of the driving subcircuit and the first electrode of the light-emitting element, the resistor is in the same layer as the control electrode of the driving subcircuit and is separately arranged, and the resistivity of the resistor is higher than the resistivity of the control electrode of the driving subcircuit.

[0011] In some embodiments, the data writing subcircuit includes a transmission gate circuit, the transmission gate circuit includes a first data writing transistor and a second data writing transistor, the first data writing transistor and the second data writing transistor each include a gate, a first electrode and a second electrode, the control signal includes a first control signal and a second control signal,

[0012] The gate of the first data write transistor is configured to receive the first control signal, the gate of the second data write transistor is configured to receive the second control signal, the first electrode of the first data write transistor and the first electrode of the second data write transistor are coupled, and both are coupled to the first end of the storage sub-circuit and the control electrode of the driving sub-circuit, the second electrode of the first data write transistor and the second electrode of the second data write transistor are coupled, and both are configured to receive the data signal.

[0013] In some embodiments, the driving subcircuit includes a driving transistor, and a gate, a first electrode, and a second electrode of the driving transistor serve as a control electrode, a first electrode, and a second electrode of the driving subcircuit, respectively.

[0014] In some embodiments, the first data writing transistor, the driving transistor, the noise reduction transistor and the bias transistor are all N-type metal-oxide semiconductor field effect transistors, and the second data writing transistor is a P-type metal-oxide semiconductor field effect transistor.

[0015] In some embodiments, the resistor and the gate of the noise reduction transistor are disposed in the same layer and are an integral structure.

[0016] In some embodiments, the storage subcircuit includes a storage capacitor, and the storage capacitor includes a first capacitor electrode and a second capacitor electrode, the first capacitor electrode and the second capacitor electrode serve as the first end and the second end of the storage subcircuit respectively; the first capacitor electrode and the resistor are insulated and arranged in the same layer.

[0017] In some embodiments, in a first direction parallel to the substrate, the transmission gate circuit is located on one side of the storage capacitor, and the driving transistor, the noise reduction transistor, the bias transistor and the resistor are located on the other side of the storage capacitor.

[0018] In some embodiments, in a second direction parallel to the substrate and perpendicular to the first direction, the second data writing transistor and the first data writing transistor are arranged in sequence, and the driving transistor, the noise reduction transistor and the bias transistor are arranged in sequence.

[0019] In some embodiments, in the first direction, the resistor is located between a combination of the driving transistor, the noise reduction transistor, and the bias transistor and the storage capacitor.

[0020] In some embodiments, the resistor includes a plurality of first sub-segments along a first direction and a plurality of second sub-segments along a second direction, and the plurality of first sub-segments and the plurality of second sub-segments are connected end to end to form a meandering structure.

[0021] In some embodiments, a shortest distance between the drive transistor and the first data write transistor is greater than a shortest distance between the drive transistor and the second data write transistor.

[0022] In some embodiments, a shortest distance between the bias transistor and the first data write transistor is smaller than a shortest distance between the bias transistor and the second data write transistor.

[0023] In some embodiments, the width of the resistor is smaller than a width of any one of the gate of the first data write transistor, the gate of the second data write transistor, the gate of the drive transistor, the gate of the noise reduction transistor, and the gate of the bias transistor.

[0024] In some embodiments, the gate of the first data writing transistor, the gate of the second data writing transistor, the gate of the driving transistor, the gate of the noise reduction transistor, the gate of the bias transistor, the first capacitor electrode and the resistor are arranged in the same layer.

[0025] In some embodiments, the second data write transistor and the first data write transistor are arranged side by side along the second direction and are symmetrical about a symmetry axis along the first direction.

[0026] In some embodiments, the second electrode of the driving transistor and the first electrode of the noise reduction transistor are arranged in the same layer and are an integral structure, and / or the second electrode of the noise reduction transistor and the first electrode of the bias transistor are arranged in the same layer and are an integral structure.

[0027] In some embodiments, the display panel includes four sub-pixels, and the four sub-pixels constitute a pixel unit group, wherein the four sub-pixels are arranged in an array along a first direction and a second direction, the first direction is perpendicular to the second direction, and the second data writing transistors of the four sub-pixels are located in the same N-type well region in the base substrate in their orthographic projection on the base substrate.

[0028] In some embodiments, resistors of adjacent sub-pixels in the first direction are symmetric about an axis of symmetry along the second direction, and resistors of adjacent sub-pixels in the second direction are symmetric about the axis of symmetry along the first direction.

[0029] In some embodiments, the transfer gate circuits of two adjacent sub-pixels in the first direction are symmetrical about the symmetry axis along the second direction, and the transfer gate circuits of two adjacent sub-pixels in the second direction are symmetrical about the symmetry axis along the first direction.

[0030] In some embodiments, driving transistors of two adjacent sub-pixels in the first direction are symmetrical about the symmetry axis along the second direction, and driving transistors of two adjacent sub-pixels in the second direction are symmetrical about the symmetry axis along the first direction.

[0031] In some embodiments, the noise reduction transistors of two adjacent sub-pixels in the first direction are symmetrical about the symmetry axis along the second direction, and the noise reduction transistors of two adjacent sub-pixels in the second direction are symmetrical about the symmetry axis along the first direction.

[0032] In some embodiments, bias transistors of two adjacent sub-pixels in the first direction are symmetrical about an axis of symmetry along the second direction, and bias transistors of two adjacent sub-pixels in the second direction are symmetrical about an axis of symmetry along the first direction.

[0033] In some embodiments, first capacitor electrodes of adjacent sub-pixels in the first direction are symmetrical about an axis of symmetry along the second direction, and first capacitor electrodes of adjacent sub-pixels in the second direction are symmetrical about an axis of symmetry along the first direction.

[0034] In some embodiments, the orthographic projection of the first capacitor electrodes in the four sub-pixels on the substrate is located outside the N-type well region and is disposed around the N-type well region.

[0035] In some embodiments, the pixel circuit further includes an isolation structure, wherein the isolation structure is coupled to the second electrode of the bias transistor, and the isolation structure is used to receive the preset voltage.

[0036] In some embodiments, an orthographic projection of at least one of the resistor, the driving transistor, the bias transistor, and the noise reduction transistor on the substrate is surrounded by an orthographic projection of the isolation structure on the substrate.

[0037] In some embodiments, the isolation structure is coupled to the first conductive layer through a plurality of vias, and a distribution density of the vias on a side of the isolation structure close to the noise reduction transistor is greater than a distribution density of the vias on a side of the isolation structure close to the storage capacitor.

[0038] In some embodiments, the isolation structure is an open-loop structure having an opening, and the first pole of the driving electrode tube is located at the opening.

[0039] In some embodiments, the width of the bias transistor gate is greater than the width of the drive transistor gate.

[0040] In some embodiments, the closest distance between the gate of the noise reduction transistor and the isolation structure is greater than the closest distance between the gate of the driving transistor and the isolation structure.

[0041] In some embodiments, a total length of the resistor is greater than a total length of the isolation structure.

[0042] Some embodiments of the present disclosure provide a display device, comprising the display panel described in the aforementioned embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Other features, objects and advantages of the present disclosure will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0044] Figure 1 is a block diagram of a display panel provided in some embodiments of the present disclosure;

[0045] Figure 2A A schematic diagram of a pixel circuit provided for some embodiments of the present disclosure;

[0046] Figure 2B A schematic diagram of a pixel circuit provided for some embodiments of the present disclosure;

[0047] Figure 3A A schematic diagram of a display panel provided for some embodiments of the present disclosure;

[0048] Figure 3B for Figure 3A A cross-sectional view along section line II';

[0049] Figure 4A A schematic diagram of a display panel provided for some embodiments of the present disclosure;

[0050] Figure 4B for Figure 4A Schematic diagram of a sub-pixel in;

[0051] Figure 5A-Figure 5I Shows Figure 4A The manufacturing steps of the display panel are shown;

[0052] Figures 6A-6C A schematic diagram of a first conductive layer of a display panel provided in some embodiments of the present disclosure;

[0053] Figure 7A-7B A schematic diagram of a second conductive layer of a display panel provided in some embodiments of the present disclosure;

[0054] Figures 8A-8B A schematic diagram of a third conductive layer of a display panel provided in some embodiments of the present disclosure;

[0055] Figures 9A-9B A schematic diagram of a fourth conductive layer of a display panel provided in some embodiments of the present disclosure;

[0056] Fig.10 A schematic diagram of a display device provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0057] The present disclosure is further described in detail below in conjunction with the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.

[0058] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0059] In addition, in the following detailed description, for the purpose of explanation, numerous specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details.

[0060] It should be understood that, although the terms first, second, etc. can be used here to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the exemplary embodiment, the first element can be named as the second element, and similarly, the second element can be named as the first element. The term "and / or" as used herein includes any combination and all combinations of one or more related listed items.

[0061] It should be understood that when an element or layer is referred to as being "formed on" another element or layer, the element or layer may be formed directly or indirectly on the other element or layer. That is, for example, there may be an intermediate element or intermediate layer. Conversely, when an element or layer is referred to as being "formed directly on" another element or layer, there are no intermediate elements or intermediate layers. Other words used to describe the relationship between elements or layers (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.) should be interpreted in a similar manner.

[0062] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the embodiments. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. It will also be understood that when the terms "comprise" and / or "include" are used herein, the description indicates the presence of the features, integral bodies, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integral bodies, steps, operations, elements, components and / or combinations thereof.

[0063] In this document, unless otherwise specified, the expressions “located on the same layer” or “arranged on the same layer” generally mean that the first component and the second component can be made of the same material and can be formed by the same patterning process. The expressions “located on different layers” or “arranged on different layers” generally mean that the first component and the second component are formed by different patterning processes.

[0064] In this document, unless otherwise specified, "coupling" of a first component and a second component means that there is a physical connection between the first component and the second component, so that there is interaction of signals, such as electrical signals, magnetic signals, etc., between the two. The specific implementation method may include direct electrical connection, and may also include connection through other electronic components.

[0065] In the field of OLED (Organic Light-Emitting Diode) display, with the rapid development of high-resolution products, higher requirements are put forward for the structural design of display panels, such as the arrangement of pixels and signal lines. For example, compared with an OLED display device with a resolution of 4K, a large-size OLED display device with a resolution of 8K has a doubling of the number of sub-pixel units that need to be set, and the pixel density increases accordingly. On the one hand, the line width of the signal line also becomes smaller, resulting in an increase in the resistance of the signal line itself; on the other hand, the overlap between the signal lines increases, resulting in an increase in the parasitic capacitance of the signal line, which leads to an increase in the resistance and capacitance load of the signal line. Correspondingly, the signal delay (RC delay) caused by the resistance and capacitance load, as well as the voltage drop (IR drop), voltage rise (IR rise) and other phenomena will also become serious. These phenomena will seriously affect the display quality of the display product.

[0066] Micro OLED displays typically have a size of less than 100 microns, such as less than 50 microns, etc., and involve the combination of organic light emitting diode (OLED) technology and CMOS technology, where an OLED array is prepared on a silicon-based substrate including a CMOS circuit.

[0067] Micro OLEDs are widely used in AR and VR fields. As technology continues to develop, higher resolutions are required, which puts higher demands on the structural design of display panels, such as the arrangement of pixels and signal lines.

[0068] The display panel provided by at least one embodiment of the present disclosure can achieve a sub-pixel area of ​​5.45um×13.6um through optimized layout and wiring design processing in the design, achieve high resolution (PPI) and optimized arrangement of the pixel circuit array, and have a good display effect.

[0069] Figure 1 is a block diagram of a display panel provided by some embodiments of the present disclosure. Figure 1 As shown, the display panel 10 includes a plurality of sub-pixels 100 distributed in an array, a plurality of scan lines 11, and a plurality of data lines 12. Each sub-pixel 100 includes a light-emitting element and a pixel circuit for driving the light-emitting element. The plurality of scan lines 11 and the plurality of data lines 12 cross each other to define a plurality of pixel areas distributed in an array in the display area, and a pixel circuit of a sub-pixel 100 is arranged in each pixel area.

[0070] like Figure 1 As shown, the display panel may further include a gate driving subcircuit 13 and a data driving subcircuit 14 located in the non-display area. The gate driving subcircuit 13 is connected to the pixel circuit through the scan line 11 to provide various control signals, such as a scan signal, and the data driving subcircuit 14 is connected to the pixel circuit through the data line 12 to provide a data signal. Figure 1 The positional relationship between the gate driving sub-circuit 13 and the data driving sub-circuit 14, the scanning lines 11 and the data lines 12 in the display panel is only an example, and the actual arrangement positions can be designed as needed.

[0071] In some embodiments, the display panel 10 may further include a control circuit. For example, the control circuit is configured to control the data drive subcircuit 14 to apply the data signal, and control the gate drive subcircuit to apply the scan signal. An example of the control circuit is a timing control circuit (T-con). The control circuit may be in various forms, for example, including a processor and a memory, the memory including an executable code, and the processor runs the executable code to execute the above-mentioned detection method.

[0072] For example, the processor may be a central processing unit (CPU) or other forms of processing devices having data processing capabilities and / or instruction execution capabilities, such as a microprocessor, a programmable logic controller (PLC), etc.

[0073] For example, the storage device may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor may execute the desired functions of the program instructions. Various applications and various data may also be stored in the computer-readable storage medium.

[0074] The pixel circuit may include a driving subcircuit, a data writing subcircuit, a storage subcircuit, and a shunt noise reduction subcircuit as needed, and may also include a compensation subcircuit, a light emitting control subcircuit, a reset circuit, etc. as needed.

[0075] Figure 2A Schematic diagram of a pixel circuit provided by some embodiments of the present disclosure. Figure 2A As shown, the pixel circuit includes a data writing sub-circuit 111 , a driving sub-circuit 112 , a storage sub-circuit 113 and a current shunting and noise reduction sub-circuit 114 .

[0076] The output end of the data writing sub-circuit 111 is electrically connected to the first end of the storage sub-circuit 113, and is configured to transmit the data signal Vd to the first end of the storage sub-circuit 113 in response to the control signal (including the first control signal SEL and the second control signal SEL_B). The second end of the storage sub-circuit 113 is configured to be electrically connected to the ground voltage GND, for example.

[0077] The driving subcircuit 112 includes a control electrode (control terminal) 150, a first electrode (first terminal) 151, and a second electrode (second terminal) 152. The control electrode 150 of the driving subcircuit is electrically connected to the first terminal of the storage subcircuit 113. The first electrode 151 of the driving subcircuit 112 is configured to receive a first power supply voltage VDD. The second electrode 152 of the driving subcircuit 112 is electrically connected to the first electrode 121 of the light-emitting element 120 at a first node S. The driving subcircuit 112 is configured to drive the light-emitting element 120 to emit light in response to the voltage at the first terminal of the storage subcircuit 113. The second electrode 122 of the light-emitting element 120 is, for example, configured to receive a second power supply voltage VSS. In some embodiments, the first power supply voltage VDD is, for example, a high voltage, and the second power supply voltage VSS is, for example, a low voltage.

[0078] The shunt noise reduction subcircuit 114 includes a control terminal, a first terminal, and a second terminal. Specifically, the control terminal of the shunt noise reduction subcircuit 114 receives a bias signal Vb, the first terminal of the shunt noise reduction subcircuit 114 is electrically connected to the first node S, and the second terminal of the shunt noise reduction subcircuit 114 receives a ground voltage GND. For example, the bias signal Vb is a constant voltage signal, also called a bias voltage Vb, for example, 0.8V-1V; the shunt noise reduction subcircuit 114 is configured to provide a constant current under the action of the bias signal Vb to achieve a shunt effect, so that the circuit passing through the branch where the light-emitting element is located is smaller, so that the voltage applied to the light-emitting element 120 is in a linear relationship with the data signal, which helps to achieve fine control of the grayscale, thereby improving the display effect. In addition, the shunt noise reduction subcircuit 114 can also reduce the voltage fluctuation at the first node S caused by the voltage noise of the bias signal Vb, which will be further explained in conjunction with a specific circuit later.

[0079] like Figure 2A As shown, the pixel circuit also includes a resistor 130, a first end 131 of the resistor 130 is electrically connected to the second electrode 152 of the driving subcircuit 112 and the first node S, and a second end 132 is electrically connected to the first electrode 121 of the light-emitting element 120, that is, the second electrode 152 of the driving subcircuit 112 is electrically connected to the first electrode 121 of the light-emitting element 120 through the resistor 130.

[0080] For example, the resistor 130 is a constant resistor or a variable resistor, or may be an equivalent resistor formed by other devices (such as a transistor).

[0081] For example, the resistor 130 is insulated from the control electrode 150 of the driving sub-circuit 112 in the same layer, and the resistivity of the resistor is higher than the resistivity of the control electrode of the driving sub-circuit, that is, the conductivity of the control electrode of the driving sub-circuit is higher than the conductivity of the resistor. For example, the resistivity of the resistor is more than ten times the resistivity of the control electrode.

[0082] In the embodiments of the present disclosure, at least one of the data writing subcircuit 111, the driving subcircuit 112, the storage subcircuit 113, and the shunt noise reduction subcircuit 114 is implemented by a transistor, and the transistors used can all be thin film transistors or field effect transistors or other switching devices with the same characteristics. In the embodiments of the present disclosure, metal-oxide semiconductor field effect transistors are used as examples for illustration. The source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be indistinguishable in structure. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor except the gate, one of the poles is directly described as the first pole and the other pole is the second pole, for example, the drain is used as the first pole and the source is used as the second pole. In addition, transistors can be divided into N-type and P-type transistors according to the characteristics of the transistor. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (for example, 0V, -5V, 30-10V or other suitable voltages).

[0083] The display panel provided by the embodiments of the present disclosure may adopt a rigid substrate, such as a glass substrate, a silicon substrate, etc., or may be formed of a flexible material with excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), triacetyl cellulose (TAC), cycloolefin polymer (COP) and cycloolefin copolymer (COC), etc. The embodiments of the present disclosure are all described by taking a silicon substrate as an example, that is, the pixel structure is prepared on a silicon substrate, however, the embodiments of the present disclosure are not limited to this.

[0084] In one embodiment, the pixel circuit includes a complementary metal oxide semiconductor circuit (CMOS circuit), that is, the pixel circuit is prepared on a single crystal silicon substrate. Relying on mature CMOS integrated circuit technology, silicon-based processes can achieve higher precision (for example, PPI can reach 6500 or even more than 10,000).

[0085] In some embodiments of the present disclosure, the data writing subcircuit 111 may include a transmission gate circuit composed of two complementary transistors connected in parallel; the control signal includes two control signals in opposite phases. The data writing subcircuit 111 adopts a transmission gate structure circuit to help transmit the data signal to the first end of the storage subcircuit 113 without loss. Specifically, the data writing subcircuit includes a first control electrode, a second control electrode, a first end, such as a signal input end, and a second end, such as a signal output end. The first control electrode and the second control electrode of the data writing subcircuit are respectively configured to receive a first control signal and a second control signal. The first end of the data writing subcircuit is configured to receive a data signal. The second end of the data writing subcircuit is electrically connected to the first end of the storage subcircuit, and is configured to transmit the data signal to the first end of the storage subcircuit in response to the first control signal and the second control signal.

[0086] Figure 2B for Figure 2A FIG. 1 is a circuit diagram of a specific implementation example of a pixel circuit. Figure 2B As shown, the data writing sub-circuit 111 includes a transmission gate circuit, and the data writing sub-circuit 111 includes a first data writing transistor N1 and a second data writing transistor P1 connected in parallel with each other. The first data writing transistor N1 and the second data writing transistor P1 are respectively an N-type metal-oxide semiconductor field effect transistor (NMOS) and a P-type metal-oxide semiconductor field effect transistor (PMOS). The control signal includes a first control signal SEL and a second control signal SEL_B that are inverse to each other. The gate N1G of the first data writing transistor N1 serves as a first control electrode of the data writing sub-circuit 111 and is configured to receive the first control signal SEL. The gate P1G of the second data writing transistor P1 serves as a second control electrode of the data writing sub-circuit and is configured to receive the second control signal SEL_B. The first electrode P1D of the first data write transistor P1 and the first electrode N1D of the first data write transistor N1 are electrically connected as the first end of the data write sub-circuit and are configured to receive the data signal Vd; the second electrode P1S of the second data write transistor P1 and the second electrode N1S of the first data write transistor N1 are electrically connected as the second end of the data write sub-circuit and are electrically connected to the control electrode 150 of the driving sub-circuit 112.

[0087] In some embodiments, the first data writing transistor N1 and the second data writing transistor P1 are of the same size and have the same channel width-to-length ratio.

[0088] The data writing subcircuit 111 utilizes the complementary electrical characteristics of transistors and has a lower on-resistance regardless of transmitting a high level or a low level, thereby having the advantage of electrical signal transmission integrity and being able to transmit the data signal Vd to the first end of the storage subcircuit 113 without loss.

[0089] like Figure 2B As shown, the driving subcircuit 112 includes a driving transistor N2, for example, the driving transistor N2 is an N-type metal-oxide semiconductor field effect transistor (NMOS). The gate N2G, the first electrode N2D and the second electrode N2S of the driving transistor N2 serve as the control electrode, the first electrode and the second electrode of the driving subcircuit 112 respectively. Specifically, the gate N2G of the driving transistor N2 is electrically connected to the second end of the data writing subcircuit 111 and the first end of the storage subcircuit 113, the first electrode N2D of the driving transistor N2 receives the first power supply voltage VDD, and the second end N2S of the driving transistor N2 is connected to the first electrode 121 of the light-emitting element 120.

[0090] like Figure 2B As shown, the storage subcircuit includes a storage transistor N3, for example, an N-type metal-oxide semiconductor field effect transistor (NMOS), the storage transistor N3 includes a gate N3G, a first electrode N3D, a second electrode N3S and an active area located between the first electrode and the second electrode, the storage transistor N3 serves as a storage capacitor Cst, the gate N3G of the storage transistor N3 serves as a first capacitor electrode 141 of the storage capacitor, the first electrode N3D and the second electrode N3S of the storage transistor are electrically connected, the first electrode, the second electrode and the active area of ​​the storage transistor N3 serve together as a second capacitor electrode 142 of the storage capacitor, the first electrode, the active area and the second electrode of the storage transistor N3 serve as a first region, a second region and a third region of the second capacitor electrode 142 respectively, the first region and the second region have the same carrier mobility, and the second region has a different carrier mobility from the first region and the third region. The first capacitor electrode 141 and the second capacitor electrode 142 serve as the first end and the second end of the storage subcircuit 113 respectively. For details, please refer to Figure 2C , Figure 2C for Figure 2B , in which the storage transistor N3 is directly shown in the form of a storage capacitor Cst.

[0091] The storage transistor N3, the first data write transistor N1, and the drive transistor N2 are all N-type metal-oxide semiconductor field effect transistors (NMOS) and can be formed using the same process. As a result, the storage capacitor Cst can be formed simultaneously when the first data write transistor N1 and the drive transistor N2 are formed, avoiding the introduction of other electrode layers to form the storage capacitor, thereby reducing the process difficulty and saving costs.

[0092] like Figure 2B and 2C As shown, the pixel circuit further includes a resistor 130, a first end 131 of the resistor 130 and a second electrode 152 of the driving sub-circuit 112 are electrically connected to a first node S, and a second end 132 is electrically connected to a first electrode 121 of the light-emitting element 120, that is, the second electrode 152 of the driving sub-circuit 112 is electrically connected to the first electrode 121 of the light-emitting element 120 through the resistor 130. By providing the resistor R, defects such as dark lines on the display panel caused by a short circuit between the first electrode 121 and the second electrode 122 of the light-emitting element 120 in the sub-pixel due to process fluctuations can be avoided.

[0093] For example, the resistor 130 includes a resistor R, which is a constant resistor or a variable resistor, or may be an equivalent resistor formed by other devices (such as a transistor).

[0094] For example, the resistor 130 is insulated from the control electrode 150 of the driving sub-circuit 112, that is, the gate N2G of the driving transistor N2, and the resistivity of the resistor 130 is higher than the resistivity of the control electrode of the driving sub-circuit, that is, the conductivity of the control electrode of the driving sub-circuit is higher than the conductivity of the resistor. For example, the resistivity of the resistor is more than ten times the resistivity of the control electrode.

[0095] In some embodiments, the resistor 130 includes a resistor R. For example, a PN junction is formed between the second electrode 152 of the driving subcircuit 112 and the substrate, and the resistance value of the resistor 130 is configured such that when the driving transistor N2 operates in a saturation region, that is, when the pixel circuit operates to drive the light-emitting element 120 to emit light, the PN junction is turned off. In this case, even if a short circuit occurs between the two electrodes of the light-emitting element 120, due to the voltage drop on the resistor 130, the potential of the second electrode 152 can be protected, thereby avoiding the occurrence of circuit failure.

[0096] It should be noted that the "same-layer arrangement" referred to in the present disclosure refers to a structure formed by two (or more) structures being formed by the same deposition process and patterned by the same composition process, and their materials may be the same or different. For example, the materials of the precursors forming the multiple structures arranged in the same layer are the same, and the materials finally formed may be the same or different. The "integrated structure" in the present disclosure refers to a structure formed by two (or more) structures being formed by the same deposition process and patterned by the same composition process to be connected to each other, and their materials may be the same or different.

[0097] Through this arrangement, the driving sub-circuit control electrode and the resistor can be formed in the same patterning process, thereby saving process.

[0098] In some embodiments, the resistor and the control electrode of the driving subcircuit are both made of polysilicon material, and the doping concentration of the resistor is lower than the doping concentration of the control electrode, so the resistor has a higher resistivity than the control electrode. For example, the resistor can be intrinsic polysilicon or lightly doped polysilicon, and the control electrode is heavily doped polysilicon.

[0099] In other embodiments, the materials of the control electrode and the resistor may be different. For example, the materials of the control electrode and the resistor may include a metal and a metal oxide corresponding to the metal, respectively. For example, the metal may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloy materials formed by combinations of the above metals.

[0100] In some embodiments, Figure 2B and 2C As shown, the light-emitting element 120 is specifically implemented as an organic light-emitting diode (OLED). For example, the light-emitting element 120 can be an OLED with a top emission structure, which can emit red light, green light, blue light or white light, etc. For example, the light-emitting element 120 is a micro OLED (Micro OLED). The embodiments of the present disclosure do not limit the specific structure of the light-emitting element. For example, the first electrode 121 of the light-emitting element 120 is the anode of the OLED, and the second electrode 122 is the cathode of the OLED, that is, the pixel circuit is a common cathode structure. However, the embodiments of the present disclosure are not limited to this, and according to the change of the circuit structure, the pixel circuit can also be a common anode structure.

[0101] In some embodiments, Figure 2B and 2C As shown, the shunt noise reduction sub-circuit 114 includes a noise reduction transistor N4 and a bias transistor N5 connected in series, the noise reduction transistor N4 includes a gate N4G, a first electrode N4D and a second electrode N4S, and the bias transistor N5 includes a gate N5G, a first electrode N5D and a second electrode N5S. The gate N4G and the first electrode N4D of the noise reduction transistor N4 are both electrically connected to the second electrode N2S of the driving transistor N2, and they are electrically connected to the first node S, the second electrode N5S of the noise reduction transistor N4 is electrically connected to the first electrode N5D of the bias transistor N5, the gate N5G of the bias transistor N5 receives the bias voltage Vb, and the second electrode N5S of the bias transistor N5 is grounded, that is, receives the ground voltage GND. The gate N5G of the bias transistor N5 serves as the control terminal of the shunt noise reduction sub-circuit 114 , the noise reduction transistor N4 includes a gate N4G and a first electrode N4D which together serve as the first terminal of the shunt noise reduction sub-circuit 114 , and the second electrode N5S of the bias transistor N5 serves as the second terminal of the shunt noise reduction sub-circuit 114 .

[0102] like Figure 2Band 2C As shown, the bias transistor N5 and the noise reduction transistor N4 are connected in series as a shunt circuit, which can shunt the large current generated by the driving transistor N2 when working in the saturation region, and avoid excessive current flowing through the light-emitting element 120, resulting in damage to the light-emitting element 120. At the same time, when the high and low grayscales of the sub-pixel are converted, the anode of the light-emitting element 120 can be initialized to avoid residual high potential thereon, thereby ensuring display quality. The gate N4G and the first electrode N4D of the noise reduction transistor N4 are electrically connected to the first node S. The noise reduction transistor N4 is equivalent to a diode in the shunt circuit, which avoids or reduces the voltage fluctuation at the second electrode N2S of the driving transistor N2 caused by the voltage noise of the bias voltage Vb.

[0103] like Figure 2B and 2C As shown, the gate N4G and the first electrode N4D of the noise reduction transistor N4 are both electrically connected to the first node S, that is, the noise reduction transistor N4 is arranged on the branch connected to the second electrode N2S of the driving transistor N2. In other embodiments, the noise reduction transistor N4 can also be arranged on the branch connected to the gate N2G of the driving transistor N2 or the branch connected to the first electrode N2D of the driving transistor N2, to play the role of noise reduction and voltage stabilization, which will not be repeated here.

[0104] It should be noted that in the description of the embodiments of the present disclosure, the symbol Vd can represent both the data signal terminal and the level of the data signal. Similarly, the symbol SEL can represent both the first control signal and the first control signal terminal, and the symbol SEL_B can represent both the second control signal and the second control signal terminal. The symbol GND can represent both the ground voltage and the ground terminal; the symbol VDD can represent both the first power supply voltage terminal and the first power supply voltage, the symbol VSS can represent both the second power supply voltage terminal and the second power supply voltage, and Vb can represent both the bias signal terminal and the level of the bias signal, that is, the bias voltage.

[0105] Figure 2D Shows Figure 2B The signal timing diagram of the pixel circuit shown below will be combined with Figure 2B The signal timing diagram shown is for Figure 2D For example, the first data writing transistor and the driving transistor are N-type transistors, and the second data writing transistor is a P-type transistor, but the embodiment of the present disclosure does not limit this.

[0106] Figure 2D The waveform diagram of each signal in two consecutive display periods T1 and T2 is shown. For example, the data signal Vd is a high grayscale voltage in the display period T1 and a low grayscale voltage in the display period T2.

[0107] For example, Figure 2D As shown, the display process of each frame of image includes a data writing stage 1 and a light emitting stage 2. A working process of the pixel circuit includes: in the data writing stage 1, the first control signal SEL and the second control signal SEL_B are both on signals, the first data writing transistor N1 and the second data writing transistor P1 are turned on, and the data signal Vd is transmitted to the gate of the driving transistor N2 through the first data writing transistor N1 and / or the second data writing transistor P1; in the light emitting stage 2, the first control signal SEL and the second control signal SEL_B are both off signals, due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains unchanged, the driving transistor N2 works in a saturated state and the current remains unchanged, and drives the light emitting element 120 to emit light. When the pixel circuit enters the display period T1 to the display period T2, the data signal Vd changes from a high grayscale voltage to a low grayscale voltage, and the bias transistor N3 generates a stable drain current under the control of the second common voltage Vcom2, and the drain current can quickly discharge the charge stored in the anode of the OLED when the display grayscale of the OLED needs to change rapidly. For example, the discharge process occurs when data is written 1 in display cycle T2, so in light emitting phase 2 of display cycle T2, the voltage of the OLED anode drops rapidly, thereby achieving a better dynamic contrast and improving the display effect.

[0108] For example, in the light-emitting stage, the light-emitting current of the light-emitting element OLED when writing grayscale data is in the nanoampere level (for example, several nanoamperes), and the bias transistor N5 operates in the saturation region under the control of the bias signal, that is, the bias voltage Vb, and the generated current is in the microampere level (for example, 1 microampere). Therefore, almost all the current flowing through the driving transistor N2 flows into the bias transistor N5. At this time, the voltage at the first node S is linearly related to the data signal (data voltage) Vd.

[0109] For example, the bias transistor N5 operates in the saturation region under the control of the bias signal Vb, and the voltage difference between the gate and the source of the bias transistor N5 is Vb-GND, which is a constant value. At this time, the current flowing through the bias transistor N3 is a constant current, so the bias transistor N5 can be regarded as a current source.

[0110] For example, when the first node S is electrically connected to the light-emitting element 120 through the resistor 130, since the current flowing through the light-emitting element 120 is extremely small, the voltage of the first node S can be approximately equal to the voltage of the first electrode 121 of the light-emitting element 120; that is, the voltage of the first electrode 121 of the light-emitting element 120 is linearly related to the data signal (data voltage) Vd, thereby achieving fine control of the grayscale and improving the display effect.

[0111] In some embodiments, the first control signal SEL and the second control signal SEL_B are differential complementary signals with the same amplitude and opposite phases. This helps to improve the anti-interference performance of the circuit. For example, the first control signal SEL and the second control signal SEL_B can be output by the same gate drive circuit unit (such as a GOA unit), thereby simplifying the circuit.

[0112] For example, Figure 1 As shown, the display panel 10 may further include a data driving circuit 13 and a scanning driving circuit 14. The data driving circuit 13 is configured to send a data signal, such as the above-mentioned data signal Vd, according to needs (such as an image signal input to the display device). The scanning driving circuit 14 is configured to output various scanning signals, such as the above-mentioned first control signal SEL and the second control signal SEL_B, which is, for example, an integrated circuit chip (IC) or a gate driving circuit (GOA) directly prepared on the display panel.

[0113] In some embodiments, the display panel uses a silicon substrate as the base substrate 101, and the pixel circuit, the data driving circuit 13 and the scanning driving circuit 14 can be integrated on the silicon substrate. In this case, since silicon-based circuits can achieve higher precision, the data driving circuit 13 and the scanning driving circuit 14 can also be formed in a region corresponding to the display region of the display panel, and are not necessarily located in the non-display region.

[0114] In some embodiments, the display panel 10 further includes a control circuit. For example, the control circuit is configured to control the data driving circuit 13 to apply the data signal Vd, and control the gate driving circuit 13 to apply various scanning signals. An example of the control circuit is a timing control circuit (T-con). The control circuit can be in various forms, for example, including a processor and a memory, the memory including an executable code, and the processor runs the executable code to execute the above-mentioned detection method.

[0115] In some embodiments, the processor may be a central processing unit (CPU) or other forms of processing devices having data processing capabilities and / or instruction execution capabilities, such as a microprocessor, a programmable logic controller (PLC), etc.

[0116] In some embodiments, the storage device may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on a computer-readable storage medium, and a processor may run the desired functions of the program instructions. Various applications and various data may also be stored in the computer-readable storage medium, such as electrical characteristic parameters obtained in the above-mentioned detection method, etc.

[0117] The following adopts Figure 2B and Figure 2C The pixel circuit shown is taken as an example to exemplarily illustrate the display panel provided by at least one embodiment of the present disclosure, but the embodiments of the present disclosure are not limited thereto.

[0118] Figure 3A Schematic diagram of a display panel provided by some embodiments of the present disclosure. Figure 3A As shown, the display panel 10 includes a base substrate 101, and a plurality of sub-pixels 100 are located on the base substrate 101. The plurality of sub-pixels 100 are arranged in a sub-pixel array, the column direction of the sub-pixel array is a first direction D1, the row direction is a second direction D2, and the first direction D1 intersects with the second direction D2, for example, they are perpendicular to each other. Figure 3A exemplarily shows four rows and six columns of sub-pixels, that is, four pixel rows and six pixel columns.

[0119] For example, the base substrate 101 may be a rigid substrate, such as a glass substrate, a silicon substrate, etc., or may be formed of a flexible material having excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene terephthalate (PET), polyethylene (PE), 5 polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), triacetyl cellulose (TAC), cycloolefin polymer (COP) and cycloolefin copolymer (COC), etc. The embodiments of the present disclosure are all described by taking the base substrate 101 as a silicon substrate as an example, but the embodiments of the present disclosure are not limited thereto.

[0120] For example, the substrate 101 includes single crystal silicon or high purity silicon. The pixel circuit is formed on the substrate 101 by a CMOS semiconductor process. For example, an active region (including a channel region of the transistor), a first electrode and a second electrode of the transistor are formed in the substrate 101 by a doping process, and each insulating layer is formed by a silicon oxidation process or a chemical vapor deposition process (CVD), and multiple conductive layers are formed by a sputtering process to form a wiring structure. The active region of each transistor is located inside the substrate 101.

[0121] Figure 3B Shows Figure 3A A cross-sectional view along section line II'. For clarity, Figure 3B Some traces or electrode structures that have no direct connection relationship are omitted.

[0122] For example, Figure 3B As shown, the display panel 10 includes a base substrate 101, a first insulating layer 201, a polysilicon layer 102, a second insulating layer 202, a first conductive layer 301, a third insulating layer 203, a second conductive layer 302, a fourth insulating layer 204, a third conductive layer 303, a fifth insulating layer 205 and a fourth conductive layer 304, which are sequentially located on the base substrate 101. The structure of the display panel 10 will be described in layers as follows. Figure 3B It will be used as a reference and explained together.

[0123] For the sake of clarity and ease of explanation, Figure 4A The portion of the display panel 10 below the first conductive layer 301 is shown, namely, the base substrate 101 and the first insulating layer 201, the polysilicon layer 102 and the second insulating layer 202 thereon, including transistors (P1, N1, N2, N4, N5), a storage capacitor Cst (i.e., a storage transistor N3) and a resistor 130; Figure 4B Shows Figure 4A A sub-pixel 100, for example Figure 4A Schematic diagram of the enlarged sub-pixel in the lower left of the figure; for clarity, Figure 4A It also shows the corresponding Figure 3A Center section line I-I'.

[0124] like Figure 4BAs shown, for example, in a direction parallel to the surface of the substrate 101, the transmission gate circuit including the first data writing transistor N1 and the second data writing transistor P1 and the driving transistor N2 are located on opposite sides of the storage capacitor Cst, for example, on opposite sides of the storage capacitor Cst in the first direction D1. The driving transistor N2, the noise reduction transistor N4, the bias transistor N5 and the resistor 130 are located on the same side of the storage capacitor Cst. Specifically, the first data writing transistor N1 and the second data writing transistor P1 are located on one side of the storage capacitor Cst, for example Figure 4B The drive transistor N2, the noise reduction transistor N4, the bias transistor N5 and the resistor 130 are located on the other side of the storage capacitor Cst. Figure 4B The lower side of the storage capacitor Cst.

[0125] In some embodiments, the storage transistor N3 serves as a storage capacitor Cst, and the storage transistor N3 includes a gate N3G, a first electrode N3D, a second electrode N3S, and an active area N3a located between the first electrode and the second electrode. The gate N3G of the storage transistor N3 serves as a first capacitor electrode 141 of the storage capacitor Cst, and the first electrode N3D and the second electrode N3S of the storage transistor N3 are electrically connected. The first electrode, the second electrode, and the active area N3a of the storage transistor N3 serve together as a second capacitor electrode 142 of the storage capacitor. Specifically, the first electrode N3D, the active area N3a, and the second electrode N3S of the storage transistor N3 serve as a first region, a second region, and a third region of the second capacitor electrode 142, respectively. The first region and the second region have the same carrier mobility, and the second region has a different carrier mobility from the first region and the third region. Figure 4B As shown, the first region, the second region and the third region of the second capacitor electrode 142 are arranged in sequence along the short side direction of the sub-pixel, i.e., the second direction D2, the first region and the second region have the same carrier mobility, the second region has a different carrier mobility from the first region and the third region, and the area of ​​the second region is larger than that of the first region and the third region.

[0126] The material of the active region N3a of the storage transistor N3 is a semiconductor material. In some embodiments, the substrate 101 is a P-type silicon-based substrate, and the material of the substrate 101 is, for example, P-type monocrystalline silicon. The active region N3a of the storage transistor N3 is formed by performing N-type light doping on the P-type silicon-based substrate. The N-type doping process can be, for example, an ion implantation process, and the doping element can be, for example, boron. When a voltage is applied to the first capacitor electrode 141, the active region N3a of the storage transistor N3 becomes a conductor, so that the first electrode N3D, the second electrode N3S and the active region N3a of the storage transistor N3 form a conductor structure, which serves as the second capacitor electrode 142 of the storage capacitor Cst.

[0127] In some embodiments, Figure 4B As shown, in the first direction D1 parallel to the substrate, the resistor 130 and the driving transistor N2 are located on the same side of the storage capacitor Cst. Figure 2B and 2C It can be seen that the second electrode N2S of the driving transistor N2 is connected to the first electrode 121 of the light emitting device 120, such as an anode, through the resistor 130. Therefore, the resistor 130 and the driving transistor N2 are located on the same side of the storage capacitor Cst, so that the distance between the resistor R and the driving transistor N2, especially the distance between the first end 131 of the resistor 130 and the second electrode N2S of the driving transistor N2 can be minimized, thereby reducing the size of the wiring connecting the first end of the resistor R and the second electrode N2S of the driving transistor N2.

[0128] In some embodiments, Figure 4B As shown, in the second direction D2, the driving transistor N2, the noise reduction transistor N4 and the bias transistor N5 are arranged in sequence. The second electrode N2S of the driving transistor N2 and the first electrode N4D of the noise reduction transistor N4 are an integrated structure, and the second electrode N4S of the noise reduction transistor N4 and the first electrode N5D of the bias transistor N5 are an integrated structure.

[0129] In some embodiments, the resistor 130 is connected between the combination of the driving transistor N2, the noise reduction transistor N4 and the bias transistor N5 and the storage capacitor Cst. The resistor 130 includes a plurality of first sub-segments along the first direction and a plurality of second sub-segments along the second direction, and the plurality of first sub-segments and the plurality of second sub-segments are connected end to end to form a bent structure. The resistor 130 configured in this way has a longer length, which ensures that the resistor 130 has a larger resistance value. A contact hole area described later is provided at the first end 131 and the second end 132 of the resistor 130. Specifically, a contact hole area is provided at the first end 131 of the resistor 130, which is used to be electrically connected to the first node S, that is, to be electrically connected to the second electrode N2S of the driving transistor N2 and the first electrode N4D of the noise reduction transistor N4. In some embodiments, as Figure 4B As shown, the first end 131 of the resistor 130 is integrated with the gate N4G of the noise reduction transistor N4. A contact hole region is provided at the second end 132 of the resistor 130 for electrically connecting with the first electrode 121 of the light emitting element 120.

[0130] In some embodiments, Figure 4BAs shown, the transmission gate circuit includes a first data writing transistor N1 and a second data writing transistor P1, and the second data writing transistor P1 and the first data writing transistor N1 are arranged side by side in the second direction D2, and are symmetrical about the symmetry axis along the first direction D1. Specifically, the gate N1G of the first data writing transistor N1 and the gate P1G of the second data writing transistor P1 are arranged side by side in the second direction D2, and are symmetrical about the symmetry axis along the first direction D1; the first electrode N1D of the first data writing transistor N1 and the first electrode P1D of the second data writing transistor P1 are arranged side by side in the second direction D2, and are symmetrical about the symmetry axis along the first direction D1; the second electrode N1S of the first data writing transistor N1 and the second electrode P1S of the second data writing transistor P1 are arranged side by side in the second direction D2, and are symmetrical about the symmetry axis along the first direction D1, and the active area N1a of the first data writing transistor N1 and the active area P1a of the second data writing transistor P1 are arranged side by side in the second direction D2, and are symmetrical about the symmetry axis along the first direction D1.

[0131] In some embodiments, the first capacitor electrode 141 of the storage capacitor Cst, that is, the gate N3G of the storage transistor N3, the gates of the transistors P1, N2, N3, N4 and N5 are all arranged in the same layer as the resistor 130, and all include polysilicon material; the polysilicon material is doped to form the first capacitor electrode 141 of the storage capacitor Cst, the gates of the transistors and the resistor 130. The doping concentration of the first capacitor electrode 141 of the storage capacitor Cst and the gates of the transistors is higher than the doping concentration of the resistor 130. The conductivity of the resistor 130 is lower than the conductivity of the first capacitor electrode 141 of the storage capacitor Cst and the gates of the transistors, that is, the resistivity of the resistor 130 is higher than the resistivity of the first capacitor electrode 141 of the storage capacitor Cst and the gates of the transistors. In some embodiments, the main body of the resistor 130 connected between the first end 131 and the second end 132 thereof may not be doped or the doping concentration may be low.

[0132] In some embodiments, Figure 4B As shown, the shortest distance between the driving transistor N2 and the first data writing transistor N1 is greater than the shortest distance between the driving transistor N2 and the second data writing transistor P1.

[0133] In some embodiments, Figure 4B As shown, the shortest distance between the bias transistor N5 and the first data writing transistor N1 is smaller than the shortest distance between the bias transistor N5 and the second data writing transistor P1.

[0134] In this article, the shortest distance between two components refers to the shortest distance between any point on one component and any point on the other component.

[0135] In some embodiments, Figure 4B As shown, the width of the resistor 130 is smaller than the width of any one of the gate N1G of the first data write transistor N1, the gate P1G of the second data write transistor P1, the gate N2G of the driving transistor N2, the gate N4G of the noise reduction transistor N4, and the gate N5G of the bias transistor N5, wherein the gate N1G of the first data write transistor N1, the gate P1G of the second data write transistor P1, the gate N2G of the driving transistor N2, and the gate N4G of the noise reduction transistor N4 extend along the first direction D1.

[0136] In some embodiments, the gates P1G, N1G, N2G, and N3G of each transistor P1, N1-N3 are all disposed in the same layer, all comprise polysilicon material, and are formed using the same doping process. Figure 4B As shown, the gate N4G of the noise reduction transistor N4 and the first end 131 of the resistor 130 are connected to each other as an integral structure.

[0137] In some embodiments, Figure 4B As shown, the sub-pixel includes a first area 401 and a second area 402, wherein the second area 402 is an N-type well area formed by N-type heavy doping in a P-type substrate 101, and the first area 401 is the remaining area of ​​the sub-pixel 100 after removing the N-type well area. The second data writing transistor P2 is formed in the second area 402. The first data writing transistor N1, the driving transistor N2, the storage capacitor Cst, the noise reduction transistor N4, the bias transistor N5 and the resistor 130 are all formed in the first area 401.

[0138] In some embodiments, Figure 4B The active areas P1a, N1a, N2a, N3a, N4a, and N5a of each transistor P1, N1-N5 are also shown. The active areas N1a, N2a, N3a, N4a, and N5a of the first data writing transistor N1, the driving transistor N2, the storage transistor N3, the noise reduction transistor N4, and the bias transistor N5 are all formed on the P-type substrate 101 using an N-type lightly doped process, and they can be formed simultaneously using the same doping process. The active area P1a of the second data writing transistor P1 is formed in the second area 402 using a P-type lightly doped process.

[0139] like Figure 4B As shown, the area of ​​the active area N2a of the driving transistor N2 is larger than the area of ​​the active area N1a of the first data writing transistor N1 and the active area P1a of the second data writing transistor P1, and a larger width-to-length ratio can be obtained, which helps to improve the driving capability of the driving transistor N2 and thus improve the display effect.

[0140] like Figure 4B As shown, the active area N3a of the storage transistor N3 is significantly larger than the active areas of other transistors, so that when the storage transistor N3 is used as the storage capacitor Cst, the capacitance value of the storage capacitor of the sub-pixel can be guaranteed to ensure the display effect.

[0141] In some embodiments, the first poles P1D, N1D, N2D, N3D, N4D, N5D and the second poles P1S, N1S, N2S, N3S, N4S, N5S of each transistor P1, N1-N5 are formed by performing a heavy doping process on a portion of the corresponding active region, for example, using the corresponding gate formed subsequently as a mask to perform the doping process. Specifically, the first poles N1D, N2D, N3D, N4D, N5D and the second poles N1S, N2S, N3S, N4S, N5S of the first data write transistor N1, the drive transistor N2, the storage transistor N3, the noise reduction transistor N4, and the bias transistor N5 are all formed in the first region 401 using an N-type heavy doping process, and they can be formed simultaneously using the same doping process. The first pole P1D and the second pole P1S of the second data write transistor P1 are formed in the second region 402 using a P-type heavy doping process.

[0142] Figure 4B Also shown are connection vias in the second insulating layer 202 for electrically connecting various components in the first metal layer to be formed subsequently with contact regions of various transistors and other components.

[0143] like Figure 4B As shown, for transistors with larger active areas, such as the driving transistor N2, since there is sufficient space, at least two contact areas can be set at the first electrode thereof to be electrically connected to the components in the subsequently formed first metal layer through two vias, so that sufficient contact can be obtained with the structure to be connected and a parallel structure can be formed, thereby reducing the contact resistance.

[0144] In some embodiments, Figure 4B Contact hole regions 411, 400a, and 400b are also shown. Among them, the contact hole region 411 is located in the second region 402, and is configured to be electrically connected to the first power supply voltage VDD, and to perform a high voltage bias on the N-type substrate where the second data write transistor P1 is located. The contact hole regions 400a and 400b are located in the first region 401, and in the first direction D1, they are respectively located on both sides of the storage capacitor Cst. The contact hole regions 400a and 400b are both configured to be electrically connected to the ground voltage GND, and to perform a low voltage bias on the P-type substrate where the transistors N1-N5 are located. The contact hole regions 400a and 400b are formed by a P-type heavy doping process, and can be formed synchronously with the first and second poles of the P-type transistor. The contact hole region 411 is formed by an N-type heavy doping process, and can be formed synchronously with the first and second poles of the N-type transistor.

[0145] In some embodiments, Figure 4B As shown, the contact hole region 400a basically has a structure surrounding the combination of the driving transistor N2, the noise reduction transistor N4, the bias transistor N5 and the resistor 130, and is used to separate the combination of the driving transistor N2, the noise reduction transistor N4, the bias transistor N5 and the resistor 130 from the storage capacitor Cst.

[0146] Specifically, in some embodiments, the contact hole region 400a is an isolation structure, also referred to as an isolation structure 400a, which is coupled to the second electrode N5S of the bias transistor N5. The orthographic projection of at least one of the resistor 130, the driving transistor N2, the bias transistor N5, and the noise reduction transistor N4 on the substrate 101 is surrounded by the orthographic projection of the isolation structure 400a on the substrate 101.

[0147] In some embodiments, in combination Figure 4B and subsequent Figure 6C The isolation structure 400a is coupled to the first conductive layer 301 through a plurality of vias. If space permits, more vias are drilled to connect a more stable ground voltage GND to the isolation structure (contact hole area) 400a, so that the storage capacitor Cst and the resistor 130 have good electrical isolation effects, and adjacent sub-pixels also have good electrical isolation effects. The vias described here include Figure 6C The vias 228a, 228c, 228e, and 227b have a distribution density on the side of the isolation structure 400a close to the noise reduction transistor N4 that is greater than a distribution density on the side of the isolation structure 400a close to the storage capacitor Cst.

[0148] In some embodiments, Figure 4B As shown, the isolation structure 400a is an open-loop structure with an opening, and the first electrode N2D of the driving electrode tube N2 is located at the opening. Specifically, the isolation structure 400a is a substantially rectangular open-loop structure.

[0149] In some embodiments, Figure 4B As shown, the width of the gate N5G of the bias transistor N5 is greater than the width of the gate N2G of the driving transistor N2.

[0150] In some embodiments, Figure 4B As shown, the closest distance between the gate N4G of the noise reduction transistor N4 and the isolation structure 400a is greater than the closest distance between the gate N2G of the driving transistor N2 and the isolation structure 400a, thereby better reducing noise.

[0151] In some embodiments, Figure 4B As shown, the total length of the resistor 130 is greater than the total length of the isolation structure 400 a.

[0152] Combined with reference Figure 4A , two sub-pixels 100 adjacent in the first direction D1 are symmetrical about the symmetry axis along the second direction D2, and two sub-pixels 100 adjacent in the second direction D2 are symmetrical about the symmetry axis along the first direction D1. Specifically, the distribution of each transistor (for example, including the shape and size of each transistor) and the storage capacitor and resistor in the two sub-pixels 100 adjacent in the first direction D1 is symmetrical about the symmetry axis along the second direction D2, that is, the corresponding structures in the two sub-pixels are symmetrical about the symmetry axis along the second direction D2. The distribution of transistors and the storage capacitor and resistor in the two sub-pixels 100 adjacent in the second direction D2 is symmetrical about the symmetry axis along the first direction D1.

[0153] This symmetrical arrangement can maximize the uniformity of process errors, thereby improving the uniformity of the display panel. In addition, this symmetrical arrangement allows some structures in the substrate that are arranged in the same layer and can be connected to each other to be formed as one piece, which can make the pixel layout more compact and improve the space utilization compared to separate arrangements, thereby improving the resolution of the display panel.

[0154] In some embodiments, Figure 4A As shown, the second regions 402 of two adjacent sub-pixels 100 in the first direction D1 are an integrated structure, and the second regions 402 of two adjacent sub-pixels 100 in the second direction D2 are an integrated structure, that is, the second regions of the four adjacent sub-pixels 100 form an N-type well region 402N. The second data writing transistors P1 of the four adjacent sub-pixels 100 are located in the same N-type well region 402N. The four adjacent sub-pixels 100 constitute a pixel group 420. Compared with setting an independent N-type well region for each sub-pixel, this setting can make the arrangement of pixels more compact while meeting the design rules, which helps to improve the resolution of the display panel.

[0155] In some embodiments, Figure 4A As shown, the four adjacent sub-pixels 100 share the same contact hole area 411, and the contact hole area 411 is located in the middle of the N-type well area 402N of the pixel group 420, forming an axisymmetric pattern, which is symmetrical relative to the symmetry axis along the first direction D1 and the symmetry axis along the second direction D2.

[0156] In some embodiments, Figure 4A and 4BAs shown, in the same pixel group 420, the active areas P1a of the second data writing transistors P1 of two adjacent sub-pixels in the first direction D1 are connected to each other as an integrated structure, and the second data writing transistors P1 of the two adjacent sub-pixels share a second electrode P1S.

[0157] In some embodiments, Figure 4A and 4B As shown, in the same pixel group 420, the active regions N1a of the first data writing transistors N1 of two adjacent sub-pixels in the first direction D1 are connected to each other as an integrated structure, and the first data writing transistors N1 of the two adjacent sub-pixels share a second electrode N1S.

[0158] like Figure 4A As shown, for two adjacent sub-pixels 100 in the second direction D2, when their driving transistors N2 are adjacent, the two adjacent sub-pixels are located in the same pixel group 420, the first electrodes N2D of the two driving transistors N2 are connected to each other as an integral structure, and the two driving transistors N2 share the first electrode N2D. This arrangement can make the arrangement of pixels more compact while meeting the design rules, which helps to improve the resolution of the display panel.

[0159] like Figure 4A As shown, for two adjacent sub-pixels 100 in the second direction D2, if the two sub-pixels are located in the same pixel group 420, the storage transistors N3 of the two adjacent sub-pixels share the first electrode N3D; if the two sub-pixels are located in different pixel groups 420, the storage transistors N3 of the two adjacent sub-pixels share the second electrode N3S. This arrangement can make the arrangement of pixels more compact while meeting the design rules, which helps to improve the resolution of the display panel.

[0160] like Figure 4A As shown, for two adjacent sub-pixels 100 in the second direction D2, the contact hole regions 400a of the two sub-pixels are an integrated structure. For two adjacent sub-pixels 100 in the first direction D1, when the two sub-pixels are located in different pixel groups 420, the contact hole regions 400a of the two sub-pixels are an integrated structure.

[0161] Figure 5A-Figure 5I Shows Figure 4A The formation process of the substrate structure shown in FIG. Figure 4A As shown, the display panel includes a plurality of pixel unit groups 420 arranged along a first direction D1 and a second direction D2.

[0162] The following combination Figures 5A-5H The formation process of the display panel provided in the embodiment of the present disclosure is exemplarily described, but this is not intended to limit the present disclosure.

[0163] For example, a silicon-based substrate 101 is provided, for example, its material is P-type single crystal silicon. N-type transistors (such as driving transistors) can be directly manufactured on the P-type silicon substrate, that is, the channel region of the N-type transistor is directly doped on the P-type substrate, which is conducive to giving full play to the high-speed advantage of NMOS devices and improving circuit performance.

[0164] Figure 5A FIG. 4 shows an N-type well region formed on a substrate. Figure 5A As shown, in some embodiments, N-type heavy doping is performed on a P-type silicon substrate to form an N-type well region 402N, including the second region 402 of the sub-pixel, to serve as a substrate for the second data writing transistor P1.

[0165] In some embodiments, the second regions 402 of two adjacent sub-pixels in the first direction D1 may be connected to each other, and the second regions 402 of two adjacent sub-pixels in the second direction D2 may be connected to each other. For example, the second regions 402 of four sub-pixels in a pixel group 420 are connected as an integrated structure to form an N-type well region 402N of the pixel group 420. Figure 5A 2 shows an N-type well region of a pixel group of two rows and three columns (corresponding to sub-pixels of four rows and six columns). In some embodiments, when performing N-type doping to form the N-type well region, an undoped region on the substrate 101 is shielded.

[0166] Figure 5B shows the active area pattern on the substrate substrate, Figure 5C The following figure shows Figure 5A An active area pattern is formed on the substrate structure shown. The active area pattern can be obtained by lightly doping the substrate. Specifically, in the N-type well region, an active area pattern of the second data write transistor P1 is formed in the N-type well region by lightly doping with P-type, which is configured to subsequently form a first electrode P1D, a second electrode P1S and an active area P1a used as a channel of the second data write transistor P1. Outside the N-type crystal well region, active area patterns of the first data write transistor N1, the drive transistor N2, the storage transistor N3, the noise reduction transistor N4 and the bias transistor N5 are formed by N-type light doping. The active area patterns of the first data write transistor N1, the drive transistor N2, the storage transistor N3, the noise reduction transistor N4 and the bias transistor N5 are respectively configured to form the first poles N1D, N2D, N3D, N4D, N5D, the second poles N1S, N2S, N3S, N4D, N5D of the first data write transistor N1, the drive transistor N2, the storage transistor N3, the noise reduction transistor N4 and the bias transistor N5, and the active areas N1a, N2a, N3a, N4a, N5a used as channels.

[0167] During the doping process, N-type doping and P-type doping need to be performed separately. When performing the N-type doping process, a barrier layer needs to be formed to shield the area where the N-type doping is not performed; when performing the P-type doping process, a barrier layer needs to be formed to shield the area where the P-type doping is not performed.

[0168] Figure 5D shows the polysilicon layer pattern on the substrate substrate, Figure 5E The following figure shows Figure 5C A polysilicon layer pattern is formed on the substrate structure.

[0169] Combination Figure 3B , Figure 4B and Figure 5E As shown, in some embodiments, a first insulating layer 201 is formed on the substrate 101, and then a polysilicon layer 102 is formed on the first insulating layer 201. It can be understood by those skilled in the art that in order to clearly indicate the relationship between the film layers, Figure 4B and Figure 5E The transparent first insulating layer 201 is omitted. In some embodiments, the pattern of the first insulating layer 201 coincides with the pattern of the polysilicon layer 102.

[0170] The first insulating layer 201 includes a gate insulating layer of each transistor and a dielectric layer 104 of the storage capacitor Cst. The polysilicon layer 102 is configured to form a first capacitor electrode 141, i.e., a gate N3G of the storage transistor N3, a resistor 130, and gates P1G, N1G, N2G, N4G, N5G of each transistor (P1, N1, N2, N4, N5).

[0171] like Figure 4B and 5E As shown, the gate P1G of the second data writing transistor P1 is located in the second region 402. The gate N1G of the first data writing transistor N1, the gate N2G of the driving transistor N2, the gate N4G of the noise reduction transistor N4, the gate N5G of the bias transistor N5, the first capacitor electrode 141 and the resistor 130 are formed on the first region 401 outside the N-type well region 402N.

[0172] In some embodiments, Figure 4B and 5E As shown, the orthographic projection of the first capacitor electrode 141 of the four sub-pixels in each pixel unit group on the substrate is located outside the N-type well region formed by the second regions 402 of the four sub-pixels, and surrounds the N-type well region. For example, the N-type well region is substantially rectangular, and the orthographic projection of the first capacitor electrode 141 of each sub-pixel on the substrate surrounds one corner of the rectangle.

[0173] like Figure 4B and 5EAs shown, the pattern of the polysilicon layer in two adjacent sub-pixels in the first direction D1 is symmetrical about the symmetry axis along the second direction D2; the pattern of the polysilicon layer in two adjacent sub-pixels in the second direction D2 is symmetrical about the symmetry axis along the first direction D1, that is, the pattern of the polysilicon layer is a symmetrical pattern. In some embodiments, as Figure 4B and 5E As shown, the resistors of the adjacent sub-pixels in the first direction are symmetrical about the symmetry axis along the second direction, and the resistors of the adjacent sub-pixels in the second direction are symmetrical about the symmetry axis along the first direction. In some embodiments, the first capacitor electrodes of the adjacent sub-pixels in the first direction are symmetrical about the symmetry axis along the second direction, and the first capacitor electrodes of the adjacent sub-pixels in the second direction are symmetrical about the symmetry axis along the first direction.

[0174] In some embodiments, the gates of the first data writing transistor N1 and the second data writing transistor P1 of two adjacent sub-pixels in the second direction D2 are respectively symmetrical about a symmetry axis along the first direction D1 .

[0175] In some embodiments, the gates of the first data writing transistor N1 and the second data writing transistor P1 of two adjacent sub-pixels in the first direction D1 are respectively symmetrical about a symmetry axis along the second direction D2 .

[0176] In some embodiments, the first insulating layer 201 is formed on the substrate by thermal oxidation. For example, the material of the first insulating layer is silicon nitride, oxide or oxynitride.

[0177] For example, a polysilicon material layer is formed on the first insulating layer by a chemical vapor deposition (PVD) process, and then a photolithography process is performed on the polysilicon material layer to form the polysilicon layer 102 .

[0178] Fig. 5F The N-type heavily doped window region of the substrate is shown. Figure 5G The P-type heavily doped window region of the substrate is shown. Figure 5H shows the shielding pattern of the resistor when N-type heavy doping is performed, Fig.5I Shown in Figure 5E The schematic diagram of the substrate structure after the substrate structure is completed with N-type heavy doping and P-type heavy doping is shown in FIG. Figure 5HThe dotted box shows the shielding pattern of the resistor. In some embodiments, an N-type heavily doped window region is used to perform N-type heavy doping and a P-type heavily doped window region is used to perform P-type heavy doping on the substrate substrate formed with the polysilicon layer 102 to form a contact hole region for electrical connection. For example, the doped window region includes the source region and the drain region of each transistor, thereby forming a first electrode of each transistor, such as a drain electrode and a second electrode, such as a source electrode. In some embodiments, the doped window region also includes each contact hole region of the substrate and the contact hole region of the resistor 130, such as Figure 4B The contact hole regions 400a, 400b, and 411 are shown. In some embodiments, since the gate of the transistor is formed of polysilicon material, the polysilicon gate also needs to be doped. When doping, a blocking layer can be formed as needed to block the non-doped area and only expose the corresponding doped window area.

[0179] It should be noted that Fig. 5F and Figure 5G Only the doping window regions are illustrated, and in the actual doping process, corresponding barrier layers / mask layers are provided to expose the corresponding doping window regions and polysilicon regions for doping. For example, the barrier layer / mask layer may be made of photoresist or oxide material.

[0180] In some embodiments, when N-type heavy doping is performed, Fig.5I and 5H As shown, a barrier layer 135, i.e., a shielding pattern, is formed corresponding to the resistor 130. In order to ensure the resistance value of the resistor 130, the resistor 130 needs to be shielded during the N-type doping process to prevent the resistor 130 from being damaged by doping. The barrier layer 135 shields the main body of the resistor 130, exposing only the contact hole areas at both ends of the resistor 130.

[0181] In some embodiments, the barrier layer 135 may be silicon nitride, oxide or oxynitride, or may be a photoresist material. After the doping process is completed, the barrier layer 135 may be retained in the display panel or removed.

[0182] In some embodiments, the barrier layer 135 of the resistor 130 may also be formed together with the barrier layer / mask layer of other regions during doping, which is not limited in the embodiments of the present disclosure.

[0183] In some embodiments, during the doping process, N-type heavy doping and P-type heavy doping need to be performed separately, for example, to form the source region and drain region of an N-type transistor and the source region and drain region of a P-type transistor. When performing the N-type heavy doping process, a barrier layer can be formed to block the area where the N-type heavy doping is not performed; when performing the P-type heavy doping process, a barrier layer can be formed to block the area where the P-type heavy doping is not performed.

[0184] In some embodiments, the control Figure 4B The gate, the first pole, and the second pole of the transistors N1-N5, and the contact hole region 411 can be formed by the N-type heavy doping process. The N-type doping process can be, for example, an ion implantation process, and the doping element can be, for example, boron. The gate, the first pole, and the second pole of the transistor P1, and the contact hole regions 400a and 400b can be formed by the P-type heavy doping process. The P-type doping process can be, for example, an ion implantation process, and the doping element can be, for example, phosphorus.

[0185] In the above-mentioned doping process, for example, by using an ion implantation process, the polysilicon pattern can act as a mask, so that the ion implantation into the silicon-based substrate happens to occur on both sides of the polysilicon, thereby forming the first and second poles of each transistor, and achieving self-alignment. In addition, the polysilicon, which originally has a high resistance, has a lower resistivity after the doping process, and can form the gate of each transistor and the first capacitor electrode. Therefore, using polysilicon material as a resistor and gate material has many beneficial effects and saves process costs.

[0186] In this way, it is formed Figure 4A The structure of the display panel shown includes transistors P1, N1, N2, N4, N5, a resistor 130, and a storage capacitor Cst.

[0187] In some embodiments, the corresponding transistors, resistors and storage capacitors Cst in two adjacent sub-pixels in the first direction D1 are symmetrical about the axis of symmetry along the second direction D2; the corresponding transistors, resistors and storage capacitors Cst in two adjacent sub-pixels in the second direction D2 are symmetrical about the axis of symmetry along the first direction D1.

[0188] It should be noted that, in the present embodiment, the storage capacitor Cst is a storage transistor T3 used as a capacitor. Specifically, the gate T3G of the storage transistor N3 serves as the first capacitor electrode 141, and the first electrode N3D, the second electrode N3S and the active area N3a therebetween of the storage transistor N3 serve as the second capacitor electrode 142. After a voltage is applied to the first capacitor electrode 141, an inversion charge is generated in the area of ​​the substrate 101 located below the first capacitor electrode 141, so that the first electrode N3D, the second electrode N3S and the active area N3a therebetween of the storage transistor N3 constitute a conductor structure.

[0189] exist Figure 4A The first conductive layer 301, the third insulating layer 203, the second conductive layer 302, the fourth insulating layer 204, the third conductive layer 303, the fifth insulating layer 205 and the fourth conductive layer 304 are sequentially formed on the substrate shown in FIG. Figure 3A The display panel shown.

[0190] Fig. 6A and Figure 6B The pattern of the first conductive layer 301 and the first conductive layer 301 are respectively shown. Figure 4A The situation on the substrate structure shown, Figure 6B Also shown is a via hole in the second insulating layer 202, which is used to electrically connect each transistor and the contact hole region with the pattern in the first conductive layer 301. For clarity, only four rows and six columns of sub-pixels are shown in the figure, and the area of ​​one sub-pixel 100 is shown with a dotted line frame. Figure 6C for Figure 6B The dotted box in the figure shows an enlarged schematic diagram of a sub-pixel.

[0191] like Fig. 6A As shown, the patterns of the first conductive layer in two adjacent sub-pixels in the first direction D1 are symmetrical about the symmetry axis along the second direction D2; the patterns of the first conductive layer in two adjacent sub-pixels in the second direction D2 are symmetrical about the symmetry axis along the first direction D1. The pattern of the first conductive layer will be exemplarily described below by taking one sub-pixel as an example.

[0192] like Fig. 6A As shown, the first conductive layer 301 includes a connecting electrode 313, and the connecting electrode 313 is used to electrically connect the first end 131 of the resistor 130 to the second electrode N2S of the driving transistor N2. Figure 4B As shown, the second electrode N2S of the driving transistor N2 and the first electrode N4D of the noise reduction transistor N4 are an integral structure. The first end 131 of the resistor 130 and the gate N4G of the noise reduction transistor N4 are an integral structure.

[0193] In some embodiments, in conjunction with reference Figure 4B , 6B 6C, the connection electrode 313 is L-shaped as a whole, including a first portion extending along the first direction D1 and a second portion extending from the first portion along the second direction D2 toward the driving transistor N2, the free end of the second portion of the connection electrode 313 is electrically connected to the second electrode N2S of the driving transistor N2 and the first electrode N4D of the noise reduction transistor N4 through the via hole 225 in the second insulating layer 202; the first portion of the connection electrode 313 is electrically connected to the first end 131 of the resistor 130 and the gate N4G of the noise reduction transistor N4 through the via hole 226 in the second insulating layer 202. The connection electrode 313 can be considered as the first node S.

[0194] In some embodiments, any one of via 225 and via 226 may be provided as one or more, for example, to reduce contact resistance.

[0195] In some embodiments, in conjunction with reference Figures 6A-6C and Figure 4B The first conductive layer 301 further includes a connecting electrode 314, which is electrically connected to the second end 132 of the resistor 130 through the via hole 229 in the second insulating layer 202, and is used to be electrically connected to the first electrode 121 of the light emitting element 120. For example, the connecting electrode 314 is L-shaped, and one branch thereof extending along the first direction D1 is electrically connected to the second end 132 of the resistor 130, and the other branch extending along the second direction D2 is used to be electrically connected to the first electrode 121 of the light emitting element 120.

[0196] In some embodiments, in combination Figures 6A-6C and Figure 4B As shown, the first conductive layer 301 further includes a connecting electrode 315, which is a strip extending along the first direction D1 and is used to introduce the ground voltage GND into the contact hole area 400a. Specifically, the connecting electrode 315 is electrically connected to the contact hole area 400a through the via 228a in the second insulating layer 202.

[0197] In some embodiments, the orthographic projection of the connecting electrode 315 on the base substrate 101 partially overlaps with the orthographic projection of the first capacitor electrode 141 on the base substrate 101. The connecting electrode 315 and the second capacitor electrode 142 of the storage capacitor Cst are both connected to the ground voltage GND. The connecting electrode 315 can serve as the third capacitor electrode of the storage capacitor Cst, thereby increasing the capacitance value of the storage capacitor Cst.

[0198] In some embodiments, an orthographic projection of the connection electrode 315 on the base substrate 101 partially overlaps with an orthographic projection of the resistor 130 on the base substrate 101 .

[0199] In some embodiments, the first conductive layer 301 also includes a connecting electrode 317, which is used to electrically connect the second end of the data writing sub-circuit with the first end of the storage sub-circuit, that is, to electrically connect the first electrode N1D of the first data writing transistor N1, the first electrode P1G of the second data writing transistor P1 and the first capacitor electrode 141.

[0200] Combined with reference Fig. 6A and Figure 6BThe connecting electrode 317 includes a first portion extending along the second direction D2, a second portion extending along the first direction D1, and a third portion located between the first portion and the second portion and connecting the first portion and the second portion, wherein the third portion is a bent structure. The first end of the first portion of the connecting electrode 317 is electrically connected to the first electrode N1D of the first data writing transistor N1 through a via hole 261a in the second insulating layer 202, and the second end of the first portion of the connecting electrode 317 is electrically connected to the second electrode P1D of the second data writing transistor P1 through a via hole 261b in the second insulating layer 202. The third portion of the connecting electrode 317 is electrically connected to the first capacitor electrode 141 through a via hole 261c in the second insulating layer 202. In some embodiments, the via hole 261c may be provided as one or more, such as Figure 6C As shown, for example, there are two to reduce contact resistance. The free end of the third portion of the connection electrode 317 is electrically connected to the gate N2G of the driving transistor N2 through the via 261d in the second insulating layer 202. The third portion of the connection electrode 317 substantially crosses the resistor 130 and the storage capacitor Cst in the first direction D1.

[0201] Combined with reference Figures 6A-6C The first conductive layer 301 further includes a first scan line connection portion 311 and a second scan line connection portion 312. The first scan line connection portion 311 is used to be electrically connected to the first scan line so that the gate of the first data writing transistor N1 receives the first control signal SEL. The second scan line connection portion 312 is used to be electrically connected to the second scan line so that the gate of the second data writing transistor P1 receives the first control signal SEL_B.

[0202] In some embodiments, the first scan line connection portion 311 is electrically connected to the gate N1G of the first data writing transistor N1 through the via 221a in the second insulating layer 202 , and the second scan line connection portion 312 is electrically connected to the gate P1G of the second data writing transistor P1 through the via 221b in the second insulating layer 202 .

[0203] In some embodiments, Figures 6A-6C As shown, the first scan line connection portion 311 and the second scan line connection portion 312 are both in the shape of long strips extending along the first direction D1 , and the length of the first scan line connection portion 311 is greater than the length of the second scan line connection portion 312 .

[0204] like Fig. 6A As shown, the first conductive layer 301 further includes a data line connecting portion 316, which is used to electrically connect to the data line so that the second electrode N1S of the first data writing transistor N1 and the second electrode P1S of the second data writing transistor P1 receive the data signal Vd transmitted by the data line.

[0205] like Figure 6B and 6C As shown, the data line connection portion 316 is in the shape of a strip extending along the second direction D2, and the first end of the data line connection portion 316 is electrically connected to the second electrode N1S of the first data writing transistor N1 through the via hole 222a in the second insulating layer 202, and the second end is electrically connected to the second electrode P1S of the second data writing transistor P1 through the hole 222b in the second insulating layer 202.

[0206] In some embodiments, Fig. 6A As shown, a plurality of data line connection portions 316 are arranged at intervals in the second direction D2, for example, at the boundary between two sub-pixel rows. For example, two adjacent sub-pixels in the first direction D1 share one data line connection portion 316.

[0207] refer to Figures 6A-6C The first conductive layer 301 further includes a connecting electrode 318, which is electrically connected to the first electrode N2D of the driving transistor N2 through the via hole 223 in the second insulating layer 202, and the connecting electrode 318 is configured to introduce the first power supply voltage VDD into the first electrode N2D of the driving transistor N2.

[0208] refer to Figures 6A-6C The first conductive layer 301 further includes a connecting electrode 319, which is in the shape of a long strip extending along the first direction D1. The connecting electrode 319 is electrically connected to the first electrode N3D of the storage transistor N3 through the via hole 227a in the second insulating layer 202, and is configured to introduce the ground voltage GND into the first electrode N3D of the storage transistor N3. The connecting electrode 319 is electrically connected to the contact hole area 400a through the via hole 227b in the second insulating layer 202, and is configured to introduce the ground voltage GND into the contact hole area 400a.

[0209] refer to Figures 6A-6C The first conductive layer 301 further includes a connecting electrode 319a, which extends in the first direction D1. The connecting electrode 319a is electrically connected to the second electrode N3S of the storage transistor N3 through the via hole 228b in the second insulating layer 202, and is configured to introduce the ground voltage GND into the second electrode N3S of the storage transistor N3. The connecting electrode 319a is electrically connected to the contact hole region 400a through the via hole 228c in the second insulating layer 202, and is configured to introduce the ground voltage GND into the contact hole region 400a. The connecting electrode 319a is electrically connected to the contact hole region 400b through the via hole 228d in the second insulating layer 202, and is configured to introduce the ground voltage GND into the contact hole region 400b.

[0210] refer to Figures 6A-6CThe first conductive layer 301 further includes a connecting electrode 319b, which extends along the second direction D2. The connecting electrodes 319b of the sub-pixels in the same row are an integrated structure, forming a connecting line extending along the second direction D2. The connecting electrode 319b is electrically connected to the contact hole area 400a through the via hole 228e in the second insulating layer 202, and is configured to introduce the ground voltage GND into the contact hole area 400a.

[0211] In some embodiments, the number of vias 227b, 228c and 228e is plural, for example greater than or equal to 5, so that the contact hole region 400a with a larger area can be placed in the ground voltage GND. The P-type substrate is connected to the ground voltage GND, that is, the P-type substrate is biased to a low voltage.

[0212] refer to Figures 6A-6C The first conductive layer 301 further includes a connecting electrode 319c, which connects the N-type substrate to the first power supply voltage terminal to receive the first power supply voltage VDD (high voltage), thereby avoiding parasitic effects such as the liner bias effect and improving the stability of the circuit. Specifically, the connecting electrode 319c is electrically connected to the contact hole area 411 in the substrate 101 through the via 224 in the second insulating layer 202, and the connecting electrode 319c is used to connect to the first power supply voltage VDD to bias the N-type substrate of the second data writing transistor P1.

[0213] refer to Figures 6A-6C The first conductive layer 301 further includes a bias voltage line 310 extending along the second direction D2. The bias voltage line 310 is electrically connected to the gate N5G of the bias transistor N5 through the via 229a in the second insulating layer 202, and is used to provide a bias voltage Vb to the gate N5G of the bias transistor N5.

[0214] Fig. 7A Schematic diagram of the second conductive layer 302 is shown, Figure 7B A second conductive layer 302 is shown on the basis of the first conductive layer 301. Figure 7B The figure also shows a via hole in the third insulating layer 203, which is used to connect the pattern in the first conductive layer 301 and the pattern in the second conductive layer 302. For the sake of clarity, only four rows and six columns of sub-pixels are shown in the figure, and the area of ​​one sub-pixel 100 is shown with a dotted line frame. It can be understood by those skilled in the art that Figure 7B The structures of various layers before the first conductive layer 301 is formed are omitted.

[0215] like Fig. 7AAs shown, the patterns of the second conductive layer in two adjacent sub-pixels in the first direction D1 are symmetrical about the symmetry axis along the second direction D2; the patterns of the second conductive layer in two adjacent sub-pixels in the second direction D2 are symmetrical about the symmetry axis along the first direction D1. The pattern of the second conductive layer will be exemplarily described below by taking one sub-pixel as an example.

[0216] like Fig. 7A and 7B As shown, the second conductive layer 302 includes a connecting electrode 324, which is electrically connected to the connecting electrode 314 in the first conductive layer 301 through the via hole 239 in the third insulating layer 203, and the connecting electrode 324 is used to be electrically connected to the first electrode 121 of the light emitting element 120. For example, the connecting electrode 324 is in the shape of a long strip extending along the second direction D2.

[0217] In some embodiments, the via hole 239 may be provided as one or more via holes. Figure 7B As shown, for example, there are two to reduce contact resistance.

[0218] In some embodiments, the orthographic projection of the connection electrode 324 on the base substrate 101 substantially falls within the orthographic projection of the connection electrode 314 on the base substrate 101. For example, the orthographic projection of the connection electrode 324 on the base substrate 101 substantially coincides with the orthographic projection of the branch of the connection electrode 314 extending along the second direction D2 on the base substrate 101.

[0219] like Figure 6C , 7A As shown in Figures 7B, for each row of sub-pixels, the second conductive layer 302 includes a first scan line 321, a second scan line 322, a ground line 325, a power line 328, and a ground line 327 extending along the second direction D2, and they are all parallel to each other. The first scan line 321 is configured to transmit a first scan signal SEL, the second scan line 322 is configured to transmit a second scan signal SEL_B, the ground line 325 and the ground line 327 are configured to transmit a ground voltage GND, and the power line 328 is configured to transmit a first voltage signal VDD. The second scan line 322, the first scan line 321, the ground line 325, the power line 328, and the ground line are sequentially away from the center of each N-type well region of the sub-pixel in the row in the first direction D1.

[0220] In some embodiments, for any two adjacent rows of sub-pixels, each of their first scan line 321, second scan line 322, ground line 325, power line 328, and ground line 327 is symmetrical with respect to the symmetry axis along the second direction D2. For two adjacent rows of sub-pixels, if the two rows of sub-pixels belong to different pixel group rows, the two rows of sub-pixels share the ground line 327.

[0221] Combined with reference Fig. 7A and Figure 7B The first scan line 321 is electrically connected to the first scan line connection portion 311 in the first electrode layer 301 through the via hole 231 in the third insulating layer 203, and is used to provide the first scan signal SEL to the gate N1G of the first data writing transistor N1. The second scan line 322 is electrically connected to the second scan line connection portion 312 in the first electrode layer 301 through the via hole 232 in the third insulating layer 203, and is used to provide the first scan signal SEL_B to the gate P1G of the second data writing transistor P1.

[0222] Combined with reference Fig. 7A and Figure 7B The grounding line 325 is electrically connected to the connecting electrode 319 in the first electrode layer 301 through the via hole 233a in the third insulating layer 203, is electrically connected to the connecting electrode 315 in the first electrode layer 301 through the via hole 233b in the third insulating layer 203, and is electrically connected to the connecting electrode 319a in the first electrode layer 301 through the via hole 233c in the third insulating layer 203, so that the first electrode N3D and the second electrode N3S of the storage transistor N3 are electrically connected, and both are connected to the ground voltage GND.

[0223] In some embodiments, the grounding line 325 has a wider width, and the orthographic projection of the connecting electrode 315 in the first electrode layer 301 on the base substrate 101 falls within the orthographic projection of the grounding line 325 on the base substrate 101, that is, the length of the connecting electrode 315 in the first direction D1 is less than or equal to the width of the grounding line 325.

[0224] Combined with reference Fig. 7A and Figure 7B The power line 328 is electrically connected to the connection electrode 318 in the first conductive layer 301 through the via hole 235 in the third insulating layer 203 , and is used to provide the first voltage signal VDD to the first electrode N2D of the driving transistor N2 through the connection electrode 318 .

[0225] In some embodiments, Fig. 7A As shown, the power line 328 is a long strip structure extending along the second direction D2.

[0226] Combined with reference Fig. 7A and Figure 7B The grounding wire 327 is electrically connected to the connecting electrode 319b in the first electrode layer 301 through the via hole 234a in the third insulating layer 203, and is electrically connected to the connecting electrode 319a in the first electrode layer 301 through the via hole 234b in the third insulating layer 203, so that the connecting electrode 319a and the connecting electrode 319b are both connected to the ground voltage GND, thereby biasing the P-type substrate at a low voltage.

[0227] Combined with reference Fig. 7Aand Figure 7B The second conductive layer 302 also includes a data line connecting portion 326, which is used to be electrically connected to the data line and is electrically connected to the data line connecting portion 316 in the first conductive layer 301 through the via 236 in the third insulating layer 203, so that the second electrode N1S of the first data writing transistor N1 and the second electrode P1S of the second data writing transistor P1 receive the data signal Vd transmitted by the data line.

[0228] like Figure 7B As shown, the data line connection portion 326 is in a strip shape extending along the second direction D2, for example, the data line connection portion 326 is located at the boundary between two sub-pixel rows. For example, in the same pixel group, two adjacent sub-pixels in the first direction D1 share one data line connection portion 326.

[0229] In some embodiments, in conjunction with reference Fig. 7A and Figure 7B In the second direction D2, the data line connection portions 326 in each column of sub-pixels are alternately biased toward the two sides of the corresponding data line connection portion 316, so as to connect the data line connection portion 316 to different data lines.

[0230] Combined with reference Fig. 7A and Figure 7B The second conductive layer 302 further includes connecting electrodes 329a and 329c, which are provided for biasing the substrate of the transistor, for example, for connecting the N-type substrate to the first power supply voltage terminal to receive the first power supply voltage VDD (high voltage), or for connecting the P-type substrate to the ground voltage terminal to receive the ground voltage GND (low voltage), thereby avoiding parasitic effects such as the bias effect and improving the stability of the circuit.

[0231] Combined with reference Figure 4B , 7A 7B, the connection electrodes 329a, 329c are electrically connected to the connection electrodes 319a, 319c in the first conductive layer through the via holes 237, 238 in the third insulating layer 203, and further electrically connected to the contact hole areas 400b, 411 in the substrate 101, respectively. The connection electrode 329a is used to connect to the ground voltage GND to bias the P-type substrate where the first data writing transistor N1 is located. The connection electrode 329b is used to connect to the first power supply voltage VDD to bias the N-type substrate of the second data writing transistor P1.

[0232] like Fig. 7A and 7B As shown, in any row of pixel groups, a plurality of data line connection portions 326 are arranged at intervals in the second direction D2, and a connection electrode 329a or a connection electrode 329c is arranged between two adjacent data line connection portions 326.

[0233] Fig. 8A Schematic diagram of the third conductive layer 303 is shown, Figure 8B A third conductive layer 303 is shown on the basis of the second conductive layer 302. Figure 7B The figure also shows a via hole in the fourth insulating layer 204, which is used to connect the pattern in the second conductive layer 302 and the pattern in the third conductive layer 303. For the sake of clarity, only four rows and six columns of sub-pixels are shown in the figure, and the area of ​​one sub-pixel 100 is shown with a dotted line frame. It can be understood by those skilled in the art that Figure 8B The structures of various layers before the first conductive layer 301 is formed are omitted.

[0234] like Fig. 8A and 8B As shown, the third conductive layer 303 includes a connecting electrode 334 extending along the first direction D1, the connecting electrode 334 is electrically connected to the connecting electrode 324 in the second conductive layer 302 through the via hole 249 in the fourth insulating layer 204, and the connecting electrode 334 is used to be electrically connected to the first electrode 121 of the light emitting element 120. For example, the connecting electrode 334 is in the shape of a long strip extending along the first direction D1. In some embodiments, the orthographic projection of the connecting electrode 334 on the base substrate 101 partially overlaps with the orthographic projection of the connecting electrode 324 on the base substrate 101.

[0235] For example, the third conductive layer 303 includes a plurality of data lines extending along the second direction D2, and the data lines are used to connect to the first end of the data writing sub-circuit in the sub-pixel to provide the data signal Vd. Fig. 8A The plurality of data lines shown include a plurality of first data lines 3361 and a plurality of second data lines 3362, and the first data lines 3361 and the second data lines 3362 are alternately arranged in the first direction D1. Figure 1 The data line 12 shown may be the first data line 3361 or the second data line 3362 .

[0236] For example, the data line is divided into a plurality of data line groups, each data line group includes a first data line 3361 and a second data line 3362. For example, each sub-pixel column is respectively connected to a corresponding data line group, that is, connected to a first data line 3361 and a second data line 3362; that is, a column of sub-pixels is driven by two data lines. This helps to reduce the load on each data line, thereby improving the driving capability of the data line, reducing signal delay, and improving display effects.

[0237] refer to Figure 8B The first data line 2361 passes through the via hole 241a in the fourth insulating layer 204 and is connected to Figure 7BThe data line connecting portion 326 in the second conductive layer 302 shown in FIG. 1 is electrically connected between the first row of sub-pixels and the second row of sub-pixels, thereby providing data signals to the first and second row of sub-pixels; the second data line 2362 is electrically connected to the first row of sub-pixels through the via hole 241b in the fourth insulating layer 204. Figure 7B The data line connection 326 between the third row of sub-pixels and the fourth row of sub-pixels in the second conductive layer 302 shown in FIG. 3 is electrically connected to provide data signals to the third and fourth row of sub-pixels.

[0238] In some embodiments, the third conductive layer 303 includes a power line 338 and a ground line 335 extending along the first direction D1. The power line 338 is used to transmit a first power voltage VDD, and the power line 335 is used to transmit a ground voltage GND. Fig. 8A As shown, the power lines 338 and the power lines 335 are arranged alternately one by one in the first direction D1.

[0239] refer to Figure 8B The power line 338 is electrically connected to the power line 328 in the second conductive layer 302 through the via 242a in the fourth insulating layer 204, thereby forming a meshed power line structure for transmitting the first power supply voltage VDD. This structure helps to reduce the resistance on the power line, thereby reducing the voltage drop on the power line, and helps to uniformly transmit the first power supply voltage VDD to each sub-pixel of the display substrate. The power line 338 is also electrically connected to the connection electrode 329c in the second conductive layer 302 through the via 242b in the fourth insulating layer, thereby electrically connected to the contact hole area 411 in the second area (N well area) 402 in the substrate 101, so as to bias the N-type substrate where the first data write transistor P1 is located.

[0240] refer to Figure 8B The ground line 335 is electrically connected to the ground lines 325 and 327 in the second conductive layer 302 through the via holes 243a and 243b in the fourth insulating layer 204, respectively, to form a meshed power line structure for transmitting the ground voltage. This structure helps to reduce the resistance on the ground line, thereby reducing the voltage rise on the ground line, and helps to evenly transmit the ground voltage GND to each sub-pixel of the display substrate. The power line 340 is also electrically connected to the connection electrode 329a in the second conductive layer 302 through the via hole 243c in the fourth insulating layer. The contact hole areas 400b and 400a in the substrate substrate 101 are both connected to the ground voltage to bias the P-type substrate where the transistors N1-N5 are located.

[0241] like Fig. 8A and 8BAs shown, the third conductive layer 303 further includes a connection electrode 333, which is located between a first data line 3361 and a second data line 3362 in a data line group. The connection electrode 333 extends along a first direction D1 and is located between the first data writing transistor N1 and the second data writing transistor P1.

[0242] Combination Fig. 8A and Figure 8B As shown, the third conductive layer 303 further includes a shielding electrode 337, for example, the shielding electrode 337 extends along the first direction D1, and the shielding electrode 337 is located between the first data line 3361 and the second data line 3362 of a data line group, for example, the first data line 3361 and the second data line 3362 are symmetrically arranged on both sides of the shielding electrode 337. The shielding electrode 337 is arranged between the two data lines to play a shielding role to prevent the signals in the two data lines from crosstalking with each other. For example, the shielding electrode 337 is configured to receive a constant voltage to improve the shielding ability. In the present embodiment, the shielding electrode 337 is used to receive a ground voltage GND. Specifically, the shielding electrode 337 is electrically connected to the ground line 325 in the second conductive layer 302 through the via 244 in the fourth insulating layer 204.

[0243] For example, the display substrate includes a plurality of shielding electrodes 337 , and the plurality of shielding electrodes 337 are arranged in one-to-one correspondence with a plurality of data line groups, and each shielding electrode is located between the first data line and the second data line of the corresponding data line group.

[0244] like Fig. 8A As shown, the connecting electrode 333, the connecting electrode 334, and the shielding electrode 337 are arranged sequentially in the first direction D1 and are located between the first data line 3361 and the second data line 3362; the connecting electrode 333, the connecting electrode 334, and the shielding electrode 337 form a shielding wall, which plays a shielding role within the entire extension range of the first data line 3361 and the second data line 3362 to prevent the signals in the two data lines from crosstalking with each other.

[0245] For example, Fig. 8A As shown, the connection electrode 333 and the shielding electrode 337 are respectively located on both sides of the connection electrode 334 and are spaced apart from the connection electrode 334. The connection electrode 333 has a protrusion 333a at one end close to the connection electrode 334. The protrusion 333a extends from the body of the connection electrode 333 toward one of the first data line 3361 and the second data line 3362 and then extends away from the body of the connection electrode 333 along the first direction D1. In the second direction D2, the protrusion 333a overlaps with the gap between the connection electrode 333 and the connection electrode 334, thereby improving the shielding effect and further avoiding signal crosstalk between the two data lines.

[0246] Similarly, the shielding electrode 337 has a protrusion 337 a at one end close to the connecting electrode 334 , which is used to further shield the gap between the shielding electrode 337 and the connecting electrode 334 to improve the shielding effect.

[0247] In this way, the shielding wall achieves full shielding in the first direction D1, and the first data line 3361 and the second data line 3362 do not have a directly face-to-face area in the first direction D1, which plays a good signal shielding role, makes the display data have better stability, and improves the display effect.

[0248] Fig. 9A Schematic diagram of the fourth conductive layer 304 is shown, Fig. 9B A fourth conductive layer 304 is shown on the basis of the third conductive layer 303. Fig. 9B The figure also shows a via hole in the fifth insulating layer 205, which is used to connect the pattern in the third conductive layer 303 and the pattern in the fourth conductive layer 304. For the sake of clarity, only four rows and six columns of sub-pixels are shown in the figure. Those skilled in the art will understand that Fig. 9B The structures of various layers before the first conductive layer 301 is formed are omitted.

[0249] like Fig. 9A and 9B As shown, the fourth conductive layer 304 includes a connecting electrode 344 , which is electrically connected to the connecting electrode 334 in the third conductive layer 303 through a via hole 259 in the fifth insulating layer 205 , and the connecting electrode 344 is used to be electrically connected to the first electrode 121 of the light emitting element 120 .

[0250] In some embodiments, the via hole 259 can be provided as one or more via holes. Fig. 9B As shown, for example, there are two to reduce contact resistance.

[0251] like Fig. 9A and 9B As shown, the fourth conductive layer 304 includes a power line 348 and a ground line 345 extending along the first direction D1. The power line 348 is used to transmit a first power voltage VDD, and the ground line 345 is used to transmit a ground voltage GND. Fig. 9A As shown, the power lines 348 and the ground lines 345 are arranged alternately one by one in the second direction D2.

[0252] For example, multiple power lines 348 are arranged in one-to-one correspondence with multiple power lines 338, and multiple ground lines 345 are arranged in one-to-one correspondence with multiple ground lines 335; in a direction perpendicular to the base substrate 101, each power line 348 overlaps and is electrically connected (e.g., in parallel) with the corresponding power line 348, and each ground line 345 overlaps and is electrically connected (e.g., in parallel) with the corresponding ground line 335. This reduces the resistance on the power line and improves display uniformity.

[0253] refer to Fig. 9B The power line 348 is electrically connected to the corresponding power line 338 through the via hole 251 in the fifth insulating layer 205, and the ground line 345 is electrically connected to the corresponding ground line 335 through the via hole 252 in the fifth insulating layer. For example, the number of the via holes 251 and 252 is at least two.

[0254] Combination Fig. 9A and Fig. 9B The fourth conductive layer 304 also includes a connecting electrode 343, which is electrically connected to the connecting electrode 333 in the third conductive layer 303 through a via 253 in the fifth insulating layer. The width of the connecting electrode 343 is greater than the width of the connecting electrode 333. In some embodiments, the orthographic projection of the connecting electrode 343 on the base substrate 101 covers the orthographic projection of the main part of the connecting electrode 333 on the base substrate 101.

[0255] Combination Fig. 9A and Fig. 9B The fourth conductive layer 304 further includes a connecting electrode 347 , which is electrically connected to the shielding electrode 337 in the third conductive layer 303 through a via hole 254 in the fifth insulating layer.

[0256] like Fig. 9A As shown, the fourth conductive layer 304 further includes a connecting portion 342 , which connects the connecting electrode 343 to a power line 348 or a ground line 345 directly adjacent to the connecting electrode 343 .

[0257] like Fig. 9A As shown, for the first row and the second sub-pixel, i.e., the first row pixel group, the connection portion 342 connects the connection electrode 343 to the power line 348 directly adjacent to the connection electrode 343. For the second third row and the fourth row of sub-pixels, i.e., the second row pixel group, the connection portion 342 connects the connection electrode 343 to the power line 345 directly adjacent to the connection electrode 343.

[0258] In some embodiments, Fig. 9A As shown, the connection electrodes 343 located on both sides of the power line 348 are symmetrically arranged about the power line 348, and the power line 348 and the connection electrodes 343 located on both sides thereof and the corresponding connection parts 342 of the connection electrodes are connected to each other as an integrated structure.

[0259] In some embodiments, Fig. 9A As shown, the connection electrodes 343 located on both sides of the grounding line 345 are symmetrically arranged about the grounding line 345, and the grounding line 345 and the connection electrodes 343 located on both sides thereof and the connection portions 342 corresponding to the connection electrodes are connected to each other as an integrated structure.

[0260] Fig. 9B 34 also shows a contact hole region 349 of the connecting electrode 344, and the contact hole region 349 is used to electrically connect to the first electrode 121 of the light emitting element 120. In some embodiments, as Figure 3B As shown, the display panel 10 also includes a sixth insulating layer 206, in which a via 267 is formed in a contact hole area corresponding to the connecting electrode 344. The via 267 is filled with a conductive material (such as tungsten) and then undergoes a polishing process (such as chemical mechanical polishing) to form a flat surface for forming the light-emitting element 120.

[0261] In some embodiments, the number of the vias 267 is at least two.

[0262] For example, Figure 3B As shown, the number of contact hole areas for electrical connection on the connecting electrodes 314, 324, 334, and 344 connected to the first electrode 121 of the light-emitting element 120 can be one or more, thereby reducing the contact resistance between the connecting electrodes, and further reducing the connection resistance between the resistor 130 and the first electrode 121 of the light-emitting element 120, thereby reducing the voltage drop on the transmission path of the data signal from the resistor 130 to the first electrode 121, alleviating the color deviation, display unevenness and other problems caused by the anode potential loss (grayscale loss) caused by the voltage drop, and improving the display effect.

[0263] like Figure 3B As shown, the light emitting element 120 includes a first electrode 121, a light emitting layer 123, and a second electrode 122 sequentially disposed on the sixth insulating layer 206. For example, the first electrode 121 and the second electrode 122 are respectively the anode and cathode of the OLED. For example, a plurality of first electrodes 121 are arranged at intervals in the same layer, corresponding to a plurality of sub-pixels one by one. For example, the second electrode 122 is a common electrode, which is arranged on the entire surface in the display panel 10.

[0264] In some embodiments, Figure 3B As shown, the display panel further includes a first encapsulation layer 124 , a color filter layer 125 , a cover plate 126 and the like, which are located on a side of the light emitting element 120 away from the base substrate 101 .

[0265] For example, the first encapsulation layer 124 is configured to seal the light-emitting element to prevent external moisture and oxygen from penetrating into the light-emitting element and the pixel circuit and causing damage to the device. For example, the encapsulation layer 124 includes an organic film or a structure including an organic film and an inorganic film alternately stacked. For example, a water absorbing layer may be provided between the encapsulation layer 124 and the light-emitting element, configured to absorb moisture and oxygen in the early stage of the light-emitting element production.

[0266] In some embodiments, Figure 3B As shown, the display panel may further include a second encapsulation layer 127 located between the color filter layer 125 and the cover plate 126 , and the second encapsulation layer 127 may protect the color filter layer 125 .

[0267] For example, the light emitting element 120 is configured to emit white light, and combined with the color filter layer 124 to achieve full color display.

[0268] In other examples, the light emitting element 120 is configured to emit light of three primary colors, and in this case, the color filter layer 124 is not necessary. The embodiment of the present disclosure does not limit the manner in which the display panel 10 realizes full-color display.

[0269] In some embodiments, the material of the first to fourth conductive layers is a metal material, such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W) and alloy materials formed by the combination of the above metals. For example, the material of the first to fourth conductive layers can also be a conductive metal oxide material, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), etc.

[0270] In some embodiments, the material of the first to sixth insulating layers is, for example, an inorganic insulating layer, such as silicon oxide, silicon nitride, silicon oxynitride or other silicon oxide, silicon nitride or silicon oxynitride, or aluminum oxide, titanium nitride or the like including metal oxynitride insulating materials.

[0271] In some embodiments, the light emitting element 120 is a top emission structure, the first electrode 121 is reflective and the second electrode 122 is transmissive or semi-transmissive. For example, the first electrode 121 is a material with a high work function to act as an anode, such as an ITO / Ag / ITO stacked structure; the second electrode 122 is a material with a low work function to act as a cathode, such as a semi-transmissive metal or metal alloy material, such as an Ag / Mg alloy material.

[0272] Some embodiments of the present disclosure also provide a display device 40, such as Fig.10As shown, the display device 40 includes any of the above-mentioned display panels 10. The display device in this embodiment can be: a display, an OLED panel, an OLED TV, an electronic paper, a mobile phone, a tablet computer, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0273] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other.

Claims

1. A display panel, characterized in that: The display panel includes a base substrate and sub-pixels on the base substrate, wherein the sub-pixels include a pixel circuit and a light-emitting element, and the pixel circuit includes a data writing sub-circuit, a storage sub-circuit, a driving sub-circuit, and a first sub-circuit: The data writing sub-circuit is configured to transmit a data signal to the first terminal of the storage sub-circuit in response to a control signal, The driving subcircuit comprises a control electrode, a first electrode and a second electrode, the control electrode of the driving subcircuit is coupled to the storage subcircuit, the first electrode of the driving subcircuit is configured to receive a first power supply voltage, the second electrode of the driving subcircuit is coupled to the first electrode of the light-emitting element, and the driving subcircuit is configured to drive the light-emitting element to emit light in response to the voltage of the control electrode, The first subcircuit includes a first transistor, the first subcircuit is a shunt noise reduction subcircuit, the first transistor is a noise reduction transistor, and the gate and the first electrode of the first transistor are coupled to the second electrode of the driving subcircuit; The shunt noise reduction sub-circuit also includes a bias transistor, the noise reduction transistor and the bias transistor are connected in series, the second electrode of the noise reduction transistor is coupled to the first electrode of the bias transistor, the gate of the bias transistor receives a bias voltage, and the second electrode of the bias transistor receives a predetermined voltage.

2. The display panel according to claim 1, wherein: The pixel circuit also includes a resistor, which is connected in series between the second electrode of the driving subcircuit and the first electrode of the light-emitting element. The resistor is in the same layer as the control electrode of the driving subcircuit and is separately arranged, and the resistivity of the resistor is higher than the resistivity of the control electrode of the driving subcircuit.

3. The display panel according to claim 2, wherein: The data writing subcircuit includes a transmission gate circuit, the transmission gate circuit includes a first data writing transistor and a second data writing transistor, the first data writing transistor and the second data writing transistor each include a gate, a first electrode and a second electrode, the control signal includes a first control signal and a second control signal, The gate of the first data write transistor is configured to receive the first control signal, the gate of the second data write transistor is configured to receive the second control signal, the first electrode of the first data write transistor and the first electrode of the second data write transistor are coupled, and both are coupled to the first end of the storage sub-circuit and the control electrode of the driving sub-circuit, the second electrode of the first data write transistor and the second electrode of the second data write transistor are coupled, and both are configured to receive the data signal.

4. The display panel according to claim 3, wherein: The driving subcircuit comprises a driving transistor, wherein a gate electrode, a first electrode and a second electrode of the driving transistor respectively serve as a control electrode, a first electrode and a second electrode of the driving subcircuit.

5. The display panel according to claim 4, wherein: The first data writing transistor, the driving transistor, the noise reduction transistor and the bias transistor are all N-type metal-oxide semiconductor field effect transistors, and the second data writing transistor is a P-type metal-oxide semiconductor field effect transistor.

6. The display panel according to claim 5, wherein: The resistor is arranged at the same layer as the gate of the noise reduction transistor and is an integrated structure.

7. The display panel according to claim 6, wherein: The storage subcircuit comprises a storage capacitor, the storage capacitor comprises a first capacitor electrode and a second capacitor electrode, the first capacitor electrode and the second capacitor electrode serve as a first end and a second end of the storage subcircuit respectively; The first capacitor electrode and the resistor are insulated and arranged in the same layer.

8. The display panel according to claim 7, wherein: In a first direction parallel to the substrate, the transmission gate circuit is located on one side of the storage capacitor, and the driving transistor, the noise reduction transistor, the bias transistor and the resistor are located on the other side of the storage capacitor.

9. The display panel according to claim 8, wherein: In a second direction parallel to the base substrate and perpendicular to the first direction, the second data writing transistor and the first data writing transistor are arranged in sequence, and the driving transistor, the noise reduction transistor and the bias transistor are arranged in sequence.

10. The display panel according to claim 9, wherein: In the first direction, the resistor is located between the combination of the driving transistor, the noise reduction transistor and the bias transistor and the storage capacitor.

11. The display panel according to claim 10, wherein: The resistor includes a plurality of first sub-segments along a first direction and a plurality of second sub-segments along a second direction, wherein the plurality of first sub-segments and the plurality of second sub-segments are connected end to end to form a bent structure.

12. The display panel according to claim 9, wherein: The shortest distance between the driving transistor and the first data writing transistor is greater than the shortest distance between the driving transistor and the second data writing transistor.

13. The display panel according to claim 9, wherein: The shortest distance between the bias transistor and the first data write transistor is smaller than the shortest distance between the bias transistor and the second data write transistor.

14. The display panel according to claim 9, wherein: The resistor has a width smaller than a width of any one of a gate of the first data write transistor, a gate of the second data write transistor, a gate of the drive transistor, a gate of the noise reduction transistor, and a gate of the bias transistor.

15. The display panel according to claim 7, wherein: The gate of the first data writing transistor, the gate of the second data writing transistor, the gate of the driving transistor, the gate of the noise reduction transistor, the gate of the bias transistor, the first capacitor electrode and the resistor are arranged in the same layer.

16. The display panel according to claim 9, wherein: The second data write transistor and the first data write transistor are arranged side by side along the second direction and are symmetrical with respect to a symmetry axis along the first direction.

17. The display panel according to claim 5, wherein: The second electrode of the driving transistor and the first electrode of the noise reduction transistor are arranged in the same layer and are an integrated structure, and / or The second electrode of the noise reduction transistor and the first electrode of the bias transistor are arranged in the same layer and form an integrated structure.

18. The display panel according to claim 7, comprising four sub-pixels, wherein the four sub-pixels constitute a pixel unit group. in, The four sub-pixels are arranged in an array along a first direction and a second direction, wherein the first direction is perpendicular to the second direction. The orthographic projections of the second data writing transistors of the four sub-pixels on the substrate are located in the same N-type well region in the substrate.

19. The display panel according to claim 18, wherein: The resistors of the sub-pixels adjacent in the first direction are symmetrical about the symmetry axis along the second direction, and the resistors of the sub-pixels adjacent in the second direction are symmetrical about the symmetry axis along the first direction.

20. The display panel according to claim 18, wherein: The transfer gate circuits of two adjacent sub-pixels in the first direction are symmetrical about the symmetry axis along the second direction, and the transfer gate circuits of two adjacent sub-pixels in the second direction are symmetrical about the symmetry axis along the first direction. 21 . The display panel according to claim 18 , wherein driving transistors of two adjacent sub-pixels in the first direction are symmetrical about an axis of symmetry along the second direction, and driving transistors of two adjacent sub-pixels in the second direction are symmetrical about an axis of symmetry along the first direction.

22. The display panel according to claim 18, wherein the noise reduction transistors of two adjacent sub-pixels in the first direction are symmetrical about the symmetry axis along the second direction, and the noise reduction transistors of two adjacent sub-pixels in the second direction are symmetrical about the symmetry axis along the first direction. 23 . The display panel according to claim 18 , wherein bias transistors of two adjacent sub-pixels in the first direction are symmetrical about an axis of symmetry along the second direction, and bias transistors of two adjacent sub-pixels in the second direction are symmetrical about the axis of symmetry along the first direction.

24. The display panel according to claim 18, wherein: The first capacitor electrodes of the adjacent sub-pixels in the first direction are symmetrical about the symmetry axis along the second direction, and the first capacitor electrodes of the adjacent sub-pixels in the second direction are symmetrical about the symmetry axis along the first direction. 25 . The display panel according to claim 24 , wherein the orthographic projections of the first capacitor electrodes in the four sub-pixels on the base substrate are located outside the N-type well region and are arranged around the N-type well region.

26. The display panel according to claim 4 or 5, wherein: The pixel circuit further includes an isolation structure, wherein the isolation structure is coupled to the second electrode of the bias transistor, and the isolation structure is used to receive a preset voltage.

27. The display panel according to claim 26, wherein: An orthographic projection of at least one of the resistor, the driving transistor, the bias transistor, and the noise reduction transistor on the substrate is surrounded by an orthographic projection of the isolation structure on the substrate.

28. The display panel according to claim 26, wherein: The isolation structure is coupled to the first conductive layer through a plurality of vias, and a distribution density of the vias on a side of the isolation structure close to the noise reduction transistor is greater than a distribution density of the vias on a side of the isolation structure close to the storage capacitor.

29. The display panel according to claim 26, wherein: The isolation structure is an open-loop structure with an opening, and the first pole of the driving electrode tube is located at the opening.

30. The display panel according to claim 26, wherein: The width of the bias transistor gate is greater than the width of the drive transistor gate.

31. The display panel according to claim 26, wherein: The closest distance between the gate of the noise reduction transistor and the isolation structure is greater than the closest distance between the gate of the driving transistor and the isolation structure.

32. The display panel according to claim 26, wherein: The total length of the resistor is greater than the total length of the isolation structure.

33. A display device comprising the display panel according to any one of claims 1-32.

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