Synchronous pulse width modulation control

Abstract

In described examples, a pulse width modulation (PWM) system (200) includes a starter (202) and a receiver (204). The starter (202) includes a starter counter (228) and a starter PWM signal generator (210). The starter counter (228) advances a starter count in response to a starter clock signal. The starter PWM signal generator (210) generates a starter PWM signal in response to the starter count. The receiver (204) includes a receiver counter (230), a receiver PWM signal generator (222), and circuitry configured to reset the receiver count. The receiver counter (230) advances a receiver count in response to a receiver clock signal. The receiver PWM signal generator (222) generates a receiver PWM signal in response to the receiver count. The circuitry resets the receiver count in response to a synchronization signal and based on an offset.

Description

Technical Field

[0001] This application relates generally to control systems, and more specifically to the synchronization of pulse width modulation control systems distributed across local networks. Background Technology

[0002] In many applications, such as industrial drive systems, it is important for various physically distributed control devices to operate synchronously to control the corresponding equipment. For example, robotic systems, machine tools, and position-controlled drive systems can incorporate multiple motors or actuators that are independently controlled by different controllers among multiple corresponding controllers. Synchronized controllers allow motors and actuators to operate together to achieve coordinated movement from precise time to precise position.

[0003] In some examples, synchronized controllers are distributed across machines, vehicles, buildings, or other measurable volumes of tens of meters or smaller, and connected via a communication network. The controllers can exchange control signals and sensor measurements via this network. Clock drift, variations in clock sources (which can lead to accumulated clock differences in separate controllers), clock generation errors, and poor clock signal propagation (e.g., software- or hardware-induced delays or transmission time differences) can cause distributed controllers that otherwise rely on the same clock timing to remain synchronized to become desynchronized.

[0004] Figure 1 illustrates an example functional block layout of a prior art pulse width modulation (PWM) controlled system 100. A primary PWM controller 102 is clocked by a primary global clock 104 (which may also be a global clock) and connected to control a first PWM controlled device 106 (which may also be referred to as a power stage). The primary PWM controller 102 uses the primary global clock 104 to maintain a primary PWM count and uses the primary PWM count to generate a PWM control signal to control the first PWM controlled device 106. Particularly in a duty cycle (time-proportional) PWM implementation, the state of the PWM signal between high and low changes in response to a change in the PWM count, for example, setting the PWM signal low when the count reaches a first value and setting it high when the count reaches a second value. (Alternatively, the PWM signal is set high when the count reaches a first value and low when the count reaches a second value.) Adjusting the first value changes the PWM duty cycle, which is the portion of the PWM signal cycle in which the PWM signal is high (or low). Adjusting the second value corresponds to changing the maximum value or modulus of the counter, which determines the period of the PWM signal cycle. The primary PWM controller 102 can also be connected to the isolation block 110 via N communication lines 108. The use of the isolation block 110 can depend on, for example, whether device 106 is high-voltage or low-voltage. The isolation block 110 includes capacitors, inductors, or optocouplers to isolate the primary PWM controller 102 from other power regimes (such as different power regimes applied to different PWM controllers). The isolation block 110 is connected via N communication lines 112 to a secondary PWM controller 114 clocked by a secondary global clock 116. The secondary PWM controller 114 is connected to control a second PWM controlled device 118. The secondary PWM controller 114 uses the secondary global clock 116 to maintain a secondary PWM count and uses the secondary PWM count to generate PWM control signals to control the second PWM controlled device 118. Summary of the Invention

[0005] In the described example, the pulse width modulation (PWM) system includes an initiator and a receiver. The initiator includes an initiator counter and an initiator PWM signal generator. The initiator counter advances the initiator count in response to an initiator clock signal. The initiator PWM signal generator generates an initiator PWM signal in response to the initiator count. The receiver includes a receiver counter, a receiver PWM signal generator, and circuitry configured to reset the receiver count. The receiver counter advances the receiver count in response to a receiver clock signal. The receiver PWM signal generator generates a receiver PWM signal in response to the receiver count. The circuitry resets the receiver count in response to a synchronization signal and based on an offset. Attached Figure Description

[0006] Figure 1 shows an example function block layout of a prior art synchronous pulse width modulation (PWM) controlled system.

[0007] Figure 2 An example function block layout of a synchronous PWM controlled system is shown.

[0008] Figure 3 An example function block layout of the starter section of a synchronous PWM controlled system is shown.

[0009] Figure 4 An example of a synchronization frame bitwise layout is shown.

[0010] Figure 5 An example of a synchronization process for a PWM-controlled system is shown. Detailed Implementation

[0011] Figure 2 An example functional block layout of a synchronized PWM controlled system 200 is shown. The PWM controlled system 200 includes a primary module 202 (also referred to as a starter module) and a secondary module 204 (also referred to as a receiver module). The primary module 202 includes a primary PWM clock unit 206 that generates a primary PWM clock signal and is connected to clock a frame trigger unit 208 and a primary PWM controller 210. For example, the primary PWM clock signal can be generated from a primary global clock system (not shown). The frame trigger unit 208 is connected to output a synchronization pulse (described further below) to the primary PWM controller 210 and a transmitter 212. The primary PWM controller 210 is connected to control a first controlled device 214. The transmitter 212 outputs to a communication line 216. The communication line 216 can be, for example, a bidirectional interconnect, such as a Fast Serial Interface (FSI). The communication line 216 can be bidirectional to allow data to also be transmitted through the communication line 216. Therefore, communication line 216 can be shared between data frame transmission and synchronization frame transmission (or other frame type transmission), and the input of receiver 218 connected to communication line 216 at this point can be referred to as shared input 232.

[0012] Secondary module 204 has a receiver 218 connected to receive frames (such as data frames or synchronization frames) from communication line 216. Receiver 218 is connected to output the received frames to a configurable logic block 220 (CLB 220), such as a field-programmable gate array (FPGA) or dedicated digital logic. CLB 220 is connected to output to a secondary PWM controller 222. A secondary PWM clock 224 is connected to clock the secondary PWM controller 222. The secondary PWM clock 224 may be generated, for example, from a secondary global clock system (not shown). The secondary PWM controller 222 is connected to control a second controlled device 226.

[0013] The primary PWM controller 210 includes a primary PWM counter 228 that generates a primary PWM count in response to a primary clock signal generated by the primary PWM clock unit 206. The primary PWM controller 210 uses the primary PWM count to generate control signals to control the first controlled device 214. For example, the primary PWM clock unit 206 may operate at 100MHz, while the primary PWM count increments at a rate of 20kHz (e.g., once every 5,000 rising clock edges). Therefore, the computational and other processing functions in the primary module 202 and the secondary module 204 operate at a higher rate relative to the device control functions of the primary PWM controller 210 and the secondary PWM controller 222, respectively, to improve the accuracy of device control.

[0014] Therefore, the control signal operating the first controlled device 214 can be described as a PWM control signal. The frame trigger unit 208 detects a predetermined synchronization condition (under which PWM count synchronization will occur) and generates a synchronization pulse when the synchronization condition is detected. The frame trigger unit 208 generates the synchronization pulse in response to the primary PWM count or other primary timer logic or standby PWM timer unit reaching a predetermined hardware-coded value, which can be stored in the programmable memory of the frame trigger unit 208 (e.g., non-volatile memory, fuse, etc.) or hard-coded into the static logic of the frame trigger unit 208. Using the predetermined hardware-coded value provides a deterministic reset timing independent of timing variations common in software layer execution, such as pauses and memory fetches. Therefore, each synchronization pulse can be generated periodically. The frame trigger unit 208 outputs the synchronization pulse to the primary PWM controller 210 and the transmitter 212. In response to the synchronization pulse, the primary PWM controller 210 resets the primary PWM count to zero. In response to a synchronization pulse, the transmitter generates a synchronization frame (also known as a PING frame) and transmits the synchronization frame to the receiver 218 of the secondary module 204 via communication line 216.

[0015] The receiver 218 of the secondary module 204 outputs received frames (such as data frames and synchronization frames) to the CLB 220. The CLB 220 detects whether a received frame is a synchronization frame, for example, by determining whether the frame includes a frame tag (bit string) with a value corresponding to a synchronization frame. (Regarding...) Figure 4 A further example structure of the synchronization frame is described. If the CLB 220 detects the synchronization frame, the CLB 220 sends a synchronization pulse to the secondary PWM controller 222.

[0016] The secondary PWM controller 222 includes a secondary PWM counter 230 that generates a secondary PWM count in response to a secondary PWM clock 224. The secondary PWM controller 222 generates a control signal in response to the secondary PWM count to control the second controlled device 226. Therefore, the control signal operating the second controlled device 226 can be described as a PWM control signal. If the secondary PWM controller 222 receives a synchronization pulse, it resets the secondary PWM count to zero plus an offset (also called a phase value).

[0017] The offset is encoded in the local hardware of the secondary PWM controller 222, and the synchronization process is performed by the hardware layer rather than the software layer. The offset is a memory variable and can be encoded in, for example, non-volatile memory or fuse logic. Avoiding software-related pauses, memory acquisitions, and other process-related delays provides deterministic synchronization timing, enhancing synchronization accuracy. The offset is determined in response to the physical distance between the primary module 202 and the secondary module 204. This offset can include the time taken for a serial bit stream, corresponding differently to the synchronization pulse and synchronization frame, to travel from the frame trigger unit 208 to the transmitter 212, through the communication line 216 to the receiver 218, to the CLB 220, and to the secondary PWM controller 222. For example, this propagation delay can be tens of nanoseconds, which can be added to the offset. Performing synchronization using the hardware layer limits the influence of variables other than propagation time and allows the offset to be accurately determined in response to (further) circuit-based delays (to compensate for circuit-based delays). Circuit-based delays (or time delays) may include, for example, the time taken to transmit the start frame, the duration of the synchronization frame, the time taken for the CLB 220 to detect the synchronization frame, the time taken to perform the secondary PWM count reset, and other delays related to the synchronization process.

[0018] In some embodiments, using a hardware layer to perform synchronization using synchronization frames and offsets related to transmission distance provides primary / secondary synchronization accurate to within a single cycle of the primary PWM clock signal. In embodiments where the primary PWM clock unit 206 operates at 100 MHz, this can correspond to primary / secondary synchronization accurate to within 10 ns. Therefore, in some embodiments where the device controlled by the primary PWM count generated by the primary PWM counter 228 and the secondary PWM count generated by the secondary PWM counter 230 operates at a frequency much lower than the corresponding primary PWM clock unit 206 or secondary PWM clock unit 224 (e.g., 20 kHz versus 100 MHz), primary / secondary synchronization can be highly accurate with respect to both the relatively low-frequency device control mechanism and the relatively high-frequency primary and secondary block 202, 204 operating mechanism.

[0019] As described above, the synchronization pulse generated by CLB 220 resets the secondary PWM count generated by the secondary PWM counter 230 of the secondary PWM controller 222. This reset, along with the added offset, effectively sets the secondary PWM count to the same or nearly the same count as the primary PWM count (generated by the primary PWM counter 228 of the primary PWM controller 210) at the time the secondary PWM count is reset. When the primary PWM count is reset and a synchronization frame is sent to the receiver 218 of the secondary module 204, the primary PWM count will also advance by an amount equal to (or approximately equal to) that offset by the time the secondary PWM count is reset to the offset. Therefore, the synchronization frame and the resulting secondary reset synchronize the primary and secondary PWM counts to within tolerances related to transmission time and other process variability (such as variations due to temperature). By limiting the physical distance between the primary module 202 and the secondary module 204 to tens of meters, the variability of transmission time can be limited, allowing the synchronization to reset the secondary PWM count more accurately to the same value as the primary PWM count at the time the secondary PWM count is reset.

[0020] As described herein, a PWM control system can use a specified synchronization frame to synchronize PWM control modules across multiple devices to provide coordinated real-time control. This synchronization can be performed by transmitting the synchronization frame over a bidirectional interconnect such as FSI (e.g., communication line 216). The synchronization frame can be adapted within a relatively limited bandwidth, and therefore can be transmitted using a shared communication line while avoiding conflicts with other data being communicated.

[0021] Using only the hardware layer to initiate the communication transmission of synchronization frames, and to receive and detect synchronization frames, avoids some or all software-related process interruptions, providing reliable timing synchronization. By using the hardware layer instead of a software protocol layer to perform synchronization, the synchronization process can be performed deterministically. Using the hardware layer instead of a software protocol layer during execution also allows the synchronization process to avoid dependence on the central processing unit (CPU) or other software-controlled subsystems. Therefore, using the hardware layer within the primary module 202 of the PWM network (such as PWM controlled system 200) to detect events within the primary module 202 using the frame triggering unit 208, generating synchronization frames in response to the detection of internal events, and synchronizing the timers of the primary PWM module 210 helps provide predictable timing synchronization events in the PWM modules 210 and 222 of the network. Furthermore, using the hardware layer within the secondary module 204 of the PWM network to receive, detect, and respond to synchronization frames helps provide predictable timing synchronization of the PWM modules of the network.

[0022] The secondary module 204 of the PWM network can use hardware to detect the received synchronization frame. The secondary module 204 generates a synchronization pulse in response to the detection of the received synchronization frame. After the secondary PWM controller 222 within the secondary module 204 receives the synchronization pulse, its timer synchronizes with the detected synchronization frame by resetting the secondary PWM count using an offset corrected for frame delay. Therefore, a known (e.g., measured) distance between the primary and secondary PWM control modules 202, 204 (in some examples, with additional delays such as additional signal propagation delays and circuit-related delays within the primary and secondary modules 202, 204 and their corresponding primary and secondary PWM modules 210, 222) can be used to generate an offset to compensate for, for example, the transmission delay caused by such a distance.

[0023] The primary PWM count can be synchronized by resetting it to zero after a synchronization pulse is transmitted (or, for example, after a synchronization pulse is generated, or after the frame triggering unit 208 initially detects an event—such as a predetermined primary PWM count value—to trigger synchronization). The secondary PWM count can be synchronized by resetting it to zero plus a generated offset in response to a synchronization frame (or a pulse following the detection of that frame). The generated offset can represent, for example, the delay between the transmission and reception of the synchronization frame, and other propagation delays of the corresponding synchronization pulses (one or more). The generated offset can also include circuit delays of the secondary module 204 and the corresponding secondary PWM controller 222, as well as the circuit delay between the reset of the primary PWM count and the transmission of the synchronization frame.

[0024] Figure 3An example functional block layout of the starter section of a synchronous PWM controlled system 300 is shown. A first input of the primary module transmitter 302 is connected to receive the output of a first detection event block 304. An input of the first detection event block 304 is connected to receive the output of a first multiplexer 306. The first multiplexer 306 has M inputs connected to M hardware layer trigger lines 308. A second input of the primary module transmitter 302 is connected to receive the output of a second detection event block 310. An input of the second detection event block 310 is connected to the output of a second multiplexer 312. The second multiplexer 312 has P inputs connected to P software layer trigger lines 314. The first and second detection event blocks 304, 310 and the first and second multiplexers 306, 312 can correspond to... Figure 2 The frame triggering unit 208.

[0025] M hardware layer trigger lines 308 can be used to connect to M different internal (e.g., on-chip) or external hardware layer trigger sources (or both) to enable the primary module transmitter 302 to generate synchronization frames. A first event detection block 304 determines whether the output of the first multiplexer 306 corresponds to a trigger event or a combination of trigger events for use by the primary module transmitter 302 to generate synchronization frames. If so, the first event detection block 304 sends a synchronization pulse to the primary module transmitter 302 to enable the primary module transmitter 302 to generate synchronization frames.

[0026] P software layer trigger lines 314 can be used to connect to P different internal or external software layer trigger sources (or both) for the primary module transmitter 302 to generate frames other than synchronous frames. A second event detection block 310 determines whether the output of the second multiplexer 312 corresponds to a trigger event or a combination of trigger events for the primary module transmitter 302 to generate software-triggered asynchronous frames. If so, the second event detection block 312 sends a signal to the primary module transmitter 302 to cause the primary module transmitter 302 to generate a software-initiated frame.

[0027] Figure 4 An example synchronization frame bitwise layout 400 is shown. Before synchronization frame 402, communication line 216 can be in (and received by receiver 218) an idle state 404. The presence of a frame is indicated by the preamble 406 of synchronization frame 402. Figure 4In the example, preamble 402 includes multiple clock edges identifying frame 402, although any other suitable preamble could be used. Following preamble 406 are start of frame 408, frame type 410, frame tag 412, end of frame 414, and one or more subsequent frame clock edges 416. Start of frame 408 indicates the beginning of the data portion of the frame. Frame type 410 indicates the type of frame from an enumeration list of possible frame types. End of frame 414 indicates that the end of the frame has been reached. Figure 4 The specific values ​​shown for these frames are merely illustrative. After the next frame clock edge 416, which separates the frame from other signals on communication line 216, communication line 216 returns to idle state 404 (or the subsequent content carried by communication line 216).

[0028] Frame tag 412 is used to identify a frame as synchronization frame 402. Frame tag 412 can be, for example, four bits, with a specific value corresponding to synchronization frame 402. CLB 220 ( Figure 2 The CLB 220 detects whether frame tag 412 has a value corresponding to synchronization frame 402 to detect the presence of synchronization frame 402 or asynchronous frame. The reception of a specific frame tag 412 by the CLB 220 receiver 418 helps avoid software intervention by automatically detecting frame tag 412 with reduced deterministic latency.

[0029] Figure 5 An example of a synchronization process 500 for a PWM-controlled system is shown. In step 502, the initiator PWM module (e.g., primary PWM controller 210, ...) is activated. Figure 2 In step 504, the starter module, including the starter PWM module, controls the first controlled device in response to the starter PWM count. In step 506, the starter module generates a synchronization pulse in response to a hardware-coded trigger (such as the value of the starter PWM count). In step 508, a synchronization frame is generated in response to the synchronization pulse, and the synchronization frame is transmitted from the starter module to the receiver module (e.g., secondary module 204). Figure 2 In step 510, the starter PWM count is reset in response to a synchronization pulse. In step 512, the receiver PWM module generates a receiver PWM count. In step 514, the receiver module, including the receiver PWM module, controls the second controlled device in response to the receiver PWM count. In step 516, the receiver module receives and detects a synchronization frame. In step 518, in response to the detection of the synchronization frame, the receiver PWM count is reset using an offset.

[0030] Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are also possible.

[0031] In some embodiments, one or more synchronization pulses and one or more synchronization frames corresponding to a single synchronization event (e.g., triggered by a single synchronization trigger) can be collectively referred to as synchronization signals. For example, synchronization pulses generated by a frame triggering unit, synchronization frames transmitted from a primary module to a secondary module, and synchronization pulses generated by a CLB in response to the detection of a synchronization frame can be collectively referred to as synchronization signals.

[0032] In some embodiments, the primary PWM count increments at a rate of 1 kHz to 1 MHz or higher.

[0033] In some embodiments, the offset, or the value to be added to the offset, is transmitted as part of the synchronization frame. For example, a value corresponding to a delay (process and propagation-related delay) associated with the internal functionality of the primary module may be transmitted as part of the synchronization frame.

[0034] In some embodiments, the propagation delay of the communication line can be determined from the data sheet of the corresponding cable, such as the number of nanoseconds per meter of cable.

[0035] In some embodiments, the synchronized PWM counting is used to perform synchronized control of the analog-to-digital converter (ADC) and the capture module, as well as the execution of a synchronization control algorithm. The capture module is a digital peripheral that accepts digital pulses and measures the pulse width of incoming pulse signals.

[0036] In some embodiments, the primary module includes a single PWM controller that controls both the controlled device and the transmitter of the primary module.

[0037] In some embodiments, Figure 2 The primary and secondary modules can be implemented using Texas Instruments Incorporated's F28004x (Potenza) microcontroller and other Texas Instruments Incorporated C2000 MCUs that include a fast serial interface.

[0038] In some embodiments, the primary PWM count is reset to an initial (or default) value other than zero in response to a synchronization pulse, and the secondary PWM count is reset to a (non-zero) initial (or default) value plus an offset in response to a synchronization pulse. In some embodiments, the initial value other than zero may be an offset corresponding to the delay between the generation of the synchronization pulse and the reset of the primary PWM count.

[0039] In some embodiments, the PWM count is incremented by one. In some embodiments, the PWM count is incremented by a number other than one. In some embodiments, the PWM count is decremented. Both the incrementing and decrementing counts are referred to herein as "push" counts. Counts performed other than in response to a synchronization frame are referred to herein as "nominal" push counts.

[0040] In some embodiments, the primary PWM count is not reset in response to a synchronization frame. In some embodiments, the primary PWM count is included in the synchronization frame, and the secondary PWM count is reset in response to the primary PWM count included in the synchronization frame and an offset. In some embodiments, the synchronization frame includes a default value, the primary PWM count is reset to the default value, and the secondary PWM count is reset to the default value plus an offset. In some embodiments, the primary PWM count is reset to a value based on the current primary PWM count (such as rounding the primary PWM count to a selected binary number), and the secondary PWM count is reset to a value based on the current secondary PWM count (such as rounding the secondary PWM count to a selected binary number) plus an offset.

[0041] FSI and Configurable Logic Block Peripherals are used as corresponding examples in this document. In some embodiments, synchronization frames and offsets as described herein are implemented using other interfaces and hardware.

[0042] In some embodiments, the transmitter 212 is connected to the receiver 218 of the additional secondary module 204 via a communication line 216 (or other communication line 216), for example, in a star or daisy-chain topology.

[0043] In some embodiments, additional frame portions are used to indicate synchronization frames. In some embodiments, the frames have different bitwise layouts.

[0044] In some embodiments, the PWM control signal enables and disables the controlled device according to the logic value of the corresponding PWM control signal.

[0045] In some embodiments, the distance between the primary module and the secondary module can be tens of meters or less. In some embodiments, the distance between the primary module and the secondary module can be longer.

[0046] In some embodiments, the synchronization of primary PWM counting and secondary PWM counting as described herein is applicable to various control mechanisms, such as distributed motor shaft control and control of distributed power stages (such as solar inverters / converters, AC / DC modules, and DC / DC modules).

Claims

1. A pulse width modulation system, i.e., a PWM system, comprising: A launcher, the launcher comprising: Starter clock signal input; A starter counter, configured to advance the starter count in response to a starter clock signal received at the starter clock signal input; A starter PWM signal generator is configured to generate a starter PWM signal in response to the starter counter; as well as A circuit system configured to generate and output synchronization signals; Receiver, the receiver comprising: Receiver clock signal input; A receiver counter, which advances the receiver count in response to a receiver clock signal received at the receiver clock signal input; A receiver PWM signal generator is configured to generate a receiver PWM signal in response to the receiver count; as well as A circuit system configured to reset the receiver count to an initial value plus an offset in response to the synchronization signal, wherein the initial value is the initiator count when the synchronization signal is sent, and wherein the offset is based on the propagation delay between the initiator and the receiver.

2. The PWM system of claim 1, wherein the propagation delay is based on the physical distance between the receiver and the initiator.

3. The PWM system according to claim 1, wherein the period of the starter PWM signal is different from the period of the receiver PWM signal.

4. The PWM system according to claim 3, The initiator is configured to reset the initiator count in response to the synchronization signal or a trigger that causes the generation of the synchronization signal; and The offset is determined in response to the physical distance between the initiator and the receiver.

5. The PWM system according to claim 1, further comprising: Communication lines; The initiator is configured in the hardware execution layer to generate the synchronization signal, output the synchronization signal to the communication line, and reset the initiator count; and The receiver is configured, in the hardware execution layer, to receive the synchronization signal from the communication line, detect the synchronization signal, and reset the receiver count.

6. The PWM system of claim 1, wherein the starter is configured to output data and the synchronization signal to the same communication line.

7. The PWM system of claim 1, wherein the starter is configured in hardware to generate the synchronization signal in response to a trigger condition determined in hardware in the starter and detected in the hardware execution layer of the starter.

8. The PWM system according to claim 1, The starter is configured to output the starter PWM signal as a first control signal; and The receiver is configured to output the receiver PWM signal as a second control signal.

9. A pulse width modulation system, i.e., a PWM system, comprising: Receiver, the receiver comprising: Receiver input; Receiver clock signal input; A receiver counter, which advances the receiver count in response to a receiver clock signal received at the receiver clock signal input; A receiver PWM signal generator is configured to generate a receiver PWM signal in response to the receiver count; as well as A circuit system configured to reset the receiver count to a predetermined initial value plus an offset in response to receiving a synchronization signal at the receiver input, wherein the offset is based on the propagation delay between the receiver and the transmission source of the synchronization signal.

10. The PWM system according to claim 9, The offset is determined in response to the circuit-based delay from the input to the receiver to the completion of the reset receiver count action.

11. The PWM system of claim 9, wherein the receiver is configured to extract a first offset portion from the synchronization signal and add the first offset portion to a second offset portion stored in the receiver to generate the offset.

12. The PWM system of claim 9, wherein the receiver is configured to detect the synchronization signal in a hardware execution layer and reset the receiver count in response to the detected synchronization signal.

13. The PWM system according to claim 9, further comprising a communication line; The receiver input is coupled to the communication line; The receiver input is configured to receive the synchronization signal via the communication line; and The receiver input is configured to receive data via the communication line.

14. A method for pulse width modulation control, i.e., PWM control, comprising: In response to the starter clock signal, the starter counter is advanced using the starter; In response to the starter count, the starter is used to control the first controlled device; The initiator is used to generate a synchronization signal; The synchronization signal is transmitted from the initiator to the receiver; In response to the receiver clock signal, the receiver is used to advance the receiver count; In response to the receiver count, the receiver is used to control a second controlled device; The receiver is used to receive and detect the synchronization signal; as well as In response to the synchronization signal, the receiver count is reset to an initial value plus an offset value, wherein the initial value is the initiator count when the synchronization signal was sent, and wherein the offset value is based on the propagation delay between the initiator and the receiver.

15. The method of claim 14, wherein the propagation delay is based on the physical distance between the receiver and the initiator.

16. The method of claim 14, wherein the frequency of the initiator clock signal is different from the frequency of the receiver clock signal.

17. The method according to claim 16, The reset of the initiator is in response to the synchronization signal or a trigger that causes the generation of the synchronization signal; and The offset value is determined in response to the physical distance between the initiator and the receiver.

18. The method according to claim 14, The synchronization signal is generated using a hardware execution layer in the initiator, transmitted to the receiver, and the initiator count is reset; and The receiver uses a hardware execution layer to receive the synchronization signal, detect the synchronization signal, and adjust the receiver count by resetting the receiver count.

19. The method of claim 14, further comprising using the same communication line as that used to transmit the synchronization signal to transmit data from the initiator to the receiver.

20. The method of claim 14, wherein generating the synchronization signal is performed in response to a trigger determined in hardware in the initiator.

21. The method of claim 14, wherein generating the synchronization signal is performed in response to a triggering condition determined in hardware in the initiator and detected in the hardware execution layer of the initiator.

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