Graphical High-Level Integrated Circuit Performance Analysis Method, System, Device and Medium

Abstract

The graphical high-level synthesis circuit performance analysis method, system, device and medium provided by the present invention, the method includes the following steps: obtaining the target circuit requirements, determining the test stimulus program code and the hardware module code according to the target circuit requirements; performing compilation conversion on the test stimulus program code to obtain the software description code; performing compilation conversion on the hardware module code to obtain the hardware description code, and performing forward compilation according to the hardware description code to obtain the register transfer level code; performing reverse compilation according to the register transfer level code to obtain the hardware simulation model; performing code instrumentation, performing simulation compilation on the instrumented hardware simulation model to obtain the hardware simulation description code; performing co-simulation, and visually displaying the performance data and the simulation process of the simulation result; greatly reducing the cost consumption brought by manual analysis, and at the same time improving the design efficiency of high-level synthesis according to the characteristics of the simulation model, and can be widely applied to the field of circuit simulation technology.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit simulation, in particular to a graphical high-level synthesis circuit performance analysis method, system, device and medium. Background Art

[0002] The core function of high-level synthesis is to automatically convert the behavior-level functions described in high-level languages into hardware description languages. High-level languages refer to programming languages with a relatively high level of abstraction. Common high-level languages include C++, C, Python, etc.; while hardware description languages generally refer to Verilog HDL, VHDL, SystemVerilog, etc., which are characterized by being directly applicable to modeling hardware circuits. During the conversion process, in addition to implementing the corresponding behavior-level functions using hardware circuits, designers often also need to care about the timing performance of the final result, such as the delay conditions of each module in the circuit, the arrangement of pipelines, and the throughput of the overall hardware design.

[0003] In order to ensure that the circuit performance meets the expectations of designers, after obtaining the hardware code generated by high-level synthesis, it is often necessary to perform performance analysis on the circuit. Traditional performance analysis methods generally involve manually reasoning and analyzing the hardware code generated by high-level synthesis. This method usually requires designing excitation signals, then building a simulation platform to test the code, and analyzing the interface signals (waveforms) generated by the simulation. However, for circuits with complex circuit structures and a large number of logic gates, manual analysis is not only time-consuming and laborious, but also prone to omissions and errors; at the same time, during the hardware design process, when it is found that a certain performance does not meet the standard or the circuit function is incomplete, it is often necessary to repeatedly adjust the high-level code and the hardware circuit.

[0004] Therefore, if only relying on human resources to analyze the circuit, it will lead to very low design efficiency of high-level synthesis, and at the same time greatly increase the labor cost and time cost. Summary of the Invention

[0005] In view of this, in order to at least partially solve one of the above technical problems or defects, the purpose of the embodiments of the present invention is to provide a graphical high-level synthesis circuit performance analysis method to improve the efficiency and stability of hardware development; in addition, the embodiments also provide a system, a device, and a storage medium capable of implementing this method.

[0006] On the one hand, the technical solution of the present application provides a graphical high-level synthesis circuit performance analysis method, including the following steps:

[0007] Obtain the target circuit requirements, and determine the test excitation program code and the hardware module code according to the target circuit requirements;

[0008] Compile and convert the test stimulus program code to obtain software description code;

[0009] Compile and convert the hardware module code to obtain hardware description code, and perform forward compilation according to the hardware description code to obtain register transfer level code;

[0010] Perform reverse compilation according to the register transfer level code to obtain a hardware simulation model;

[0011] Insert sampling code into the hardware simulation model, and perform simulation compilation on the hardware simulation model after inserting the sampling code to obtain hardware simulation description code;

[0012] Perform co-simulation according to the software description code and the hardware simulation description code, and visually display the performance data and simulation process of the simulation results.

[0013] In a feasible embodiment of the solution of this application, the step of obtaining the target circuit requirements and determining the test stimulus program code and the hardware module code according to the target circuit requirements includes:

[0014] Determine the hardware function requirements in the target circuit requirements;

[0015] According to the hardware function requirements, perform function encapsulation through keywords and control statements in a high-level programming language to obtain the hardware module code.

[0016] In a feasible embodiment of the solution of this application, the step of compiling and converting the hardware module code to obtain hardware description code and performing forward compilation according to the hardware description code to obtain register transfer level code includes:

[0017] Perform high-level synthesis optimization on the hardware description code, and create a data flow and a control structure according to the optimization result;

[0018] Integrate the data flow and the control structure to obtain the register transfer level code.

[0019] In a feasible embodiment of the solution of this application, the step of inserting sampling code into the hardware simulation model, performing simulation compilation on the hardware simulation model after inserting the sampling code to obtain hardware simulation description code includes:

[0020] Determine the high-level programming language of the hardware module code, and determine the sampling function declared in the high-level programming language according to the writing format of the high-level programming language;

[0021] Determine the starting position of the sampling function, and insert the sampling function into the hardware simulation model according to the starting position.

[0022] In a feasible embodiment of the solution of the present application, inserting sampling code into the hardware simulation model, and performing simulation compilation on the hardware simulation model after inserting the sampling code to obtain a hardware simulation description code further includes at least one of the following steps:

[0023] Recording the hierarchical structure of the hardware modules in the hardware simulation model through the sampling function;

[0024] Recording the types of the hardware modules in the hardware simulation model through the sampling function;

[0025] Recording the clock cycle count of the hardware circuit corresponding to the hardware simulation model through the sampling function.

[0026] In a feasible embodiment of the solution of the present application, performing co-simulation according to the software description code and the hardware simulation description code, and visually displaying the performance data and the simulation process of the simulation result includes at least one of the following steps:

[0027] Constructing a timeline according to the front and back delay relationships between the hardware modules, and visually displaying the timeline;

[0028] Visually displaying the module hierarchical structure of the hardware simulation model;

[0029] Determining a timing relationship according to the delay overlap between the hardware modules, and visually displaying the timing relationship.

[0030] In a feasible embodiment of the solution of the present application, performing co-simulation according to the software description code and the hardware simulation description code, and visually displaying the performance data and the simulation process of the simulation result further includes:

[0031] Obtaining the log file generated by the sampling function, obtaining the performance data from the log file, and visually displaying the performance data.

[0032] On the other hand, a graphical high-level synthesis circuit performance analysis system includes:

[0033] A requirement acquisition unit, configured to acquire target circuit requirements, and determine a test stimulus program code and a hardware module code according to the target circuit requirements;

[0034] A software coding unit, configured to compile and convert the test stimulus program code to obtain a software description code;

[0035] A forward compilation unit, configured to compile and convert the hardware module code to obtain a hardware description code, and perform forward compilation according to the hardware description code to obtain a register transfer level code;

[0036] A reverse compilation unit, configured to perform reverse compilation according to the register transfer level code to obtain a hardware simulation model;

[0037] A model construction unit, configured to insert sampling code into the hardware simulation model, and perform simulation compilation on the hardware simulation model after inserting the sampling code to obtain a hardware simulation description code;

[0038] A visualization unit, configured to perform co-simulation according to the software description code and the hardware simulation description code, and visually display the performance data and simulation process of the simulation result.

[0039] On the other hand, the technical solution of the present application further provides a graphical high-level integrated circuit performance analysis device, and the device includes:

[0040] At least one processor;

[0041] At least one memory, configured to store at least one program;

[0042] When the at least one program is executed by the at least one processor, the at least one processor runs the graphical high-level integrated circuit performance analysis method according to any one of the first aspect.

[0043] On the other hand, the technical solution of the present application further provides a storage medium, in which a processor-executable program is stored, and the processor-executable program is used to execute the graphical high-level integrated circuit performance analysis method according to any one of the first aspect when executed by a processor.

[0044] The advantages and beneficial effects of the present invention will be partially given in the following description, and the other parts can be understood through the specific implementation manners of the present invention:

[0045] The technical solution of this application provides a graphical high-level synthesis circuit performance analysis method, system, device, and medium. The method constructs a test stimulus program code and a hardware module code based on the requirements of the target circuit, then compiles them separately through a compilation tool, and successively performs forward compilation on the hardware module code part to obtain register transfer level code, and reverse compiles the RTL code to obtain a hardware simulation model. During the process of constructing the simulation model, sampling code is inserted into the value model through code instrumentation. Finally, simulation is performed through the hardware simulation description code and the software description code, and the results obtained from the simulation are visualized. The solution greatly reduces the cost consumption caused by manual analysis through the conversion between codes and based on the code descriptions of hardware and software, and at the same time improves the design efficiency of high-level synthesis according to the characteristics of the simulation model. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for description in the embodiments. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0047] Figure 1 It is a flowchart of the steps of the graphical high-level synthesis circuit performance analysis method provided in the technical solution of this application;

[0048] Figure 2 It is a flowchart of the steps of another graphical high-level synthesis circuit performance analysis method provided in the technical solution of this application;

[0049] Figure 3 It is a schematic diagram of the graphical interface of performance data in the technical solution of this application;

[0050] Figure 4 It is a flowchart of the steps of graphical performance analysis based on the SHANG high-level synthesis tool in the technical solution of this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0051] The following details the embodiments of the present invention. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions from beginning to end. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present invention and should not be construed as a limitation of the present invention. For the step numbers in the following embodiments, they are only set for the convenience of explanation and illustration, and no limitation is imposed on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0052] First, some technical terms in the technical solution of this application are explained:

[0053] High-level Synthesis (HLS) refers to the process of automatically converting the logical structure described in a high-level language into a circuit model described in a low-level abstraction language. HLS tools can reduce the design time of hardware engineers and also enable software engineers to complete hardware design.

[0054] LLVM (Low Level Virtual Machine) is a compiler framework. As a compiler framework, LLVM requires various functional modules to support it. Both clang and lld can be regarded as components of LLVM. According to the characteristics of its framework, one can develop one's own modules based on the functions provided by LLVM, integrate them into the LLVM system to increase its functions, or use LLVM to support the underlying implementation during the development of software tools.

[0055] Regarding what is pointed out in the background of the specification, in the related technical solutions, there is a problem that the design efficiency of high-level synthesis is very low due to over-reliance on manual analysis methods, and at the same time, the labor cost and time cost are greatly increased. First, in the first aspect, as Figure 1 shown, the embodiments of the present invention first propose a graphical high-level synthesis circuit performance analysis method, and the method includes steps S100 - S600:

[0056] S100. Obtain the target circuit requirements, and determine the test stimulus program code and the hardware module code according to the target circuit requirements;

[0057] Among them, the target circuit refers to the hardware circuit that needs to perform high-level synthesis performance analysis. Specifically in the embodiment, in the embodiment, a core code of a double-precision floating-point adder can be generated through a general programming language, such as C language, as the hardware simulation model code in the embodiment; at the same time, a test program is generated, which includes the test stimulus program code.

[0058] In some feasible embodiment manners, step S100 of the embodiment method for obtaining the target circuit requirements and determining the test stimulus program code and the hardware module code according to the target circuit requirements may include steps S110 - S120:

[0059] S110. Determine the hardware function requirements in the target circuit requirements;

[0060] S120. According to the hardware function requirements, perform function encapsulation through keywords and control statements in a high-level programming language to obtain the hardware module code;

[0061] Specifically, in the embodiments, it is first necessary to generate test stimulus program code and hardware module code based on high-level languages such as C, C++, and Python. The process of generating the hardware module code is to model the hardware functions that the target circuit needs to implement. During the modeling process, keywords and control statements provided by the high-level language can be used. The top-level hardware module is encapsulated in the form of a function, and the input and output of the function correspond to the input and output of the hardware module. In addition, the designed test stimulus program code needs to include the following steps: generating test vectors, calling the hardware module and sending the test vectors, and verifying whether the returned results are correct.

[0062] S200. Compile and convert the test stimulus program code to obtain software description code;

[0063] As Figure 2 shown, specifically, in the embodiments, after the test stimulus program code is generated through step S100, it is compiled by the front-end compilation tool of LLVM. The compilation and conversion process in the embodiments mainly relies on the automatic implementation of this tool. After the conversion is completed, the intermediate representation (Intermediate Representation, IR) of the test stimulus program code part is obtained. In the embodiments, the LLVM-IR description form uses the underlying instruction set (LLVM-specific assembly instruction set), which can provide high-level information for subsequent analysis and optimization while keeping the code form relatively simple.

[0064] S300. Compile and convert the hardware module code to obtain hardware description code, and perform forward compilation according to the hardware description code to obtain register transfer level code;

[0065] Among them, the process of converting from a high-level language to register transfer level (RTL) code is called forward compilation. As Figure 2 shown, specifically, in the embodiments, similar to the compilation process of the test stimulus program code, the embodiments compile through the front-end compilation tool of LLVM to generate the intermediate representation IR of the hardware part for the input hardware module code. The RTL code is obtained through the conversion of the compiled language for the obtained intermediate representation IR of the hardware part.

[0066] S400. Perform reverse compilation according to the register transfer level code to obtain a hardware simulation model;

[0067] Specifically in the embodiment, the RTL code obtained according to step S300 is simulated; first, the embodiment needs to perform reverse compilation on the RTL code, and the purpose is to obtain a hardware simulation model described in a high-level language. More specifically, in the embodiment, reverse compilation can be performed through a hardware code compilation tool, such as Verilator, v2c, etc.; for example, the RTL code can be compiled back to a C++ model through a hardware code compilation tool.

[0068] S500. Insert sampling code into the hardware simulation model, and perform simulation compilation on the hardware simulation model after inserting the sampling code to obtain hardware simulation description code;

[0069] Specifically in the embodiment, after obtaining the high-level language description of the simulation model through step S400, code instrumentation is performed on the code in the simulation model to track the running status of each module during the simulation; among them, code instrumentation refers to adding additional event sampling code to the program.

[0070] S600. Perform co-simulation according to the software description code and the hardware simulation description code, and visually display the performance data of the simulation results and the simulation process;

[0071] As Figure 2 shown, specifically in the embodiment, the hardware simulation model code after instrumentation is compiled by the LLVM of the simulation tool to generate an IR file of the hardware simulation model, and the software IR is sent to the software and hardware co-simulation platform for simulation together; among them, the programs that need to be set in the software and hardware co-simulation platform include: a simulation process control program, a performance data collection program, a simulation result display program, and a performance data visualization program. In the embodiment, the simulation process control program is written based on the TCL script, and its main functions include: controlling the environment variables of the simulator, declaring input files, declaring output files, jumping to the sub-project directory, and controlling the simulation process. In addition, the simulation result display program is implemented based on QT, and its main functions include: printing the execution status of each step during the simulation in the result window, and simultaneously displaying the results output in the test stimulus program.

[0072] In some feasible implementation manners, in step S300 of the embodiment method, the hardware module code is compiled and converted to obtain hardware description code, and forward compilation is performed according to the hardware description code to obtain register transfer level code, which may include step S310 and step S320:

[0073] S310. Perform high-level synthesis optimization on the hardware description code, and create a data flow and a control structure according to the optimization result; S320. Integrate the data flow and the control structure to obtain the register transfer level code;

[0074] Specifically in the embodiments, the LLVM IR file of the hardware module code first needs to go through the optimization process of high-level synthesis. The high-level synthesis tool creates corresponding data flow and control structures according to the results of the scheduling and resource binding processes, and finally synthesizes the RTL code describing the hardware circuit.

[0075] In some feasible implementation manners, in step S500 of the embodiment method, inserting sampling code into the hardware simulation model, and performing simulation compilation on the hardware simulation model after inserting the sampling code to obtain the hardware simulation description code may include steps S510 - S520:

[0076] S510. Determine the high-level programming language of the hardware module code, and determine the sampling functions declared in the high-level programming language according to the writing format of the high-level programming language;

[0077] S520. Determine the starting position of the sampling function, and insert the sampling function into the hardware simulation model according to the starting position;

[0078] Specifically in the embodiments, the process of code instrumentation is as follows: Read the C++ code of the hardware module, determine all the functions declared in the code according to the writing format of functions in C++; Determine the starting position of each function according to the key characters, and insert the code block of the event sampling function at this position; Search the entire code file and modify each function; Save the modified code to the hard disk.

[0079] In some feasible implementation manners, in step S500 of the embodiment method, inserting sampling code into the hardware simulation model, and performing simulation compilation on the hardware simulation model after inserting the sampling code to obtain the hardware simulation description code may further include steps S530 - S550:

[0080] S530. Record the hierarchical structure of the hardware modules in the hardware simulation model through the sampling function;

[0081] S540. Record the types of the hardware modules in the hardware simulation model through the sampling function;

[0082] S550. Record the clock cycle count of the hardware circuit corresponding to the hardware simulation model through the sampling function;

[0083] Specifically in the embodiments, the instrumentation of the code does not affect the specific behavioral functions of the hardware simulation model. The content recorded by the event sampling function includes but is not limited to the following:

[0084] Hierarchical structure of the hardware circuit module; The hierarchical structure of the hardware circuit is crucial for performance analysis. By analyzing the hierarchical structure within each module, the data dependence relationships within the circuit can be analyzed, which is beneficial for constructing an appropriate pipeline and performing targeted optimization on the circuit.

[0085] Types of hardware circuit modules; When using a high-level synthesis tool to generate hardware modules, various different types of modules will be automatically generated, such as data reading modules, calculation modules, and data write-back modules.

[0086] Clock cycle counting at runtime; The timing of the hardware circuit generally uses the number of clock cycles as the calculation unit. Therefore, when the program calls the current module, only by recording the clock cycles at the current runtime can the specific position of the module on the timeline be determined, which is used for subsequent timing logic analysis.

[0087] In some feasible embodiments, in the method of the embodiment, step S600, co-simulating according to the software description code and the hardware simulation description code, and visually displaying the performance data and the simulation process of the simulation result, may include steps S610 - S630:

[0088] S610, constructing a timeline based on the front-back delay relationship between the hardware modules and visually displaying the timeline;

[0089] S620, visually displaying the module hierarchical structure of the hardware simulation model;

[0090] S630, determining the timing relationship according to the delay overlap between the hardware modules and visually displaying the timing relationship;

[0091] Specifically in the embodiment, to facilitate developers' analysis of the hardware design, the embodiment also provides a presentation method based on a graphical interface, the schematic diagram of which is as Figure 3 shown. As Figure 3 shown, this graphical interface is implemented based on QtableWidget of QT. The first row in the plug-in is set as the number of clock cycles, such as C0, C1... Cn. The first column on the left is used to present the hierarchical structure of the modules, and the main part of the plug-in is used to present the execution status of each module in different clock cycles. The content that can be displayed in the graphical interface 301 includes but is not limited to:

[0092] Timeline 302; In the graphical interface of the performance data, the basic unit of the timeline is one clock cycle. Further, the timeline does not need to display all the clock cycles executed during the simulation. Since the visualization result only shows the front-back delay relationship between the hardware modules to the developers, the timeline only needs to satisfy one complete data transfer process.

[0093] Program hierarchy 303; In the hardware code generated by high-level synthesis, a large module is often composed of several small modules spliced together. Developers need to understand the module hierarchy of the hardware as much as possible in order to optimize the circuit targeted. Further, in the graphical interface, the module hierarchy should be arranged from coarse to fine, and the delay of the upper-layer module is composed of the delays of each lower-layer module.

[0094] Timing relationship visualization area 304; Mainly display the timing relationships of each module. Further, since there are often parallel executions in the hardware circuit, that is, the previous module has not finished executing while the next module has already started executing. Therefore, the delays between modules are allowed to overlap.

[0095] In some feasible embodiments, in the method of the embodiment, step S600, perform co-simulation according to the software description code and the hardware simulation description code, and visually display the performance data and the simulation process of the simulation result, may further include step S640:

[0096] S640, obtain the log file generated by the sampling function, obtain the performance data from the log file, and visually display the performance data;

[0097] Specifically in the embodiment, during the visualization process, the performance data collection program can be a text processing program written in C. Its main function is to automatically process the log file generated by the event sampling function, and extract the hierarchy of each module, the type of each module, and the start time and end time of module operation. After collection, the performance data is saved in the form of a text file on the local hard disk.

[0098] Combined with the attached Figure 4 description of the drawings, a complete description of the implementation process of the technical solution of this application is given:

[0099] First, design the core code and test program of a double-precision floating-point adder using C language, and then use the Clang front-end tool to compile and convert the code file designed in C language into adder IR and test program IR. The Clang front-end is a C / C++ / Objective-C compiler based on LLVM.

[0100] Based on the high-level synthesis tool SHANG, perform multi-level optimization on the IR of the adder, and finally synthesize and generate the RTL code implementation of the adder. The Shang high-level synthesis tool is a high-level synthesis system developed by the EDA research group of the School of Electronics and Information Engineering, Sun Yat-sen University.

[0101] Verilator is a cycle-accurate open-source simulator that supports Verilog HDL / SystemVerilog. In this embodiment, the Verilator compilation tool is used to synthesize the RTL code of the adder circuit into a C++ simulation model.

[0102] After that, code instrumentation is performed on the hardware simulation model (C++). A pre-designed code reading program is used to parse the simulation model code, and then an event sampling function is inserted into each module in the adder. Finally, it is saved again to the new project code path.

[0103] In this embodiment, a front-end compiler for the simulation program is developed based on Clang, and the simulation model code of the adder with instrumentation is compiled into a hardware simulation model IR. The generated hardware simulation model IR and the test program IR are sent to a software and hardware co-simulation platform for simulation. The simulation platform is built based on python, which includes a simulation process control program, a performance data collection program, a simulation result display program, and a performance data visualization program.

[0104] The simulation process control program first further compiles the input IR file into an executable file. During the compilation process, checks are performed. If the interfaces do not match or there are compilation errors, the designer is reminded to make modifications.

[0105] After successful compilation, the performance data collection program thread is first started, and then another thread is started to execute the simulation program. According to the order of clock cycles, the co-simulation program is gradually executed. During this period, the performance data collection program keeps running and obtains the collected data from the memory.

[0106] After the simulation ends, the simulation process control program closes the performance data collection program thread and loads all the collected data into the memory for visualization. The visualization interface is built using pyside. Among them, the performance data presentation window is drawn using QT, and the execution order and delay time of each module in the double-precision floating-point adder are described in the graphical interface.

[0107] On the other hand, the embodiment of the present invention also provides a graphical high-level synthesis circuit performance analysis system, which includes:

[0108] A requirement acquisition unit, configured to acquire target circuit requirements, and determine test stimulus program code and hardware module code according to the target circuit requirements;

[0109] A software coding unit, configured to compile and convert the test stimulus program code to obtain software description code;

[0110] A forward encoding unit, configured to compile and convert the hardware module code to obtain a hardware description code, and perform forward compilation according to the hardware description code to obtain a register transfer level code;

[0111] A reverse compilation unit, configured to perform reverse compilation according to the register transfer level code to obtain a hardware simulation model;

[0112] A model construction unit, configured to insert sampling code into the hardware simulation model, and perform simulation compilation on the hardware simulation model after inserting the sampling code to obtain a hardware simulation description code;

[0113] A visualization unit, configured to perform co-simulation according to the software description code and the hardware simulation description code, and visually display the performance data and simulation process of the simulation result.

[0114] On the other hand, the technical solution of the present application further provides a graphical high-level integrated circuit performance analysis device; it includes:

[0115] At least one processor; at least one memory, where the memory is used to store at least one program; when at least one program is executed by at least one processor, at least one processor runs the graphical high-level integrated circuit performance analysis method as in the first aspect.

[0116] The embodiment of the present invention further provides a storage medium, which stores a corresponding execution program, and the program is executed by a processor to implement the graphical high-level integrated circuit performance analysis method in the first aspect.

[0117] From the above specific implementation process, it can be summarized that the technical solution provided by the present invention has the following advantages or advantages compared with the prior art:

[0118] In addition, although the present invention is described in the context of functional modules, it should be understood that, unless otherwise stated to the contrary, one or more of the functions and / or features may be integrated in a single physical device and / or software module, or one or more functions and / or features may be implemented in separate physical devices or software modules. It can also be understood that a detailed discussion of the actual implementation of each module is not necessary for understanding the present invention. More precisely, considering the attributes, functions, and internal relationships of the various functional modules in the devices disclosed herein, the actual implementation of the modules will be understood within the ordinary skills of an engineer. Therefore, those skilled in the art can implement the present invention as set forth in the claims without undue experimentation using ordinary skills. It can also be understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present invention, and the scope of the present invention is determined by the full scope of the appended claims and their equivalents.

[0119] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a definitional sequence list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or used in combination with these instruction execution systems, apparatuses, or devices.

[0120] In the description of this specification, the descriptions with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0121] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and purposes of the present invention, and the scope of the present invention is defined by the claims and their equivalents.

[0122] The above has specifically described the preferred embodiments of the present invention, but the present invention is not limited to the above embodiments. Those skilled in the art can also make various equivalent deformations or substitutions without departing from the spirit of the present invention, and these equivalent deformations or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A graphical high-level synthesis circuit performance analysis method, characterized in that, Including the following steps: Obtain the target circuit requirements, and determine the test stimulus program code and the hardware module code according to the target circuit requirements; Compile and convert the test stimulus program code to obtain the software description code; Compile and convert the hardware module code to obtain the hardware description code, and perform forward compilation according to the hardware description code to obtain the register transfer level code; Perform reverse compilation according to the register transfer level code to obtain the hardware simulation model; Insert sampling code into the hardware simulation model, and perform simulation compilation on the hardware simulation model after inserting the sampling code to obtain the hardware simulation description code; Perform co-simulation according to the software description code and the hardware simulation description code, and visually display the performance data and the simulation process of the simulation results; The step of inserting sampling code into the hardware simulation model, performing simulation compilation on the hardware simulation model after inserting the sampling code to obtain the hardware simulation description code includes: Determine the high-level programming language of the hardware module code, and determine the sampling function declared in the high-level programming language according to the writing format of the high-level programming language; Determine the starting position of the sampling function, and insert the sampling function into the hardware simulation model according to the starting position; The step of inserting sampling code into the hardware simulation model, performing simulation compilation on the hardware simulation model after inserting the sampling code to obtain the hardware simulation description code further includes at least one of the following steps: Record the hierarchical structure of the hardware modules in the hardware simulation model through the sampling function; Record the types of the hardware modules in the hardware simulation model through the sampling function; Record the clock cycle count of the hardware circuit corresponding to the hardware simulation model through the sampling function.

2. The graphical high-level integrated circuit performance analysis method according to claim 1, wherein The step of obtaining the target circuit requirements, and determining the test stimulus program code and the hardware module code according to the target circuit requirements includes: Determine the hardware function requirements in the target circuit requirements; According to the hardware function requirements, perform function encapsulation through keywords and control statements in the high-level programming language to obtain the hardware module code.

3. The method for analyzing the performance of a graphically high-level integrated circuit according to claim 1, wherein The step of compiling and converting the hardware module code to obtain the hardware description code, and performing forward compilation according to the hardware description code to obtain the register transfer level code includes: Perform high-level synthesis optimization on the hardware description code, and create a data flow and a control structure according to the optimization result; Integrate the data flow and the control structure to obtain the register transfer level code.

4. The graphical high-level integrated circuit performance analysis method according to claim 1, wherein The step of performing co-simulation according to the software description code and the hardware simulation description code, and visually displaying the performance data and the simulation process of the simulation results includes at least one of the following steps: Construct a timeline according to the forward and backward delay relationships between the hardware modules, and visually display the timeline; Visually display the module hierarchical structure of the hardware simulation model; Determine the timing relationship according to the delay overlap between the hardware modules, and visually display the timing relationship.

5. The method for analyzing the performance of a graphically high-level integrated circuit according to claim 4, wherein Performing co-simulation based on the software description code and the hardware simulation description code, and visually displaying the performance data of the simulation result and the simulation process, further includes: Obtaining the log file generated by the sampling function, obtaining the performance data from the log file, and visually displaying the performance data.

6. A system for implementing the graphical high-level synthesis circuit performance analysis method according to any one of claims 1-5, characterized in that, Including: A requirement acquisition unit, configured to acquire target circuit requirements, and determine a test stimulus program code and a hardware module code according to the target circuit requirements; A software coding unit, configured to compile and convert the test stimulus program code to obtain a software description code; A forward coding unit, configured to compile and convert the hardware module code to obtain a hardware description code, and perform forward compilation according to the hardware description code to obtain a register transfer level code; A reverse compilation unit, configured to perform reverse compilation according to the register transfer level code to obtain a hardware simulation model; A model construction unit, configured to insert sampling code into the hardware simulation model, and perform simulation compilation on the hardware simulation model after inserting the sampling code to obtain a hardware simulation description code; A visualization unit, configured to perform co-simulation according to the software description code and the hardware simulation description code, and visually display the performance data of the simulation result and the simulation process.

7. Graphic high-level integrated circuit performance analysis device, characterized in that, Including: At least one processor; At least one memory, configured to store at least one program; When the at least one program is executed by the at least one processor, the at least one processor runs the graphical high-level integrated circuit performance analysis method according to any one of claims 1-5.

8. A storage medium storing a program executable by a processor, characterized in that, The program executable by the processor, when executed by the processor, is used to run the graphical high-level integrated circuit performance analysis method according to any one of claims 1-5.

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