Control circuit and memory

Abstract

An embodiment of the present application provides a control circuit and a memory. The control circuit includes: an external data line for receiving original data and an original ECC check code; a first check module for detecting and / or correcting errors according to the original ECC check code when a data transmission error occurs, and outputting the corrected data and the corrected ECC check code; a comparison module for bit-by-bit detecting whether the data on the external data line is the same as the data on the global data line, and outputting a detection result; a counting module for receiving a switching control signal, when the switching control signal is in a first state, for counting the output result of the comparison module and outputting a first control signal; when the switching control signal is in a second state, for counting the high-level data in the corrected data and the corrected ECC check code output by the first check module, and outputting a second control signal and a parity code. The embodiment of the present application aims to reduce the low power consumption of the data transmission line and improve the reliability of data storage, etc.

Description

Technical Field

[0001] The present application relates to the field of semiconductor circuit design, and in particular to a control circuit and a memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) is widely used in modern electronic systems due to its high storage density and fast transmission speed. With the development of semiconductor technology, DRAM technology is becoming more and more advanced, and the integration of storage units is becoming higher and higher; at the same time, various applications have higher and higher requirements on DRAM performance, power consumption and reliability, such as DDR5 and LPDDR5.

[0003] However, the existing memory data transmission lines with error detection and correction (ECC) functions still have room for improvement in power consumption, reliability, etc. There is an urgent need to design an ECC memory that can reduce data transmission power consumption and improve storage reliability, and further improve the comprehensive performance of the existing ECC memory to meet the needs of various application scenarios. Summary of the invention

[0004] The embodiments of the present application provide a control circuit and a memory to reduce the power consumption of a data transmission line and improve the reliability of data storage.

[0005] To solve the above technical problems, an embodiment of the present application provides a control circuit for writing data to and reading data from a storage unit, including: an external data line for receiving original data and an original ECC check code; a first check module connected to the external data line for performing error detection and / or error correction according to the original ECC check code when an error occurs in data transmission, and outputting corrected data and the corrected ECC check code, wherein if no error occurs in data transmission, the corrected data is consistent with the original data, and the corrected ECC check code is consistent with the original ECC check code; a comparison module connected to the external data line and the global data line for detecting bit by bit whether the data currently transmitted by the external data line is the same as the data currently transmitted by the global data line, and outputting the detection result of each bit; a counting module connected to the comparison module and the first check module for receiving a switching control signal, and when the switching control signal is in the first state, for comparing the data The output result of the module is counted, and a first control signal is outputted to indicate whether the difference between the original data, the original ECC check code and the data currently transmitted by the global data line exceeds a first preset value; when the switching control signal is in the second state, it is used to count the high-level data in the corrected data output by the first check module and the corrected ECC check code, and output a second control signal to indicate whether the number of bits occupied by the high-level data exceeds a second preset value, and output a parity code indicating whether the number of high-level data is an odd number or an even number; the second control signal and the parity code are stored in the storage unit as mark bit data, so that the second control signal and the parity code are read out in the process of reading data; wherein the first control signal is used to control whether the data to be written needs to be flipped in the write operation, the second control signal is used to control whether the data to be read needs to be flipped in the read operation, and the parity code is used to perform error detection and / or error correction on the data to be read in the read operation.

[0006] Compared with the related art, through a shared counting module, the number of differences between the original data, the original ECC check code and the data transmitted in the global data line is counted according to the switching control signal in time-sharing to obtain the first control signal, and the number of high levels in the corrected data and the corrected ECC check code is counted to obtain the second control signal, thereby saving circuit area; at the same time, the newly generated parity code is used together with the corrected ECC check code for subsequent error detection and correction of the data in the read operation, and the newly generated parity code together with the corrected ECC check code can detect 2-bit errors to enhance the error detection and correction capabilities in the memory and further improve the reliability of data storage.

[0007] In addition, the control circuit also includes: a data buffer module, which is connected to the first check module and the counting module, and is used to transmit the corrected data and the corrected ECC check code to the global data line or flip the corrected data and the corrected ECC check code and then transmit them to the global data line according to the first control signal.

[0008] In addition, the control circuit also includes: a write module, which is connected between the local data line and the global data line, controls the data in the global data line to be transmitted to the local data line, and based on a third control signal, determines whether data flipping is performed during the process of transmitting the data in the global data line to the local data line, wherein the third control signal is used to indicate whether the value of the first control signal is the same as the value of the second control signal.

[0009] In addition, the control circuit also includes: an array area reading unit, which is used to read the corrected data, the corrected ECC check code, the second control signal and the parity code in the storage cell to the local data line in a read operation, or to read the opposite value of the corrected data, the opposite value of the corrected ECC check code, the second control signal and the parity code in the storage cell to the local data line in a read operation.

[0010] In addition, the control circuit also includes: a second check module, which is used to determine whether an error occurs in the corrected data during storage based on the corrected ECC check code and parity code, and / or to correct the corrected data again if an error occurs; a read-out module, which is used to control whether the data on the local data line needs to be flipped when it is transmitted backward based on the read-out second control signal; if the number of bits occupied by the high-level data exceeds the second preset value, the read-out module is configured to ultimately transmit the opposite value of the data on the local data line to the second check module; if the number of bits occupied by the high-level data does not exceed the second preset value, the read-out module is configured to ultimately transmit the data on the local data line to the second check module.

[0011] In addition, the data buffer module includes: a conversion module, which is used to control whether the corrected data and the corrected ECC check code need to be flipped when they are transmitted to the global data line according to a first control signal; if the number of difference bits exceeds a first preset value, the conversion module is configured to flip the corrected data and the corrected ECC check code and transmit them to the global data line; if the number of difference bits does not exceed the first preset value, the conversion module is configured to transmit the corrected data and the corrected ECC check code to the global data line.

[0012] In addition, it is detected bit by bit whether the data currently transmitted by the external data line is the same as the data currently transmitted by the global data line, and the detection result of each bit is output, including: if the data transmitted by the current external data line is different from the data transmitted by the current global data line, a first sub-control signal is generated; if the data transmitted by the current external data line is the same as the data transmitted by the current global data line, a second sub-control signal is generated.

[0013] In addition, when the switching control signal is in the first state, the counting module is used to obtain the first sub-control signal and the second sub-control signal. If the number of first sub-control signals exceeds a first preset value, a first control signal is generated. The first preset value is a preset percentage of the sum of the number of first sub-control signals and the number of second sub-control signals.

[0014] In addition, the preset percentage is 50%.

[0015] In addition, the second preset value is 50% of the sum of the number of bits of the corrected data and the corrected ECC check code.

[0016] In addition, the writing module includes: an enabling control module, which is used to receive the first control signal and the second control signal, and output a third control signal used to indicate whether the first control signal and the second control signal are the same.

[0017] In addition, the enable control module is further used to receive a write enable signal, and if the write enable signal is at a valid level, output a third control signal used to indicate whether the first control signal and the second control signal are the same.

[0018] In addition, the local data line includes a first local data line and a second local data line which are differential data transmission lines; data flipping is performed during the process of transferring data in the global data line to the local data line, including: the writing module is configured to flip the data in the global data line and transfer it to the first local data line, and / or the writing module is configured to transfer the data in the global data line to the second local data line. By setting the first local data line and the second local data line for transmitting differential data, the stability of data flipping between the local data line and the global data line is ensured.

[0019] In addition, the writing module also includes: a first conversion circuit including a first MOS tube, a second MOS tube and a third MOS tube; the gate of the first MOS tube receives a third control signal, the source is connected to the global data line, and the drain is connected to the first local data line; the gate of the second MOS tube is connected to the global data line, the drain is connected to the second local data line, and the source is connected to the drain of the third MOS tube; the gate of the third MOS tube receives the third control signal, and the source is grounded.

[0020] In addition, the writing module also includes: a second conversion circuit including a fourth MOS tube, a fifth MOS tube and a sixth MOS tube; the gate of the fourth MOS tube receives a fourth control signal, the source is connected to the global data line, the drain is connected to the second local data line, and the third control signal and the fourth control signal are mutually inverted signals; the gate of the fifth MOS tube is connected to the global data line, the drain is connected to the first local data line, and the source is connected to the drain of the sixth MOS tube; the gate of the sixth MOS tube receives the fourth control signal, and the source is grounded.

[0021] In addition, the readout module is connected between the local data line and the global data line, and is used to control the data transmission between the local data line and the global data line according to the second control signal. If the number of bits occupied by the high-level data exceeds the second preset value, the readout module is configured to transmit the opposite value of the data in the local data line to the global data line; if the number of bits occupied by the high-level data does not exceed the second preset value, the readout module is configured to transmit the data in the local data line to the global data line.

[0022] In addition, the readout module connects the global data line and the second verification module, and is used to control the data transmission between the global data line and the second verification module according to the second control signal. If the number of bits occupied by the high-level data exceeds the second preset value, the readout module is configured to flip the data in the global data line and transmit it to the second verification module; if the number of bits occupied by the high-level data does not exceed the second preset value, the readout module is configured to transmit the data in the global data line to the second verification module.

[0023] In addition, the conversion module includes: a first transmission element, one end of which is connected to the first verification module through an inverter, and the other end is connected to the global data line; a second transmission element, one end of which is connected to the first verification module, and the other end is connected to the global data line; the first transmission element and the second transmission element are also used to receive a first control signal, and are used to select and turn on the first transmission element or the second transmission element according to the first control signal.

[0024] An embodiment of the present application also provides a memory, including the above-mentioned control circuit, and also including: a storage unit connected to a local data line, and the local data line is used to write data to and read data from the storage unit.

[0025] Compared with the related art, through a shared counting module, the number of differences between the original data, the original ECC check code and the data transmitted in the global data line is counted according to the switching control signal in time-sharing to obtain the first control signal, and the number of high levels in the corrected data and the corrected ECC check code is counted to obtain the second control signal, thereby saving circuit area; at the same time, the newly generated parity code is used together with the corrected ECC check code for subsequent error detection and correction of the data in the read operation, and the newly generated parity code together with the corrected ECC check code can detect 2-bit errors to enhance the error detection and correction capabilities in the memory and further improve the reliability of data storage. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of a control circuit provided in one embodiment of the present application;

[0027] Figure 2 A schematic diagram of the structure of a comparison module and a counting module provided in an embodiment of the present application;

[0028] Figure 3 A circuit diagram of a conversion module provided in one embodiment of the present application;

[0029] Figure 4 A circuit diagram of an enabling control module provided in an embodiment of the present application;

[0030] Figure 5 A circuit diagram of a first conversion circuit provided in an embodiment of the present application;

[0031] Figure 6 A circuit diagram of a second conversion circuit provided in an embodiment of the present application;

[0032] Figure 7 Corresponding to an embodiment of the present application Figure 1 A circuit diagram of a readout module;

[0033] Figure 8 A schematic diagram of the structure of another control circuit provided in one embodiment of the present application;

[0034] Fig. 9 Corresponding to an embodiment of the present application Figure 8 A circuit diagram of a readout module;

[0035] Fig.10 A schematic diagram of the structure of another control circuit provided in an embodiment of the present application;

[0036] Fig.11 A circuit diagram of a first writing circuit provided in an embodiment of the present application;

[0037] Fig.12 A circuit diagram of a second writing circuit provided in an embodiment of the present application;

[0038] Fig.13 Corresponding to an embodiment of the present application Fig.10 A circuit diagram of a readout module;

[0039] Fig.14 A schematic diagram of the structure of another control circuit provided in one embodiment of the present application;

[0040] Fig.15 Corresponding to an embodiment of the present application Fig.14 A circuit diagram of a readout module;

[0041] Fig.16 and Fig.17 A schematic diagram of the structure of a memory provided in another embodiment of the present application. DETAILED DESCRIPTION

[0042] With the advancement of technology, the integration of storage cells in memory is getting higher and higher, and the length of data transmission lines in storage cell arrays is getting longer and longer. In the process of storing and reading data in storage cells of the memory, a power saving algorithm is applied to the data transmission lines in the storage cell array. As the length of the data transmission lines in the storage cell array is getting longer and longer, the power consumption of writing and reading data in the storage cells is getting higher and higher; in addition, the applicant has found that the ability of DRAM to sense high levels is lower than the ability to sense low levels; at the same time, the leakage of accessing high-level data to the storage cells of DRAM is more serious than that of accessing low-level data.

[0043] To solve the above problems, an embodiment of the present application provides a control circuit for writing data to and reading data from a storage unit, including: an external data line for receiving original data and an original ECC check code; a first check module connected to the external data line for performing error detection and / or error correction according to the original ECC check code when an error occurs in data transmission, and outputting corrected data and the corrected ECC check code, wherein if no error occurs in data transmission, the corrected data is consistent with the original data, and the corrected ECC check code is consistent with the original ECC check code; a comparison module connected to the external data line and the global data line for detecting bit by bit whether the data currently transmitted by the external data line is the same as the data currently transmitted by the global data line, and outputting the detection result of each bit; a counting module connected to the comparison module and the first check module for receiving a switching control signal, and for comparing the comparison module with the first check module when the switching control signal is in the first state. The output result of the block is counted, and a first control signal is outputted to indicate whether the difference between the original data, the original ECC check code and the data currently transmitted by the global data line exceeds a first preset value; when the switching control signal is in the second state, it is used to count the high-level data in the corrected data output by the first check module and the corrected ECC check code, and output a second control signal to indicate whether the number of bits occupied by the high-level data exceeds a second preset value, and output a parity code indicating whether the number of high-level data is an odd number or an even number; the second control signal and the parity code are stored in the storage unit as mark bit data, so that the second control signal and the parity code are read out in the process of reading data; wherein the first control signal is used to control whether the data to be written needs to be flipped in the write operation, the second control signal is used to control whether the data to be read needs to be flipped in the read operation, and the parity code is used to perform error detection and / or error correction on the data to be read in the read operation.

[0044] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present application, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can also be implemented. The division of the following embodiments is for the convenience of description, and the specific implementation of the present application should not be construed as any limitation, and the various embodiments can be combined with each other and quoted from each other without contradiction.

[0045] Figure 1 A schematic diagram of a control circuit provided in this embodiment. Figure 2 A schematic diagram of the structure of the comparison module and the counting module provided in this embodiment, Figure 3 A circuit diagram of the conversion module provided in this embodiment, Figure 4 A circuit diagram of the enabling control module provided in this embodiment, Figure 5 A circuit diagram of a first conversion circuit provided in this embodiment, Figure 6 A circuit diagram of a second conversion circuit provided in this embodiment, Figure 7 The corresponding Figure 1 The circuit diagram of the readout module, Figure 8 A schematic diagram of another control circuit provided in this embodiment, Fig. 9 The corresponding Figure 8 The circuit diagram of the readout module, Fig.10 A schematic diagram of a control circuit according to another embodiment of the present invention is shown in FIG. Fig.11 A circuit diagram of a first writing circuit provided in this embodiment, Fig.12 A circuit diagram of a second writing circuit provided in this embodiment, Fig.13 The corresponding Fig.10 The circuit diagram of the readout module, Fig.14 A schematic diagram of the structure of another control circuit provided in this embodiment, Fig.15 The corresponding Fig.14 The circuit diagram of the readout module is as follows; the control circuit provided in this embodiment is further described in detail in conjunction with the accompanying drawings.

[0046] refer to Figure 1 , the control circuit 100 is used to write data into and read data from the storage unit 501, including:

[0047] The external data line DataBus is used to receive the original data and the original ECC check code. The original data is the data to be written into the memory, and the original ECC check code is the ECC check code corresponding to the original data. When the user passes through the error detection and correction module of the memory, the original data is error-checked and corrected by the original ECC check code.

[0048] It should be noted that the external data line DataBus mentioned in this embodiment is only to distinguish that it is not the same transmission line as the global data line YIO. The "external" in the external data line DataBus refers to the outside of the global data line YIO and the storage unit 501 array, not the data line outside the chip.

[0049] The first check module 105 is connected to the external data line DataBus, and is used to perform error detection and / or error correction according to the original ECC check code when an error occurs in data transmission, and output corrected data and a corrected ECC check code, wherein if no error occurs in data transmission, the corrected data is consistent with the original data, and the corrected ECC check code is consistent with the original ECC check code.

[0050] refer to Figure 1 and Figure 2 The comparison module 111 is connected to the external data line DataBus and the global data line YIO, and is used to detect bit by bit whether the data currently transmitted by the external data line DataBus is the same as the data currently transmitted by the global data line YIO, and output the detection result of each bit.

[0051] Specifically, if the data transmitted by the current external data line DataBus is different from the data transmitted by the current global data line YIO, a first sub-control signal is generated; if the data transmitted by the current external data line DataBus is the same as the data transmitted by the current global data line YIO, a second sub-control signal is transmitted. The method of generating the first sub-control signal and the second sub-control signal is referred to the following table:

[0052] DataBus Data YIO Data produce First place 0 1 The first sub-control signal Second Place 0 0 Second sub control signal Third Place 1 1 Second sub control signal Fourth Place 1 0 The first sub-control signal

[0053] The counting module 112 is connected to the comparison module 111 and the first verification module 105, and receives a switching control signal. When the switching control signal is in the first state, the counting module 112 is used to count the output result of the comparison module 105, and output a first control signal Flag representing whether the difference in the number of bits between the original data, the original ECC check code and the data currently transmitted by the global data line YIO exceeds a first preset value; the first control signal Flag is used to control whether the data to be written needs to be flipped in a write operation.

[0054] It should be noted that the switching control signal can be a control signal issued by an off-chip control chip of the memory (such as a processor, etc.), or it can be a control signal generated inside the memory. The first state of the switching control signal is a high level state in some embodiments, and can also be a low level state in other embodiments.

[0055] Specifically, when the switching control signal is in the first state, the counting module 112 is used to obtain the first sub-control signal and the second sub-control signal. If the number of the first sub-control signals exceeds the first preset value, the first control signal is generated. The first preset value is a preset percentage of the sum of the number of the first sub-control signals and the number of the second sub-control signals. The method of generating the first control signal Flag refers to the following table (taking the sum of the number of the first sub-control signal and the second sub-control signal as 40 as an example, which is only for illustration):

[0056] Preset percentage The first sub-control signal number Second sub-control signal quantity The first control signal Flag 40 18 22 1 50 23 17 1 60 22 18 0

[0057] It should be noted that, in this example, the preset percentage is 50%. By setting the preset percentage to 50%, it is ensured that when the number of difference bits between the original data, the original ECC check code and the data currently transmitted by the global data line YIO is greater than the same number of bits, a first control signal Flag is generated, and the original data and the original ECC check code are flipped and transmitted to the global data line YIO, thereby reducing the number of data flips in the global data line YIO and saving energy consumption during data transmission.

[0058] Continue to refer Figure 1 The control circuit 100 includes: a data buffer module 106, which is connected to the first check module 105 and the counting module 112, and is used to transmit the corrected data and the corrected ECC check code to the global data line YIO or flip the corrected data and the corrected ECC check code and transmit them to the global data line YIO according to the first control signal Flag.

[0059] It should be noted that the first error detection module 105 needs to undergo a first time delay to perform error detection and correction on the original data and the original ECC check code, and the comparison module 111 and the counting module need to undergo a second time delay to compare the original data, the original ECC check code and the data in the global data line YIO; wherein, error detection and correction and data comparison can be performed simultaneously, and in specific applications, the first time delay and the second time delay can be controlled to be equal to avoid extending the data writing time of the memory, that is, the acquisition of the first control signal Flag mentioned in the present application will not extend the data writing time of the memory.

[0060] Specifically, the data buffer module 106 includes:

[0061] The conversion module 101 is used to control whether the corrected data and the corrected ECC check code need to be flipped when they are transmitted to the global data line YIO according to the first control signal Flag.

[0062] For the conversion module 101, if the number of bits of difference between the corrected data and the corrected ECC check code and the data currently transmitted by the global data line YIO exceeds a first preset value, the conversion module 101 is configured to flip the corrected data and the corrected ECC check code and transmit them to the global data line YIO; if the number of bits of difference between the corrected data and the corrected ECC check code and the data currently transmitted by the global data line YIO does not exceed the first preset value, the conversion module 101 is configured to transmit the corrected data and the corrected ECC check code to the global data line YIO.

[0063] In one example, refer to Figure 3 The conversion module 101 includes: a third transmission element 303, one end of which is connected to the first verification module 105 through an inverter, and the other end is connected to the global data line YIO; a fourth transmission element 304, one end of which is connected to the first verification module 105, and the other end is connected to the global data line YIO; wherein the third transmission element 303 and the fourth transmission element 304 are also used to receive the first control signal Flag, and are used to select and turn on the third transmission element 303 or the fourth transmission element 304 according to the first control signal Flag.

[0064] This embodiment is described by taking the low level control of the third transmission element 303 and the fourth transmission element 304 as an example, and the details are as follows:

[0065] When the first control signal Flag is "1", the third transmission element 303 turns on the signal transmission line, and the first verification module 105 is connected to the global data line YIO through the inverter, so that the corrected data and the corrected ECC check code are flipped and transmitted to the global data line YIO; the fourth transmission element 304 turns off the signal transmission line. When the control signal Flag is "0", the third transmission element 303 turns off the signal transmission line, and the fourth transmission element 304 turns on the signal transmission line. At this time, the first verification module 105 is directly connected to the global data line YIO, so that the corrected data and the corrected ECC check code are directly transmitted to the global data line YIO.

[0066] It should be noted that, in other embodiments, different control methods can also be used to control the conduction of the third transmission element and the fourth transmission element. As long as the number of bits of the corrected data and the corrected ECC check code differing from the data currently transmitted by the global data line YIO exceeds a first preset value, the corrected data and the corrected ECC check code are flipped and transmitted to the global data line YIO; when the number of bits of the corrected data and the corrected ECC check code differing from the data currently transmitted by the global data line YIO does not exceed the first preset value, the corrected data and the corrected ECC check code are directly transmitted to the global data line YIO.

[0067] Continue to refer Figure 1 and Figure 2 , for the counting module 112, when the switching control signal is in the second state, it is used to count the high-level data in the corrected data and the corrected ECC check code output by the first check module 105, and output a second control signal 1 "more" indicating whether the number of bits occupied by the high-level data exceeds the second preset value. The second control signal 1 "more" is used to control whether the data to be read needs to be flipped during the read operation. The method of generating the second control signal 1 "more" refers to the following table (the corrected data and the corrected ECC check code constitute the data to be counted, and the second preset value is 50% of the number of bits to be counted as an example):

[0068] The number of medium and high levels to be counted The number of low and medium levels to be counted The second control signal 1 "more" 22 18 1 19 21 0

[0069] It should be noted that the second state of the switching control signal is a low level state in some embodiments, and may also be a high level state in other embodiments.

[0070] It should be noted that, in other embodiments, it can also be configured that when the number of high-level data in the corrected data and the corrected ECC check code is greater than the number of low-level data in the corrected data and the corrected ECC check code, the second control signal 1 "more" is 0; when the number of high-level data in the corrected data and the corrected ECC check code is less than the number of low-level data in the corrected data and the corrected ECC check code, the second control signal 1 "more" is 1.

[0071] In addition, the second control signal 1 "more" is stored in the storage unit 501 as flag bit data, so that the second control signal 1 "more" can be read out during the data reading process.

[0072] It should be noted that, in this example, the second preset value is 50%. By setting the second preset value to 50%, it is ensured that when the corrected data and the corrected ECC check code are stored in the storage unit 501, the amount of data stored in the low level is not less than the amount of data stored in the high level, thereby improving the reliability of storage and reading of the corrected data and the corrected ECC check code.

[0073] Continue to refer Figure 1 and Figure 2 When the switching control signal is in the second state, the counting module 112 outputs a parity code o / e indicating whether the number of high-level data bits is an odd number or an even number. The parity code o / e is used to perform error detection and / or error correction on the data to be read in the read operation.

[0074] In addition, the parity code o / e is stored in the storage unit 501 as a mark bit data, so that the parity code o / e can be read out during the process of reading out data.

[0075] The purpose of the parity code o / e is to enhance the error detection and correction function of the memory in subsequent read operations; for 128-bit data, the 8-bit check code can only detect 1-bit error and correct 1-bit error. After adding the parity code o / e, 2-bit errors can be detected and 1-bit error can be corrected.

[0076] Specifically, if the parity of the corrected data after reading and the corrected ECC check code is consistent with the parity code o / e, an error is found through the corrected ECC check code, which means that a 2-bit error has occurred and can no longer be repaired; no error is found through the corrected ECC check code, which means that no error has occurred in all data; if the parity of the corrected data after reading and the corrected ECC check code is inconsistent with the parity code o / e, an error is found through the corrected ECC check code, which means that a 1-bit error has occurred and can be repaired; no error is found through the corrected ECC check code, which means that an error has occurred in the parity code o / e (here it is assumed that at most 2-bit errors occur).

[0077] Continue to refer Figure 1 The control circuit 100 further includes: a write module 103 connected between the local data line LIO and the global data line YIO, controlling the data in the global data line YIO to be transmitted to the local data line LIO, and judging whether to perform data flipping in the process of transmitting the data in the global data line YIO to the local data line LIO based on the third control signal WrEn, wherein the third control signal WrEn is used to indicate whether the value of the first control signal Flag is the same as the value of the second control signal 1 "more". Specifically, the third control signal WrEn is used to control the number of data stored in the low level to be not less than the number of data stored in the high level.

[0078] In this embodiment, when the first control signal Flag is 1, it indicates that the corrected data and the corrected ECC check code need to be flipped when they are transmitted to the global data line YIO; when the second control signal 1 "more" is 1, it indicates that the corrected data and the corrected ECC check code need to be flipped when they are finally read out; at this time, the data has been flipped when it is transmitted to the global data line YIO, so there is no need to flip the data again when the data is finally read out, that is, when the third control signal WrEn is 1, the data does not need to be flipped. Correspondingly, when the first control signal Flag is 1, it indicates that the corrected data and the corrected ECC check code need to be flipped when they are transmitted to the global data line YIO; when the second control signal 1 "more" is 0, it indicates that the data does not need to be flipped when it is finally read out; at this time, the data has been flipped when it is transmitted to the global data line YIO, so the data needs to be flipped back when it is finally read out, that is, when the third control signal WrEn is 0, the data needs to be flipped. The configuration of the third control signal WrEn refers to the following table:

[0079] The first control signal Flag The second control signal 1 "more" The third control signal WrEn Flip Flip No flip Flip No flip Flip No flip Flip Flip No flip No flip No flip

[0080] It should be noted that when the setting mode of the first control signal Flag and the second control signal 1 "more" changes, the setting mode of the third control signal WrEn needs to adapt to the change in the setting mode of the first control signal Flag and the second control signal 1 "more" to ensure that the number of low-level data finally stored in the storage unit 501 is not less than the number of high-level data stored in the storage unit 501.

[0081] Continue to refer Figure 1 The first writing module 103 includes: an enabling control module 133, which is used to generate a third control signal WrEn according to the first control signal Flag and the second control signal 1 "more".

[0082] In addition, in this embodiment, the enable control module 133 is also used to receive a write enable signal WriteEnable (see Figure 4 ), if the write enable signal WriteEnable is at a valid level, a third control signal WrEn is outputted to indicate whether the first control signal and the second control signal are the same.

[0083] In one example, refer to Figure 4 The first control signal Flag and the second control signal 1 "more" are connected through an XOR gate, and the output end of the XOR gate and the inverted signal WriteEnable- of the write enable signal WriteEnable are connected to the same NOR gate.

[0084] In this example, the enable control module 133 is also used to receive the first control signal Flag, the second control signal 1 "more" and the inverted signal WriteEnable- of the write enable signal. When the write enable signal WriteEnable is at a valid level, a fourth control signal WrEn- is generated. The third control signal WrEn and the fourth control signal WrEn- are inverted signals of each other.

[0085] Specifically, the first control signal Flag and the second control signal 1 "more" are connected through an XOR gate, the output end of the XOR gate is connected to an inverter, and is connected to the same NOR gate with the inverted signal WriteEnable- of the write enable signal WriteEnable.

[0086] For the generation circuit of the third control signal WrEn and the fourth control signal WrEn-, when the write enable signal WriteEnable is 0, the inverted signal WriteEnable- of the write enable signal is 1. At this time, the third control signal WrEn and the fourth control signal WrEn- must be 0, and the memory cannot perform a write operation, indicating that the memory is not in the write operation stage at this time; when the write enable signal WriteEnable is 1, the inverted signal WriteEnable- of the write enable signal is 0. At this time, the function of the circuit is as follows:

[0087] If the first control signal Flag is 1 and the second control signal 1 "more" is 1, since the working principle of the XOR gate XOR is "same is 0, different is 1", the output signal of the XOR gate XOR is 0. At this time, the generated third control signal WrEn is 1 and the fourth control signal WrEn- is 0.

[0088] If the first control signal Flag is 1 and the second control signal 1 "more" is 0, since the working principle of the XOR gate XOR is "same is 0, different is 1", the output signal of the XOR gate XOR is 1. At this time, the generated third control signal WrEn is 0, and the fourth control signal WrEn- is 1.

[0089] If the first control signal Flag is 0 and the second control signal 1 "more" is 1, since the working principle of the XOR gate XOR is "same is 0, different is 1", the output signal of the XOR gate XOR is 1. At this time, the generated third control signal WrEn is 0, and the fourth control signal WrEn- is 1.

[0090] If the first control signal Flag is 0 and the second control signal 1 "more" is 0, since the working principle of the XOR gate XOR is "same is 0, different is 1", the output signal of the XOR gate XOR is 0. At this time, the generated third control signal WrEn is 1 and the fourth control signal WrEn- is 0.

[0091] Continue to refer Figure 1 In this embodiment, the local data line LIO includes a first local data line LIO1 and a second local data line LIO2 which are differential data transmission lines. By setting the first local data line LIO1 and the second local data line LIO2 for transmitting differential data, the stability of data flipping between the local data line LIO and the global data line YIO is ensured.

[0092] The data inversion is performed during the process of transferring the data in the global data line YIO to the local data line LIO, including: the write module 103 is configured to transfer the data in the global data line YIO to the first local data line LIO1 after inversion, and / or the write module 103 is configured to transfer the data in the global data line YIO to the second local data line LIO2.

[0093] Specifically, the writing module 103 includes: a first conversion circuit 113 and a second conversion circuit 123 .

[0094] The first conversion circuit 113 is configured to control the data in the global data line YIO to be transmitted to the first local data line LIO1 , and / or control the opposite value of the data in the global data line YIO to be transmitted to the second local data line LIO2 .

[0095] In one example, refer to Figure 5 The first conversion circuit 113 includes: a first MOS transistor 401 , a second MOS transistor 402 and a third MOS transistor 403 .

[0096] Among them, the gate of the first MOS tube 401 receives the third control signal WrEn, the source is connected to the global data line YIO, and the drain is connected to the first local data line LIO1; the gate of the second MOS tube 402 is connected to the global data line YIO, the drain is connected to the second local data line LIO2, and the source is connected to the drain of the third MOS tube 403; the gate of the third MOS tube 403 receives the third control signal WrEn, and the source is grounded GND (not shown).

[0097] It should be noted that the “source” or “drain” in the first MOS transistor 401 , the second MOS transistor 402 and the third MOS transistor 403 is only used to distinguish the ports of the MOS transistors and does not impose any limitation, that is, the concepts of source and drain are interchangeable.

[0098] The second conversion circuit 123 is configured to control the data in the global data line YIO to be transmitted to the second local data line LIO2 , and / or control the opposite value of the data in the global data line YIO to be transmitted to the first local data line LIO1 .

[0099] In one example, refer to Figure 6 The second conversion circuit 123 includes: a fourth MOS transistor 404 , a fifth MOS transistor 405 and a sixth MOS transistor 406 .

[0100] The gate of the fourth MOS transistor 404 receives the fourth control signal WrEn-, the source is connected to the global data line YIO, and the drain is connected to the second local data line LIO2; the gate of the fifth MOS transistor 405 is connected to the global data line YIO, the drain is connected to the first local data line LIO1, and the source is connected to the drain of the sixth MOS transistor 406; the gate of the sixth MOS transistor 406 receives the fourth control signal WrEn-, and the source is grounded (not shown).

[0101] It should be noted that the “source” or “drain” in the fourth MOS transistor 404 , the fifth MOS transistor 405 and the sixth MOS transistor 406 is only used to distinguish the ports of the MOS transistors and does not impose any limitation, that is, the concepts of source and drain are interchangeable.

[0102] The working principles of the first conversion circuit 113 and the second conversion circuit 123 are as follows:

[0103] When the third control signal WrEn is 1, the fourth control signal WrEn is 0. At this time, the data transmission between the global data line YIO and the first local data line LIO1 and the second local data line LIO2 is regulated by the first conversion circuit 113 . Specifically, when YIO is 1, the gates of the first MOS transistor 401, the second MOS transistor 402 and the third MOS transistor 403 are all turned on, the global data line YIO and the first local data line LIO1 are connected through the first MOS transistor 401, and the first local data line LIO1 and the global data line YIO are 1; the second local data line LIO2 is grounded through the second MOS transistor 402 and the third MOS transistor 403, that is, the second local data line LIO2 is 0; when YIO is 0, the global data line YIO and the first local data line LIO1 are connected through the first MOS transistor 401, and the first local data line LIO1 and the global data line YIO are 0; because the global data line YIO is 0, the source and drain of the second MOS transistor 402 are not turned on, and the second local data line LIO2 is not grounded. Due to the influence of precharging (that is, LIO1 and LIO2 will be precharged to a high level before writing), the second local data line LIO2 is 1.

[0104] When the third control signal WrEn is 0, the fourth control signal WrEn is 1. At this time, the data transmission between the global data line YIO and the first local data line LIO1 and the second local data line LIO2 is regulated by the second conversion circuit 123 . Specifically, when YIO is 1, the gates of the fourth MOS transistor 404, the fifth MOS transistor 405 and the sixth MOS transistor 406 are all turned on, the global data line YIO and the second local data line LIO2 are connected through the fourth MOS transistor 404, and the second local data line LIO2 and the global data line YIO are 1; the first local data line LIO1 is grounded through the fifth MOS transistor 405 and the sixth MOS transistor 406, that is, the first local data line LIO1 is 0; when YIO is 0, the global data line YIO and the second local data line LIO2 are connected through the fourth MOS transistor 404, and the second local data line LIO2 and the global data line YIO are 0; because the global data line YIO is 0, the source and drain of the fifth MOS transistor 405 are not turned on, the first local data line LIO1 is not grounded, and due to the influence of precharging (that is, LIO1 and LIO2 will be precharged to a high level before writing), the first local data line LIO1 is 1.

[0105] Continue to refer Figure 1 , the control circuit 100 further includes:

[0106] The array area reading unit 502 is used to read the corrected data, the corrected ECC check code, the second control signal 1 "more" and the parity code o / e in the storage unit 501 to the local data line LIO in a read operation, or to read the opposite value of the corrected data, the opposite value of the corrected ECC check code, the second control signal 1 "more" and the parity code o / e in the storage unit 501 to the local data line LIO in a read operation.

[0107] The second check module 108 is used to determine whether an error occurs in the corrected data in the storage device according to the corrected ECC check code and the parity code o / e, and / or to correct the corrected data again if an error occurs.

[0108] The readout module 102 is used to control whether the data on the local data line LIO needs to be flipped when it is transmitted backward according to the readout second control signal 1 "more"; if the number of bits occupied by the high-level data exceeds the second preset value, the readout module 102 is configured to flip the data on the local data line LIO and finally transmit it to the second verification module 108; if the number of bits occupied by the high-level data does not exceed the second preset value, the readout module 102 is configured to finally transmit the data on the local data line LIO to the second verification module 108; it should be noted that, in this embodiment, the data on the local data line LIO includes corrected data and corrected ECC check code, or the opposite value of the corrected data and the opposite value of the corrected ECC check code.

[0109] It should be noted that, in the present embodiment, a data buffer module 106 (not shown in the drawings) is also included between the read module 102 and the error detection module 108. Since data buffering during data reading does not involve the core solution of the present application, it is not elaborated here. Those skilled in the art understand that when the memory reads data, the data also needs to pass through the data buffer module 106.

[0110] In one example, refer to Figure 1 In this embodiment, the read module 102 is connected between the local data line LIO and the global data line YIO, and is used to control the data transmission between the local data line LIO and the global data line YIO according to the second control signal 1 "more".

[0111] If the number of bits occupied by the high-level data exceeds the second preset value, the read-out module 102 is configured to flip the data in the local data line LIO and transmit it to the global data line YIO; if the number of bits occupied by the high-level data does not exceed the second preset value, the read-out module 102 is configured to transmit the data in the local data line LIO to the global data line YIO.

[0112] Specifically, the local data line LIO includes a first local data line LIO1 and a second local data line LIO2 which are differential data transmission lines. By setting the first local data line LIO1 and the second local data line LIO2 for transmitting differential data, the stability of data flipping between the local data line LIO and the global data line YIO is ensured.

[0113] The data in the first local data line LIO1 is flipped and then transmitted to the global data line YIO, including: the readout module 102 is configured to transmit the opposite value of the data in the first local data line LIO1 to the global data line YIO, and / or the readout module 102 is configured to transmit the data in the second local data line LIO2 to the global data line YIO.

[0114] refer to Figure 7The readout module 102 includes: a seventh MOS transistor 407 , an eighth MOS transistor 408 , a ninth MOS transistor 409 , a tenth MOS transistor 410 and an eleventh MOS transistor 411 .

[0115] Among them, the gate of the seventh MOS transistor 407 is connected to the first local data line LIO1, the drain is connected to the global data line YIO, and the source is connected to the drain of the ninth MOS transistor 409; the gate of the eighth MOS transistor 408 is connected to the second local data line LIO2, the drain is connected to the global data line YIO, and the source is connected to the drain of the tenth MOS transistor 410; the gate of the ninth MOS transistor 409 receives the second control signal 1 "more", and the source is connected to the drain of the eleventh MOS transistor 411; the gate of the tenth MOS transistor 410 receives the fifth control signal 1 "more" -, and the source is connected to the drain of the eleventh MOS transistor 411, and the second control signal 1 "more" and the fifth control signal 1 "more" - are inverted signals to each other; the gate of the eleventh MOS transistor 411 receives the read enable signal ReadEnable, and the source is grounded GND (not shown).

[0116] For the above conversion circuit, when the read enable signal ReadEnable is 0, the memory cannot perform a read operation, indicating that the memory is not in the read operation stage at this time; when the read enable signal ReadEnable is 1, its working principle is as follows:

[0117] When the second control signal 1 "more" is 1, the fifth control signal 1 "more" - is 0, which is equivalent to turning on only the left circuit, indicating that the opposite value of the data in the first local data line LIO1 is transmitted to the global data line YIO. When the first local data line LIO1 is 1, the seventh MOS tube 407 is turned on, and the global data line YIO is grounded at this time, and the global data line YIO is 0, so that the opposite value of the data in the first local data line LIO1 is transmitted to the global data line YIO; when the first local data line LIO1 is 0, the seventh MOS tube 407 is turned off. At this time, due to the influence of pre-charging (that is, YIO will be pre-charged to a high level before reading), the global data line YIO is 1, so that the opposite value of the data in the first local data line LIO1 is transmitted to the global data line YIO.

[0118] When the second control signal 1 "more" is 0, the fifth control signal 1 "more" - is 1, which is equivalent to turning on only the left circuit, indicating that the opposite value of the data in the second local data line LIO2 is transmitted to the global data line YIO. When the second local data line LIO2 is 1, the ninth MOS tube 409 is turned on, and the global data line YIO is grounded at this time, and the global data line YIO is 0, so that the opposite value of the data in the second local data line LIO2 is transmitted to the global data line YIO; when the second local data line LIO2 is 0, the ninth MOS tube 409 is turned off. At this time, due to the influence of pre-charging (that is, YIO will be pre-charged to a high level before reading), the global data line YIO is 1, so that the opposite value of the data in the second local data line LIO2 is transmitted to the global data line YIO.

[0119] It should be noted that the “source” or “drain” in the seventh MOS tube 407 , the eighth MOS tube 408 , the ninth MOS tube 409 , the tenth MOS tube 410 and the eleventh MOS tube 411 is only used to distinguish the ports of the MOS tubes and is not limited in any way, that is, the concepts of source and drain are interchangeable.

[0120] In another example, refer to Figure 8 In this embodiment, the readout module 102 is connected to the global data line YIO and the second verification module 108, and is used to control the data transmission between the global data line YIO and the second verification module 108 according to the second control signal 1 "more".

[0121] Specifically, if the number of bits occupied by the high-level data exceeds the second preset value, the read-out module 102 is configured to flip the data in the global data line YIO and transmit it to the second verification module 108; if the number of bits occupied by the high-level data does not exceed the second preset value, the read-out module 102 is configured to transmit the data in the global data line YIO to the second verification module 108.

[0122] More specifically, refer to Fig. 9 , this embodiment is described by taking the low-level control of the first transmission element 301 and the second transmission element 302 as an example, specifically as follows: when the second control signal 1 "more" is 1, the first transmission element turns on the signal transmission line where it is located, and at this time the global data line YIO is connected to the second verification module 108 through an inverter, so that the global data line YIO flips the transmitted data and transmits it to the second verification module 108; the second transmission element 302 turns off the signal transmission line where it is located. When the second control signal 1 "more" is 0, the first transmission element 301 turns off the signal transmission line where it is located, and the second transmission element 302 turns on the signal transmission line where it is located, and at this time the global data line YIO is directly connected to the second verification module 108, so that the global data line YIO directly transmits the transmitted data to the second verification module 108.

[0123] In addition, refer to Fig.10 and Fig.14 The global data line YIO includes a first global data line YIO1 and a second global data line YIO2 which are differential data transmission lines. By setting the first global data line YIO1 and the second global data line YIO2 for transmitting differential data, the stability of data flipping between the first local data line LIO1, the second local data line LIO2 and the first global data line YIO1, the second global data line YIO2 is ensured.

[0124] In an example, the first check module 105 and the second global data line YIO2 are also provided with a data conversion circuit similar to the conversion module 101, and its control process is opposite to that of the conversion module 101, that is, when the first control signal Flag is "1", the control is turned on to transmit the corrected data and the corrected ECC check code directly to the second global data line YIO2, and when the first control signal Flag is "0", the control is turned on to transmit the corrected data and the corrected ECC check code to the second global data line YIO2 through the inverter.

[0125] In some embodiments, an amplifier circuit may be provided between the first global data line YIO1 and the second global data line YIO2 to enable the first global data line YIO1 and the second global data line YIO2 to transmit signals of opposite phases.

[0126] At this time, the first writing module 103 includes: an enabling control module 113, a first writing circuit 213 and a second writing circuit 223

[0127] The first write circuit 213 is configured to control the data in the first global data line YIO1 to be transmitted to the first local data line LIO1 , or to transmit the data in the second global data line YIO2 to the first local data line LIO1 .

[0128] In one example, refer to Fig.11 The first writing circuit 213 includes: a first MOS transistor 601 and a second MOS transistor 602 .

[0129] Among them, the gate of the first MOS transistor 601 receives the third control signal WrEn, the source is connected to the first global data line YIO1, and the drain is connected to the first local data line LIO1; the gate of the second MOS transistor 602 receives the third control signal WrEn, the source is connected to the second global data line YIO2, and the drain is connected to the first local data line LIO1.

[0130] It should be noted that the “source” or “drain” in the first MOS transistor 601 and the second MOS transistor 602 is only used to distinguish the ports of the MOS transistors and does not impose any limitation, that is, the concepts of source and drain are interchangeable.

[0131] The second write circuit 223 is configured to control the data in the first global data line YIO1 to be transmitted to the second local data line LIO2 , or to transmit the data in the second global data line YIO2 to the second local data line LIO2 .

[0132] In one example, refer to Fig.12 The second writing circuit 223 includes: a third MOS tube 603 and a fourth MOS tube 604.

[0133] Among them, the gate of the third MOS tube 603 receives the fourth control signal WrEn-, the source is connected to the first global data line YIO1, the drain is connected to the second local data line LIO2, and the third control signal WrEn and the fourth control signal WrEn- are inverted signals to each other; the gate of the fourth MOS tube 604 receives the third control signal WrEn-, the source is connected to the second global data line YIO2, and the drain is connected to the second local data line LIO2.

[0134] It should be noted that the “source” or “drain” in the third MOS transistor 603 and the fourth MOS transistor 604 is only used to distinguish the ports of the MOS transistors and does not impose any limitation, that is, the concepts of source and drain are interchangeable.

[0135] The working principles of the first writing circuit 213 and the second writing circuit 223 are as follows:

[0136] When the third control signal WrEn is 1 and the fourth control signal WrEn- is 0, the data transmission between the first global data line YIO1, the second global data line YIO2 and the first local data line LIO1, the second local data line LIO2 is regulated by the first write circuit 213 and the second write circuit 223. Specifically, when YIO1 is 1, the gates of the first MOS transistor 601 and the fourth MOS transistor 604 are turned on, the first global data line YIO1 and the first local data line LIO1 are connected through the first MOS transistor 601, and the first local data line LIO1 and the first global data line YIO1 are 1; the second global data line YIO2 and the second local data line LIO2 are connected through the fourth MOS transistor 604, and the second local data line LIO2 and the second global data line YIO2 are 0. When YIO1 is 0, the gates of the first MOS transistor 601 and the fourth MOS transistor 604 are turned on, the first global data line YIO1 and the first local data line LIO1 are connected through the first MOS transistor 601, and the first local data line LIO1 and the first global data line YIO1 are 0; the second global data line YIO2 and the second local data line LIO2 are connected through the fourth MOS transistor 604, and the second local data line LIO2 and the second global data line YIO2 are 1.

[0137] When the third control signal WrEn is 0 and the fourth control signal WrEn- is 1, the data transmission between the first global data line YIO1, the second global data line YIO2 and the first local data line LIO1, the second local data line LIO2 is regulated by the first write circuit 213 and the second write circuit 223. Specifically, when YIO1 is 1, the gates of the second MOS transistor 602 and the third MOS transistor 603 are turned on, the second global data line YIO2 and the first local data line LIO1 are connected through the second MOS transistor 602, and the first local data line LIO1 and the second global data line YIO2 are 0; the first global data line YIO1 and the second local data line LIO2 are connected through the third MOS transistor 603, and the second local data line LIO2 and the first global data line YIO1 are 1. When YIO1 is 0, the gates of the second MOS transistor 602 and the third MOS transistor 603 are turned on, the second global data line YIO2 and the first local data line LIO1 are connected through the second MOS transistor 602, and the first local data line LIO1 and the second global data line YIO2 are 1; the first global data line YIO1 and the second local data line LIO2 are connected through the third MOS transistor 603, and the second local data line LIO2 and the first global data line YIO1 are 0.

[0138] In one example, refer to Fig.10The readout module 102 is connected between the first local data line LIO1, the second local data line LIO2, the first global data line YIO1 and the second global data line YIO2, and is used to control the data transmission between the first local data line LIO1, the second local data line LIO2 and the first global data line YIO1, the second global data line YIO2 according to the second control signal 1 "more".

[0139] Specifically, if the number of bits occupied by the high-level data exceeds the second preset value, the read-out module 102 is configured to transmit the opposite value of the data in the first local data line LIO1 to the first global data line YIO1, and / or transmit the opposite value of the data in the second local data line LIO2 to the second global data line YIO2; if the number of bits occupied by the high-level data does not exceed the second preset value, the read-out module 102 is configured to transmit the opposite value of the data in the first local data line LIO1 to the second global data line YIO2, and / or transmit the opposite value of the data in the second local data line LIO2 to the first global data line YIO1.

[0140] More specifically, refer to Fig.13 The readout module 102 includes: a fifth MOS tube 605, a sixth MOS tube 606, a seventh MOS tube 607, an eighth MOS tube 608, a ninth MOS tube 609, a tenth MOS tube 610, an eleventh MOS tube 611, a twelfth MOS tube 612, a thirteenth MOS tube 613 and a fourteenth MOS tube 614.

[0141] Among them, the gate of the 13th MOS tube 613 is connected to the first local data line LIO1, the drain is connected to the second global data line YIO2, and the source is connected to the drain of the 7th MOS tube 607; the gate of the 5th MOS tube 605 is connected to the second local data line LIO2, the drain is connected to the second global data line YIO2, and the source is connected to the drain of the 8th MOS tube 608; the gate of the 7th MOS tube 607 is connected to the fifth control signal 1 "more"-, and the source is connected to the drain of the 11th MOS tube 611, and the second control signal 1 "more" and the fifth control signal 1 "more"- are inverted signals to each other; the gate of the 8th MOS tube 608 is connected to the second control signal 1 "more", and the source is connected to the drain of the 11th MOS tube 611; the gate of the 11th MOS tube 611 receives the read enable signal ReadEn able, and the source is grounded GND (not shown); the gate of the 14th MOS tube 614 is connected to the second local data line LIO2, the drain is connected to the first global data line YIO1, and the source is connected to the drain of the 9th MOS tube 609; the gate of the 6th MOS tube 606 is connected to the first local data line LIO1, the drain is connected to the first global data line YIO1, and the source is connected to the drain of the 10th MOS tube 610; the gate of the 9th MOS tube 609 is connected to the fifth control signal 1 "more"-, and the source is connected to the drain of the 12th MOS tube 612; the gate of the 10th MOS tube 610 is connected to the second control signal 1 "more", and the source is connected to the drain of the 12th MOS tube 612; the gate of the 12th MOS tube 612 receives the read enable signal ReadEnable, and the source is grounded GND (not shown).

[0142] For the above conversion circuit, when the read enable signal ReadEnable is 0, the memory cannot perform a read operation, indicating that the memory is not in the read operation stage at this time; when the read enable signal ReadEnable is 1, its working principle is as follows:

[0143] When the second control signal 1 "more" is 1, the fifth control signal 1 "more" - is 0, which is equivalent to turning on only the intermediate circuit, indicating that the opposite value of the data in the first local data line LIO1 is transmitted to the first global data line YIO1, and the opposite value of the data in the second local data line LIO2 is transmitted to the second global data line YIO2. When the first local data line LIO1 is 1, the sixth MOS transistor 606 is turned on, at which time the first global data line YIO1 is grounded, and the first global data line YIO1 is 0, so that the opposite value of the data in the first local data line LIO1 is transmitted to the first global data line YIO1; when the second local data line LIO2 is 1, the fifth MOS transistor 605 is turned on, at which time the second global data line YIO2 is grounded, and the second global data line YIO2 is 0, so that the opposite value of the data in the second local data line LIO2 is transmitted to the second global data line YIO2.

[0144] When the second control signal 1 "more" is 0, the fifth control signal 1 "more" - is 1, which is equivalent to turning on only the edge circuit, indicating that the opposite value of the data in the first local data line LIO1 is transmitted to the second global data line YIO2, and the opposite value of the data in the second local data line LIO2 is transmitted to the first global data line YIO1. When the first local data line LIO1 is 1, the 13th MOS transistor 613 is turned on, at which time the second global data line YIO2 is grounded, and the second global data line YIO2 is 0, so as to realize the transmission of the opposite value of the data in the first local data line LIO1 to the second global data line YIO2; when the second local data line LIO2 is 1, the 14th MOS transistor 614 is turned on, at which time the first global data line YIO1 is grounded, and the first global data line YIO1 is 0, so as to realize the transmission of the opposite value of the data in the second local data line LIO2 to the first global data line YIO1.

[0145] It should be noted that the “source” or “drain” in the fifth MOS tube 605 , the sixth MOS tube 606 , the seventh MOS tube 607 , the eighth MOS tube 608 , the ninth MOS tube 609 , the tenth MOS tube 610 , the eleventh MOS tube 611 , the twelfth MOS tube 612 , the thirteenth MOS tube 613 and the fourteenth MOS tube 614 is only used to distinguish the ports of the MOS tubes and is not limited in any way, that is, the concepts of source and drain are interchangeable.

[0146] In another example, refer to Fig.14 The readout module 102 is connected to the first global data line YIO1, the second global data line YIO2 and the error detection module 108, and is used to control the data transmission between the first global data line YIO1, the second global data line YIO2 and the second check module 108 according to the second control signal 1 "more".

[0147] Specifically, refer to Fig.15 The readout module 102 includes: a first transmission element 301, one end of which is connected to the second global data line YIO2, and the other end is connected to the second verification module 108; a second transmission element 302, one end of which is connected to the first global data line YIO1, and the other end is connected to the second verification module 108; the first transmission element 301 and the second transmission element 302 are also used to receive the second control signal 1 "more", and are used to turn on the first transmission element 301 or the second transmission element 302 according to the second control signal 1 "more".

[0148] This embodiment is described by taking the low-level control of the first transmission element 301 and the second transmission element 302 as an example, specifically as follows: when the second control signal 1 "more" is 1, the first transmission element turns on the signal transmission line where it is located, and at this time the second global data line YIO2 is connected to the second verification module 108, so that the second global data line YIO2 transfers the transmitted data to the second verification module 108; the second transmission element 302 turns off the signal transmission line where it is located. When the second control signal 1 "more" is 0, the first transmission element 301 turns off the signal transmission line where it is located, and the second transmission element 302 turns on the signal transmission line where it is located, and at this time the first global data line YIO1 is connected to the second verification module 108, so that the first global data line YIO1 transfers the transmitted data to the second verification module 108.

[0149] Compared with the related art, through a shared counting module, the number of differences between the original data, the original ECC check code and the data transmitted in the global data line is counted according to the switching control signal in time-sharing to obtain the first control signal, and the number of high levels in the corrected data and the corrected ECC check code is counted to obtain the second control signal, thereby saving circuit area; at the same time, the newly generated parity code is used together with the corrected ECC check code for subsequent error detection and correction of the data in the read operation, and the newly generated parity code together with the corrected ECC check code can detect 2-bit errors to enhance the error detection and correction capabilities in the memory and further improve the reliability of data storage.

[0150] It is worth mentioning that all units involved in this embodiment are logical units. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed by this application, but this does not mean that there are no other units in this embodiment.

[0151] Yet another embodiment of the present application relates to a memory, comprising the control circuit provided by the above embodiment, and further comprising: a storage unit connected to a local data line, wherein the local data line is used to write data to and read data from the storage unit.

[0152] Fig.16 and Fig.17 A schematic diagram of the structure of the memory provided in this embodiment; the memory provided in this embodiment is further described in detail below in conjunction with the accompanying drawings, and the parts that are the same as those in the above embodiments are not repeated in this embodiment.

[0153] The external data line DataBus is used to receive original data and original ECC check code.

[0154] The first check module 105 is connected to the external data line DataBus, and is used to perform error detection and / or error correction according to the original ECC check code when an error occurs in data transmission, and output corrected data and a corrected ECC check code, wherein if no error occurs in data transmission, the corrected data is consistent with the original data, and the corrected ECC check code is consistent with the original ECC check code.

[0155] The comparison module 111 is connected to the external data line DataBus and the global data line YIO, and is used to detect bit by bit whether the data currently transmitted by the external data line DataBus is the same as the data currently transmitted by the global data line YIO, and output the detection result of each bit.

[0156] The counting module 112 is connected to the comparison module 111 and the first verification module 105, and receives a switching control signal. When the switching control signal is in the first state, the counting module 112 is used to count the output result of the comparison module 105, and output a first control signal Flag representing whether the difference in the number of bits between the original data, the original ECC check code and the data currently transmitted by the global data line YIO exceeds a first preset value; the first control signal Flag is used to control whether the data to be written needs to be flipped in a write operation.

[0157] For the counting module 112, when the switching control signal is in the second state, it is used to count the high-level data in the corrected data and the corrected ECC check code output by the first check module 105, and output a second control signal 1 "more" indicating whether the number of bits occupied by the high-level data exceeds a second preset value. The second control signal 1 "more" is used to control whether the data to be read needs to be flipped in the read operation.

[0158] When the switching control signal is in the second state, the counting module 112 outputs a parity code o / e indicating whether the number of high-level data bits is an odd number or an even number. The parity code o / e is used for error detection and / or error correction of the data to be read in a read operation.

[0159] The data buffer module 106 is connected to the first check module 105 and the counting module 112, and is used to transmit the corrected data and the corrected ECC check code to the global data line YIO or to flip the corrected data and the corrected ECC check code and then transmit them to the global data line YIO according to the first control signal Flag.

[0160] The writing module 103 is connected between the local data line LIO and the global data line YIO, controls the data in the global data line YIO to be transmitted to the local data line LIO, and determines whether to perform data flipping during the data transmission from the global data line YIO to the local data line LIO based on the third control signal WrEn, wherein the third control signal WrEn is used to indicate whether the value of the first control signal Flag is the same as the value of the second control signal 1 "more". Specifically, the third control signal WrEn is used to control the number of data stored in the low level to be not less than the number of data stored in the high level.

[0161] The array area reading unit 502 is used to read the corrected data, the corrected ECC check code, the second control signal 1 “more” and the parity code o / e in the storage unit 501 to the local data line LIO in a read operation.

[0162] The second check module 108 is used to determine whether an error occurs in the corrected data in the storage device according to the corrected ECC check code, and / or to correct the corrected data again if an error occurs.

[0163] The readout module 102 is used to control whether the corrected data and the corrected ECC check code of the local data line LIO need to be flipped when they are transmitted backward according to the readout second control signal 1 "more"; if the number of bits occupied by the high-level data exceeds the second preset value, the readout module 102 is configured to flip the corrected data and the corrected ECC check code and finally transmit them to the second check module 108; if the number of bits occupied by the high-level data does not exceed the second preset value, the readout module 102 is configured to finally transmit the corrected data and the corrected ECC check code to the second check module 108.

[0164] In one example, refer to Fig.16 The readout module 102 is connected between the local data line LIO and the global data line YIO, and is used to control the data transmission between the local data line LIO and the global data line YIO according to the second control signal 1 "more". If the number of bits occupied by the high-level data exceeds the second preset value, the readout module 102 is configured to flip the data in the local data line LIO and transmit it to the global data line YIO; if the number of bits occupied by the high-level data does not exceed the second preset value, the readout module 102 is configured to transmit the data in the local data line LIO to the global data line YIO.

[0165] In another example, refer to Fig.17, the readout module 102 is connected to the global data line YIO and the second verification module 108, and is used to control the data transmission between the global data line YIO and the second verification module 108 according to the second control signal 1 "more". Specifically, if the number of bits occupied by the high-level data exceeds the second preset value, the readout module 102 is configured to flip the data in the global data line YIO and transmit it to the second verification module 108; if the number of bits occupied by the high-level data does not exceed the second preset value, the readout module 102 is configured to transmit the data in the global data line YIO to the second verification module 108.

[0166] It should be noted that, in this embodiment, the local data line LIO is connected to the storage unit 501 including: direct connection and indirect connection. In this embodiment, the local data line LIO is not directly connected to the storage unit 501, but the storage unit 501 is actually connected to the bit line BitLine, and the bit line is connected to the local data line LIO through column selection.

[0167] Compared with the related art, through a shared counting module, the number of differences between the original data, the original ECC check code and the data transmitted in the global data line is counted according to the switching control signal in time-sharing to obtain the first control signal, and the number of high levels in the corrected data and the corrected ECC check code is counted to obtain the second control signal, thereby saving circuit area; at the same time, the newly generated parity code is used together with the corrected ECC check code for subsequent error detection and correction of the data in the read operation, and the newly generated parity code together with the corrected ECC check code can detect 2-bit errors to enhance the error detection and correction capabilities in the memory and further improve the reliability of data storage.

[0168] It is worth mentioning that all units involved in this embodiment are logical units. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed by this application, but this does not mean that there are no other units in this embodiment.

[0169] Since the above embodiments correspond to this embodiment, this embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments are still valid in this embodiment, and the technical effects that can be achieved in the above embodiments can also be achieved in this embodiment. In order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the above embodiments.

[0170] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present application, and in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present application.

Claims

1. A control circuit for writing data to and reading data from a storage unit, characterized in that, it includes: An external data line for receiving original data and an original ECC check code; A first check module connected to the external data line, for detecting and / or correcting errors according to the original ECC check code when a data transmission error occurs, and outputting corrected data and a corrected ECC check code. Wherein, if no data transmission error occurs, the corrected data is the same as the original data, and the corrected ECC check code is the same as the original ECC check code; A comparison module connected to the external data line and the global data line, for bit-by-bit detecting whether the data currently transmitted on the external data line is the same as the data currently transmitted on the global data line, and outputting the detection result of each bit; A counting module connected to the comparison module and the first check module, and receiving a switching control signal. When the switching control signal is in the first state, it is used to count the output result of the comparison module, and output a first control signal indicating whether the number of different bits between the original data, the original ECC check code and the data currently transmitted on the global data line exceeds a first preset value; when the switching control signal is in the second state, it is used to count the high-level data in the corrected data and the corrected ECC check code output by the first check module, output a second control signal indicating whether the number of bits occupied by the high-level data exceeds a second preset value, and output a parity code indicating whether the number of high-level data is odd or even; the second control signal and the parity code are stored in the storage unit as marker bit data, so that the second control signal and the parity code can be read out during the data reading process; wherein, the first control signal is used to control whether the data to be written needs to be flipped during the write operation, the second control signal is used to control whether the data to be read needs to be flipped during the read operation, and the parity code is used to detect and / or correct errors in the data to be read during the read operation.

2. The control circuit according to claim 1, characterized in that, it further includes: A data buffer module connected to the first check module and the counting module, for transmitting the corrected data and the corrected ECC check code to the global data line or transmitting the corrected data and the corrected ECC check code after flipping to the global data line according to the first control signal.

3. The control circuit according to claim 2, characterized in that, it further includes: A writing module connected between the local data line and the global data line, controlling the data in the global data line to be transmitted to the local data line, and based on a third control signal, judging whether data flipping occurs during the process of transmitting the data in the global data line to the local data line, wherein the third control signal is used to represent whether the value of the first control signal and the value of the second control signal are the same.

4. The control circuit according to claim 1, characterized in that, it further includes: An array region reading unit, configured to read the corrected data, the corrected ECC check code, the second control signal, and the parity code in the storage unit to a local data line during a read operation, or read the opposite value of the corrected data, the opposite value of the corrected ECC check code, the second control signal, and the parity code in the storage unit to the local data line during a read operation.

5. The control circuit according to claim 1, wherein, it further comprises: A second verification module, configured to determine whether an error occurs in the corrected data during storage according to the corrected ECC check code and the parity code, and / or correct the corrected data with an error again; A reading module, configured to control whether the data on the local data line needs to be inverted when being transmitted backward according to the read second control signal; If the number of bits occupied by the high-level data exceeds the second preset value, the reading module is configured to finally transmit the opposite value of the data on the local data line to the second verification module; If the number of bits occupied by the high-level data does not exceed the second preset value, the reading module is configured to finally transmit the data on the local data line to the second verification module.

6. The control circuit according to claim 2, wherein, The data buffer module includes: a conversion module, configured to control whether the corrected data and the corrected ECC check code need to be inverted when being transmitted to the global data line according to the first control signal; if the number of different bits exceeds the first preset value, the conversion module is configured to transmit the corrected data and the corrected ECC check code to the global data line after inversion; if the number of different bits does not exceed the first preset value, the conversion module is configured to transmit the corrected data and the corrected ECC check code to the global data line.

7. The control circuit according to claim 1, wherein, successively detecting whether the data currently transmitted on the external data line is the same as the data currently transmitted on the global data line, and outputting a detection result for each bit, including: if the data transmitted on the external data line for the current bit is different from the data transmitted on the global data line for the current bit, generating a first sub-control signal, and if the data transmitted on the external data line for the current bit is the same as the data transmitted on the global data line for the current bit, generating a second sub-control signal.

8. The control circuit according to claim 7, wherein, When the switching control signal is in the first state, the counting module is configured to obtain the first sub-control signal and the second sub-control signal, and if the number of the first sub-control signals exceeds the first preset value, generate the first control signal, and the first preset value is a preset percentage of the sum of the number of the first sub-control signals and the number of the second sub-control signals.

9. The control circuit according to claim 8, wherein, the preset percentage is 50%.

10. The control circuit according to claim 1, wherein, The second preset value is 50% of the sum of the number of bits of the corrected data and the corrected ECC check code.

11. The control circuit according to claim 3, wherein, the writing module includes: an enable control module, configured to receive the first control signal and the second control signal, and output a third control signal for indicating whether the first control signal and the second control signal are the same.

12. The control circuit according to claim 11, wherein, the enable control module is further configured to receive a write enable signal, and if the write enable signal is at an effective level, output the third control signal for indicating whether the first control signal and the second control signal are the same.

13. The control circuit according to claim 11, wherein, the local data line includes a first local data line and a second local data line that are differential data transmission lines; During the process of transmitting the data in the global data line to the local data line, data inversion occurs, including: the writing module is configured to invert the data in the global data line and then transmit it to the first local data line, and / or the writing module is configured to transmit the data in the global data line to the second local data line.

14. The control circuit according to claim 13, wherein, the writing module further includes: a first conversion circuit including a first MOS transistor, a second MOS transistor, and a third MOS transistor; The gate of the first MOS transistor receives the third control signal, the source is connected to the global data line, and the drain is connected to the first local data line; The gate of the second MOS transistor is connected to the global data line, the drain is connected to the second local data line, and the source is connected to the drain of the third MOS transistor; The gate of the third MOS transistor receives the third control signal, and the source is grounded.

15. The control circuit according to claim 13, wherein, the writing module further includes: a second conversion circuit including a fourth MOS transistor, a fifth MOS transistor, and a sixth MOS transistor; The gate of the fourth MOS transistor receives a fourth control signal, the source is connected to the global data line, the drain is connected to the second local data line, and the third control signal and the fourth control signal are inverse signals of each other; The gate of the fifth MOS transistor is connected to the global data line, the drain is connected to the first local data line, and the source is connected to the drain of the sixth MOS transistor; The gate of the sixth MOS transistor receives the fourth control signal, and the source is grounded.

16. The control circuit according to claim 5, wherein, The readout module is connected between the local data line and the global data line, and is configured to control data transmission between the local data line and the global data line according to a second control signal. If the number of bits occupied by the high-level data exceeds the second preset value, the readout module is configured to transmit the opposite value of the data in the local data line to the global data line; if the number of bits occupied by the high-level data does not exceed the second preset value, the readout module is configured to transmit the data in the local data line to the global data line.

17. The control circuit according to claim 5, wherein, the readout module is connected to the global data line and the second verification module, and is configured to control data transmission between the global data line and the second verification module according to a second control signal. When the number of bits occupied by the high-level data exceeds the second preset value, the readout module is configured to transmit the inverted data in the global data line to the second verification module; when the number of bits occupied by the high-level data does not exceed the second preset value, the readout module is configured to transmit the data in the global data line to the second verification module.

18. The control circuit according to claim 6, wherein, the conversion module includes: a first transmission element, one end of which is connected to the first verification module through an inverter and the other end is connected to the global data line; a second transmission element, one end of which is connected to the first verification module and the other end is connected to the global data line; the first transmission element and the second transmission element are further configured to receive the first control signal and to selectively turn on the first transmission element or the second transmission element according to the first control signal.

19. A memory, wherein, it includes the control circuit according to any one of claims 1 to 18 above, and further includes: a storage unit connected to the local data line, and the local data line is used for writing data to and reading data from the storage unit.

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