Memory devices and apparatuses with power management capabilities

Abstract

The present disclosure relates to power management. A memory device can include a controller configured to cause the memory device to generate a first sum of expected peak current flow values for a plurality of memory devices if the memory device is to initiate a next phase of an access operation in a selected operating mode, and generate a second sum of expected peak current flow values for a subset of the plurality of memory devices; compare the first sum to a first current demand budget for the plurality of the memory devices; compare the second sum to a second current demand budget for the subset of memory devices; and initiate the next phase of the access operation in the selected operating mode in response to the first sum being less than or equal to the first current demand budget and the second sum being less than or equal to the second current demand budget.

Description

[0001] Related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 195,202, filed on June 1, 2021, which is hereby incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to power management in integrated circuit devices, and more particularly, in one or more embodiments, this disclosure relates to methods and apparatus for utilizing predictive peak current monitoring and multiple current demand budgets in power management. Background Technology

[0004] Memory (e.g., memory devices) is typically provided in computers or other electronic devices as internal semiconductor integrated circuit devices. Many different types of memory exist, including random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

[0005] Flash memory has evolved into a popular source of non-volatile memory for a wide variety of electronic applications. Flash memory typically uses single-transistor memory cells that support high memory density, high reliability, and low power consumption. By programming the charge storage structure (e.g., floating gate or charge trap) or other physical phenomena (e.g., phase transition or polarization), changes in the threshold voltage (Vt) of the memory cell determine the data state (e.g., data value) of each memory cell. Common applications of flash memory and other non-volatile memories include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and removable memory modules, and the applications of non-volatile memory continue to expand.

[0006] NAND flash memory is a common type of flash memory device, so named because of the logical arrangement of its basic memory cell configuration. Typically, the memory cell arrays used in NAND flash memory are arranged such that the control gates of each memory cell in a row of the array are connected together to form an access line, such as a word line. Columns in the array contain strings of memory cells (often called NAND strings) connected in series between a pair of select gates, such as between a source select transistor and a drain select transistor. Each source select transistor can be connected to the source, and each drain select transistor can be connected to a data line, such as a column bit line. Variations using more than one select gate between the memory cell string and the source and / or between the memory cell string and the data line are known.

[0007] Power consumption is often a critical consideration in the design and use of memory devices. Problems can arise when multiple memory devices are operated in parallel. These problems can include exceeding power consumption specifications and / or adversely affecting service quality. Summary of the Invention

[0008] In one aspect, this disclosure provides a memory device comprising: a memory cell array; a plurality of registers, wherein each of the plurality of registers corresponds to a respective memory device among a plurality of memory devices containing the memory device, wherein each of the plurality of registers is configured to store an expected peak current value of its respective memory device, wherein the plurality of registers includes a plurality of register subsets, and wherein a particular subset of memory devices within the plurality of memory device subsets contains the memory device; and a controller for accessing the memory cell array, wherein the controller is configured to cause the memory device to perform the following operations: determining whether the memory device is expecting to initiate a next stage of an access operation to the memory cell array; and in response to determining that the memory device is expecting to initiate the next stage of the access operation: generating a value from the plurality of registers other than the corresponding register of the memory device. The first sum is generated by taking the expected peak current value of each register other than the corresponding register of the memory device and the expected peak current value of the next stage of the access operation in the selected operating mode; generating a second sum of the expected peak current value of each register in a specific subset of registers other than the corresponding register of the memory device and the expected peak current value of the next stage of the access operation in the selected operating mode; comparing the first sum with a first current demand budget for the plurality of memory devices; comparing the second sum with a second current demand budget for the specific subset of memory devices, wherein the second current demand budget is less than the first current demand budget; and in response to the first sum being less than or equal to the first current demand budget and the second sum being less than or equal to the second current demand budget, initiating the next stage of the access operation in the selected operating mode.

[0009] In another aspect, this disclosure provides a memory device comprising: a memory cell array; nodes for connection to signal lines; a plurality of registers, wherein one of the plurality of registers is configured to store an expected peak current value of the memory device, and wherein the remaining registers of the plurality of registers are each configured to store a corresponding expected peak current value of a different memory device in a memory device group containing the memory device; and a controller for accessing the memory cell array, wherein the controller is configured to cause the memory device to perform the following operations: determining whether the memory device is expecting to initiate a next stage of an access operation to the memory cell array; in response to determining that the memory device is expecting to initiate the next stage of the access operation: determining, at least in response to, whether there is a first current demand budget for the memory device group sufficient to initiate the next stage of the access operation in a selected operating mode: the corresponding expected peak current value of the remaining registers of the plurality of registers; and the selected The expected peak current value of the next stage of the access operation in the selected operating mode; and at least in response to determining whether there exists a second current demand budget sufficient to initiate the next stage of the access operation in the selected operating mode for a subset of memory devices containing the memory device in the memory device group: the corresponding expected peak current value of the registers in the plurality of registers for memory devices other than the memory device in the subset of memory devices; and the expected peak current value of the next stage of the access operation in the selected operating mode; and in response to determining that there exists a first current demand budget and a second current demand budget sufficient to initiate the next stage of the access operation in the selected operating mode, outputting the expected peak current value of the next stage of the access operation in the selected operating mode to the node and storing the expected peak current value of the next stage of the access operation in the selected operating mode in one of the plurality of registers.

[0010] In another aspect, this disclosure provides an apparatus comprising: a plurality of dies, wherein each of the plurality of dies communicates with each remaining die of the plurality of dies, wherein the plurality of dies includes a plurality of die subsets, wherein a particular die of the plurality of dies is a member of the particular die subset of the plurality of dies, and wherein the particular die of the plurality of dies includes: a controller configured to cause the particular die to perform the following operations: storing a corresponding expected peak current value for each of the plurality of dies; determining whether the particular die is expecting to initiate the next stage of an access operation; and in response to determining that the particular die is expecting to initiate the next stage of the access operation: determining whether there is sufficient for the plurality of dies to initiate an access operation in a selected operating mode. The process involves: initiating a first current requirement budget for the next stage of the access operation; determining whether there exists a second current requirement budget smaller than the first current budget for the specific die subset sufficient to initiate the next stage of the access operation in the selected operating mode; initiating the next stage of the access operation in the selected operating mode in response to determining that there exists a first current requirement budget and a second current requirement budget sufficient to initiate the next stage of the access operation in the selected operating mode; and pausing the specific die in response to determining that there is no first current requirement budget sufficient to initiate the next stage of the access operation in the selected operating mode or no second current requirement budget sufficient to initiate the access operation in the selected operating mode. Attached Figure Description

[0011] Figure 1 This is a simplified block diagram of a memory that communicates with a processor as part of an electronic system, according to an embodiment.

[0012] Figure 2 This is a simplified block diagram of a memory module that communicates with a host as part of an electronic system, according to another embodiment.

[0013] Figures 3A-3D This is a side view representing a multi-die package according to various embodiments.

[0014] Figures 4A-4D This is a schematic diagram of a multi-die package according to various embodiments.

[0015] Figure 5 This is a conceptual timing diagram of the signal and register contents according to an embodiment.

[0016] Figure 6 It is a timing diagram depicting the clock and other signals according to an embodiment.

[0017] Figure 7 This is a flowchart of a method for operating a bare die according to an embodiment.

[0018] Figure 8 This is a flowchart of a method for operating multiple dies according to an embodiment.

[0019] Figures 9A-9B This is a flowchart of a portion of a method for operating a bare die according to an embodiment.

[0020] Figures 10A-10C This is a flowchart of a portion of a method for operating a bare die according to an embodiment. Detailed Implementation

[0021] In the following detailed description, reference is made to the accompanying drawings, which form part of the detailed description and illustrate specific embodiments therein by means of illustration. Throughout the drawings, similar reference numerals describe substantially similar components. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be regarded in a limiting sense.

[0022] Unless otherwise apparent from the context, the term "conductive" as used herein, and its various related forms (e.g., conduct, conductively, conducting, conduction, conductivity, etc.), refer to electrical conductivity. Similarly, unless otherwise apparent from the context, the term "connecting" as used herein, and its various related forms (e.g., connect, connected, connection, etc.), refer to electrical connection through a conductive path.

[0023] As used in this article, the simultaneous execution of multiple actions means that each of these actions is performed in corresponding time periods, and each of these corresponding time periods partially or completely overlaps with each of the remaining corresponding time periods. In other words, those actions are performed simultaneously for at least some time period.

[0024] This paper recognizes that even when values ​​are expected to be equal, the variability and precision of industrial processing and operation can still cause differences from their expected values. These variability and precision will generally depend on the technology used in the manufacture and operation of integrated circuit devices. Therefore, if values ​​are expected to be equal, then those values ​​are considered equal regardless of their resulting values.

[0025] NAND flash memory is widely used in managed NAND (MNAND) and solid-state drive (SSD) systems. Common examples of MNAND include embedded multimedia cards (eMMC) commonly found in SSD systems, embedded USB (eUSB) commonly found in industrial applications, and general-purpose flash memory devices commonly found in digital cameras, mobile phones, and other consumer electronics devices. The capacitive load of three-dimensional NAND is typically large and can continue to grow as the process scales. Various access lines, data lines, and voltage nodes may need to be charged or discharged very quickly during sensing (e.g., read or verify), programming, and erasing operations, requiring memory array access operations to meet performance specifications often needed to meet data throughput targets indicated by consumer requirements or industry standards. Multi-plane operations are often used to increase system throughput for sequential reads or programming. Therefore, a typical NAND memory can have peak current consumption close to 200 mA, which can be four to five times the average current amplitude. Operating more than four NAND memories in parallel can become challenging given the typical market demand of 400-1000 mA total current requirements for MNAND systems.

[0026] Various techniques have been employed to manage the power consumption of memory systems containing multiple memory devices, many of which rely on memory controllers to interleave activity across the memory devices in an attempt to avoid high-power portions of concurrent access operations across more than one memory device. The various embodiments described herein facilitate power management across multiple dies (e.g., memory) by: directing a given die toward its expected peak current value and determining how to respond to a first current demand budget (CB) of a primary die group containing the given die. Main ), and a second current demand budget (CB) in response to a subset of the main group of dies that also contains a given die, which is less than the first current demand budget. Sub The decision continues. A bare chip group may contain multiple bare chip subsets. Each bare chip subset is mutually exclusive with each remaining bare chip subset, and the union of bare chip subsets may contain all the bare chips in the bare chip group.

[0027] Figure 1 This is a simplified block diagram illustrating communication between a first device in the form of memory (e.g., a memory device) 100 and a second device in the form of a processor 130 as part of a third device in the form of an electronic system, according to an embodiment. Examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and the like. The processor 130 (e.g., a controller external to the memory device 100) may be a memory controller or other external host device.

[0028] Memory device 100 includes an array 104 of memory cells that can be logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access line (collectively referred to as a word line), while memory cells in logical columns are typically selectively connected to the same data line (collectively referred to as a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 1 (Not shown in the text) can be programmed to be one of at least two target data states.

[0029] Row decoding circuitry 108 and column decoding circuitry 110 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 100 also includes input / output (I / O) control circuitry 112 for managing inputs of commands, addresses, and data to memory device 100, as well as outputs of data and status information from memory device 100. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 110 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 112 and control logic 116 to latch incoming commands.

[0030] A controller (e.g., control logic 116 within memory device 100) controls access to memory cell array 104 in response to the command and may generate status information for external processor 130, i.e., the control logic 116 is configured to perform access operations (e.g., sensing operations [which may include read and verification operations], programming operations, and / or erase operations) on memory cell array 104. Control logic 116 communicates with row decoding circuitry 108 and column decoding circuitry 110 to control them in response to an address. Control logic 116 may include instruction register 126, which may represent computer-available memory for storing computer-readable instructions. In some embodiments, instruction register 126 may represent firmware. Alternatively, instruction register 126 may represent a grouping of memory cells in memory cell array 104, such as a reserved block of memory cells.

[0031] Control logic 116 can also communicate with cache register 118. Cache register 118 latches incoming or outgoing data, such as data guided by control logic 116, to temporarily store data while memory cell array 104 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 118 to data register 120 to be transferred to memory cell array 104; then, new data can be latched from I / O control circuitry 112 into cache register 118. During read operations, data can be transferred from cache register 118 to I / O control circuitry 112 to be output to external processor 130; then, new data can be transferred from data register 120 to cache register 118. Cache register 118 and / or data register 120 may form a page buffer of memory device 100 (e.g., may form a portion thereof). The page buffer may additionally include sensing devices ( Figure 1 (Not shown in the diagram) to sense the data state of the memory cells, for example, by sensing the state of the data lines connected to the memory cells in the memory cell array 104. The status register 122 can communicate with the I / O control circuitry 112 and control logic 116 to latch status information for output to the processor 130.

[0032] The memory device 100 receives control signals from the processor 130 via control link 132 at control logic 116. These control signals may include chip enable (CE#), command latch enable (CLE), address latch enable (ALE), write enable (WE#), read enable (RE#), and write protection (WP#). Depending on the nature of the memory device 100, additional or alternative control signals (not shown) may be received via control link 132. The memory device 100 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the processor 130 via multiplexed input / output (I / O) bus 134 and outputs data to the processor 130 via I / O bus 134.

[0033] For example, a command can be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then written to command register 124. An address can be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then written to address register 114. Data can be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and then written to cache register 118. The data can then be written to data register 120 for programming memory cell array 104. In another embodiment, cache register 118 can be omitted, and data can be written directly to data register 120. Data can also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connections to the memory device 100 via external devices (e.g., processor 130).

[0034] Memory device 100 and / or processor 130 may receive power from power supply 136. Power supply 136 may represent any combination of circuitry for supplying power to memory device 100 and / or processor 130. For example, power supply 136 may comprise a single power supply (e.g., a battery), a wire-connected power supply (e.g., a switch-mode power supply common in desktop computers and servers or an AC adapter common in portable electronic devices), or a combination of both. Power is typically received from power supply 136 using two or more voltage supply nodes 137, such as a supply voltage node (e.g., Vcc or Vccq) and a reference voltage node (e.g., Vss or Vssq, such as ground or 0V). Providing more than two voltage supply nodes 137 is uncommon for power supply 136. For simplicity, the power distribution from voltage supply nodes 137 to components within memory device 100 is not depicted.

[0035] Those skilled in the art should understand that additional circuitry and signals can be provided, and that simplification has been achieved. Figure 1 The memory device 100. It should be understood that, with reference to Figure 1 The functionality of the various block components described need not be separated from different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device can be adapted to perform... Figure 1The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1 The functionality of a single block component.

[0036] Furthermore, although specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0037] A given processor 130 may communicate with one or more memory devices 100 (e.g., dies). Figure 2 This is a simplified block diagram of a device, according to another embodiment, in the form of a memory module 201 that is part of an electronic system and communicates with a host 240. The memory device 100 and processor 130 may be as described in reference... Figure 1 As described herein. Although memory module (e.g., memory package) 201 is depicted as having four memory devices 100 (e.g., dies), memory module 201 may have fewer or more memory devices 100. As used herein, die refers to an individual integrated circuit device that may contain memory devices 100 and may contain other integrated circuit devices.

[0038] Because the processor 130 (e.g., a memory controller) is located between the host 240 and the memory device 100, communication between the host 240 and the processor 130 may involve a different communication link than that used between the processor 130 and the memory device 100. For example, the memory module 201 may be an embedded multimedia memory card (eMMC) of a solid-state drive (SSD). According to existing standards, communication with the eMMC may include a data link 242 (e.g., an 8-bit link) for data transfer, a command link 244 for command transfer and device initialization, and a clock link 246 providing a clock signal to synchronize transfers on the data link 242 and the command link 244. The processor 130 can autonomously handle many activities, such as error correction, management of defective blocks, wear leveling, and address translation.

[0039] Figure 3A This is a side view representing a multi-die package 300 according to an embodiment. Figure 3AThe multi-die package 300 is depicted as comprising four dies 100 mounted to a circuit board 302 (i.e., 1000-1003 corresponding to dies 0-3), but the multi-die package may have fewer or more such dies. Each of the dies (e.g., memory devices) 100 may include one or more bonding pads 306 (e.g., bonding pads 3060-3063) for receiving a supply voltage or for inputting and / or outputting data signals, address signals, command signals, clock signals, status signals, etc. The multi-die package 300 may include bonding pads 304 of the circuit board 302 connected to one or more of the bonding pads 306 and thus connected to the dies 100. For example, in Figure 3A In this embodiment, bonding pad 304 is connected to bonding pads 3060 and 3061 via bonding wire 3080, and further connected to bonding pads 3062 and 3063 via bonding wire 3081. Bonding pad 304 may be further connected to one or more conductive nodes 310 of the circuit board 302, such as conductive bumps or other types of conductive nodes, for connection to external devices. Figure 3A The connection between the bonding pad 304 and the conductive node 310 is not depicted. Although Figure 3A Only one bonding pad 306 for each die 100 and one bonding pad 304 for the circuit board 302 are depicted, but the die 100 and the circuit board 302 typically have many such bonding pads 304 / 306 for various voltages and signals used therebetween.

[0040] To improve power delivery through the multi-die package 300, the supply voltage is typically connected to more than one bonding pad 304 and more than one conductive node 310. For example, each bonding pad 304 for the supply voltage may be connected to more than one conductive node 310 spaced around the multi-die package 300 and configured to receive the supply voltage, and each conductive node 310 configured to receive the supply voltage may be connected to more than one bonding pad 304. In this way, any bonding pad 304 configured to receive the supply voltage may be connected to each of the remaining bonding pads 304 configured to receive the supply voltage through a common connection to the same set of conductive nodes.

[0041] Figure 3A The multi-die package 300 may additionally include an extra die 100 in a mirror configuration. Figure 3B This is a side view representing a multi-die package 300 according to an embodiment having a mirror configuration. Figure 3B The multi-die package 300 is described as comprising eight dies 100 (i.e., 100 corresponding to dies 0L-dies 3L and dies 0R-dies 3R respectively). 0L -100 3L and 100 0R -1003R However, multiple die packages may have fewer or more such dies. Each of the dies (e.g., memory devices) 100 may include one or more bonding pads 306 (e.g., bonding pads 306) for receiving supply voltage or for inputting and / or outputting data signals, address signals, command signals, clock signals, status signals, etc. 0L -306 3L and 306 0R -306 3R The multi-die package 300 may include a circuit board 302 connected to a bonding pad 306. 0L -306 3L One or more of the first joint pads 304 L For example, in Figure 3B In the embodiment, the coupling gasket 304 L Through joint line 308 0L Connected to joint liner 306 0L and 306 1L And through the bonding line 308 1L Further connected to the joint liner 306 2L and 306 3L 304 bonding pad L It can be further connected to one or more conductive nodes 310 or other conductive nodes for connection to external devices. Figure 3B The joint liner 304 is not depicted in the text. L Connection to conductive node 310.

[0042] The multi-die package 300 may additionally include a connection of the circuit board 302 to the bonding pad 306. 0R -306 3R One or more of the second bonding pads 304 R For example, in Figure 3B In the embodiment, the coupling gasket 304 R Through joint line 308 0R Connected to joint liner 306 0R and 306 1R And through the bonding line 308 1R Further connected to the joint liner 306 2R and 306 3R 304 bonding pad R It can be further connected to one or more conductive nodes 310 or other conductive nodes for connection to external devices, and can be further connected to the bonding pad 304, for example, through the same set of conductive nodes. L .exist Figure 3B The joint liner 304 is not depicted in the text. R To conductive node 310 and bonding pad 304L The connection. Although Figure 3B Only one bonding pad 306 for each die 100 and two bonding pads 304 for the circuit board 302 are depicted, but the die 100 and the circuit board 302 typically have many such bonding pads 304 / 306 for various voltages and signals used therebetween.

[0043] Figure 3C This is a side view representing a multi-die package 300 according to another embodiment. Figure 3C The multi-die package 300 is depicted as comprising eight dies 100 (i.e., 1000-1007 corresponding to dies 0-7), although the multi-die package may have fewer or more such dies. Each of the dies (e.g., memory devices) 100 may include one or more bonding pads 306 (e.g., bonding pads 3060-3067) for receiving supply voltage or for inputting and / or outputting data signals, address signals, command signals, clock signals, status signals, etc. The multi-die package 300 may include a circuit board 302 connected to one or more bonding pads 304 of the bonding pads 306. For example, in Figure 3C In this embodiment, the bonding pad 304 is connected to bonding pads 3060-3063 via bonding wire 3080, and further connected to bonding pads 3064-3067 via bonding wire 3081. The bonding pad 304 may be further connected to one or more conductive nodes 310 or other conductive nodes for connection to external devices. Figure 3C The connection between the bonding pad 304 and the conductive node 310 is not depicted. Although Figure 3C Only one bonding pad 306 for each die 100 and two bonding pads 304 for the circuit board 302 are depicted, but the die 100 and the circuit board 302 will typically have many such bonding pads 304 / 306 for various voltages and signals used therebetween. Figure 3C The multi-die package 300 may additionally include, for example, similar to, in Figure 3A and Figure 3B The differences depicted between them are in a mirror configuration of an additional 100 nuggets.

[0044] Figure 3D This is a side view representing a multi-die package 300 according to yet another embodiment. Figure 3DThe multi-die package 300 is depicted as comprising eight dies 100 (i.e., 1000-1007 corresponding to dies 0-7), although the multi-die package may have fewer or more such dies. Each of the dies (e.g., memory devices) 100 may include one or more bonding pads 306 (e.g., bonding pads 3060-3067) for receiving supply voltage or for inputting and / or outputting data signals, address signals, command signals, clock signals, status signals, etc. The multi-die package 300 may include a circuit board 302 connected to one or more bonding pads 304 of the bonding pads 306. For example, in Figure 3D In this embodiment, the bonding pad 304 is connected to bonding pads 3060 and 3061 via bonding wire 3080, to bonding pads 3062 and 3063 via bonding wire 3081, to bonding pads 3064 and 3065 via bonding wire 3082, and to bonding pads 3066 and 3067 via bonding wire 3083. The bonding pad 304 may be further connected to one or more conductive nodes 310 or other conductive nodes for connection to external devices. Figure 3D The connection between the bonding pad 304 and the conductive node 310 is not depicted. Although Figure 3D Only one bonding pad 306 for each die 100 and one bonding pad 304 for the circuit board 302 are depicted, but the die 100 and the circuit board 302 will typically have many such bonding pads 304 / 306 for various voltages and signals used therebetween. Figure 3D The multi-die package 300 may additionally include, for example, similar to, in Figure 3A and Figure 3B The differences depicted between them are in a mirror configuration of an additional 100 nuggets.

[0045] Figure 4A This is a schematic representation of a multi-die package 300 comprising four dies 100 (e.g., 1000-1003) according to an embodiment. Figure 4A For example Figure 3A The embodiment depicted is a schematic representation. Signal HC# can be shared between the bare dies 100 via bonding pad 3045. Bonding pad 3045 can be connected via bonding line 308. 5-0 Connect to bare dies 1000 and 1001, and via bonding line 308. 5-1 Further connections are made to dies 1002 and 1003. The signal HC# can be shared with external devices via a conductive node 3105 connected to the bonding pad 3045 via resistor 416. Conductive node 3105 can be configured to receive a supply voltage, such as supply voltage Vcc. Therefore, the signal HC# can normally be pulled to a specific state, such as a nominal high condition. This configuration of resistor 416 can be referred to as a weak pull-up resistor, or simply a pull-up resistor.

[0046] The clock signal ppmCLK can be shared between the die 100 via bonding pad 3044. Bonding pad 3044 can be shared via bonding line 308. 4-0 Connect to bare dies 1000 and 1001, and via bonding line 308. 4-1 Further connections are made to bare dies 1002 and 1003. For clarity, in Figure 4A The connection between the bonding line 308 and the bonding pad 306 of the die 100 is not depicted. A clock signal ppmCLK can be received from an external device via a conductive node 3104 connected to the bonding pad 3044. Alternatively, the clock signal ppmCLK can be generated by one of the dies 100. Such clock signal generation is described in U.S. Patent No. 9,417,685, commonly assigned to Ha et al.

[0047] Clock signal ppmCLK and signal HC# can be used to transmit the expected peak current value of each die 100 to each remaining die 100. A method for transmitting expected peak current values ​​between dies 100 is described in U.S. Patent Application Publication 2021 / 0055772 A1, co-assigned to Guo. Such methods will be used in describing the various embodiments described herein. A method for transmitting expected peak current values ​​and additional information (such as priority tokens) between dies 100 is described in U.S. Provisional Patent Application Serial No. 63 / 182,015, co-assigned to Yu et al. Such methods are also suitable for use with the embodiments described herein. In general, any method for transmitting expected current requirements between dies 100 is suitable for use with the embodiments described herein.

[0048] The ready / busy control signal RB# can be shared between the bare dies 100 via bonding pad 3043. Bonding pad 3043 can be shared via bonding line 308. 3-0 Connect to bare dies 1000 and 1001, and via bonding line 308. 3-1 Further connections are made to dies 1002 and 1003. The ready / busy control signal RB# can be shared with external devices via a conductive node 3103 connected to the bonding pad 3043 via resistor 420. The conductive node 3103 can be configured to receive a supply voltage, such as supply voltage Vcc. Therefore, the ready / busy control signal RB# can be normally pulled to a specific state, such as being pulled high.

[0049] One or more control signals (e.g.) Figure 1 The control signals of the control link 132 depicted in the figure can be shared among the bare dies 100. Figure 4AThis describes an instance of control signals shared between the bare dies 100 via the bonding pad 3042. The bonding pad 3042 can be connected via the bonding line 308. 2-0 Connect to bare dies 1000 and 1001, and via bonding line 308. 2-1 Further connections are made to bare dies 1002 and 1003. Control signals can be received from external devices via conductive nodes 3102 connected to bonding pads 3042. Remaining control signals can be connected similarly.

[0050] One or more I / O signals (e.g.) Figure 1 The I / O signals of the I / O bus 134 depicted in the figure can be shared among the dies 100. Figure 4A This describes an instance of an I / O signal shared between the die 100 via a bonding pad 3041. The bonding pad 3041 can be connected via bonding line 308. 1-0 Connect to bare dies 1000 and 1001, and via bonding line 308. 1-1 Further connections are made to dies 1002 and 1003. I / O signals can be received from external devices via conductive nodes 3101 connected to bonding pads 3041. The remaining I / O signals can be connected similarly.

[0051] One or more supply voltages (e.g.) Figure 1 The supply voltage of the voltage supply node 137 depicted in the figure can be shared among the dies 100. Figure 4A This depicts an example of a voltage supply commonly shared between the bare dies 100 via a bonding pad 3040. The bonding pad 3040 can be connected via bonding wire 308. 0-0 Connect to bare dies 1000 and 1001, and via bonding line 308. 0-1 Further connections are made to bare dies 1002 and 1003. A supply voltage Vcc can be received from an external device via a conductive node 3100 connected to the bonding pad 3040. The remaining supply voltage can be connected similarly.

[0052] Figure 4B According to the embodiment, it includes eight bare dies 100 (e.g., 100 0L -100 3L and 100 0R -100 3R Schematic representation of a multi-die package 300. Figure 4B For example Figure 3B The illustration depicts an illustrative representation of an embodiment. One or more supply voltages (e.g., Figure 1 The supply voltage of the voltage supply node 137 depicted in the figure can be shared among the dies 100. Figure 4B Depicting the joint liner 304 0L and 3040R A common supply voltage, such as Vcc, is shared among the bare dies 100. Bonding pad 304 0L Through the 308 bonding line 0L-0 Connect to bare die 100 0L and 100 1L And through the bonding line 308 0L-1 Further connection to bare die 100 2L and 100 3L 304 bonding pad 0R Through the 308 bonding line 0R-0 Connect to bare die 100 0R and 100 1R And through the bonding line 308 0R-1 Further connection to bare die 100 2R and 100 3R It can be connected to the 304 coupling gasket. 0L Conductive node 310 0-0 And by connecting to the coupling liner 304 0R Conductive node 310 0-1 Receives supply voltage Vcc from an external device. Conductive node 310 0-0 Can be connected to conductive node 310 0-1 The remaining supply voltage can be connected similarly. For clarity, Figure 4B Connections for the clock signal ppmCLK, signal HC#, ready / busy control signal RB#, control signals, and I / O signals are not depicted. However, their connectivity may include the same configuration of bonding lines 308 and bonding pads 304 as depicted in the schematic diagram for supplying voltage Vcc.

[0053] Figure 4C This is a schematic representation of a multi-die package 300 comprising eight dies 100 (e.g., 1000-1007) according to an embodiment. Figure 4C For example Figure 3C The illustration depicts an illustrative representation of an embodiment. One or more supply voltages (e.g., Figure 1 The supply voltage of the voltage supply node 137 depicted in the figure can be shared among the dies 100. Figure 4C This depicts an instance of a supply voltage, such as Vcc, shared between the bare dies 100 via bonding pad 3040. Bonding pad 3040 can be connected via bonding line 308. 0-0 Connect to bare die 1000-1003, and through bonding line 308. 0-1Further connection is made to bare die 1004-1007. The supply voltage Vcc can be received from an external device via the conductive node 3100 connected to the bonding pad 3040. The remaining supply voltage can be connected similarly. For clarity, Figure 4C Connections for the clock signal ppmCLK, signal HC#, ready / busy control signal RB#, control signals, and I / O signals are not depicted. However, their connectivity may include the same configuration of bonding lines 308 and bonding pads 304 as depicted in the schematic diagram for supplying voltage Vcc.

[0054] Figure 4D This is a schematic representation of a multi-die package 300 comprising eight dies 100 (e.g., 1000-1007) according to an embodiment. Figure 4D For example Figure 3D The illustration depicts an illustrative representation of an embodiment. One or more supply voltages (e.g., Figure 1 The supply voltage of the voltage supply node 137 depicted in the figure can be shared among the dies 100. Figure 4D This depicts an instance of a supply voltage, such as Vcc, shared between the bare dies 100 via bonding pad 3040. Bonding pad 3040 can be connected via bonding line 308. 0-0 Connect to bare dies 1000 and 1001 via bonding wire 308 0-1 Connected to bare dies 1002 and 1003 via bonding line 308 0-2 Connected to bare dies 1004 and 1005, and via bonding line 308 0-3 Connect to bare dies 1006 and 1007. The supply voltage Vcc can be received from an external device via the conductive node 3100 connected to the bonding pad 3040. The remaining supply voltage can be connected similarly. For clarity, Figure 4D Connections for the clock signal ppmCLK, signal HC#, ready / busy control signal RB#, control signals, and I / O signals are not depicted. However, their connectivity may include the same configuration of bonding lines 308 and bonding pads 304 as depicted in the schematic diagram for supplying voltage Vcc.

[0055] In power management of multi-die packages, current demand budgets can be set for some major groups of dies within the multi-die package. This may involve all or some of the dies in the multi-die package sharing a common supply voltage. The current demand budget can be configured to help meet the power specifications of the multi-die package. For example, Figure 4A The main die groups of multi-die packages can include die 1000-1003; Figure 4B The primary die grouping of a multi-die package may include shared bonding pads 304. 0L 100 connected bare chips 0L-100 3L Shared with the joint liner 304 0R 100 connected bare chips 0R -100 3R Or nude film 100 0L -100 3L and 100 0R -100 3R ; Figure 4C The main die groups in multi-die packages can include die 1000-1007, and Figure 4D The main die groups for multi-die packages can include die 1000-1007.

[0056] However, it has been determined that lower current requirements of a subset of the die main group sharing the supply voltage (e.g., a subset of dies connected to the same bonding pad) can result in a voltage drop in the supply voltage, even when the die main group has a total current requirement less than specified. Therefore, various embodiments herein use a second current requirement budget for die subset 100, which is smaller than the current requirement budget for the die main group 100 containing that die subset 100. For some embodiments, where the number of dies in the die main group is N and the number of dies in a subset of the die main group is M, the second current requirement budget can be greater than M / N times the current requirement budget for the die main group. For example, for a group of four dies with a first current requirement budget of 600 mA, a subset of two dies can have a second current greater than 300 mA.

[0057] For simplicity, each die subset in the main die group can have the same second current demand budget. However, due to the different RC characteristics of the different bonding wires, such as due to different lengths, different die subsets can have different second current demand budgets.

[0058] Reference Figure 3A and 4A The multi-die package 300 discusses various embodiments. Clearly, such embodiments can utilize... Figure 3A and 4A The diagram depicts fewer or more dies 100. Generally, access operations on die 100 can be divided into several stages. These stages can be determined such that the access operation can be paused after completing one stage and before starting the next stage, without unnecessarily hindering the completion of the access operation except for causing delays. For example, pausing at the point would require discharging a node and restoring charge to the node before starting the next stage, so pausing the access operation may be undesirable. Similarly, pausing at the point would risk data loss or corruption, so pausing the access operation may be undesirable.

[0059] Each stage may correspond to a specific duration, which may be predefined (e.g., a stage with the same or similar timing characteristics each time it is executed) or variable (e.g., a stage whose timing characteristics change based on the detection of a certain analog characteristic). Each stage may further correspond to a specific expected peak current value. Table 1 provides an example of the expected peak current values ​​that can be assigned to the various stages of an access operation.

[0060] Table 1

[0061] Level Encoded value Expected peak current value 0 000 <=25mA 1 001 <=50mA 2 010 <=75mA 3 011 <=100mA 4 100 <=125mA 5 101 <=150mA 6 110 <=175mA 7 111 <=200mA

[0062] While the examples in Table 1 depict expected peak current values ​​for eight different levels, other numbers of expected peak current value levels can be used with the embodiments. For example, sixteen expected peak current value levels can be defined using four-digit encoded values ​​(e.g., digital representations), which provides finer control over the total current usage of a multi-die system. Furthermore, while the examples in Table 1 depict expected peak current value levels differing from adjacent expected peak current value levels by a constant difference, the current difference between adjacent levels does not need to be constant. The expected peak current value may not represent the actual peak current value, but rather the peak current value that will be used in determining whether and how to proceed with the next or initial phase of the access operation. For example, the actual peak current value may be high, but may also have a very short duration, thus being considered negligible.

[0063] Various embodiments facilitate power management in multi-die packages by: directing the dies in the package toward the expected peak current values ​​of that die and each remaining die in the die master group, and making decisions on how to proceed in response to a value indicating the sum of the expected peak current values ​​of the die master group and the sum of the expected peak current values ​​of the die subset of the die master group, in the event that that die will initiate the next phase of its access operation. Each die may broadcast its expected peak current value to the remaining dies, and each die may make informed decisions based on the sum of the expected peak current values. For example, if execution of the next phase under normal operating conditions would be considered to exceed a first current demand budget of the die master group containing that die and / or exceed a second current demand budget less than the first current demand budget of the die subset containing that die, then the die may decide to pause the access operation after completing its current phase of the access operation, or initiate the next phase in a different operating mode (e.g., a lower peak current operating mode).

[0064] Regarding the expected peak current value, the die can determine whether a transition to the next stage of operation is expected, which could be the next stage of the current operation or the initial stage of a new operation. If such a transition is expected, then its expected peak current value for the next stage can be determined. If such a transition is not expected, then its expected peak current value can be determined to be the expected peak current value of its current conditions (which may include an idle state). It should be noted that an idle die (e.g., a stage where no access operations are actively performed) can be considered to have a base value for the expected peak current value, which can be the lowest of a plurality of defined expected peak current values. It should also be noted that while an idle die can be considered to have an expected peak current value corresponding to the lowest of the plurality of expected peak current values, the lowest of the plurality of expected peak current values ​​may be sufficient to further correspond to certain stages of an operation actively performed by the die.

[0065] Alternatively, if the next stage of its operation can operate in a low peak current (LPC) operating mode, and such operation is enabled, the die can recalculate the total expected peak current value using the expected peak current value of the next stage's LPC operating mode. As an example, a LPC operating mode may include slowing down the charge pump or other voltage-generating devices to reduce current usage. This can increase the duration of the next stage, for example, the node may not quickly reach a predetermined voltage level. If at least one of the first and second current demand budgets is considered to exceed the expected peak current value of the next stage under normal operating conditions, but not to exceed the expected peak current value of the next stage's LPC operating mode, then the die can broadcast its expected peak current value to the remaining dies, having a value corresponding to the LPC operating mode of the next stage of its operation, and continue performing the next stage in the LPC operating mode.

[0066] Figure 5 This is a conceptual timing diagram of signals and register contents for manipulating the main packets of the die, according to an embodiment. Figure 5 Suppose, for example Figure 3A and 4A The multi-die package depicted has four dies 100. Figure 5In an example, the current demand budget for the main group of dies (e.g., a first current demand budget for die 0 1000, die 1 1001, die 2 1002, and die 3 1003) may be 600 mA. The current demand budget for each subset of dies (e.g., a second current demand budget for die 0 1000 and die 1 1001, or a second current demand budget for die 2 1002 and die 3 1003) may each be 350 mA. Each die 100 may have four registers 570 for storing information (e.g., current demand information) about the corresponding expected peak current value for each of the dies 100, such as die 0_ICC_reg 5700, die 1_ICC_reg 5701, die 2_ICC_reg 5702, and die 3_ICC_reg 5703.

[0067] The die pointer or memory device pointer Dptr indicates when each die or memory device 100 will broadcast its expected peak current value. (See reference...) Figure 6 In more detail, this may include a single clock signal in which each die 100 counts repeatedly and then responds when the count corresponds to that die 100. Alternatively, the die pointer Dptr may include a corresponding control signal for each of the dies 100, such as control signals C0-C3, wherein each of the dies 100 responds when its control signal has a predetermined logic level. The expected peak current value that will occur soon can be determined before the die 100 broadcasts its current demand information. (See reference...) Figure 6 In more detail, the broadcast of current demand information may include decoding the shared signal HC#. For Figure 5 For example, the various levels of the expected peak current magnitude can correspond to the levels in Table 1. Although not considered essential to the embodiments disclosed herein, U.S. Patent Application Publication No. 2021 / 0055772 A1, commonly assigned to Guo, discloses methods and apparatus for determining expected peak current magnitudes, and methods and apparatus for generating a signal HC#.

[0068] exist Figure 5Before time t0, die 0 may be idle, for example, having a expected peak current value of 25 mA, or less than or equal to 25 mA. Die 1 may be performing an access operation with a expected peak current value of 100 mA (e.g., less than or equal to 100 mA). Die 2 may be performing an access operation with a expected peak current value of 50 mA (e.g., less than or equal to 50 mA). Die 3 may be performing an access operation with a expected peak current value of 100 mA (e.g., less than or equal to 100 mA). Dies 1, 2, and 3 may be performing different access operations, or may be performing the same access operation but at different stages of that access operation.

[0069] In addition Figure 5 Before time t0, die 0 may receive a command indicating the intention to initiate an access operation. The initial phase of the access operation for die 0 may have an expected peak current of 200 mA in normal operating mode, and may not have an available low peak current operating mode. Given that the first current demand budget of 600 mA for the main die group comprising die 0, die 1, die 2, and die 3 is small, and given that die 1, die 2, and die 3 have expected peak currents of 100 mA, 50 mA, and 100 mA respectively, die 0 therefore determines that there exists a first current demand budget sufficient to initiate the next phase in normal operating mode, i.e., 200 mA + 100 mA + 50 mA + 100 mA <= 600 mA. Similarly, under a second current demand budget of 350 mA for a subset of dies including die 0 and die 1, and for die 1 with an expected peak current of 100 mA, die 0 also determines that there exists a second current demand budget sufficient to initiate the next phase in normal operating mode, i.e., 200 mA + 100 mA <= 350 mA. Therefore, its expected peak current will be 200 mA, and die 0 can broadcast its current demand information between times t0 and t1 as the expected peak current of 200 mA. Each of the dies can then update its register 5700 accordingly. If the sum of the expected peak current of each other die in the main die group plus the expected peak current of the die that determines whether to initiate its next phase is less than (e.g., less than or equal to) the first current demand budget, then the first current demand budget is sufficient. Similarly, if the sum of the expected peak current value of each other die in the determined subset of dies plus the expected peak current value of the die determining whether to initiate its next phase is less than (e.g., less than or equal to) the second current demand budget, then the second current demand budget may be sufficient. If the corresponding sum of the expected peak current values ​​is greater than that current demand budget, then the current demand budget may be insufficient.

[0070] exist Figure 5 Before time t1, die 1 can complete its access operation at one stage and determine that the subsequent stage of its access operation has an expected peak current of 200 mA in normal operating mode, and may not have an available low peak current operating mode. Die 1 will therefore determine that there exists a first current demand budget sufficient to initiate the next stage in normal operating mode (e.g., 200 mA + 200 mA + 50 mA + 100 mA <= 600 mA). However, die 1 will also determine that there does not exist a second current demand budget sufficient to initiate the next stage in normal operating mode (e.g., 200 mA + 200 mA > 350 mA). Therefore, it can be determined that a pause will be needed, e.g., a continued pause, and its expected peak current is expected to decrease to the level of an idle die, e.g., 25 mA. Die 1 can therefore broadcast its current demand information between time t1 and t2 as an expected peak current of 25 mA. Each of the dies can then update its register 5701 accordingly.

[0071] exist Figure 5 Before time t2, die 2 can complete its access operation at one stage and determine that the subsequent stage of its access operation has an expected peak current of 200 mA in normal operating mode, and may not have an available low peak current operating mode. Die 2 will therefore determine that there exists a first current demand budget sufficient to initiate the next stage in normal operating mode (e.g., 200 mA + 25 mA + 200 mA + 100 mA <= 600 mA) and a second current demand budget sufficient to initiate the next stage in normal operating mode (e.g., 200 mA + 100 mA <= 350 mA). Therefore, its expected peak current will be 200 mA, and die 2 can broadcast its current demand information between times t2 and t3 as the expected peak current of 200 mA. Each of the dies can then update its register 5702 accordingly.

[0072] exist Figure 5Before time t3, die 3 can complete its access operation at one stage and determine that the subsequent stage of its access operation has an expected peak current of 200 mA in normal operating mode and an expected peak current of 75 mA in low peak current operating mode. Die 3 will therefore determine that there is no first current demand budget sufficient to initiate the next stage in normal operating mode (e.g., 200 mA + 25 mA + 200 mA + 200 mA > 600 mA) and no second current demand budget sufficient to initiate the next stage in normal operating mode (e.g., 200 mA + 200 mA > 350 mA). Die 3 can further determine (e.g., subsequently determine) that there is a first current demand budget sufficient to initiate the next stage in low peak current operating mode (e.g., 200 mA + 25 mA + 200 mA + 75 mA <= 600 mA) and a second current demand budget sufficient to initiate the next stage in low peak current operating mode (e.g., 200 mA + 75 mA <= 350 mA). Therefore, its expected peak current value will be 75 mA, and die 3 can broadcast its current demand information between times t3 and t4 as the expected peak current value of 75 mA. Each of the dies can then update its register 5703 accordingly.

[0073] exist Figure 5 Before time t4, die 0 can complete its access operation at one stage and determine that the subsequent stage of its access operation has an expected peak current of 100 mA in normal operating mode, and may not have an available low peak current operating mode. Die 0 will therefore determine that there exists a first current demand budget sufficient to initiate the next stage in normal operating mode (e.g., 100 mA + 25 mA + 200 mA + 75 mA <= 600 mA), and a second current demand budget sufficient to initiate the next stage in normal operating mode (e.g., 100 mA + 25 mA <= 350 mA). Therefore, its expected peak current will be 100 mA, and die 0 can broadcast its current demand information between times t4 and t5 as the expected peak current of 100 mA. Each of the dies can then update its register 5700 accordingly.

[0074] exist Figure 5Before time t5, die 1 can still wait for the next phase, which has an expected peak current of 200 mA, to initiate its access operation in normal operating mode. At this time, die 1 will determine that there exists a first current demand budget sufficient to initiate the next phase in normal operating mode (e.g., 100 mA + 200 mA + 200 mA + 75 mA <= 600 mA), and a second current demand budget sufficient to initiate the next phase in normal operating mode (e.g., 100 mA + 200 mA <= 350 mA). Therefore, its expected peak current will be 200 mA, and die 1 can broadcast its current demand information between times t5 and t6 as the expected peak current of 200 mA. Each of the dies can then update its register 5701 accordingly.

[0075] exist Figure 5 Before time t6, die 2 can determine that it is still in the phase of performing its access operation. Therefore, its expected peak current value is expected to remain at 200 mA, and die 2 can broadcast its current demand information between times t6 and t7 as the expected peak current value of 200 mA. Each of the dies can then update its register 5702 accordingly.

[0076] exist Figure 5 Before time t7, die 3 can complete its access operation at one stage and determine that the subsequent stage of its access operation has an expected peak current of 200 mA in normal operating mode and an expected peak current of 100 mA in low peak current operating mode. Die 3 will therefore determine that there is no first current demand budget sufficient to initiate the next stage in normal operating mode (e.g., 100 mA + 200 mA + 200 mA + 200 mA > 600 mA) and no second current demand budget sufficient to initiate the next stage in normal operating mode (e.g., 200 mA + 200 mA > 350 mA). Die 3 can further determine (e.g., subsequently determine) that there is a first current demand budget sufficient to initiate the next stage in low peak current operating mode (e.g., 100 mA + 200 mA + 200 mA + 100 mA <= 600 mA) and a second current demand budget sufficient to initiate the next stage in low peak current operating mode (e.g., 200 mA + 100 mA <= 350 mA). Therefore, its expected peak current value will be 100 mA, and die 3 can broadcast its current demand information between times t7 and t8 as the expected peak current value of 100 mA. Each of the dies can then update its register 5703 accordingly.

[0077] Figure 6 This is an example of a timing diagram depicting clocks and other signals according to an embodiment. Figure 6 Suppose, for example Figure 3A and 4A The image depicts four nude pieces 100, and corresponds to, as per the description... Figure 5 A multi-die package displaying current demand information. Various embodiments provide each die (e.g., sequentially) with the opportunity to: assess its expected peak current value over a certain time period (e.g., a future time period) to determine whether to continue or suspend its operation, and to broadcast its expected peak current value to the remaining dies before or during that time period. Figure 6 In the diagram, trace 650 may represent the clock signal ppmCLK.

[0078] In one embodiment, trace 652 may represent a die pointer Dptr generated by dividing the clock signal ppmCLK. For example, the control signal for trace 652 may represent one pulse for every X cycles of the clock signal ppmCLK, where in this example, X=4. Each of dies 1000-1003 may then count the pulses of the die pointer Dptr in a repeatable manner (e.g., counting from 0 to 3), and then repeat the sequence starting from count 0 in response to subsequent pulses of the die pointer Dptr. Each of dies 1000-1003 may be assigned a corresponding count value. In this way, die 1000 may respond to each count 0, die 1001 may respond to each count 1, die 1002 may respond to each count 2, and die 1003 may respond to each count 3. The value of X may be selected in response to the desired number of cycles of the clock signal ppmCLK used when broadcasting the expected peak current value to other dies, as will be described in more detail below. Using the example in Table 1, the expected peak current value is represented by three digits of the data, and three clock cycles can be used for the broadcast of this digital representation. Therefore, the value of X can be equal to or greater than the number of clock cycles used for broadcasting.

[0079] Alternatively, each die 100 may respond to a separate control signal. For example, traces 6540-6543 may represent counter signals C0-C3, respectively. The control signals for traces 6540-6543 may represent pulses every D*X cycles of the clock signal ppmCLK, where in this example, D=4 and X=4. The value of D may be equal to the number of dies sharing the clock signal ppmCLK, and the number of counter signals may be equal to D. The value of X may be selected in response to the desired number of cycles of the clock signal ppmCLK used when broadcasting the expected peak current value to other dies, as will be described in more detail below, and the pulses of traces 6540-6543 may be staggered from each other by X cycles of the clock signal ppmCLK. In this embodiment, each die 1000-1003 may respond to a corresponding counter signal C0-C3. For example, die 1000 can respond to the counter signal C0 of trace 6540, die 1001 can respond to the counter signal C1 of trace 6541, die 1002 can respond to the counter signal C2 of trace 6542, and die 1003 can respond to the counter signal C3 of trace 6543.

[0080] Furthermore, the counter signals C0-C3 of traces 6540-6543 can be provided as combined control signals with D-digit information to each die 1000-1003. Each of dies 1000-1003 can be assigned a corresponding value of the combined control signal. In this way, die 1000 can respond to the value (e.g., a digital value) 1000, die 1001 can respond to the value 0100, die 1002 can respond to the value 0010, and die 1003 can respond to the value 0001. While not considered essential to the embodiments disclosed herein, U.S. Patent No. 9,417,685, commonly assigned to Ha et al., describes a circuit system of the type that can be used to generate counter signals C0-C3.

[0081] The following example of broadcasting current demand information will use counter signals C0-C3 to determine which die 1000-1003 is designated to broadcast its current demand information. However, it will be apparent that any method of sequentially cycling through the dies can be used. Various embodiments utilize a shared signal (e.g., signal HC#) to provide the encoded value (e.g., digital representation) of the current demand information of one die in a multi-die package to each remaining die of signal HC# on the shared trace 656 of the multi-die package. It should be noted that although Figure 6For convenience, the counter signals C0-C3 of traces 6540-6543 are depicted as aligned with the clock signal ppmCLK of trace 650. However, it is expected that there will be some delay in the generation of counter signals C0-C3 from the clock signal ppmCLK, such that the time t0 of the counter signals C0-C3 may not be aligned with the time t0 of the clock signal ppmCLK. Similarly, the time t0 of signal HC# may not be aligned with the time t0 of the clock signal ppmCLK. However, a transition in one of these signals at a specific time can be considered as a response to a transition in the clock signal ppmCLK corresponding to that specific time. Figure 6 Each time period (e.g., t0-t1, t1-t2, t3-t4, etc.) corresponds to one clock cycle of the clock signal ppmCLK.

[0082] refer to Figure 6 Trace 6540 can transition to a first logic level at time t0 and time t16, trace 6541 can transition to a first logic level at time t4 and time t20, trace 6542 can transition to a first logic level at time t8 and time t24, and trace 6543 can transition to a first logic level at time t12 and time t28. This mode can continue while die 100 is in operation. Traces 6540-6543 may also have a second logic level different from their first logic level. For example, trace 654's first logic level may be logic high, and its second logic level may be logic low.

[0083] In this example, die 1000 can be specified at time t0, for example, in response to trace 6540 transitioning to a first logic level. Die 1000 can then broadcast its current demand information by encoding the signal HC# of trace 656 as representing a three-digit value 111 during one or more subsequent cycles of the clock signal ppmCLK of trace 650. For example, die 1000 can cause the signal HC# to have its first logic level during time periods t1-t2, t2-t3, and t3-t4, thereby representing the digital value 111.

[0084] Die 1001 can be specified at time t4, for example, in response to trace 6541 transitioning to a first logic level. Die 1001 can then broadcast its current demand information by encoding the signal HC# to represent a three-digit value 001. For example, die 1001 can cause the signal HC# to have its second logic level during time periods t5-t6 and t6-t7, and its first logic level during time period t7-t8, thus representing the digital value 001.

[0085] Die 1002 can be specified at time t8, for example, in response to trace 6542 transitioning to a first logic level. Die 1002 can then broadcast its current demand information by encoding the signal HC# to represent a three-digit value 111. For example, die 1002 can cause the signal HC# to have its first logic level during time periods t9-t10, t10-t11, and t11-t12, thereby representing the digital value 111.

[0086] At time t12, for example, in response to trace 6543 transitioning to a first logic level, die 1003 can be specified. Die 1003 can then broadcast its current demand information by encoding the signal HC# to represent a three-digit value 010. For example, die 1003 can cause the signal HC# to have its second logic level during time period t13-t14, its first logic level during time period t14-t15, and its second logic level during time period t15-t16, thereby representing the digital value 010.

[0087] At time t16, die 1000 can be re-designated, for example, in response to trace 6540 transitioning back to the first logic level. Die 1000 can then broadcast its current demand information by encoding the signal HC# to represent the three-digit value 011. For example, die 1000 can cause the signal HC# to have its second logic level during time periods t17-t18 and its first logic level during time periods t18-t19 and t19-t20, thus representing the digital value 011.

[0088] At time t20, die 1001 can be re-designated, for example, in response to trace 6541 transitioning back to the first logic level. Die 1001 can then broadcast its current demand information by encoding the signal HC# to represent the three-digit value 111. For example, die 1001 can cause the signal HC# to have its first logic level during time periods t21-t22, t22-t23, and t23-t24, thereby representing the digital value 111.

[0089] At time t24, for example, in response to trace 6542 transitioning back to the first logic level, die 1002 can be re-designated. Die 1002 can then broadcast its current demand information by encoding the signal HC# to represent the three-digit value 111. For example, die 1002 can cause the signal HC# to have its first logic level during time periods t25-t26, t26-t27, and t27-t28, thereby representing the digital value 111.

[0090] At time t28, die 1003 can be re-designated, for example, in response to trace 6543 transitioning back to the first logic level. Die 1003 can then broadcast its current demand information by encoding the signal HC# to represent the three-digit value 010. For example, die 1003 can cause the signal HC# to have its second logic level during time period t29-t30, its first logic level during time period t30-t31, and its second logic level during time period t31-t32, thereby representing the digital value 010.

[0091] Given the foregoing examples, it will be clear that fewer or more clock cycles of the clock signal ppmCLK can be used to represent digital representations of different sequences, to represent lower or higher granularity of the expected peak current value, respectively. Furthermore, while the foregoing examples complete the broadcasting of the digital representation for a die before specifying the next die, these two actions can overlap. For example, the counter signal C0 may transition at time t0, and die 1000 may broadcast its digital representation from time t1 to time t4, as... Figure 6 As described in the text. However, in this alternative example, the counter signal C1 may change at time t3, for example, when die 1000 is broadcasting the last digit of its digital representation, and die 1001 may begin broadcasting its digital representation at time t4. Similarly, the counter signal C2 may change at time t6, for example, when die 1001 is broadcasting the last digit of its digital representation, and die 1002 may begin broadcasting its digital representation at time t7, and so on.

[0092] Figure 7 A flowchart depicts a method for operating a die (e.g., a memory device or other integrated circuit device) according to an embodiment. The method may be in the form of computer-readable instructions, for example, stored in instruction register 128. Such computer-readable instructions may be executed by a controller (e.g., control logic 116) to cause the die (e.g., associated components of the die) to perform the method.

[0093] At 703, a determination can be made as to whether the die is expecting to initiate the next stage of an access operation, which may be the initial stage of the access operation. As used herein, a die expecting to initiate the next stage of an access operation includes a die that has completed the previous stage of the access operation, a die that has completed the previous access operation, or a die that is paused and waiting to initiate the next stage of the access operation, or a die that is performing the previous stage of the access operation, which will be completed, for example, within a predetermined time period before the die is re-assigned to make its determination. In response to determining that the die is not expecting to initiate the next stage of the access operation, the die may proceed to 705 and continue its current condition. The die may additionally broadcast current demand information for its current condition. The die's current condition may be idle, even if it has received a command to perform the next access operation, and the die may additionally remain in an idle state. Alternatively, the die's current condition may be a stage where the access operation is actively performed, and the die may continue performing that stage of the access operation. In some embodiments, the current demand information may include an indicator of the expected peak current value.

[0094] In response to determining that the die is expected to initiate the next stage of an access operation, such as after the previous stage of an access operation has been completed or after a previous access operation has been completed, the process may proceed to 711 and determine whether there exists a first current demand budget (CB) for the next stage of the access operation in the selected operating mode of one or more operating modes of the die main group containing the die, sufficient to initiate the access operation in the next stage of the access operation of the die in the die main group. Main ), and whether there exists a second current demand budget (CB) for the next stage of the main die group that also contains the die, sufficient to initiate the access operation in the selected operating mode. Sub In response to determining that there are sufficient first and second current demand budgets to continue, the die may initiate the next phase of its access operation at 713 in the selected operating mode. The die may additionally broadcast the current demand information of the selected operating mode for that phase of its access operation. The selected operating mode may be a normal operating mode, regardless of whether a low-peak-current operating mode is available. Alternatively, the selected operating mode may be a normal operating mode in response to determining that there is sufficient available current demand budget to initiate the next phase in the normal operating mode, and may be a low-peak-current operating mode in response to determining that there is no available current demand budget to initiate the next phase in the normal operating mode, but there is sufficient available current demand budget to initiate the next phase in the low-peak-current operating mode.

[0095] In response to the determination that there is no sufficient first or second current requirement budget to continue in the selected operating mode, the die may switch to 715 and suspend its operation to wait for sufficient current requirement budget, such as delaying the initiation of the next stage of the access operation. The die may additionally broadcast the current requirement information of the suspended die, which may be the same as the current requirement information of the idle die.

[0096] Figure 7 The process can be repeated sequentially for each die in the main die group when the die is enabled, for example, by a chip enable signal. In some embodiments, Figure 7 The process can be repeated for an enabled die in response to at least one of the dies in a multi-die package indicating that it is busy (e.g., indicated by a shared ready / busy control signal).

[0097] Figure 8 A flowchart depicts a method for operating multiple dies (e.g., memory devices or other integrated circuit devices) according to an embodiment. The method may be in the form of computer-readable instructions, for example, stored in instruction register 128. Such computer-readable instructions may be executed by a controller, such as control logic 116, causing the dies (e.g., associated components of the dies) to perform the method.

[0098] At position 801, variable N can be initialized to the value N. init The value of variable N can represent an integer value of a counter (e.g., a wrap-around counter) used to count the representative value of each die in a multi-die package. For example, in a first embodiment with D dies, the value of N can be N... init Initialized at point D, and countable to the value D + N. init -1. For example, when D=4 and N init When N = 0, the counter can advance (e.g., increment) from 0 to 3 before being reinitialized to 0. Alternatively, if for this instance, N = 0, then N = 0. init If the value is 1, then the counter can advance from 1 to 4 before being reinitialized to 1. In other embodiments, the variable N can represent the corresponding digit pattern among D digit patterns, for example, refer to... Figure 6 The digital modes of the four control signals C0, C1, C2, and C3 are described. Therefore, Figure 8 The variable N described in the text can be represented by a loop of D unique values. Figure 6 The described numerical pattern is a cycle of 1000, 0100, 0010, and 0001. Furthermore, while referring to the discussion of increasing sequences... Figure 8 The embodiments described herein may vary, but the sequence of values ​​for N may alternatively decrease in a visually apparent manner during the disclosed process, for example, the value of N may decrease at N... init Initialize at the point, and count to the value N before reinitialization.init + 1 - D. For example, when D=4 and N init With a value of 3, the counter can advance (e.g., decrement) from 3 to 0 before being reinitialized to 3. Other sequencing schemes with a sequence of D unique values ​​can be used, where each of the D dies broadcasts current demand information on a shared signal in response to the value of N corresponding to the corresponding unique value among the D unique values.

[0099] At 803, a determination can be made as to whether the die corresponding to the current value of N (e.g., die N) is expecting to initiate the next stage of an access operation, which may be the initial stage of the expected execution of the access operation, or the next stage of the currently executing access operation. In response to determining that die N is not expecting to initiate the next stage of its access operation, the process can proceed to 805 and the die may continue with its current condition. Die N may additionally broadcast current demand information for its current condition. The current condition of die N may be idle, and die N may additionally continue in an idle state. Alternatively, the current condition of die N may be a stage where an access operation is actively performed, and die N may continue to perform that stage of the access operation. In some embodiments, the current demand information may include an indicator of the expected peak current value.

[0100] In response to determining that die N is expected to initiate the next stage of an access operation, such as after the previous stage of an access operation has been completed or after a previous access operation has been completed, the process may proceed to 811 and determine whether there exists a first current demand budget (CB) for the next stage of the access operation in the selected operating mode of one or more operating modes of the die main group containing the die, sufficient to initiate the access operation in the next stage of the access operation of the die in the die main group. Main ), and whether there exists a second current demand budget (CB) for the next stage of the access operation in the selected operating mode, which is sufficient to include a subset of dies that also contains die N for the main die group. SubN In response to determining that there are sufficient first and second current demand budgets to continue, the die may initiate the next phase of its access operation at 813 in the selected operating mode. The die may additionally broadcast the current demand information of the selected operating mode for that phase of its access operation. The selected operating mode may be a normal operating mode, regardless of whether a low-peak-current operating mode is available. Alternatively, the selected operating mode may be a normal operating mode in response to determining that there are sufficient available current demand budgets to initiate the next phase in the normal operating mode, and may be a low-peak-current operating mode in response to determining that there are no available current demand budgets to initiate the next phase in the normal operating mode, but there are available current demand budgets to initiate the next phase in the low-peak-current operating mode.

[0101] In response to the determination that there is no sufficient first or second current requirement budget to continue in the selected operating mode, the die may switch to 815 and suspend its operation to wait for sufficient current requirement budget, such as delaying the initiation of the next stage of the access operation. The die may additionally broadcast the current requirement information of the suspended die, which may be the same as the current requirement information of the idle die.

[0102] From 805, 813, or 815, the process can proceed to 807 and determine whether the value of N is, for example, the last value of the sequence. In response to determining that the value of N is not the last value of the sequence, the value of N can advance at 809, for example, by incrementing an increment counter, decrementing a decrement counter, changing to the next digit pattern in a sequence of multiple digit patterns, etc. From 809, the process can return to 803. In response to determining at 807 that the value of N is the last value of the sequence, the process can return to 801 to initialize (e.g., reinitialize) the value of N before continuing to 803.

[0103] Figure 8 The process can be repeated when D dies are enabled, for example, by a chip enable signal. In some embodiments, Figure 8 The process can be repeated for an enabled die in response to at least one indication in the die that it is busy (e.g., indicated by a shared ready / busy control signal).

[0104] Figure 9A This is a flowchart of a method for operating a die (e.g., a memory device or other integrated circuit device) according to various embodiments. Figure 9A Provide additional details on how to make determinations about the following: for example, in Figure 7 711 or Figure 8 At point 811, does the die have sufficient first and second current requirement budgets to initiate the next stage of an access operation in the selected operating mode, and for example in... Figure 7 713 or Figure 8At 913, the selected operating mode can be any operating mode. For example, at 911-1, the die can determine whether there are first and second current requirement budgets sufficient to initiate the next stage of the access operation in the normal operating mode for the die's access operation. In response to determining that there are first and second current requirement budgets sufficient to initiate the next stage of the access operation in the normal operating mode, the normal operating mode is the selected operating mode, and the die can initiate the next stage of the access operation in the normal operating mode at 913-1. In response to determining that there are no first and / or second current requirement budgets sufficient to initiate the next stage of the access operation in the normal operating mode, the process can proceed to 912-2, where a determination can be made regarding the existence of an available low peak current (LPC) operating mode. In response to determining at 912-2 that no LPC operating mode is available, the die can suspend its operation or continue to suspend its operation, waiting for sufficient current requirement budget. In response to determining that an available LPC operating mode exists, the process can proceed to 911-2.

[0105] At 911-2, the die can determine whether there are first and second current requirement budgets sufficient to initiate the next stage of the access operation in a low-peak-current operating mode for the die's access operation. In response to determining that there are first and second current requirement budgets sufficient to initiate the next stage of the access operation in a low-peak-current operating mode, which is the selected operating mode, the die can initiate the next stage of the access operation in the low-peak-current operating mode at 913-2. In response to determining that there are no first and / or second current requirement budgets sufficient to initiate the next stage of the access operation in the low-peak-current operating mode, the die can pause its operation or continue to pause its operation, waiting for sufficient current requirement budgets.

[0106] Figure 9B This is a flowchart of a method for operating a die (e.g., a memory device or other integrated circuit device) according to various embodiments. Figure 9B Provide additional details on how to make determinations about the following: for example, in Figure 7 711 or Figure 8 At point 811, does the die have sufficient first and second current requirement budgets to initiate the next stage of an access operation in the selected operating mode, and for example in... Figure 7 713 or Figure 8At 813, the selected operating mode can be any operating mode. For example, at 911-1, the die can determine whether there are first and second current requirement budgets sufficient to initiate the next stage of the access operation in a first operating mode (which may be a normal operating mode) for the die's access operation. In response to determining that there are first and second current requirement budgets sufficient to initiate the next stage of the access operation in the first operating mode, the first operating mode being the selected operating mode, and the die can initiate the next stage of the access operation in the first operating mode at 913-1. In response to determining that there are no first and / or second current requirement budgets sufficient to initiate the next stage of the access operation in the first operating mode, the process can proceed to 912-2, where a determination can be made regarding the existence of a second operating mode (which may be a low-peak-current operating mode). In response to determining at 912-2 that no second operating mode is available, the die can suspend its operation or continue to suspend its operation, waiting for sufficient current requirement budget. In response to determining that a second operating mode is available, the process can proceed to 911-2.

[0107] At 911-2, the die can determine whether there are first and second current requirement budgets sufficient to initiate the next stage of the access operation in a second operating mode for the next stage of the access operation for the die. In response to determining that there are first and second current requirement budgets sufficient to initiate the next stage of the access operation in the second operating mode, where the second operating mode is the selected operating mode, the die can initiate the next stage of the access operation in the second operating mode at 913-2. In response to determining that there are no first and / or second current requirement budgets sufficient to initiate the next stage of the access operation in the second operating mode, the process can proceed to determining whether any subsequent operating modes are available, and whether those operating modes satisfy the first and second current requirement budgets before making a determination at 912-N whether the Nth operating mode is available. In response to determining that the Nth operating mode is available, the process can proceed to 911-N.

[0108] At 911-N, the die can determine whether there are first and second current requirement budgets sufficient to initiate the next stage of the access operation in the Nth operating mode for the next stage of the access operation for the die. In response to determining that there are first and second current requirement budgets sufficient to initiate the next stage of the access operation in the Nth operating mode, where the Nth operating mode is the selected operating mode, the die can initiate the next stage of the access operation in the Nth operating mode at 913-N. In response to determining that there are no first and / or second current requirement budgets sufficient to initiate the next stage of the access operation in the Nth operating mode, the die can suspend its operation or continue to suspend its operation, waiting for sufficient current requirement budget.

[0109] The selected operating mode can be the optimal operating mode among the available operating modes where there are sufficient first and second current demand budgets. For example, for an access operation with N operating modes arranged in order from the first operating mode considered the most preferred (e.g., normal operating mode) to the Nth operating mode considered the least preferred, the die can evaluate the expected peak current value of each of the N operating modes until it is determined that one operating mode has an expected peak current value that satisfies the first and second current demand budgets. It should be noted that the operating modes do not need to be arranged in descending order of expected peak current demand.

[0110] Figures 10A-10C This is a flowchart of a portion of a method for operating a bare die according to an embodiment. Specifically, Figures 10A-10C The determination of whether there are first and second current demand budgets sufficient to initiate the next phase in the selected operating mode can be performed in parallel (e.g., simultaneously) or sequentially. For example, Figure 10A Describe parallel operations, while Figure 10B and 10C Describe the sequence of operations. Figures 10A-10C Each can express their own opinion. Figure 7 Frame 711 Figure 8 Box 811, or Figure 9B Any box 911-X, where X represents any value of N for the N operation mode.

[0111] refer to Figure 10A At 1021, the die can determine whether there exists a first current demand budget for the main die group containing the die, sufficient to initiate the next stage of the access operation in a selected operating mode among one or more operating modes of the die. At 1023, the die can determine whether there exists a second current demand budget for the main die group, also containing the die, sufficient to initiate the next stage of the access operation in a selected operating mode among one or more operating modes of the die. Both 1021 and 1023 can be executed simultaneously and can each be evaluated to true or false, e.g., 1 or 0, and these outputs can be provided as inputs to AND gate 1025. At 1027, if the output of AND gate 1025 is true, e.g., 1, then the process can proceed to 713 / 813 / 913-X to initiate the next stage of the access operation. If the output of AND gate 1025 is false, such as 0, then the process can proceed to 715 / 815 to pause the die. Clearly, other logic levels and circuitry can be used to determine whether both 1021 and 1023 are evaluated as true.

[0112] It should be noted that when the die is switched to 713 / 813 / 913-X, the selected operating mode can be the operating mode with the lowest peak current value between the determination at 1021 and the determination at 1023. For example, if there is a sufficient first current demand budget at 1021 in the normal operating mode, and a sufficient second current demand budget at 1023 only in the low peak current operating mode, then the selected operating mode will be the low peak current operating mode.

[0113] refer to Figure 10B At 1021, the die can determine whether there exists a first current requirement budget for the next stage of the access operation in a selected operating mode of one or more operating modes for the main die group containing the die, sufficient to initiate the access operation of the die in the next stage of the access operation of the die. In response to determining at 1021 that there is a sufficient first current requirement budget, the process can proceed to 1023, and in response to determining at 1021 that there is no sufficient first current requirement budget, the process can proceed to 715 / 815 to pause the die operation, which allows avoiding the evaluation of whether there is a sufficient second current requirement budget. At 1023, the die can determine whether there exists a second current requirement budget for the next stage of the access operation in a selected operating mode of one or more operating modes for the main die group, which also contains the die, sufficient to initiate the access operation of the next stage of the access operation of the die in the next stage of the access operation of the die in the next stage of the access operation of the die. In response to determining at 1023 that there is a sufficient second current requirement budget, the process can proceed to 713 / 813 / 913-X to initiate the next stage of the access operation. In response to the determination at 1023 that there is no sufficient budget for the second current requirement, the process can be switched to 715 / 815 to pause the die.

[0114] for Figure 10B The die can evaluate multiple operating modes at 1021, considering N operating modes in descending order of current demand. At 1023, the die can then consider operating modes where there is a sufficient first current demand budget at 1021, and continue in descending order of current demand from there. If the die transitions from 1023 to 713 / 813 / 913-X, the selected operating mode can be the one that satisfies the determined operating mode at 1023.

[0115] refer to Figure 10CAt 1023, the die can determine whether there exists a second current requirement budget for the next stage of the access operation in a selected operating mode, which is sufficient for the primary die group and also contains the die, to initiate the access operation in one or more operating modes of the die. In response to determining at 1023 that there is a sufficient second current requirement budget, the process can proceed to 1021, and in response to determining at 1023 that there is no sufficient second current requirement budget, the process can proceed to 715 / 815 to pause the die operation, which allows avoiding the evaluation of whether there is a sufficient first current requirement budget. At 1021, the die can determine whether there is a first current requirement budget for the primary die group sufficient to initiate the next stage of the access operation in a selected operating mode. In response to determining at 1021 that there is a sufficient first current requirement budget, the process can proceed to 713 / 813 / 913-X to initiate the next stage of the access operation. In response to the determination at 1021 that there is no sufficient budget for the first current requirement, the process can be switched to 715 / 815 to pause the die.

[0116] for Figure 10C The evaluation of multiple operating modes allows the die to consider N operating modes at 1023 in descending order of current demand. At 1021, the die can then consider operating modes where there is a sufficient second current demand budget at 1023, and continue the descending order of current demand from there. If the die transitions from 1021 to 713 / 813 / 913-X, the selected operating mode can be the one that satisfies the determined operating mode at 1021.

[0117] in conclusion

[0118] While specific embodiments have been illustrated and described herein, those skilled in the art will understand that any arrangement contemplated to achieve the same purpose may replace the specific embodiments shown. Many adaptations to the embodiments will be apparent to those skilled in the art. Therefore, this application is intended to cover any adaptations or variations of the embodiments.

Claims

1. A memory device comprising: an array of memory cells; a plurality of registers, wherein each register of the plurality of registers corresponds to a respective memory device of a plurality of memory devices that includes the memory device, wherein each register of the plurality of registers is configured to store an expected peak current flow value of its respective memory device, wherein the plurality of registers comprises a plurality of subsets of registers, and wherein a particular subset of memory devices of a plurality of subsets of memory devices includes the memory device; and a controller for accessing the array of memory cells, wherein the controller is configured to cause the memory device to: determine whether the memory device is expecting a next phase of an access operation to be initiated to the array of memory cells; in response to determining that the memory device is expecting the next phase of the access operation to be initiated: generate a first sum of a respective expected peak current flow value of each register of the plurality of registers other than a respective register of the memory device and an expected peak current flow value for the next phase of the access operation in a selected mode of operation; generate a second sum of a respective expected peak current flow value of each register of a particular subset of registers other than the respective register of the memory device and an expected peak current flow value for the next phase of the access operation in the selected mode of operation; compare the first sum to a first current demand budget for the plurality of memory devices; compare the second sum to a second current demand budget for the particular subset of memory devices, wherein the second current demand budget is less than the first current demand budget; and in response to the first sum being less than or equal to the first current demand budget and the second sum being less than or equal to the second current demand budget, initiate the next phase of the access operation in the selected mode of operation.

2. The memory device of claim 1, wherein the controller is further configured to cause the memory device to: in response to the first sum being greater than the first current demand budget or the second sum being greater than the second current demand budget, suspend the memory device.

3. The memory device of claim 1, wherein each subset of memory devices of the plurality of subsets of memory devices has a respective second current demand budget.

4. The memory device of claim 2, wherein the respective second current demand budget for each subset of memory devices of the plurality of subsets of memory devices is the same second current demand budget.

5. The memory device of claim 2, wherein the respective second current demand budget for one subset of memory devices of the plurality of subsets of memory devices is different than the respective second current demand budget for a different subset of memory devices of the plurality of subsets of memory devices.

6. The memory device of claim 1, wherein each of the plurality of subsets of memory devices is mutually exclusive from each remaining subset of the plurality of subsets of memory devices.

7. The memory device of claim 1, wherein the controller configured to cause the memory device to generate the first sum and generate the second sum comprises the controller configured to cause the memory device to: generate the first sum of the respective expected peak current flow amount value of each register of the plurality of registers other than the respective register of the memory device and an expected peak current flow amount value for the next phase of the access operation in a first mode of operation; generate the second sum of the respective expected peak current flow amount value of each register of the particular subset of registers other than the respective register of the memory device and an expected peak current flow amount value for the next phase of the access operation in the first mode of operation; in response to the first sum being greater than the first current demand budget or the second sum being greater than the second current demand budget: generate a third sum of the respective expected peak current flow amount value of each register of the plurality of registers other than the respective register of the memory device and an expected peak current flow amount value for the next phase of the access operation in a second mode of operation; generate a fourth sum of the respective expected peak current flow amount value of each register of the particular subset of registers other than the respective register of the memory device and an expected peak current flow amount value for the next phase of the access operation in the second mode of operation; compare the third sum to the first current demand budget for the plurality of memory devices; compare the fourth sum to the second current demand budget for the particular subset of memory devices; and in response to the third sum being less than or equal to the first current demand budget and the fourth sum being less than or equal to the second current demand budget, initiate the next phase of the access operation in the second mode of operation.

8. The memory device of claim 7, wherein the expected peak current flow amount value for the first mode of operation is greater than the expected peak current flow amount value for the second mode of operation.

9. The memory device of claim 7, wherein the first mode of operation is a normal mode of operation and the second mode of operation is a low peak current mode of operation.

10. The memory device of claim 7, wherein the controller is further configured to cause the memory device to: in response to the third sum being greater than the first current demand budget or the fourth sum being greater than the second current demand budget, suspend the memory device.

11. The memory device of claim 7, wherein the controller is further configured to cause the memory device to: ​ in response to the fifth sum being greater than the first current demand budget or the sixth sum being greater than the second current demand budget: generating a fifth sum of the respective expected peak current magnitude value of each register of the plurality of registers other than the respective register of the memory device and an expected peak current magnitude value for the next phase of the access operation in a third operational mode; generating a sixth sum of the respective expected peak current magnitude value of each register of the particular subset of registers other than the respective register of the memory device and an expected peak current magnitude value for the next phase of the access operation in the third operational mode; comparing the fifth sum to the first current demand budget for the plurality of memory devices; comparing the sixth sum to the second current demand budget for the particular subset of memory devices; and in response to the fifth sum being less than or equal to the first current demand budget and the sixth sum being less than or equal to the second current demand budget, initiating the next phase of the access operation in the third operational mode.

12. The memory device of claim 11, wherein the expected peak current magnitude value for the second operational mode is greater than the expected peak current magnitude value for the third operational mode.

13. The memory device of claim 11, wherein the controller is further configured to cause the memory device to: in response to the fifth sum being greater than the first current demand budget or the sixth sum being greater than the second current demand budget, suspend the memory device.

14. The memory device of claim 1, wherein each memory device in the particular subset of memory devices is connected to the same bond wire.

15. The memory device of claim 1, wherein each subset of memory devices of the plurality of subsets of memory devices corresponds to a respective bond wire of a plurality of bond wires, and wherein for each subset of memory devices of the plurality of subsets of memory devices, each memory device of that subset of memory devices is directly connected to the respective bond wire of that subset of memory devices.

16. The memory device of claim 15, wherein the respective bond wire for one subset of memory devices of the plurality of subsets of memory devices is connected to the respective bond wire for a different subset of memory devices of the plurality of subsets of memory devices by a respective bond pad.

17. A memory device, comprising: an array of memory cells; a node for connection to a signal line; a plurality of registers, wherein one register of the plurality of registers is configured to store an expected peak current magnitude value of the memory device, and wherein remaining registers of the plurality of registers are each configured to store a respective expected peak current magnitude value of a respective different memory device of a memory device grouping of the memory device; and a controller for accessing the array of memory cells, wherein the controller is configured to cause the memory device to: in response to the fifth sum being greater than the first current demand budget or the sixth sum being greater than the second current demand budget: generate a fifth sum of the respective expected peak current magnitude value of each register of the plurality of registers other than the respective register of the memory device and an expected peak current magnitude value for the next phase of the access operation in a third operational mode; generate a sixth sum of the respective expected peak current magnitude value of each register of the particular subset of registers other than the respective register of the memory device and an expected peak current magnitude value for the next phase of the access operation in the third operational mode; compare the fifth sum to the first current demand budget for the plurality of memory devices; compare the sixth sum to the second current demand budget for the particular subset of memory devices; and in response to the fifth sum being less than or equal to the first current demand budget and the sixth sum being less than or equal to the second current demand budget, initiate the next phase of the access operation in the third operational mode. determining whether the memory device is expecting a next phase of an access operation to be initiated to the array of memory cells; in response to determining that the memory device is expecting the next phase of the access operation to be initiated: determining whether there is a first current demand budget for the grouping of memory devices sufficient to initiate the next phase of the access operation in a selected operating mode: the respective expected peak current amount value of the remaining registers of the plurality of registers; and the expected peak current amount value of the next phase of the access operation in the selected operating mode; and determining whether there is a second current demand budget for a subset of memory devices of the grouping of memory devices containing the memory device sufficient to initiate the next phase of the access operation in the selected operating mode: the respective expected peak current amount value of the registers of the plurality of registers for memory devices of the subset of memory devices other than the memory device; and the expected peak current amount value of the next phase of the access operation in the selected operating mode; and in response to determining that there is a first current demand budget and a second current demand budget sufficient to initiate the next phase of the access operation in the selected operating mode, outputting the expected peak current amount value of the next phase of the access operation in the selected operating mode to the node and storing the expected peak current amount value of the next phase of the access operation in the selected operating mode to the one of the plurality of registers.

18. The memory device of claim 17, wherein the first current demand budget is equal to a total current demand budget available to the memory device and available to each of the remaining registers of the plurality of registers for a respective memory device.

19. The memory device of claim 17, wherein the next phase of the access operation is an initial phase of the access operation.

20. The memory device of claim 17, wherein the controller is further configured to cause the memory device to: in response to determining that the memory device is not expecting the next phase of the access operation to be initiated: continue using the memory device in a current condition.

21. The memory device of claim 20, wherein the controller being configured to cause the memory device to continue using the memory device in the current condition comprises the controller being further configured to broadcast an expected peak current amount value of the current condition of the memory device.

22. The memory device of claim 21, wherein the current condition is selected from the group consisting of: a suspend, an idle, and a current phase of the access operation being performed.

23. The memory device of claim 17, wherein the selected operating mode is a normal operating mode for the next phase of the access operation.

24. The memory device of claim 23, wherein the selected mode of operation is the normal mode of operation for the next stage of the access operation in response to a determination that there is a first current demand budget and a second current demand budget sufficient to initiate the next stage in the normal mode of operation, and is the low peak current mode of operation for the next stage of the access operation in response to a determination that there is not a first current demand budget or a second current demand budget sufficient to initiate the next stage in the normal mode of operation, but there is a first current demand budget and a second current demand budget sufficient to initiate the next stage in a low peak current mode of operation.

25. The memory device of claim 17, wherein the selected mode of operation is a most preferred mode of operation for the next stage of the access operation in which there is a first current demand budget and a second current demand budget sufficient to initiate the next stage in that mode of operation.

26. The memory device of claim 17, wherein the controller is further configured to cause the memory device to store each expected peak current amount value broadcast by any of the remaining memory devices in the group of memory devices.

27. The memory device of claim 26, wherein the controller is configured to cause the memory device to store each expected peak current amount value broadcast by any of the remaining memory devices in the memory device grouping includes: the controller is configured to cause the memory device to overwrite any previously stored expected peak current amount value for each memory device in the remaining memory devices in the group of memory devices that broadcast an updated expected peak current amount value.

28. The memory device of claim 17, wherein the controller is configured to cause the memory device to determine whether the memory device is expecting to initiate the next phase of the access operation comprises: the controller is configured to cause the memory device to determine whether the memory device is expecting to initiate the next stage of the access operation in response to a memory device pointer having a value corresponding to the memory device.

29. The memory device of claim 28, wherein each memory device in the group of memory devices corresponds to a respective value in a plurality of values of the memory device pointer.

30. The memory device of claim 29, wherein each value in the plurality of values of the memory device pointer is selected from the group consisting of a value of a counter and a digital pattern of a plurality of control signals.

31. An apparatus comprising: a plurality of dies, wherein each die in the plurality of dies is in communication with each remaining die in the plurality of dies, wherein the plurality of dies comprises a plurality of subsets of dies, wherein a particular die in the plurality of dies is a member of a particular subset of dies of the plurality of dies, and wherein the particular die in the plurality of dies comprises: a controller configured to cause the particular die to: store a respective expected peak current amount value for each die in the plurality of dies; determine whether the particular die is expecting to initiate a next stage of an access operation; in response to a determination that the particular die is expecting to initiate the next stage of the access operation: determine whether there is a first current demand budget for the plurality of dies sufficient to initiate the next stage of the access operation in a selected mode of operation; determining whether a second current demand budget, less than the first current budget, exists for the particular subset of dies sufficient to initiate the next phase of the access operation in the selected operating mode; responsive to determining that a first current demand budget and a second current demand budget exist sufficient to initiate the next phase of the access operation in the selected operating mode, initiating the next phase of the access operation in the selected operating mode; and responsive to determining that either a first current demand budget does not exist sufficient to initiate the next phase of the access operation in the selected operating mode or a second current demand budget does not exist sufficient to initiate the access operation in the selected operating mode, suspending the particular die.

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