A chip testing system and a testing method

Abstract

The application is suitable for the technical field of chip testing, and provides a chip testing system and a testing method.The chip testing system comprises an upper computer module;and a lower computer module in communication with the upper computer module;the upper computer module comprises a PC end and a control unit connected with the PC end;the lower computer module comprises a plurality of cascaded lower computers, the lower computers are connected with chips to be tested, and among the plurality of cascaded lower computers, the first lower computer is in communication connection with the control unit; and the control unit automatically configures the GPIO port of the test master of the chip to be tested according to the GPIO configuration information sent by the PC end.By increasing the control unit to automatically configure the GPIO port of the test master of the chip to be tested, the application replaces the existing manual code dialing for configuration, can save time and labor cost, and improves the testing efficiency of the storage chip.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of chip testing, and particularly relates to a chip testing system and a testing method. BACKGROUND

[0002] Memory chips need to be subjected to high-temperature aging sorting levels, and therefore, memory chips need to be subjected to high-temperature aging testing in large quantities. In the prior art, two solutions are mainly provided: Solution 1: a single test seat or test board is used, memory chips are first manually installed, test signals are then manually configured, the code switches reserved on the test seat are then manually set to specified positions, and finally the test seat or test board is inserted into the interface of a high-temperature aging cabinet for aging. Solution 2: on the basis of solution 1, multiple test seats or test boards are concentrated on a larger test board, and the test signal configuration and subsequent test operation mode are similar.

[0003] In view of the existing technical solutions, it can be seen that in the prior art, test signals are manually configured, the labor cost is high, the error rate is also high, and the test efficiency is low. SUMMARY

[0004] The present application provides a chip testing system, which aims to solve the problem of high labor cost, high error rate and low test efficiency in the prior art by manually configuring test signals.

[0005] The present application is implemented in the following manner: a chip testing system is provided, which comprises an upper computer module; and

[0006] a lower computer module in communication with the upper computer module;

[0007] The upper computer module comprises a PC end and a control unit connected to the PC end.

[0008] The lower computer module comprises a plurality of cascaded lower computers, the lower computers are connected to the chips to be tested, and among the plurality of cascaded lower computers, the first lower computer is in communication connection with the control unit.

[0009] The control unit automatically configures the GPIO port of the test master of the chip to be tested according to the GPIO configuration information sent by the PC end.

[0010] Furthermore, a power module connected to the control unit and the lower computers is further included, and the control unit and the lower computers are powered by the power module.

[0011] Furthermore, the upper computer further comprises a display unit connected to the control unit, and the configuration state of the control unit is displayed by the display unit.

[0012] Further, the plurality of cascaded lower computers are arranged on a test board for testing the to-be-tested chip.

[0013] Further, the control unit is externally connected to the test board or arranged on the test board.

[0014] The chip testing method of the chip testing system is also provided.

[0015] The control unit receives the configuration file sent by the PC end, wherein the configuration file comprises the GPIO configuration information corresponding to the ID value of the to-be-tested chip.

[0016] The GPIO configuration information is sent to the lower computer connected in communication, and the GPIO configuration information is sequentially verified by the plurality of cascaded lower computers.

[0017] If the GPIO configuration information is sequentially verified by the plurality of cascaded lower computers, the control unit automatically configures the GPIO port of the test master of the to-be-tested chip based on the GPIO configuration information.

[0018] Further, before the control unit receives the configuration file sent by the PC end, the method further comprises the steps of:

[0019] Serial port data sent by the test master of the to-be-tested chip is acquired.

[0020] The serial port data is sent to the PC end for data analysis, and it is determined whether the serial port data matches the information in the ID configuration table created in the PC end.

[0021] If the serial port data matches the information in the ID configuration table, the control unit receives the configuration file sent by the PC end and matching the ID configuration table.

[0022] Further, the step of sequentially verifying the GPIO configuration information by the plurality of cascaded lower computers comprises:

[0023] The control unit sends the GPIO configuration information to the first lower computer connected in communication, verifies the GPIO configuration information based on the first lower computer, and determines whether the GPIO configuration information corresponds to the serial port data.

[0024] If the first lower computer completes the verification of the GPIO configuration information, the control unit receives the feedback information sent by the first lower computer.

[0025] If the control unit determines that the validation passes based on the feedback information, the GPIO configuration information is sent to the next lower level of the lower level machine for validation based on the cascade of the lower level machines, and the validation is sequentially performed until the last lower level machine, wherein the control unit receives the feedback information sent by the corresponding lower level machine after the validation of each lower level machine.

[0026] If the control unit determines that the validation fails based on the feedback information, it is determined that the GPIO configuration information is read incorrectly, and the GPIO port configuration of the test master of the chip under test is suspended.

[0027] The application provides a chip testing system, based on the communication connection between the upper machine module and the lower machine module, by adding a control unit in the upper machine module, the control unit acquires the GPIO configuration information corresponding to the ID value of the chip under test sent by the PC end in the upper machine module, and sends the GPIO configuration information to the first lower machine connected in communication, based on the cascade of the lower machines, the GPIO configuration information is sequentially and orderly validated by each lower machine, after the validation of all lower machines succeeds, the control unit automatically configures the GPIO port of the test master of the chip under test based on the GPIO configuration information, which replaces the existing manual code dialing configuration. Therefore, the application can save time and labor cost, and improve the testing efficiency of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a structural schematic diagram of a chip testing system provided by an embodiment of the application;

[0029] Figure 2 is a test device structure diagram of a chip under test provided by an embodiment of the application;

[0030] Figure 3 is a flowchart of a chip testing method provided by an embodiment of the application;

[0031] Figure 4 is a flowchart before step S101 provided by an embodiment of the application;

[0032] Figure 5 is a port configuration flowchart of a control unit provided by an embodiment of the application;

[0033] Figure 6 is a flowchart of step S102 provided by an embodiment of the application;

[0034] In the figure, 1 is an upper machine module, 11 is a PC end, 12 is a control unit, 2 is a lower machine module, 3 is a test board, 31 is a control test board, 32 is a test probe, 4 is a tray, 5 is a heating module, 6 is a chip under test, and 7 is a movable guide column. DETAILED DESCRIPTION

[0035] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application.

[0036] The prior art has the problems of high labor cost, high error rate and low test efficiency by manually configuring test signals. Based on the communication connection between the upper computer module and the lower computer module, the control unit is added in the upper computer module, the GPIO configuration information including the ID value corresponding to the chip to be tested is obtained by the control unit from the PC end in the upper computer module, and the GPIO configuration information is sent to the first lower computer connected in communication. Based on the cascading mode of the lower computer, the GPIO configuration information is sequentially verified by each lower computer in order. After the verification of all lower computers is successful, the control unit will automatically configure the GPIO port of the test master of the chip to be tested based on the GPIO configuration information, replacing the existing manual code dialing configuration. Therefore, the present application can save time and labor cost and improve the test efficiency of the chip.

[0037] Example One

[0038] Reference Figure 1 As shown in the figure, Figure 1 A structural schematic diagram of a chip test system is provided for an embodiment of the present application. The chip test system comprises an upper computer module 1, and

[0039] A lower computer module 2 in communication with the upper computer module 1;

[0040] The upper computer module 1 comprises a PC end 11 and a control unit 12 connected with the PC end 11;

[0041] The lower computer module 2 comprises a plurality of cascaded lower computers, the lower computers are connected with the chip to be tested, and among the plurality of cascaded lower computers, the first lower computer is in communication connection with the control unit;

[0042] The control unit 12 automatically configures the GPIO port of the test master of the chip to be tested according to the GPIO configuration information sent by the PC end 11.

[0043] Among them, the upper computer module 1 comprises a PC end 11 and a control unit 12 (MCU). The MCU includes but is not limited to single-chip microcomputer, FPGA and other chips that can realize signal control. When the MCU is a single-chip microcomputer, the GPIO port of the test master of the chip to be tested can be configured by the single-chip microcomputer. The PC end 11 can be various electronic devices with display screen and supporting web browsing, including but not limited to smart phones, tablet computers, laptop computers and desktop computers, etc.

[0044] The to-be-tested chip includes a memory chip, which includes but is not limited to a NAND, a NOR, a DRAM, and the like, and a BGA, a TSOP, a QFN, and the like. Each memory chip has a corresponding ID value, and the type of the memory chip can be determined through the ID value. When testing a batch of memory chips, batch testing of the same type of memory chip can be performed.

[0045] The upper computer module 1 and the lower computer module 2 are in bidirectional communication, and the communication mode includes but is not limited to a wired or wireless communication mode such as a serial port and a CAN. Similarly, the communication mode between the PC end 11 and the control unit 12 in the upper computer module 1 includes but is not limited to a wired or wireless communication mode such as a serial port and a CAN. The communication mode between the control unit 12 and the first lower computer includes but is not limited to a wired or wireless communication mode such as a serial port and a CAN. The communication mode between the plurality of cascaded lower computers includes but is not limited to a wired or wireless communication mode such as a serial port and a CAN. The lower computer includes a test master, and one lower computer is connected to one to-be-tested chip.

[0046] Specifically, the ID mapping table is stored in the PC end 11, and the ID mapping table stores the correspondence between different types of to-be-tested chips and GPIO configuration information. The GPIO configuration information corresponding to the ID value can be read in the ID mapping table. The GPIO configuration information can include a GPIO configuration table corresponding to the ID value, a voltage, and corresponding card opening software.

[0047] More specifically, based on the bidirectional communication between the upper computer module 1 and the lower computer module 2, when the to-be-tested chip is connected to the lower computer, the PC end 11 can read the ID value of the to-be-tested chip, read the corresponding GPIO configuration information based on the ID value, encapsulate the GPIO configuration information, form a configuration file that can be recognized by the MCU, and send the configuration file to the MCU. When the MCU receives the GPIO configuration information, the MCU can send the GPIO configuration information to the first lower computer in the cascade based on the communication connection between the MCU and the lower computer, and verify the GPIO configuration information based on the cascade of the lower computer. If the verification is passed, the MCU can automatically configure the GPIO port of the test master of the to-be-tested chip according to the GPIO configuration table and the voltage corresponding to the GPIO configuration table. According to the correspondence between the GPIO configuration table and the voltage in the GPIO configuration information, the GPIO port of the test master of the to-be-tested chip is correctly configured by pulling up / pulling down the potential of the GPIO port.

[0048] The lower computer cascade can be represented as: the lower computer 100 is connected to the lower computer 200, and then the lower computer 200 is connected to the lower computer 300,..., and the lower computer N-1 is connected to the lower computer N. After the first lower computer completes the GPIO configuration information verification, it enters a waiting state. Based on the communication between the lower computers, the next lower computer will continue to verify the GPIO configuration information, until all the lower computers complete the verification. The MCU will automatically configure the GPIO port of the test master of the batch of chips to be tested based on the GPIO configuration information when all the lower computers pass the verification. The feedback information includes verification pass / verification failure, and the feedback information includes the number of the lower computer.

[0049] As a possible embodiment, referring to Figure 2 , Figure 2 is a structure diagram of a chip under test device of a chip test system provided in the embodiment. The test device can be a tool for high-temperature testing of the chip under test, and the chip test system can be used in high-temperature testing of a memory chip. After the GPIO port configuration of the test master of the chip under test 6 is completed, the chip under test 6 can be subjected to high-temperature testing by the test device. In the high-temperature testing, a tray 4 can be placed below the test board 3, and each cell of the tray 4 is provided with a chip under test 6. The test board 3 includes a test control board 31 and test pogo pins 32, the test pogo pins 32 are arranged on the side fixed to the tray 4, and the test pogo pins 32 are electrically connected to the chip under test 6 in the tray 4. A heating module 5 is arranged below each cell of the tray 4 to uniformly heat the whole tray. In this way, the heating effect of each chip under test can be more consistent, and the risk of missed selection due to uneven environmental temperature during chip sorting can be reduced. Compared with using a high-temperature aging cabinet, the energy consumption and cost are reduced. The movable guide column 7 is arranged below the heating module 5, and the movable guide column 7 can be used to automatically control the position movement of the heating module 5 and the tray 4.

[0050] In the embodiment, a chip test system is provided. Based on the communication connection between the upper computer module 1 and the lower computer module 2, a control unit 12 is added to the upper computer module 1. The control unit 12 acquires the GPIO configuration information corresponding to the ID value of the chip under test sent by the PC end 11 in the upper computer module 1, and sends the GPIO configuration information to the first lower computer connected by communication in the lower computer module 2. Based on the lower computer cascade mode, each lower computer sequentially and orderly verifies the GPIO configuration information. After all the lower computers pass the verification, the control unit 12 automatically configures the GPIO port of the test master of the chip under test based on the GPIO configuration information, instead of manual code dialing for configuration. Therefore, the application can save time and labor cost, and improve the testing efficiency of the chip.

[0051] Example Two

[0052] Based on the above embodiment one, in this embodiment, the power module of the connection control unit and the lower computer is further included, and the power module supplies power to the control unit and the lower computer.

[0053] The power module (not shown) can be connected with the power input port of the MCU to provide working voltage for the MCU, and the power module can provide working voltage for the lower computer when connected with the lower computer. The power module can be connected with one of the lower computers, and adjacent lower computers can be connected with each other through the power input / output port of the test master in the lower computer, so as to supply power to all the lower computers.

[0054] Example Three

[0055] Based on the above embodiment one to embodiment two, in this embodiment, the upper computer further includes a display unit connected with the control unit, and the configuration state of the control unit is displayed through the display unit.

[0056] As a possible embodiment, a display unit (not shown) can also be connected, and the display unit can be a display screen with display function. The configuration state of the MCU can be displayed on the display unit, including the working progress of the current MCU, the progress of the lower computer verification, feedback information, etc. For example, when the lower computer 100 passes the verification, the lower computer 100 sends feedback information to the MCU to express that the verification is passed. Therefore, the display unit is beneficial to real-time view the configuration state of the MCU.

[0057] As another possible embodiment, the system can further include a storage unit for storing the data of the configuration state of the MCU in each configuration process. When the port configuration fails, the storage unit is set, which is beneficial to analyze the reason for the port configuration failure according to the data stored in the storage unit. The data in the storage unit can be updated regularly.

[0058] Example Four

[0059] Based on the above embodiment one, in this embodiment, a plurality of cascaded lower computers are arranged on a test board for testing a to-be-tested chip. The control unit is externally connected with the test board or arranged on the test board.

[0060] The plurality of cascaded lower computers can be arranged on the test board for testing the to-be-tested chip, and the MCU can also be arranged on the test board. The first lower computer is connected with the MCU on the test board. Possibly, the MCU can also be externally connected with the test board.

[0061] Example Five

[0062] In the embodiment, a chip testing method employing the chip testing system in any of the above embodiments is provided, as shown in Figure 3 Figure 3 A flowchart of a chip testing method provided in the embodiment is shown. The chip testing method comprises the following steps:

[0063] S101, the control unit receives the configuration file sent by the PC end, wherein the configuration file comprises GPIO configuration information corresponding to the ID value of the chip to be tested.

[0064] In the embodiment, the control unit and the PC end belong to the upper computer, and the control unit and the PC end can perform data transmission through wired or wireless communication modes including but not limited to serial port, CAN, etc. The wireless connection mode can include but is not limited to 3G / 4G connection, WiFi connection, Bluetooth connection, WiMAX connection, Zigbee connection, UWB (ultra wideband) connection, and other now known or future developed wireless connection modes.

[0065] Specifically, the ID mapping table of various types of chips to be tested is configured in the PC end, and the ID mapping table comprises the mapping relationship between the ID value of the chip to be tested and the GPIO configuration information. Based on the ID value of the chip to be tested, the GPIO configuration information corresponding to the ID value can be read in the ID mapping table, and the GPIO configuration information can include the GPIO configuration table, voltage, and corresponding card opening software corresponding to the ID value. After the PC end reads the GPIO configuration information, the GPIO configuration information can be packaged to form a configuration file that can be recognized by the MCU, and the configuration file is sent to the MCU in the upper computer.

[0066] S102, the GPIO configuration information is sent to the communication-connected lower computer, and the GPIO configuration information is sequentially verified based on the plurality of cascaded lower computers.

[0067] The lower computer and the upper computer are bidirectional communication, and the lower computer comprises a test master of the chip to be tested. Specifically, the types of the chips to be tested in the same batch are the same type. After the MCU receives the GPIO configuration information, it is sent to the communication-connected lower computer, and then based on the cascade of the lower computer, the GPIO configuration information is sequentially verified in turn, to determine whether the GPIO configuration information is in the mapping relationship with the ID value of the chip to be tested. When verifying, it is sequentially performed in order, first the lower computer in communication with the MCU is verified, and after the verification is successful, feedback information is sent to the MCU and enters a waiting state until all the lower computers are verified.

[0068] ​S103, if the plurality of cascaded subordinate machines pass the GPIO configuration information in turn, the control unit automatically configures the GPIO port of the test master of the chip to be tested based on the GPIO configuration information.

[0069] When all the subordinate machines pass the GPIO configuration information corresponding to the ID value of the chip to be tested through cascading, the MCU configures the GPIO port based on the correspondence between the GPIO configuration table in the GPIO configuration information and the voltage, and realizes the GPIO port configuration by pulling up / pulling down the voltage of the GPIO port of the test master of the chip to be tested. If there is a GPIO configuration information reading error during the verification, the MCU can pause the continuous GPIO port configuration.

[0070] In the embodiment of the application, a chip testing method is provided, based on the communication connection between the host computer and the subordinate machine, by adding an MCU in the host computer, the MCU obtains the configuration file sent by the PC end and including the GPIO configuration information corresponding to the chip to be tested, and sends the GPIO configuration information to the subordinate machine, the GPIO configuration information is sequentially verified through the cascading of the subordinate machines, after all the subordinate machines complete the verification step by step, the MCU configures the GPIO port based on the correspondence between the GPIO configuration table in the GPIO configuration information and the voltage, and realizes the GPIO port configuration by pulling up / pulling down the voltage of the GPIO port of the test master of the chip to be tested, instead of the existing manual code dialing configuration. Therefore, the application can save time and labor cost, and improve the testing efficiency of the chip to be tested.

[0071] Example Six

[0072] Reference Figure 4 As shown in the figure, Figure 4 The flowchart before step S101 is provided for another embodiment of the application. Before step S101, it also includes the following steps:

[0073] S201, obtaining the serial port data sent by the test master of the chip to be tested.

[0074] Based on the bidirectional communication between the host computer and the subordinate machine and the cascading of the subordinate machines, as shown in the figure, Figure 5 When the chip to be tested is connected to the test master of the subordinate machine, the MCU can obtain the serial port data sent by the test master through any one of serial port, network port, wireless, etc. The serial port data can include the ID value of the chip to be tested, and the ID value can identify the type of the chip to be tested.

[0075] S202, sending the serial port data to the PC end for data analysis, and judging whether the serial port data matches the information in the ID configuration table created in the PC end.

[0076] The MCU can send the received serial port data to the PC end for data analysis through any communication mode such as a serial port, a network port or wireless communication, based on the communication between the PC end and the MCU. The data analysis includes analyzing the serial port data to obtain the ID value of the chip under test, and when the ID value of the chip under test is found in the ID mapping table, the corresponding GPIO configuration information of the ID value is read from the ID mapping table.

[0077] S203, if the serial port data matches the information in the ID configuration table, the control unit receives the configuration file sent by the PC end and matching the ID configuration table.

[0078] When the ID configuration table matches the GPIO configuration information corresponding to the ID value, the PC end sends the identifiable configuration file to the MCU, and the GPIO configuration information corresponding to the ID value in the ID configuration table is sent to the MCU.

[0079] In the embodiment of the application, the MCU is added in the host computer, the serial port data is obtained by the MCU before the configuration file is obtained, and the serial port data is sent to the PC end for data analysis, which is beneficial to find the GPIO configuration information corresponding to the ID value in the serial port data.

[0080] Example Seven

[0081] Reference Figure 6 As shown in the figure, Figure 6 The specific flow chart of step S102 provided by another embodiment of the application is shown. Step S102 specifically includes the following steps:

[0082] S301, the control unit issues the GPIO configuration information to the first slave machine connected in communication, and based on the verification of the GPIO configuration information by the first slave machine, it is determined whether the GPIO configuration information corresponds to the serial port data.

[0083] In combination with Figure 1 and Figure 5 As shown in the figure, based on the cascade of the slave machines, the MCU can send the received GPIO configuration information to the first slave machine 100 connected in communication with the MCU, and through the first slave machine 100, it is identified whether the GPIO configuration information and the ID value of the chip under test included in the serial port data are in a mapping relationship, i.e. whether they match.

[0084] S302, if the first slave machine completes the verification of the GPIO configuration information, the control unit receives the feedback information sent by the first slave machine.

[0085] When the slave machine 100 completes the verification, feedback information is sent to the MCU. After the MCU determines that the slave machine 100 passes the verification according to the feedback information, the slave machine 100 enters a waiting state, waiting for other slave machines to perform the verification in turn. The feedback information can feed back the verification result, for example, matching success, verification pass, verification failure, etc. The feedback information includes the number of the slave machine.

[0086] S303, the control unit determines that the verification passes based on the feedback information, then configures the GPIO configuration information to the next slave machine based on the cascade of the slave machines for verification, and verifies in turn until the last slave machine. After each slave machine is verified, the control unit receives the feedback information sent by the corresponding slave machine.

[0087] When the slave machine 100 passes the verification, the slave machine 100 continues the verification of the slave machine 200 based on the cascade of the slave machines. The MCU sends the GPIO configuration information to the next slave machine 200. The slave machine 200 continues to identify the mapping relationship between the GPIO configuration information and the ID value of the chip to be tested. If the identification is successful, the slave machine 200 sends feedback information indicating that the verification passes to the MCU, and enters a waiting state. Similarly, based on the above verification method, the remaining slave machines verify the GPIO configuration information in turn until the last slave machine N passes the verification. The MCU outputs a control signal to automatically configure the GPIO port of the test master of the chip to be tested. Figure 5 The control signal can be an electrical signal that controls the GPIO port to be high / low.

[0088] S304, the control unit determines that the verification fails according to the feedback information, and determines that the GPIO configuration information is read incorrectly, and suspends the configuration of the GPIO port of the test master of the chip to be tested.

[0089] Of course, during the verification process of the slave machine 100 to the slave machine N, if any slave machine fails the verification, i.e., the GPIO configuration information is read incorrectly on the PC side, the verification can be suspended, and feedback information is sent to the MCU for feedback to find the problem in time.

[0090] In this embodiment, the MCU is added to the host computer. The MCU sends the GPIO configuration information sent by the PC to the slave machine. The GPIO configuration information is sequentially verified by the cascaded slave machines. Through the step-by-step verification, it can be ensured that the GPIO configuration information is correct. After all the slave machines complete the verification step by step, the MCU configures the GPIO port of the test master of the chip to be tested by pulling up / pulling down the voltage of the GPIO port based on the corresponding relationship between the GPIO configuration table in the GPIO configuration information and the voltage, instead of the existing manual code dialing configuration. Therefore, the present application can save time and labor cost, and improve the test efficiency of the chip to be tested.

[0091] The terms "first", "second", and the like, in the description and in the claims of this application or in the above summary, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. Describing a particular feature as being "connected," "coupled," "linked," or "joined" to another part, element, or feature can mean that they are either directly or indirectly connected, coupled, linked, or joined, and that the parts, elements, or features involved are electrically or mechanically connected, coupled, linked, or joined, or are in communication, whether electrically, mechanically, magnetically, optically, chemically, causally, or by a combination thereof; and permit a flow of current, energy, or other item between the parts, elements, or features to which they are connected, coupled, linked, or joined. The terms "comprise," "comprising," "include," "including," and the like, when used in this specification and in the following claims, are intended to specify the presence of stated features, elements, and components, but do not preclude the presence or addition of one or more other features, elements, or components.

[0092] The preferred embodiments of the present application have been described above with the intent to enable those skilled in the art to make and use it. Various modifications to these embodiments will occur to those skilled in the art and are intended to be encompassed by the description. The above description is intended to be illustrative and not restrictive. Changes can be made without departing from the scope of the application. Changes in form and detail can be made in the implementation of the application without departing from the spirit, and the general principles of the application. The embodiments described herein should be understood, therefore, as being in all respects illustrative only and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein.

Claims

1. A chip testing system, characterized by, The application relates to a test system for a chip under test, comprising: a host computer module; and a lower computer module in communication with the host computer module; the host computer module comprises a PC end and a control unit connected with the PC end; the lower computer module comprises a plurality of cascaded lower computers connected with the chip under test, and the first lower computer in the plurality of cascaded lower computers is in communication connection with the control unit; the control unit automatically configures the GPIO port of the test master of the chip under test according to the GPIO configuration information sent by the PC end; the host computer further comprises a storage unit for storing the data of the configuration state of the control unit in the configuration process.

2. The chip testing system of claim 1, wherein, The application further comprises a power module connected with the control unit and the lower computer, and the control unit and the lower computer are powered through the power module.

3. The chip testing system of any one of claims 1-2, wherein, The host computer further comprises a display unit connected with the control unit, and the configuration state of the control unit is displayed through the display unit.

4. The chip testing system of claim 1, wherein, The plurality of cascaded lower computers are arranged on a test board for testing the chip under test.

5. The chip testing system of claim 4, wherein, The control unit is externally connected with the test board or arranged on the test board.

6. A chip testing method employing the chip testing system according to any one of claims 1 to 5, characterized by, The application comprises the following steps: the control unit receives the configuration file sent by the PC end, wherein the configuration file comprises the GPIO configuration information corresponding to the ID value of the chip under test; the GPIO configuration information is sent to the communicatively connected lower computer, and the GPIO configuration information is sequentially verified by the plurality of cascaded lower computers; if the GPIO configuration information is sequentially verified by the plurality of cascaded lower computers, the control unit automatically configures the GPIO port of the test master of the chip under test based on the GPIO configuration information.

7. The chip testing method according to Claim 6, wherein Before the control unit receives the configuration file sent by the PC end, the following steps are further included: serial port data sent by the test master of the chip under test is acquired; the serial port data is sent to the PC end for data analysis, and it is judged whether the serial port data matches the information in the ID configuration table created in the PC end; if the serial port data matches the information in the ID configuration table, the control unit receives the configuration file sent by the PC end and matched with the ID configuration table.

8. The chip testing method according to Claim 7, wherein The step of sequentially verifying the GPIO configuration information by the plurality of cascaded lower computers comprises: the control unit sends the GPIO configuration information to the first lower computer in communication connection, verifies the GPIO configuration information based on the first lower computer, and judges whether the GPIO configuration information corresponds to the serial port data; if the first lower computer completes the verification of the GPIO configuration information, the control unit receives the feedback information sent by the first lower computer; if the control unit judges that the verification is passed based on the feedback information, the GPIO configuration information is sent to the second lower computer based on the cascade of the lower computer for verification, and the verification is sequentially performed until the last lower computer, wherein the control unit receives the feedback information sent by the corresponding lower computer after the verification of each lower computer. If the control unit determines that the validation fails according to the feedback information, it is determined that the GPIO configuration information reading is wrong, and the GPIO port configuration of the test master of the chip under test is suspended.

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