A method for preparing a multi-bit storage field-effect transistor based on ZrO2 antiferroelectricity

Abstract

The present invention discloses a method for preparing a multi-bit storage field-effect transistor based on the antiferroelectric property of ZrO2. The method comprises the following steps: depositing a SiO2 layer on a Si substrate, photolithography and etching the SiO2 layer to expose the substrate and form a gate window; passivating the Si substrate using nitrogen plasma to form a Si3N4 thin layer; forming a HZO / ZrO2 / HZO stacked structure, adjusting the thickness of the ZrO2 to impart appropriate antiferroelectric properties to the ZrO2, and adjusting the thickness of the HZO on both sides of the ZrO2 to adjust the magnitude of the ZrO2 reversal current, thereby adjusting the shift of the characteristic peak of the antiferroelectric current of the ZrO2 layer, thereby enabling the device to have non-volatile multi-state storage and expanding the storage window; forming a TiN layer as a gate and annealing it in an N2 atmosphere; etching away the SiO2 layers on both sides, photolithography to define the positions of the source and drain, and performing ion implantation and doping; forming SiO2 sidewalls, performing ion implantation again, and high-temperature rapid annealing to activate the doped ions; and forming contact electrodes on the surfaces of the source, drain, and gate.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a multi-bit storage field effect transistor based on ZrO2 antiferroelectricity. Background Art

[0002] In 2011, TS Boscke discovered that HfO₂-doped Si exhibits ferroelectric properties. Subsequently, ferroelectric properties were observed when HfO₂ was doped with elements such as Al, Zr, and La. Consequently, FeFET research shifted to hafnium-based ferroelectrics, which are compatible with mainstream CMOS. Further research revealed that hafnium oxide exhibits ferroelectric properties in a multi-domain structure, making ferroelectric field-effect transistors a promising candidate for next-generation multi-state non-volatile memory.

[0003] However, as devices scale, the uneven number and distribution of ferroelectric domains causes changes in device performance, which has a serious impact on device arrays. Furthermore, for multistate memory devices, localized polarization changes can lead to severe state overlap. Current approaches involve overlapping the ferroelectric and dielectric layers to separate the device's peaks, but this results in a smaller remnant polarization intensity, indicating a significant reduction in the number of finite domains, thus limiting the performance of multistate memory based on ferroelectric devices.

[0004] Antiferroelectricity, a property found in zirconium-based ferroelectric materials, requires a lower effective field during switching compared to traditional hafnium-based ferroelectrics. This characteristic reduces the operating voltage during cycling, resulting in superior device durability and is gaining increasing attention and development. Summary of the Invention

[0005] The invention discloses a method for preparing a multi-bit storage field effect transistor based on the antiferroelectric property of ZrO2. The method comprises the following steps: depositing a SiO2 layer on a Si substrate, and performing photolithography and etching on the SiO2 layer to expose the substrate to form a gate window; performing passivation treatment on the Si substrate using nitrogen plasma to form a Si3N4 thin layer; forming a HZO / ZrO2 / HZO stacked structure, adjusting the thickness of ZrO2 so that the ZrO2 has appropriate antiferroelectric properties, and adjusting the thickness of HZO on both sides of the ZrO2 to adjust the magnitude of the ZrO2 reversal current, thereby adjusting the shift of the characteristic peak of the antiferroelectric current of the ZrO2 layer, so that the device has non-volatile multi-state storage while expanding the storage window; forming a TiN layer as a gate and annealing in an N2 atmosphere; etching away the SiO2 layers on both sides, photolithographically determining the positions of the source and drain, and performing ion implantation and doping; forming SiO2 sidewalls, performing ion implantation again, and performing high-temperature rapid annealing to activate the doped ions; and forming contact electrodes on the surfaces of the source, drain, and gate.

[0006] In the method for preparing a multi-bit storage field effect transistor based on ZrO2 antiferroelectricity of the present invention, preferably, the thickness of the HZO is 1nm to 3nm, and the thickness of the ZrO2 layer is 6nm to 9nm.

[0007] In the method for preparing a multi-bit storage field effect transistor based on ZrO2 antiferroelectricity of the present invention, preferably, the annealing temperature in an N2 atmosphere is 500°C to 600°C, and the time is 30s to 60s.

[0008] In the method for preparing a multi-bit storage field effect transistor based on the antiferroelectricity of ZrO2 of the present invention, preferably, a plasma enhanced atomic layer deposition method is used to form a HZO / ZrO2 / HZO stacked structure.

[0009] Beneficial effects:

[0010] The HZO / ZrO2 / HZO device structure was constructed using PEALD, which increased the ferroelectric properties of the ferroelectric layer while regulating the movement of the ZrO2 antiferroelectric characteristic peak, allowing the device to have non-volatile polymorphic storage while expanding the storage window.

[0011] The band gap widths of zirconia and HZO are basically the same, which reduces the accumulation of charge at the interface during polarization reversal and enhances the tolerance characteristics of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a flow chart of a method for preparing a multi-bit storage field effect transistor based on ZrO2 antiferroelectricity.

[0013] Figures 2 to 7 This is a structural schematic diagram of each stage of the preparation method of a multi-bit storage field effect transistor based on ZrO2 antiferroelectricity. DETAILED DESCRIPTION

[0014] In order to make the purpose, technical solutions and advantages of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. The described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0015] In the description of the present invention, it should be noted that the terms "upper," "lower," "vertical," and "horizontal," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0016] In addition, many specific details of the present invention are described below, such as device structure, materials, dimensions, processing techniques, and technologies, to facilitate a clearer understanding of the present invention. However, as will be appreciated by those skilled in the art, the present invention may be practiced without following these specific details. Unless otherwise noted below, various components of the device may be constructed from materials known to those skilled in the art, or materials with similar functions developed in the future may be used.

[0017] Figure 1 This is a flow chart of the method for preparing a multi-bit storage field effect transistor based on ZrO2 antiferroelectricity. Figure 1 As shown, the method for preparing a multi-bit storage field effect transistor based on ZrO2 antiferroelectricity includes the following steps:

[0018] Step S1: deposit a 100nm thick SiO2101 layer on the Si substrate 100, and expose the gate window by photolithography and etching. The resulting structure is as follows: Figure 2 shown.

[0019] In step S2, the Si substrate 100 is passivated using nitrogen plasma in a plasma enhanced chemical vapor deposition (PECVD) apparatus to form a Si 3 N 4 thin layer 102 .

[0020] Step S3, depositing in a plasma enhanced atomic layer deposition device (PEALD) to form a HZO103 / ZrO2104 / HZO105 stacked structure, the resulting structure is as follows Figure 3 As shown in the figure, the thickness of HZO is 1nm to 3nm, and the thickness of the ZrO2 layer is 6nm to 9nm. The HZO 103 / ZrO2 104 / HZO105 stacked structure not only enhances the ferroelectric properties of the ferroelectric layer, but also, by adjusting the thickness of ZrO2 (to 6-9nm), imparts ZrO2 with appropriate antiferroelectric properties (ZrO2's antiferroelectric properties increase with increasing film thickness), thereby regulating the magnitude of the ZrO2 inversion current. The characteristic antiferroelectric current peak of the ZrO2 layer will also shift to both sides as the ZrO2 thickness increases, thus enabling the device to have stable non-volatile polymorphic storage while expanding the storage window.

[0021] In addition, since the band gap widths of ZrO2 and HZO are basically the same, the accumulation of charge at the interface during polarization reversal is reduced, which can further enhance the tolerance characteristics of the device.

[0022] Step S4, depositing a TiN layer 106 as a gate in a physical vapor deposition device (PVD), and annealing it at 500° C. to 600° C. for 30s to 60s in an N2 atmosphere. Figure 4 shown.

[0023] Step S5, forming a photoresist 107 on the surface of the TiN layer 106, etching away the SiO2 101 on both sides, photoetching the positions of the source 108 and the drain 109 and performing P + Ion implantation doping, such as Figure 5 shown.

[0024] Step S7, using chemical vapor deposition (CVD) to deposit SiO2 sidewalls 110 on both sides of the gate stack, removing the photoresist 107, and performing P + Ion implantation and doping, and finally rapid annealing at 600℃~900℃ to activate the doped ions, such as Figure 6 shown.

[0025] Step S6, PVD sputtering Co on the surface of the source 108, drain 109 and gate 106 forms contact electrodes 111, 112, 113 as shown in FIG. Figure 7 shown.

[0026] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with this technical field within the technical scope disclosed in the present invention should be covered by the scope of protection of the present invention.

Claims

1. A method for preparing a multi-bit storage field effect transistor based on ZrO2 antiferroelectricity, characterized in that: The following steps are involved: Depositing a SiO2 layer on a Si substrate, and performing photolithography and etching on the SiO2 layer to expose the substrate and form a gate window; The Si substrate is passivated using nitrogen plasma to form a Si3N4 thin layer; By forming a HZO / ZrO2 / HZO stacked structure, the ZrO2 is given appropriate antiferroelectric properties by adjusting the thickness of the ZrO2. The magnitude of the ZrO2 inversion current is controlled by adjusting the thickness of the HZO on both sides of the ZrO2, thereby adjusting the shift of the characteristic peak of the antiferroelectric current in the ZrO2 layer, so that the device has non-volatile polymorphic storage while expanding the storage window. Forming a TiN layer as a gate and annealing it in an N2 atmosphere; Etch away the SiO2 layers on both sides, photoetch out the positions of the source and drain, and perform ion implantation and doping; SiO2 sidewalls are formed on both sides of the gate stack, and ion implantation is performed again, followed by high-temperature rapid annealing to activate the doped ions; Contact electrodes are formed on the surfaces of the source, drain and gate.

2. The method for preparing a multi-bit storage field effect transistor based on ZrO2 antiferroelectricity according to claim 1, characterized in that: The thickness of the HZO layer is 1 nm to 3 nm, and the thickness of the ZrO2 layer is 6 nm to 9 nm.

3. The method for preparing a multi-bit storage field effect transistor based on ZrO2 antiferroelectricity according to claim 1, characterized in that: The annealing temperature in N2 atmosphere is 500°C to 600°C, and the time is 30s to 60s.

4. The method for preparing a multi-bit storage field effect transistor based on ZrO2 antiferroelectricity according to claim 1, characterized in that: The HZO / ZrO2 / HZO stacked structure was formed by plasma enhanced atomic layer deposition.

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