Packaging structure and packaging method

Abstract

The present application discloses a packaging structure and packaging method, which includes: at least two chips arranged in a stacked manner; a packaging layer, which is arranged on the side of the top chip away from other chips, wherein a solder pad is provided on the side of the packaging layer away from the top chip; other chips except the top chip include: first-class signal lines and second-class signal lines, the first-class signal lines pass through all chips and are respectively connected to each chip and the solder pad; the second-class signal lines are connected to the solder pad, and the second-class signal lines do not pass through the chip. The packaging structure of the present application will lead out important signal lines that do not need to be connected to other chips in advance, and do not need to pass through other chips, but are directly connected to the solder pads on the packaging layer, effectively avoiding signal loss caused by the signal lines passing through other chips, ensuring signal integrity, and also alleviating the routing pressure of other chips, leaving more routing space for other chips.

Description

Technical Field

[0001] The present application relates to the technical field of device packaging, and in particular to a packaging structure and a packaging method. Background Art

[0002] In today's multi-layer combinations of CHIP to Wafer, Wafer to Wafer, and CHIP to CHIP, connecting each layer requires 3DIC (three-dimensional chip) technology, which uses TSV (Through Silicon Via redistribution lines) to penetrate the silicon to connect two different chips, so that the upper and lower chips are connected, and the signal in the lower chip passes through the upper chip and then connects to the pad of the external package.

[0003] In the existing technology, two chips are directly connected through redistribution lines, so that signal lines that do not need to pass through the upper chip also need to pass through the redistribution lines to enter the upper chip, and finally be connected out through the solder pads of the upper chip. This not only increases signal loss, but also increases routing pressure on the upper chip. Summary of the Invention

[0004] The main technical problem solved by this application is to provide a packaging structure and a packaging method to meet the demand of reducing signal loss in the packaging structure.

[0005] In order to solve the above technical problems, the first technical solution adopted in this application is to provide a packaging structure, including: at least two chips arranged in a stacked manner; a packaging layer, arranged on the side of the top chip away from other chips, wherein a solder pad is provided on the side of the packaging layer away from the top chip; other chips except the top chip include: first-class signal lines and second-class signal lines, the first-class signal lines pass through all chips and are respectively connected to each chip and the solder pad; the second-class signal lines are connected to the solder pad, and the second-class signal lines do not pass through the chips.

[0006] Among them, the second type of signal lines are led out from other chips except the top chip, extend to the pads through the non-overlapping positions of the chips, and are connected to the pads.

[0007] Among them, through holes are provided at set positions of the top chip and / or at least part of the middle layer chips, and the second type of signal lines are led out from other chips except the top chip, pass through the through holes, and penetrate the packaging layer to connect with the pads.

[0008] The cross section of the through hole of each chip along the chip stacking direction is stepped.

[0009] Among them, the first type signal line and the second type signal line pass through the packaging layer.

[0010] The packaging structure further includes a connection layer, which is arranged between the chips.

[0011] Among them, a plurality of redistribution lines are also provided in the connection layer. The first type of signal lines pass through all chips through the redistribution lines, and the second type of signal lines are led out from the bottom chip through the redistribution lines.

[0012] To solve the above technical problems, the second technical solution adopted in this application is to provide a packaging method, including: preparing at least two chips; preparing a first type of signal line and a second type of signal line, wherein the first type of signal line passes through all chips to be connected to each chip respectively, and the second type of signal line does not pass through the chip; making a packaging layer on the side of the top chip away from other chips, and making multiple pads on the packaging layer; passing the first type of signal line and the second type of signal line through the packaging layer and connecting them to the pads.

[0013] Among them, the step of passing the first type signal line and the second type signal line through the packaging layer and connecting to the pad includes: leading the second type signal line from other chips except the top chip; the led-out second type signal line passes through the non-overlapping position of each chip, passes through the packaging layer, and is connected to the pad.

[0014] Among them, the step of passing the first type signal line and the second type signal line through the packaging layer and connecting them to the pad includes: making through holes at set positions of the top layer chip and / or at least part of the chips in the middle layer; after leading the second type signal line from other chips except the top layer chip, passing through the through hole, passing through the packaging layer, and connecting to the pad.

[0015] After the step of preparing at least two chips and before the step of preparing the first type of signal lines and the second type of signal lines, the method further includes: making at least one connection layer; and arranging the connection layer between the chips.

[0016] The beneficial effects of the present application are: different from the existing technology, the present application provides a packaging structure and a packaging method. The packaging structure of the present application rationally utilizes the characteristics of different sizes of each chip, and leads out important signal lines that do not need to be connected to other chips in advance, so that they do not pass through other chips and are directly connected to the pads on the packaging layer, effectively avoiding the signal loss caused by the above-mentioned signal lines in the process of passing through other chips, while also alleviating the routing pressure of other chips and reserving more routing space for other chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:

[0018] Figure 1 This is a structural diagram of the first embodiment of the packaging structure of the present application;

[0019] Figure 2 This is a structural diagram of the second embodiment of the packaging structure of the present application;

[0020] Figure 3 This is a structural diagram of the third embodiment of the packaging structure of the present application;

[0021] Figure 4 This is a schematic structural diagram of a fourth embodiment of the packaging structure of the present application;

[0022] Figure 5 This is a flow chart of the first embodiment of the packaging method of the present application;

[0023] Figure 6 It is a flow chart of the second embodiment of the packaging method of the present application.

[0024] Reference numerals: 100 / 200 / 300 / 400, package structure; 101 / 201 / 301 / 401, chip; 1011 / 2011 / 3011 / 4011, top chip; 1012 / 2012 / 3012 / 4012, bottom chip; 3013 / 4013, middle chip; 30131 / 40131, first middle sub-layer chip; 30132 / 40132, second middle sub-layer chip; 102 / 202 / 302 / 402, package layer; 103 / 203 / 303 / 403, first type signal line; 3031 / 4031, first signal line No. 1 signal connection line; 3032 / 4032, second signal connection line; 3033 / 4033, third signal connection line; 3034 / 4034, third connection line; 104 / 204 / 304 / 404, second type signal line; 3041 / 4041, first signal line; 3042 / 4042, second signal line; 3043 / 4043, third signal line; 105 / 205 / 305 / 405, connection layer; 106 / 206 / 306 / 406, redistribution line; 207 / 407, through hole; 4071, first through hole; 4072, second through hole; 4073, third through hole. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0026] The terms used in the examples of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms "a," "the," and "the" used in the examples of this application and the appended claims are also intended to include plural forms. Unless otherwise clearly indicated above, "a plurality" generally includes at least two, but does not exclude the inclusion of at least one.

[0027] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0028] It should be understood that the terms "comprises," "comprising," or any other variations used herein are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0029] Since signal lines that do not need to be connected to other chips in the existing packaging structure also need to pass through other chips, signal loss occurs and the wiring difficulty of other chips is increased.

[0030] Based on the above problems, the present invention proposes a packaging structure and packaging method, in which signal lines that do not need to pass through other chips are brought out in advance in the packaging structure and directly connected to the pads on the packaging layer without passing through other chips, which can effectively solve the above problems.

[0031] The packaging structure and packaging method provided by the present application are described in detail below with reference to the accompanying drawings and embodiments.

[0032] See also Figure 1 , Figure 1 FIG1 is a schematic diagram of the structure of the first embodiment of the package structure of the present application. In this embodiment, the package structure 100 includes: at least two chips 101 and a package layer 102.

[0033] Among them, the chip 101 can specifically be a chip, or it can be any reasonable circuit element such as a wafer, and the packaging layer 102 can specifically include at least two patterned copper clad boards to form a circuit layer, and an insulating material layer is also provided between each two adjacent patterned copper clad boards, and conductive metal holes are also formed in the insulating material layer for connecting the patterned copper clad boards located at different layers. It can be specifically understood as a circuit packaging board that encapsulates or mounts functional elements, and includes one or more functional units of any reasonable circuit board components such as patterned copper clad boards, insulating material layers, pads, etc. that can realize electrical connection between the functional elements, so that circuit logic can be designed. This application does not limit this.

[0034] Furthermore, at least two chips 101 are specifically stacked on each other. For ease of understanding, in this embodiment, the one of the at least two chips 101 closest to the packaging layer 102 is the top chip 1011, and the one farthest from the packaging layer 102 is the bottom chip 1012 as an example for explanation. It can be seen that the packaging layer 102 is specifically arranged on the side of the top chip 1011 away from other chips 101, and a plurality of pads (not marked in the figure) are also provided on the side away from the packaging layer 102 for connection with external circuits.

[0035] In addition, the other chips 101 except the top chip 1011 further include: a first type of signal line 103 and a second type of signal line 104 .

[0036] Among them, the first type of signal line 103 passes through all chips 101 to be connected to each chip 101 and the pads on the packaging layer 102 respectively, so as to realize signal transmission between each chip 101 and also realize signal transmission interaction with external circuits through the pads.

[0037] The second type of signal line 104 is connected to the pad on the packaging layer 102, and the second type of signal line 104 does not pass through any chip 101. That is, the second type of signal line 104 is specifically led out from other chips 101 except the top chip 1011, and extends to the pad on the packaging layer 102 through the non-overlapping positions of the chips 101 to connect with the pad.

[0038] Specifically, the projection of the top chip 1011 along the arrangement direction of the two chips 101 is smaller than the projection of the bottom chip 1012 along the arrangement direction of the two chips 101, that is, there is a blank area between the top chip 1011 and the bottom chip 1012, and the second type of signal line 104 specifically passes through the above-mentioned blank area so that it does not need to pass through the top chip 1011, and after passing through the packaging layer 102, it is directly connected to the pad on the packaging layer 102, thereby effectively avoiding the signal loss caused by the second type of signal line 104 in the process of passing through other chips 101, and at the same time alleviating the routing pressure of other chips 101, and reserving more routing space for other chips 101.

[0039] In one embodiment, the signal line connected to the second type signal line 104 in the bottom chip 1012 can be bent and extended toward the above-mentioned blank area to avoid the obstruction of the top chip 1011 in advance, so that the second type signal line 104 does not pass through each chip 101, and is thus led out in advance.

[0040] It is understandable that the second-class signal line 104 specifically corresponds to a signal line that has no connection requirements in other chips 101 except the underlying chip 1012. That is to say, the second-class signal line 104 does not actually need to pass through other chips 101 except the underlying chip 1012, that is, the second-class signal line 104 does not need to be connected to the pads on the packaging layer 102 through other chips 101 except the underlying chip 1012, so that the second-class signal line 104 can be led out from the underlying chip 1012 in advance, so that the second-class signal line 104 does not pass through other chips 101 except the underlying chip 1012, but is directly connected to the pads on the packaging layer 102.

[0041] Among them, by leading out the second-class signal line 104 in advance, the signal loss caused by the second-class signal line 104 in the process of passing through other chips 101 except the underlying chip 1012 can be effectively reduced, and the integrity of the signal can be effectively guaranteed. At the same time, the second-class signal line 104 does not need to pass through other chips 101 except the underlying chip 1012, that is, the second-class signal line 104 does not need to be routed in other chips 101 except the underlying chip 1012, so that other chips 101 save more routing space and alleviate the routing pressure of other chips 101.

[0042] In one embodiment, the first type signal lines 103 and the second type signal lines 104 both penetrate the packaging layer 102 to connect to pads on a side of the packaging layer 102 away from the top chip 1011 .

[0043] In one embodiment, the package structure 100 further includes a connection layer 105 , and the connection layer 105 is specifically disposed between the chips 101 .

[0044] Furthermore, a plurality of redistribution lines 106 are provided in the connection layer 105, and the first type of signal lines 103 specifically pass through all the chips 101 via the redistribution lines 106. The first type of signal lines 103 specifically include a first signal connection line 1031 and a second signal connection line 1032, and the opposite ends of the corresponding redistribution lines 106 are specifically connected to the first signal connection line 1031 and the second signal connection line 1032, respectively, to achieve connection between the chips 101.

[0045] After being led out from the bottom chip 101 , the second type signal line 104 is also led out in advance through the corresponding redistribution line 106 in the connection layer 105 , so that the second type signal line 104 does not need to pass through other chips 101 but is directly connected to the pad on the packaging layer 102 .

[0046] It can be understood that the opposite ends of at least some of the multiple redistribution lines 106 are specifically connected to the first type of signal line 103 in different chips 101 to achieve connection between the chips 101, and one end of another part of the multiple redistribution lines 106 is specifically connected to the corresponding signal line in the underlying chip 1011, and the other end is correspondingly connected to the second type of signal line 104 to lead out the signal line in the underlying chip 1011 in advance, so that the second type of signal line does not need to pass through other chips 101 and is directly connected to the pad on the packaging layer 102.

[0047] Furthermore, the redistribution lines 106 in the connection layer 105 can be bent and extended to avoid the obstruction of the top chip 1011 in advance, so that the second-type signal lines 104 do not pass through the chips 101 and are thus led out in advance.

[0048] It should be noted that when each chip 101 is specifically a chip, each redistribution line 106 in the connection layer 105 can also be specifically connected to the silicon via of each chip substrate, so as to further realize the connection with the first type signal line 103 or the second type signal line 104 through the silicon via.

[0049] Please continue reading Figure 2 , Figure 2 This is a schematic diagram of the second embodiment of the packaging structure of the present application. Figure 1 The difference from the first embodiment of the package structure provided in the present application is that a through hole 207 is further provided at the setting position of the top chip 2011 in the package structure 200 .

[0050] The through hole 207 can be obtained by any reasonable method such as etching or drilling, and is formed at a position that does not interfere with the wiring of the top chip 2011 itself.

[0051] Specifically, a through hole 207 is formed in the middle position, edge position or any other reasonable area without designed routing of the top chip 2011, so that the second type signal line 204 can pass through the through hole 207, and is led out in advance from other chips 201 except the top chip 2011, and then connected to the pad on the packaging layer 202.

[0052] It is understood that, in this embodiment, the bottom chip 2012, the packaging layer 202, the first type of signal line 203, the second type of signal line 204, the connection layer 205 and the redistribution layer 206 are respectively connected to the bottom chip 1012, the packaging layer 102, the first type of signal line 103, the second type of signal line 104, the connection layer 105 and the redistribution layer 106. For details, see Figure 1 And the related text content will not be repeated here.

[0053] Please continue reading Figure 3 , Figure 3 This is a schematic diagram of the structure of the third embodiment of the packaging structure of this application. Figure 1 The difference from the first embodiment of the package structure provided in the present application is that the top layer chip 3011 and at least part of the middle layer chips 3013 in the package structure 300 are further provided with through holes (not shown).

[0054] For ease of understanding, the packaging structure 300 is taken as an example to explain that it specifically includes four chips 301, namely a top chip 3011, a bottom chip 3012 and a middle layer chip 3013, and the middle layer chip 3013 further includes a first middle sub-layer chip 30131 and a second middle sub-layer chip 30132. It can be seen that the first middle sub-layer chip 30131 is specifically arranged on the side close to the top chip 3011, and the projection of the top chip 3011 along the arrangement direction of the four chips 301 is smaller than the projection of the first middle sub-layer chip 30131, the projection of the first middle sub-layer chip 30131 along the arrangement direction of the four chips 301 is smaller than the projection of the second middle sub-layer chip 30132, and the projection of the second middle sub-layer chip 30132 along the arrangement direction of the four chips 301 is smaller than the projection of the bottom chip 3012.

[0055] That is to say, the through holes on the top chip 3011, the first intermediate sub-layer chip 30131 and the second intermediate sub-layer chip 30132 are specifically formed at the edge position, and the through holes of each chip 301 are specifically stepped in cross-section along the stacking direction of the chip 301, and there are blank areas between the top chip 3011 and the first intermediate sub-layer chip 30131, the first intermediate sub-layer chip 30131 and the second intermediate sub-layer chip 30132, and the second intermediate sub-layer chip 30132 and the bottom chip 3012.

[0056] The second type of signal line 304 specifically passes directly between two chips 301 whose projections do not overlap, that is, the above-mentioned blank area, without passing through the chips 301 with smaller projections. Specifically, it passes through the through hole and then penetrates the packaging layer 302, and is directly connected to the pad on the packaging layer 302.

[0057] Specifically, the second type of signal line 304 specifically includes a first signal line 3041, a second signal line 3042 and a third signal line 3043. After the first signal line 3041 is led out from the first intermediate sub-layer chip 30131, it passes through the blank area between the top chip 3011 and the first intermediate sub-layer chip 30131, so that the first signal line 3041 does not need to pass through the top chip 3011, and passes through the packaging layer 302, and is directly connected to the pad on the packaging layer 302; the second signal line 3042 is led out from the second intermediate sub-layer chip 30132, passes through the first intermediate sub-layer chip 30131 and the second intermediate sub-layer chip 30131. The blank area between the layer chips 30132 makes the second signal line 3042 not need to pass through the top chip 3011 and the first intermediate sub-layer chip 30131. After passing through the packaging layer 302, it is directly connected to the solder pad on the packaging layer 302; the third signal line 3043 is led out from the bottom chip 3012, passes through the blank area between the second intermediate sub-layer chip 30132 and the bottom chip 3012, so that the third signal line 3043 does not need to pass through the top chip 3011, the first intermediate sub-layer chip 30131 and the second intermediate sub-layer chip 30132. After passing through the packaging layer 302, it is directly connected to the solder pad on the packaging layer 302.

[0058] In one embodiment, the packaging structure 300 also includes multiple connection layers 305, and the multiple connection layers 305 are respectively formed between each two adjacent chips 301, and the first signal line 3041, the second signal line 3042 and the third signal line 3043 are specifically respectively led out from the redistribution line 306 in the connection layer, so as to pass through the packaging layer 302 and directly connect to the pads on the packaging layer 302.

[0059] Furthermore, the first type of signal line 303 in the packaging structure 300 corresponds to the top chip 3011, the first intermediate sub-layer chip 30131, the second intermediate sub-layer chip 30132 and the bottom chip 3012, respectively forming a first signal connection line 3031, a second signal connection line 3032, a third signal connection line 3033 and a fourth connection line 3034, and each adjacent two connection lines are specifically connected through the redistribution line 306 in the connection layer 305.

[0060] It is understandable that in other embodiments, the number of chips 301 in the packaging structure 300 can be any reasonable number such as 3, 5 or 6, and when there is a chip 301 that does not need to be directly connected to the packaging layer 302, a chip 301 adjacent to the chip 301 and close to the top chip 3011 can also be equal to the area size of the chip 301, that is, the cross-sectional dimensions of the corresponding through holes at the two chips 301 can also be equal, and this application does not limit this.

[0061] The above-mentioned packaging structure 300 solves the problem that when the sizes of the chips 301 from the top layer to the bottom layer are not equal, the signal lines that do not need to pass through other chips 301 are led out in advance through the blank areas between the chips 301 to directly connect with the pads on the packaging layer 302, thereby reducing the signal loss in the process of the signal lines passing through other chips 301.

[0062] It is understood that in this embodiment, the top chip 3011, the bottom chip 3012, the packaging layer 302, the connection layer 305 and the redistribution layer 306 are respectively connected to the top chip 3011, the bottom chip 1012, the packaging layer 102, the connection layer 105 and the redistribution layer 106. Figure 1 And the related text content will not be repeated here.

[0063] Please continue reading Figure 4 , Figure 4 This is a schematic diagram of the structure of the fourth embodiment of the packaging structure of the present application. Figure 3 The difference of the third embodiment of the packaging structure provided in the present application is that the corresponding through holes 407 arranged on the top layer chip 4011 and at least part of the middle layer chip 4013 in the packaging structure 400 are specifically formed in the middle position of the top layer chip 4011 and at least part of the middle layer chip 4013.

[0064] Among them, the second type of signal line 404 in the packaging structure 400 specifically includes a first signal line 4041, a second signal line 4042 and a third signal line 4043, and the middle positions of the top chip 4011, the first intermediate sub-layer chip 40131 and the second intermediate sub-layer chip 40132 are respectively provided with a first through hole 4071, a second through hole 4072 and a third through hole 4073, and the cross-section of the above-mentioned through hole 407 along the stacking direction of the four chips 401 is specifically stepped.

[0065] Specifically, the first signal line 4041 is led out from the first intermediate sub-layer chip 40131 and connected to the pad on the packaging layer 402 through the first through-hole 4071 on the top chip 4011; the second signal line 4042 is led out from the second intermediate sub-layer chip 40132 and connected to the pad on the packaging layer 402 through the first through-hole 4071 on the top chip 4011 and the second through-hole 4072 on the first intermediate sub-layer chip 40131; the third signal line 4043 is led out from the bottom chip 4012 and connected to the pad on the packaging layer 402 through the first through-hole 4071, the second through-hole 4072 and the third through-hole 4073 on the top chip 4011, the first intermediate sub-layer chip 40131 and the second intermediate sub-layer chip 40132.

[0066] It can be understood that, in this embodiment, the top chip 4011, the bottom chip 4012, the first intermediate sub-layer chip 40131, the second intermediate sub-layer chip 40132, the packaging layer 402, the first type of signal line 403, the first signal connection line 4031, the second signal connection line 4032, the third signal connection line 4033, the fourth connection line 4034, the second type of signal line 404, the connection layer 405, and the redistribution layer 406 are respectively connected to the top chip 3011, the bottom chip 3012, the first intermediate sub-layer chip 30131, the second intermediate sub-layer chip 30132, the packaging layer 302, the first type of signal line 303, the first signal connection line 3031, the second signal connection line 3032, the third signal connection line 3033, the fourth connection line 3034, the second type of signal line 304, the connection layer 305, and the redistribution layer 306. For details, see Figure 3 And the related text content will not be repeated here.

[0067] In order to clearly illustrate the preparation process of the above-mentioned packaging structure, the present application proposes a packaging method accordingly. Figure 5 , Figure 5 This is a flow chart of the first embodiment of the packaging method provided by this application. Specifically, it may include the following steps:

[0068] S11: Prepare at least two chips.

[0069] Specifically, at least two chips are stacked, wherein the prepared chips can be chips or wafers.

[0070] S12: preparing first-type signal lines and second-type signal lines, wherein the first-type signal lines pass through all chips to be connected to each chip respectively, and the second-type signal lines do not pass through the chips.

[0071] The step of passing the first type of signal line through all chips specifically includes: leading the first type of signal line from the bottom chip, passing through all chips through the redistribution line, and connecting with other layers of chips and pads.

[0072] The second type of signal lines do not pass through the chip, so that the second type of signal lines are led out from other chips except the top chip in advance, without passing through the chip, to directly connect with the pads on the packaging layer.

[0073] S13: A packaging layer is formed on a side of the top chip away from other chips, and a plurality of pads are provided on the packaging layer.

[0074] The packaging layer is formed on the side of the top chip away from other chips, and a plurality of pads are correspondingly formed on the side of the packaging layer away from the top chip.

[0075] S14: The first type signal line and the second type signal line pass through the packaging layer and connect to the pads on the packaging layer.

[0076] In this embodiment, the first type of signal lines passing through all chips pass through the packaging layer after the packaging layer is completed, and are connected to the pads on the packaging layer. Second type of signal lines that do not need to pass through each chip are led out from other chips except the top chip. During the process of manufacturing the packaging layer, they pass through the packaging layer and are connected to the pads on the completed packaging layer.

[0077] Different from the existing technology, the packaging method of this embodiment reasonably utilizes the characteristics of different sizes of each chip, and uses the connection layer to advance the important signal lines in the bottom chip that are not required to connect to other chips from other chips except the top chip, so that the above-mentioned signal lines do not need to pass through other chips and are directly connected to the pads on the packaging layer, avoiding the loss of the signal in the process of passing through other chips and ensuring the integrity of the signal. At the same time, since the above-mentioned signal lines do not need to pass through other chips, the routing difficulty of other chips will not be increased, so that other chips have more routing space.

[0078] Furthermore, in one embodiment, in the above S14, it can also specifically include: leading out the second type of signal lines from other chips except the top chip, without passing through each chip, and the led-out second type of signal lines pass through the non-overlapping position of each chip, penetrate the packaging layer, and connect to the pad.

[0079] It is understandable that the projections of each chip along the arrangement direction of the multiple chips do not overlap, that is, when the sizes of the chips from the top layer to the bottom layer are not equal, there is a blank area between the two adjacent chips. After the second type of signal line is led out from the chips other than the top layer chip, it passes through the above-mentioned blank area and penetrates the packaging layer, so that the bottom chip is connected to the pad on the packaging layer.

[0080] The above packaging structure solves the problem of unequal sizes of chips from the top layer to the bottom layer. Signal lines that are not required to connect to other layers are led out in advance so that they do not need to pass through other chips other than the bottom chip, thereby avoiding signal loss caused by the process of connecting to other chips.

[0081] Furthermore, in another embodiment, in the above S14, it can specifically include: making through holes at set positions of the top chip and / or at least part of the middle layer chips, and leading the second type of signal line from other chips except the top chip, passing through the through hole, and penetrating the packaging layer to connect with the pad.

[0082] It can be understood that when the projections of each chip along the arrangement direction of multiple chips overlap, that is, the sizes of the chips from the top layer to the bottom layer are equal, through holes are pre-made at the set positions of the top chip and / or other chips, and the second type of signal line is led out from the chips other than the top chip, passes through the through hole, and penetrates the packaging layer to be connected to the pads on the packaging layer.

[0083] The above packaging method solves the problem that when the chips from the top layer to the bottom layer are of equal size, the signal lines that are not required to connect to other chips are led out in advance so that they do not need to pass through other chips except the top chip, thereby avoiding signal loss caused by the process of connecting to other chips. At the same time, since the above signal lines do not need to pass through other chips, there is more routing space for other chips, which reduces the routing difficulty of other chips.

[0084] Please continue reading Figure 6 , Figure 6 The schematic diagram of the second embodiment of the packaging method provided by this application. The packaging method in this embodiment is a detailed embodiment of the first embodiment of the packaging method provided by this application. Figure 5 S11 in corresponds to Figure 6 corresponds to S21 in , and Figure 5 S12 to S14 in the Figure 6 S23 to S25 are the same as those in FIG. 1 and will not be described in detail here.

[0085] and Figure 6 Examples and Figure 5 The difference between the embodiments is that:

[0086] S22: making at least one connection layer, and disposing the connection layer between the chips.

[0087] Specifically, a connection layer is formed between the chips to connect every two adjacent chips.

[0088] Through the above packaging method, signal lines that do not need to pass through other chips can be led out in advance, thereby reducing the loss caused by the signal passing through other chips and ensuring the integrity of the signal.

[0089] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent principle transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A packaging structure, characterized in that: The packaging structure includes: At least two chips arranged in a stacked manner; An encapsulation layer is provided on a side of the top chip away from other chips, wherein a pad is provided on the side of the encapsulation layer away from the top chip; The other chips except the top chip include: first-class signal lines and second-class signal lines, wherein the first-class signal lines pass through all the chips and are respectively connected to each chip and the pad; the second-class signal lines are connected to the pad and do not pass through the chip; The top layer chip and / or at least part of the middle layer chips are provided with through holes at set positions, and the second type signal lines are led out from other chips except the top layer chip, pass through the through holes, and are connected to the pads.

2. The packaging structure according to claim 1, wherein: The second type of signal lines are led out from chips other than the top chip, and extend to the pads through non-overlapping positions of the chips to be connected to the pads.

3. The packaging structure according to claim 1, wherein: The cross section of the through hole of each chip along the chip stacking direction is stepped.

4. The packaging structure according to any one of claims 1 to 3, characterized in that: The first type signal lines and the second type signal lines pass through the packaging layer.

5. The packaging structure according to claim 1, wherein: The packaging structure further includes a connection layer, which is arranged between the chips.

6. The packaging structure according to any one of claims 5, characterized in that: A plurality of redistribution lines are further provided in the connection layer. The first type of signal lines pass through all the chips through the redistribution lines, and the second type of signal lines are led out from the bottom chip through the redistribution lines.

7. A packaging method, characterized in that: The packaging method comprises: preparing at least two chips; preparing first-type signal lines and second-type signal lines, wherein the first-type signal lines pass through all the chips to be connected to each chip respectively, and the second-type signal lines do not pass through the chips; A packaging layer is formed on a side of the top chip away from other chips, wherein a plurality of pads are formed on the packaging layer; The first type of signal line and the second type of signal line pass through the packaging layer and connect to the pad, including: making through holes at set positions of the top layer chip and / or at least part of the chips in the middle layer; The second-type signal lines are led out from chips other than the top chip, passed through the through holes, penetrated the packaging layer, and connected to the pads.

8. The packaging method according to claim 7, wherein: The step of passing the first type signal line and the second type signal line through the packaging layer and connecting them to the pads includes: Leading the second-type signal lines out from other chips except the top chip; The second-type signal lines are led out through non-overlapping positions of the chips, penetrate the packaging layer, and are connected to the pads.

9. The packaging method according to claim 7, wherein: After the step of preparing at least two chips and before the step of preparing the first type signal line and the second type signal line, the method further includes: Make at least one connecting layer; The connection layer is arranged between the chips.

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