Semiconductor device

Abstract

The present application provides a semiconductor device; wherein the semiconductor device comprises a substrate, a normally-on GaN element, a low-voltage silicon field effect transistor and a metal gate MOSFET. The low-voltage silicon field effect transistor is coupled to the normally-on GaN element, and the normally-on GaN element and the metal gate MOSFET are formed on the same substrate. The metal gate MOSFET serves as a clamp diode, so its metal gate and source are coupled to the low-voltage silicon field effect transistor, and the drain of the metal gate MOSFET is coupled to the normally-on GaN element. In another semiconductor device, the above-mentioned metal gate MOSFET is directly used to replace the low-voltage silicon field effect transistor to form a common source and common gate circuit with the normally-on GaN element.

Description

Technical Field

[0001] This invention relates to a cascode circuit for normally open transistors, and more particularly to a semiconductor device having a metal-gate MOSFET (metal-oxide-semiconductor field-effect transistor) and a normally open transistor. Background Technology

[0002] Normally open (D-mode) GaN devices need to be combined with low-voltage silicon (LV Si) MOSFETs through packaging technology to form a common-source, common-gate structure for normal operation.

[0003] However, when the system performs a turn-on / turn-off transition, the instantaneous high voltage between the source of the gallium nitride (GaN) device and the drain of the low-voltage silicon MOSFET is more than twice the threshold voltage (Vt) of the GaN device. Therefore, such a high voltage may damage the device due to parasitic effects.

[0004] Furthermore, if the voltage between the source of the GaN device and the drain of the low-voltage silicon MOSFET is increased to a high voltage, damage to the gate of the GaN device and the gate of the low-voltage silicon MOSFET, as well as damage to the drain junction of the low-voltage silicon MOSFET, may occur during system switching. Summary of the Invention

[0005] This invention relates to a semiconductor device that can prevent damage to the gate of an open GaN device and the drain junction of a low-voltage silicon field-effect transistor (LSP).

[0006] This invention relates to another semiconductor device that reduces parasitic effects and prevents damage to the semiconductor device due to excessive voltage.

[0007] According to an embodiment of the present invention, a semiconductor device includes a substrate, a normally open GaN element, a low-voltage silicon field-effect transistor (SDS transistor), and a metal-gate MOSFET. Both the normally open GaN element and the metal-gate MOSFET are formed on the substrate, and the SSD transistor is coupled to the normally open GaN element. The metal gate and source of the metal-gate MOSFET are coupled to the SSD transistor, and the drain of the metal-gate MOSFET is coupled to the normally open GaN element.

[0008] In a semiconductor device according to an embodiment of the present invention, the source of the metal gate MOSFET is coupled to the metal gate and the source of the low-voltage silicon field-effect transistor.

[0009] In a semiconductor device according to an embodiment of the present invention, the drain of the metal gate MOSFET is coupled to the source of the normally open GaN element.

[0010] In a semiconductor device according to an embodiment of the present invention, the drain of the low-voltage silicon field-effect transistor is coupled to the source of the normally open GaN element.

[0011] According to another embodiment of the present invention, a semiconductor device includes a substrate, a normally open GaN element, and a metal-gate MOSFET. Both the normally open GaN element and the metal-gate MOSFET are formed on the substrate, wherein the normally open GaN element includes a source, a drain, and a gate. The metal gate of the metal-gate MOSFET is coupled to a control terminal, the source of the metal-gate MOSFET is in contact with the substrate and coupled to the gate of the normally open GaN element, and the drain of the metal-gate MOSFET is in contact with the substrate and coupled to the source of the normally open GaN element.

[0012] In a semiconductor device according to another embodiment of the present invention, the metal gate MOSFET and the normally open GaN element have the same ground (GND) potential.

[0013] In the semiconductor device according to all embodiments of the present invention, the metal gate MOSFET may further include a plurality of first conductivity type doped regions and a second conductivity type doped region. The first conductivity type doped regions are respectively formed in the substrate on both sides of the metal gate of the metal gate MOSFET. The second conductivity type doped region is formed in the substrate below the source of the metal gate MOSFET and is separated from the metal gate by the first conductivity type doped region.

[0014] In the semiconductor device according to all embodiments of the present invention, the normally open GaN element includes a buffer layer formed on the surface of the substrate, a channel layer formed on the buffer layer, a barrier layer formed on the channel layer, the source and drain electrodes that pass through the barrier layer and contact the channel layer, and the gate electrode formed on the barrier layer.

[0015] Based on the above, in the semiconductor device of the present invention, a metal-gate MOSFET is added as a clamping diode in the common-source, common-gate circuit of the normally open GaN element and the low-voltage silicon field-effect transistor (SDS transistor). This suppresses unnecessary voltage rises, preventing damage to the gates of the GaN element and the SSD transistor, as well as damage to the drain junction of the SSD transistor, during system on / off switching. Furthermore, if the metal-gate MOSFET replaces the SSD, since it is formed on the same substrate as the normally open GaN element, the short connection distance significantly reduces parasitic effects. Additionally, the shared ground (GND) potential between the metal-gate MOSFET and the normally open GaN element lowers the voltage between the source of the normally open GaN element and the drain of the metal-gate MOSFET to near the absolute value of the threshold voltage (Vt) of the normally open GaN element, thereby preventing damage to the semiconductor device.

[0016] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0018] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device according to a first embodiment of the present invention.

[0019] Figure 2 yes Figure 1 The equivalent circuit diagram of a semiconductor device.

[0020] Figure 3 This is a cross-sectional schematic diagram of a semiconductor device according to a second embodiment of the present invention.

[0021] Figure 4 yes Figure 3 The equivalent circuit diagram of a semiconductor device.

[0022] Figure Labels

[0023] 100: Substrate

[0024] 110: Normally Open GaN Device

[0025] 112: Buffer layer

[0026] 114: Channel Layer

[0027] 116: Barrier layer

[0028] 118: Top Cover Layer

[0029] 120: Low-voltage silicon field-effect transistor

[0030] 130: Metal Gate MOSFET

[0031] 132: First conductivity type doped region

[0032] 134: Second conductivity type doped region

[0033] 136: Gate insulating layer

[0034] 2DEG: Two-dimensional electron gas

[0035] D1, D2, D3: Drain electrode

[0036] G1, G2: Gate

[0037] MG: Metal Gate

[0038] S1, S2, S3: Source Detailed Implementation

[0039] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Furthermore, for clarity, the relative thicknesses, distances, and positions of various regions or films may be reduced or enlarged. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0040] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device according to a first embodiment of the present invention.

[0041] Please refer to Figure 1The semiconductor device of this embodiment includes a substrate 100, a normally open GaN element 110, a low-voltage silicon (LPSi) field-effect transistor 120, and a metal-gate MOSFET 130. The normally open GaN element 110 is formed on the substrate 100, and the metal-gate MOSFET 130 is formed on the same substrate 100. The LPSi field-effect transistor 120 is coupled to the normally open GaN element 110 to form a common-source, common-gate GaN circuit semiconductor device, so that the normally open GaN element 110 is controlled to become a normally off element (or E-mode element) by the LPSi field-effect transistor 120. For example, the drain D2 of the LPSi field-effect transistor 120 is coupled to the source S1 of the normally open GaN element 110 through packaging technology, and the gate G2 can be connected to a gate driver (not shown). In this embodiment, the metal gate MG and source S3 of the metal gate MOSFET 130 are coupled to the low-voltage silicon field-effect transistor 120, such as to the source S2 of the low-voltage silicon field-effect transistor 120; the drain D3 of the metal gate MOSFET 130 is coupled to the normally open GaN element 110, such as to the source S1 of the normally open GaN element 110. Therefore, the metal gate MOSFET 130 can act as a clamp diode to prevent the voltage transferred from the drain D2 of the low-voltage silicon field-effect transistor 120 to the source S1 of the normally open GaN element 110 from continuously rising to the avalanche voltage during the system's turn-on / turn-off transition.

[0042] exist Figure 1In the normally open GaN device 110, a buffer layer 112 formed on the surface of a substrate 100, a channel layer 114 formed on the buffer layer 112, a barrier layer 116 formed on the channel layer 114, a source S1 and a drain D1 that pass through the barrier layer 116 and contact the channel layer 114, and a gate G1 formed on the barrier layer 116. The buffer layer 112 can mitigate the strain of the channel layer 114 subsequently formed above the buffer layer 112 and has the effect of preventing defects from forming in the channel layer 114. The material of the buffer layer 112 may include, but is not limited to, aluminum nitride, gallium nitride, aluminum gallium nitride, or combinations thereof. The channel layer 114 may be formed of undoped gallium nitride (GaN). The material of the barrier layer 116 is an undoped III-V semiconductor material, including, but not limited to, aluminum gallium nitride or other suitable III-V materials. The channel layer 114 and the barrier layer 116 are heterogeneous materials, forming a heterogeneous interface between them. The band gap difference between the heterogeneous materials allows a two-dimensional electron gas (2DEG) to form on this interface. Furthermore, a capping layer 118 can be grown on the barrier layer 116 to protect the underlying film layers. The barrier layer 116 can be made of materials such as silicon nitride or other suitable materials. Each layer in the normally open GaN device 110 can be formed into an epitaxial structure using epitaxial processes such as metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), or a combination of these methods.

[0043] exist Figure 1In this embodiment, the metal gate MOSFET 130 may further include multiple first conductivity type doped regions 132 and second conductivity type doped regions 134. The first conductivity type doped regions 132 are formed in the substrate 100 on both sides of the metal gate MG of the metal gate MOSFET 130, while the second conductivity type doped regions 134 are formed in the substrate 100 below the source S3 of the metal gate MOSFET 130 and are separated from the metal gate MG by the first conductivity type doped regions 132. That is, there are two doped regions of different conductivity types contacting the source S3. In one embodiment, the first conductivity type doped region 132 is an N+ type doped region and the second conductivity type doped region 134 is a P+ type doped region; in another embodiment, the first conductivity type doped region 132 is a P+ type doped region and the second conductivity type doped region 134 is an N+ type doped region. A gate insulating layer 136 is provided between the metal gate MG and the substrate 100. The fabrication method of the metal gate MOSFET 130 includes, but is not limited to, the following: after the formation of the epitaxial structure of the normally open GaN element 110 and before the formation of the electrodes (source S1, drain D1, and gate G1), the epitaxial structure in the region where the metal gate MOSFET 130 is to be formed is removed. Then, a first conductivity type doped region 132 and a second conductivity type doped region 134 are formed in a portion of the substrate 100 using methods such as ion implantation. Subsequently, the source S1 and drain D1 of the normally open GaN element 110 are formed. Then, the gate G1 of the normally open GaN element 110 can be formed together with the source S3, drain D3, and metal gate MG of the metal gate MOSFET 130. Before the formation of the metal gate MG, there is usually a step of forming a gate insulating layer 136. The aforementioned steps may include processes such as deposition, photolithography, and etching, but the present invention is not limited to these.

[0044] Figure 2 yes Figure 1 The equivalent circuit diagram of the semiconductor device. Since the metal gate MG of the metal gate MOSFET 130 is coupled to the source S3 to the source S2 of the low-voltage silicon field-effect transistor 120, avalanche breakdown of the cascode circuit can be avoided, thereby protecting the normally open GaN device 110.

[0045] Figure 3 This is a cross-sectional schematic diagram of a semiconductor device according to a second embodiment of the present invention, wherein the same element symbols as in the first embodiment are used to represent the same or similar parts and components, and the relevant content of the same or similar parts and components can also refer to the content of the first embodiment, and will not be repeated here.

[0046] Please refer to Figure 3The semiconductor device of this embodiment includes a substrate 100, a normally open GaN element 110, and a metal-gate MOSFET 130. The normally open GaN element 110 and the metal-gate MOSFET 130 are formed on the same substrate 100. The metal gate MG of the metal-gate MOSFET 130 is coupled to a control terminal, the source S3 of the metal-gate MOSFET 130 is in contact with the substrate 100 and coupled to the gate G1 of the normally open GaN element 110, and the drain D3 of the metal-gate MOSFET 130 is in contact with the substrate 100 and coupled to the source S1 of the normally open GaN element 110. The detailed structures of the normally open GaN element 110 and the metal-gate MOSFET 130 can be referred to the description in the first embodiment, and will not be repeated here.

[0047] In other words, the second embodiment uses a metal-gate MOSFET 130 to replace the low-voltage silicon field-effect transistor in the first embodiment, and forms a common-source, common-gate circuit with the normally open GaN element 110. Please refer to the following: Figure 4 The equivalent circuit. Because the metal gate MOSFET 130 and the normally open GaN element 110 are formed on the same substrate 100, not only can the parasitic effect be reduced due to the significantly shortened wire connection distance between the two, but also the voltage between the source S1 of the normally open GaN element 110 and the drain D3 of the metal gate MOSFET 130 can be reduced to near the absolute value of the threshold voltage (Vt) of the normally open GaN element 110 by using the same ground (GND) potential between the metal gate MOSFET 130 and the normally open GaN element 110, thereby avoiding damage to the semiconductor device.

[0048] In summary, this invention, through specific component design, adds a metal gate MOSFET as a clamping diode to the common-source cascode circuit of a normally open transistor, or directly uses a metal gate MOSFET on the same substrate to replace a low-voltage silicon field-effect transistor, so as to prevent damage to the semiconductor device when the system performs on / off switching.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that, include: One substrate; A normally open GaN device is formed on the substrate; A low-voltage silicon field-effect transistor is coupled to the normally open GaN device; as well as A metal gate MOSFET is formed on the substrate, wherein the metal gate and source of the metal gate MOSFET are coupled to the low-voltage silicon field-effect transistor, and the drain of the metal gate MOSFET is coupled to the normally open GaN device.

2. The semiconductor device according to claim 1, characterized in that, The source of the metal-gate MOSFET is coupled to the metal gate and then to the source of the low-voltage silicon field-effect transistor.

3. The semiconductor device according to claim 1, characterized in that, The drain of the metal gate MOSFET is coupled to the source of the normally open GaN element.

4. The semiconductor device according to claim 1, characterized in that, The metal gate MOSFET further includes: Multiple first conductivity type doped regions are respectively formed in the substrate on both sides of the metal gate of the metal gate MOSFET; and A second conductivity-type doped region is formed in the substrate below the source of the metal gate MOSFET and is separated from the metal gate of the metal gate MOSFET by the first conductivity-type doped region.

5. The semiconductor device according to claim 1, characterized in that, The drain of the low-voltage silicon field-effect transistor is coupled to the source of the normally open GaN element.

6. The semiconductor device according to claim 1, characterized in that, The normally open GaN device includes: A buffer layer is formed on the surface of the substrate; The channel layer is formed on the buffer layer; A barrier layer is formed on the channel layer; The source and drain electrodes pass through the barrier layer and contact the channel layer; and A gate is formed on the barrier layer.

7. A semiconductor device, characterized in that, include: One substrate; A normally open GaN device is formed on the substrate, wherein the normally open GaN device includes a source, a drain, and a gate; as well as A metal-gate MOSFET is formed on the substrate, wherein the metal gate of the metal-gate MOSFET is coupled to a control terminal, the source of the metal-gate MOSFET is in contact with the substrate and coupled to the gate of the normally open GaN device, and the drain of the metal-gate MOSFET is in contact with the substrate and coupled to the source of the normally open GaN device. The metal gate MOSFET further includes a plurality of first conductivity type doped regions, which are respectively formed in the substrate on both sides of the metal gate of the metal gate MOSFET.

8. The semiconductor device according to claim 7, characterized in that, The metal gate MOSFET and the normally open GaN element have the same ground potential.

9. The semiconductor device according to claim 7, characterized in that, The metal gate MOSFET further includes: A second conductivity-type doped region is formed in the substrate below the source of the metal gate MOSFET and is separated from the metal gate of the metal gate MOSFET by the first conductivity-type doped region.

10. The semiconductor device according to claim 7, characterized in that, The normally open GaN device includes: A buffer layer is formed on the surface of the substrate; A channel layer is formed on the buffer layer; A barrier layer is formed on the channel layer; The source and drain electrodes pass through the barrier layer and contact the channel layer; and The gate is formed on the barrier layer.

Images