Array substrate and display panel

Abstract

The present application discloses an array substrate and a display panel. The array substrate includes a substrate, a metal transition layer, a pixel definition layer, and a cathode layer. The substrate has a display area and a non-display area surrounding the display area. The metal transition layer is disposed on the substrate and located in the non-display area. The pixel definition layer is disposed on a side of the metal transition layer away from the substrate. The pixel definition layer includes a plurality of spaced dams, and the metal transition layer is located between two adjacent dams. Among them, the distance between two adjacent dams in the non-display area is greater than the distance between two adjacent dams in the display area. The cathode layer covers the metal transition layer and the pixel definition layer. This array substrate can reduce the lap impedance between the metal transition layer and the cathode layer and improve the current tolerance of the array substrate.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to an array substrate and a display panel. Background Art

[0002] Currently, Active Matrix Organic Light Emitting Displays (AMOLEDs) are widely used in various fields due to their advantages such as high brightness, low power consumption, fast response, high clarity, good flexibility, and high luminous efficiency. As the application scope of AMOLED display products becomes wider and wider, the requirements for the resolution, brightness, narrow borders, etc. of AMOLED display products are getting higher and higher. With the compression of the product border size, the conduction impedance of the power signal lines in the non-display area is getting larger and larger.

[0003] Existing AMOLED displays adopt a common cathode structure, that is, the pixel emission currents of the panel all flow through the surface cathode. Among them, the power signal lines electrically connected to the cathode are distributed in the non-display area, and the cathode is short-circuited with the power signal lines through a transfer layer and multiple nested vias to flow through the total panel current. In the existing panel, the latching impedance between the cathode and the transfer layer is relatively large, and the current-carrying risk of the panel is relatively high. In severe cases, it may even cause the panel to burn out.

[0004] Therefore, how to reduce the latching impedance between the cathode and the transfer layer and improve the current-carrying performance of the panel is an urgent problem to be solved. Summary of the Invention

[0005] This application provides an array substrate and a display panel, which can reduce the latching impedance between the metal transfer layer and the cathode layer and improve the current-carrying performance of the array substrate.

[0006] In a first aspect, an embodiment of this application provides an array substrate, including: a substrate, a metal transfer layer, a pixel definition layer, and a cathode layer. The substrate has a display area and a non-display area surrounding the display area; the metal transfer layer is disposed on the substrate and located in the non-display area; the pixel definition layer is disposed on a side of the metal transfer layer away from the substrate. The pixel definition layer includes a plurality of spaced dams, and the metal transfer layer is located between two adjacent dams. Among them, the distance between two adjacent dams in the non-display area is greater than the distance between two adjacent dams in the display area; the cathode layer covers the metal transfer layer and the pixel definition layer.

[0007] Optionally, in some embodiments of the present application, the array substrate further includes a power supply trace layer and a passivation layer. The power supply trace layer is disposed on the substrate and located in the non-display area. The passivation layer is disposed on a side of the power supply trace layer away from the substrate and located in the non-display area. A first via hole is provided on the passivation layer, and the metal transfer layer covers the first via hole.

[0008] Optionally, in some embodiments of the present application, in the non-display area, the array substrate further includes a data trace layer, a buffer layer, and an interlayer dielectric layer. The data trace layer is disposed on the substrate and located between two adjacent dams. The buffer layer is disposed on a side of the data trace layer away from the substrate. The interlayer dielectric layer is disposed on a side of the buffer layer away from the substrate. The power supply trace layer is disposed on a side of the interlayer dielectric layer away from the substrate.

[0009] Optionally, in some embodiments of the present application, a plurality of second via holes are further provided on the power supply trace layer. The data trace layer includes a plurality of data signal lines arranged at intervals in a first direction. A positive projection of the second via hole on the substrate at least partially overlaps a positive projection of the data signal line on the substrate.

[0010] Optionally, in some embodiments of the present application, the plurality of second via holes are arranged at intervals in a second direction. A positive projection of the second via hole on the substrate at least partially overlaps positive projections of the plurality of data signal lines on the substrate.

[0011] Optionally, in some embodiments of the present application, a cross-sectional width of the first via hole extending in the first direction is greater than or equal to a cross-sectional width of the second via hole extending in the first direction.

[0012] Optionally, in some embodiments of the present application, the plurality of second via holes are arranged at intervals in the first direction. A positive projection of the second via hole on the substrate at least partially overlaps a positive projection of the data signal line on the substrate.

[0013] Optionally, in some embodiments of the present application, a cross-sectional length of the first via hole extending in the second direction is greater than or equal to a cross-sectional length of the second via hole extending in the second direction.

[0014] Optionally, in some embodiments of the present application, the plurality of second via holes are arranged in an array, and a cross-sectional area of the first via hole is greater than a sum of cross-sectional areas of the plurality of second via holes.

[0015] On the other hand, the present application provides a display panel including the above-mentioned array substrate.

[0016] The present application provides an array substrate and a display panel. The array substrate includes a substrate, a metal transfer layer, a pixel definition layer, and a cathode layer. The substrate has a display area and a non-display area surrounding the display area. The metal transfer layer is disposed on the substrate and located in the non-display area. The pixel definition layer is disposed on a side of the metal transfer layer away from the substrate. The pixel definition layer includes a plurality of spaced dams, and the metal transfer layer is located between two adjacent dams. Among them, the distance between two adjacent dams in the non-display area is greater than the distance between two adjacent dams in the display area. The cathode layer covers the metal transfer layer and the pixel definition layer. By increasing the distance between the dams in the pixel definition layer in the non-display area, the cross-sectional width / area of the metal transfer layer disposed between two adjacent dams correspondingly increases, thereby increasing the overlapping area between the cathode layer and the metal transfer layer, reducing the overlapping impedance between the cathode layer and the metal transfer layer, improving the current-carrying capacity of the array substrate, and increasing the product yield and lifespan. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. The following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0018] Figure 1 is a top view structural schematic diagram of the array substrate provided by an embodiment of the present application;

[0019] Figure 2 is Figure 1 the first cross-sectional structural schematic diagram of the array substrate provided in along the AA' direction;

[0020] Figure 3 is a top view structural schematic diagram of the non-display area of the array substrate provided by the first embodiment of the present application;

[0021] Figure 4 is Figure 1 the second cross-sectional structural schematic diagram of the array substrate provided in along the AA' direction;

[0022] Figure 5 is one of the top view schematic diagrams of the non-display area of the array substrate provided by the second embodiment of the present application;

[0023] Figure 6 is the other top view schematic diagram of the non-display area of the array substrate provided by the second embodiment of the present application;

[0024] Figure 7 isFigure 1 The third cross-sectional structure diagram of the array substrate along the AA' direction provided in

[0025] Figure 8 It is a top view structure diagram of the non-display area of the array substrate provided in the third embodiment of the present application. Detailed implementation manners

[0026] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0027] The embodiments of the present application provide an array substrate and a display panel, which can reduce the lap impedance between the metal transfer layer and the cathode layer and improve the current resistance of the panel. The following will be described in detail respectively. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments. In addition, in the description of the present application, the term "including" means "including but not limited to". The terms "first", "second", "third", etc. are only used as labels and are used to distinguish different objects, rather than to describe a specific order.

[0028] Please refer to Figures 1 to 3 , Figure 1 It is a top view structure diagram of the array substrate provided in the embodiments of the present application; Figure 2 is Figure 1 The first cross-sectional structure diagram of the array substrate along the AA' direction provided in Figure 3 It is a top view structure diagram of the non-display area NA of the array substrate provided in the first embodiment of the present application. As Figures 1 to 3 shown, the embodiments of the present application provide an array substrate 100, including: a substrate substrate 10, a metal transfer layer 20, a pixel definition layer 30, and a cathode layer 40. The substrate substrate 10 has a display area AA and a non-display area NA surrounding the display area AA; the metal transfer layer 20 is disposed on the substrate substrate 10 and is located in the non-display area NA; the pixel definition layer 30 is disposed on the side of the metal transfer layer 20 away from the substrate substrate 10. The pixel definition layer 30 includes a plurality of spaced dams. The metal transfer layer 20 is located between two adjacent dams. Among them, the distance 31 between two adjacent dams in the non-display area NA is greater than the distance between two adjacent dams in the display area AA; the cathode layer 40 covers the metal transfer layer 20 and the pixel definition layer 30.

[0029] The array substrate 100 provided by the present application increases the spacing between the dams in the pixel definition layer 30 located in the non-display area NA, so that the cross-sectional width / area of the metal transfer layer 20 disposed between two adjacent dams correspondingly increases, thereby increasing the overlapping area between the cathode layer 40 and the metal transfer layer 20, reducing the overlapping impedance between the cathode layer 40 and the metal transfer layer 20, improving the current-carrying capacity of the array substrate, and increasing the product yield and lifespan.

[0030] In the embodiment of the present application, the array substrate 100 further includes a power supply trace layer 50 and a passivation layer 60. The power supply trace layer 50 is disposed on the substrate 10 and located in the non-display area NA; the passivation layer 60 is disposed on the side of the power supply trace layer 50 away from the substrate 10 and located in the non-display area NA. A first via 61 is provided on the passivation layer 60, and the metal transfer layer 20 covers the first via 61. Specifically, the metal transfer layer 20 is electrically connected to the power supply trace layer 50 through the first via 61. Further, the cathode layer 40 is electrically connected to the power supply trace layer 50 by overlapping with the metal transfer layer 20.

[0031] It should be noted that the metal transfer layer 20 can be provided on the same layer as the anode of the light-emitting element in the display area AA. The material and thickness of the metal transfer layer 20 and the anode can be the same, but it is not equivalent to the anode in the light-emitting element. The light-emitting element in the display area AA is used for emitting light, and a light-emitting layer is provided between its cathode and anode. The cathode in the non-display area NA needs to be directly overlapped with the metal transfer layer 20, thereby realizing the short circuit between the metal transfer layer 20 and the power supply trace layer 50.

[0032] In the embodiment of the present application, in the non-display area NA, the array substrate 100 further includes a data trace layer 70, a buffer layer 80, and an interlayer dielectric layer 90. The data trace layer 70 is disposed on the substrate 10 and located between two adjacent dams. The buffer layer 80 is disposed on the side of the data trace layer 70 away from the substrate 10. The interlayer dielectric layer 90 is disposed on the side of the buffer layer 80 away from the substrate 10. The power supply trace layer 50 is disposed on the side of the interlayer dielectric layer 90 away from the substrate 10.

[0033] In the embodiments of the present application, the buffer layer 80, the interlayer dielectric layer 90, and the passivation layer 60 may be made of any one or more of silicon oxide, silicon nitride, and silicon oxynitride, and may be a single layer, multiple layers, or a composite layer. The buffer layer 80 is used to improve the water and oxygen resistance of the substrate 10. The data trace layer 70 and the power trace layer 50 may be made of a metal material, such as any one or more of silver, copper, aluminum, titanium, and molybdenum, or an alloy material of the above metals, such as an aluminum-neodymium alloy or a molybdenum-niobium alloy, and may be a single-layer structure or a multi-layer composite structure, such as titanium / aluminum / titanium, etc. The metal transfer layer 20 may include indium tin oxide or indium zinc oxide. The pixel definition layer 30 may be made of polyimide, acrylic, polyethylene terephthalate, etc. The cathode layer 40 may be made of any one or more of metal materials such as magnesium, silver, aluminum, copper, and lithium, or an alloy made of any one or more of the above metals.

[0034] In the embodiments of the present application, a plurality of second vias 51 are further provided on the power trace layer 50 and arranged at intervals. The data trace layer 70 includes a plurality of data signal lines DATA arranged at intervals along the first direction X. The orthographic projection of the second via 51 on the substrate 10 at least partially overlaps with the orthographic projection of the data signal line DATA on the substrate 10. Among them, the power trace layer 50 includes a cathode signal line, and the cathode signal line is electrically connected to the cathode and is used to transmit a low-level power signal to the cathode. The design of arranging the second via 51 at the position corresponding to the data signal line DATA is beneficial to reducing the coupling capacitance between the data signal line DATA and the cathode signal line, thereby avoiding horizontal crosstalk caused by the coupling capacitance between the data signal line DATA and the cathode signal line, and is beneficial to improving the display effect.

[0035] In the embodiments of the present application, the plurality of second vias 51 are arranged at intervals along the second direction Y, and the orthographic projection of the second via 51 on the substrate 10 at least partially overlaps with the orthographic projections of the plurality of data signal lines DATA on the substrate 10. Specifically, under the condition of maintaining a spacing distance between the first via 61 and the second via 51 to avoid overlap, the cross-sectional area of the second via 51 is as large as possible, which is beneficial to further reducing the coupling capacitance between the data signal line DATA and the cathode signal line.

[0036] In the embodiment of the present application, the cross-sectional width of the first via 61 extending along the first direction X is greater than or equal to the cross-sectional width of the second via 51 extending along the first direction X. Preferably, the orthographic projection of the second via 51 on the substrate 10 overlaps at least partially with the orthographic projection of each data signal line DATA on the substrate 10, and the cross-sectional width of the first via 61 extending along the first direction X is greater than the cross-sectional width of the second via 51 extending along the first direction X. Such a design is beneficial to reducing the coupling capacitance between the data signal line DATA and the cathode signal line while maximizing the overlapping area between the metal transition layer 20 and the power trace layer 50, thereby further reducing the overlapping impedance between the cathode layer 40 and the metal transition layer 20, resulting in a lower current-carrying risk, that is, further improving the current-carrying capacity of the array substrate and further enhancing the current distribution uniformity.

[0037] Please refer to Figures 4 to 6 , Figure 4 is Figure 1 the second cross-sectional structure schematic diagram of the array substrate provided in Figure 5 the top view structure schematic diagram of the non-display area NA in the array substrate provided in the second embodiment of the present application; Figure 6 is the second top view structure schematic diagram of the non-display area NA in the array substrate provided in the second embodiment of the present application. As Figures 4 to 6 shown, the embodiment of the present application provides an array substrate 200. The difference between the array substrate 200 and the array substrate 100 is that a plurality of second vias 51 in the array substrate 200 are arranged at intervals along the first direction X, and the orthographic projection of the second via 51 on the substrate 10 overlaps at least partially with the orthographic projection of the data signal line DATA on the substrate 10.

[0038] In the embodiment of the present application, the cross-sectional length of the first via 61 extending along the second direction Y is greater than or equal to the cross-sectional length of the second via 51 extending along the second direction Y. Such a design is beneficial to maximizing the overlapping area between the metal transition layer 20 and the power trace layer 50, and also maximizing the reduction of the overlapping impedance, thereby improving the current-carrying capacity of the array substrate 200.

[0039] As Figure 4As shown, the array substrate 200 provided by the present application includes: a substrate 10, a data trace layer 70, a buffer layer 80, an interlayer dielectric layer 90, a power trace layer 50, a passivation layer 60, a metal transition layer 20, a pixel definition layer 30, and a cathode layer 40. The substrate 10 has a display area AA and a non-display area NA surrounding the display area AA. The data trace layer 70 is disposed on the substrate 10 and located between two adjacent dams. The buffer layer 80 is disposed on a side of the data trace layer 70 away from the substrate 10. The interlayer dielectric layer 90 is disposed on a side of the buffer layer 80 away from the substrate 10. The power trace layer 50 is disposed on a side of the interlayer dielectric layer 90 away from the substrate 10.

[0040] The passivation layer 60 is disposed on a side of the power trace layer 50 away from the substrate 10 and located in the non-display area NA. A first via 61 is provided on the passivation layer 60. The metal transition layer 20 is disposed on the substrate 10 and located in the non-display area NA. The metal transition layer 20 covers the first via 61. Specifically, the metal transition layer 20 is electrically connected to the power trace layer 50 through the first via 61. Further, the cathode layer 40 is electrically connected to the power trace layer 50 by overlapping with the metal transition layer 20.

[0041] The pixel definition layer 30 is disposed on a side of the metal transition layer 20 away from the substrate 10. The pixel definition layer 30 includes a plurality of dams arranged at intervals. The metal transition layer 20 is located between two adjacent dams. Among them, the distance between two adjacent dams in the non-display area NA is greater than the distance between two adjacent dams in the display area AA. The cathode layer 40 covers the metal transition layer 20 and the pixel definition layer 30.

[0042] In the embodiment of the present application, a plurality of second vias 51 arranged at intervals are further provided on the power trace layer 50. The data trace layer 70 includes a plurality of data signal lines DATA arranged at intervals along the first direction X. The orthographic projection of the second via 51 on the substrate 10 overlaps at least partially with the orthographic projection of the data signal line DATA on the substrate 10. Among them, the power trace layer 50 includes a cathode signal line, and the cathode signal line is electrically connected to the cathode and is used to transmit a low-level power signal to the cathode. The design of providing the second via 51 at the position corresponding to the data signal line DATA is beneficial to reducing the coupling capacitance between the data signal line DATA and the cathode signal line, and further avoiding horizontal crosstalk caused by the coupling capacitance between the data signal line DATA and the cathode signal line, which is beneficial to improving the display effect.

[0043] As Figure 5As shown, a plurality of second via holes 51 in the array substrate 200 are arranged at intervals along the first direction X, and the orthographic projection of the second via hole 51 on the base substrate 10 overlaps at least partially with the orthographic projection of the data signal line DATA on the base substrate 10, and the second via hole 51 and the data signal line DATA are arranged in a one-to-one correspondence. Such a design can accurately reduce the overlapping area between the data signal line DATA and the cathode signal line to reduce the coupling capacitance, and can also be more conducive to keeping the film layer flat.

[0044] like Figure 6 As shown, a plurality of second via holes 51 in the array substrate 200 are arranged at intervals along the first direction X, and the orthographic projection of the second via hole 51 on the base substrate 10 overlaps at least partially with the orthographic projection of the data signal line DATA on the base substrate 10, and the second via hole 51 is arranged corresponding to at least two data signal lines DATA. Specifically, the second via hole 51 may also overlap with three, four or even more data signal lines DATA. Figure 5 It is only exemplarily shown that the second via hole 51 is arranged corresponding to the two data signal lines DATA. Those skilled in the art can adjust the overlapping of the via hole and the data signal line DATA as needed, and this application does not make any specific limitation here.

[0045] The array substrate 200 provided in the present application, on the one hand, increases the spacing between the dams in the pixel definition layer 30 located in the non-display area NA, so that the cross-sectional width / area of ​​the metal transfer layer 20 disposed between two adjacent dams is correspondingly increased, thereby increasing the overlap area between the cathode layer 40 and the metal transfer layer 20, so as to reduce the overlap impedance between the cathode layer 40 and the metal transfer layer 20, improve the current resistance of the array substrate, and improve the product yield and life. On the other hand, a plurality of second vias 51 arranged at intervals along the first direction X and having an orthographic projection on the base substrate 10 at least partially overlapped with the orthographic projection of the data signal line DATA on the base substrate 10 are provided at the position corresponding to the data signal line DATA, which is conducive to reducing the coupling capacitance between the data signal line DATA and the cathode signal line, thereby avoiding horizontal crosstalk caused by the coupling capacitance between the data signal line DATA and the cathode signal line, and is conducive to improving the display effect.

[0046] See also Figure 7 and Figure 8 , Figure 7 yes Figure 1 A third cross-sectional structural schematic diagram of the array substrate along the AA' direction provided in; Figure 8 is a schematic diagram of a top view of a non-display area NA in an array substrate provided in the third embodiment of the present application. Figure 7 and Figure 8As shown in the figure, an array substrate 300 provided by an embodiment of the present application is different from the array substrate 100 in that: a plurality of second vias 51 in the array substrate 300 are arranged in an array, and the cross-sectional area of the first via 61 is larger than the sum of the cross-sectional areas of the plurality of second vias 51. Specifically, that is, a plurality of second vias 51 are correspondingly arranged on each data signal line DATA.

[0047] As Figure 7 shown in the figure, the array substrate 300 provided by the present application includes: a substrate 10, a data trace layer 70, a buffer layer 80, an interlayer dielectric layer 90, a power trace layer 50, a passivation layer 60, a metal transition layer 20, a pixel definition layer 30, and a cathode layer 40. The substrate 10 has a display area AA and a non-display area NA surrounding the display area AA; the data trace layer 70 is disposed on the substrate 10 and located between two adjacent dams, the buffer layer 80 is disposed on a side of the data trace layer 70 away from the substrate 10, the interlayer dielectric layer 90 is disposed on a side of the buffer layer 80 away from the substrate 10, and the power trace layer 50 is disposed on a side of the interlayer dielectric layer 90 away from the substrate 10.

[0048] The passivation layer 60 is disposed on a side of the power trace layer 50 away from the substrate 10 and located in the non-display area NA, and a first via 61 is provided on the passivation layer 60; the metal transition layer 20 is disposed on the substrate 10 and located in the non-display area NA, and the metal transition layer 20 covers the first via 61. Specifically, the metal transition layer 20 is electrically connected to the power trace layer 50 through the first via 61. Further, the cathode layer 40 is electrically connected to the power trace layer 50 by overlapping with the metal transition layer 20.

[0049] The pixel definition layer 30 is disposed on a side of the metal transition layer 20 away from the substrate 10. The pixel definition layer 30 includes a plurality of dams arranged at intervals, and the metal transition layer 20 is located between two adjacent dams. Among them, the distance between two adjacent dams in the non-display area NA is greater than the distance between two adjacent dams in the display area AA; the cathode layer 40 covers the metal transition layer 20 and the pixel definition layer 30.

[0050] In an embodiment of the present application, a plurality of second vias 51 arranged at intervals are further provided on the power supply trace layer 50. The data trace layer 70 includes a plurality of data signal lines DATA arranged at intervals along the first direction X. The orthographic projection of the second via 51 on the substrate 10 overlaps at least partially with the orthographic projection of the data signal line DATA on the substrate 10. Among them, the power supply trace layer 50 includes a cathode signal line, and the cathode signal line is electrically connected to the cathode and is used to transmit a low-level power signal to the cathode. The design of arranging the second via 51 at the position corresponding to the data signal line DATA is beneficial to reducing the coupling capacitance between the data signal line DATA and the cathode signal line, thereby avoiding horizontal crosstalk caused by the coupling capacitance between the data signal line DATA and the cathode signal line, and is beneficial to improving the display effect.

[0051] In an embodiment of the present application, as Figure 8 shown, a plurality of second vias 51 are arranged in an array. Specifically, the specific position of the second via 51 can be set at the intersection where the data signal line DATA overlaps with the cathode signal line. Thus, while accurately reducing the overlapping area between the data signal line DATA and the cathode signal line and reducing the coupling capacitance between the data signal line DATA and the cathode signal line, the area of the second via 51 is reduced, and the flatness of the film layer is improved.

[0052] In an embodiment of the present application, the cross-sectional area of the first via 61 is larger than the sum of the cross-sectional areas of the plurality of second vias 51. Under the condition of ensuring that the first via 61 and the second vias 51 are kept at intervals and avoiding overlapping, increasing the cross-sectional area of the first via 61 as much as possible is beneficial to increasing the overlapping area between the cathode layer 40 and the metal transition layer 20, so as to reduce the overlapping impedance between the cathode layer 40 and the metal transition layer 20, improve the current-carrying capacity of the array substrate, and improve the product yield and lifespan.

[0053] For the array substrate 300 provided by the present application, on the one hand, by increasing the distance between the dams in the pixel definition layer 30 located in the non-display area NA, the cross-sectional width / area of the metal transition layer 20 provided between two adjacent dams correspondingly increases, thereby increasing the overlapping area between the cathode layer 40 and the metal transition layer 20, reducing the overlapping impedance between the cathode layer 40 and the metal transition layer 20, improving the current-carrying capacity of the array substrate, and improving the product yield and lifespan. On the other hand, a plurality of second vias 51 arranged in an array are provided at the position corresponding to the data signal line DATA, which is beneficial to reducing the coupling capacitance between the data signal line DATA and the cathode signal line, thereby avoiding horizontal crosstalk caused by the coupling capacitance between the data signal line DATA and the cathode signal line, and is beneficial to improving the display effect. At the same time, the flatness of the film layer is maintained.

[0054] On the other hand, the present application provides a display panel including the above-mentioned array substrate. It should be noted that the display panel can be applied to any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc.

[0055] The present application provides an array substrate 100 / 200 / 300 and a display panel. The array substrate 100 / 200 / 300 includes: a substrate 10, a metal transfer layer 20, a pixel definition layer 30, and a cathode layer 40. The substrate 10 has a display area AA and a non-display area NA surrounding the display area AA; the metal transfer layer 20 is disposed on the substrate 10 and located in the non-display area NA; the pixel definition layer 30 is disposed on a side of the metal transfer layer 20 away from the substrate 10. The pixel definition layer 30 includes a plurality of spaced dams, and the metal transfer layer 20 is located between two adjacent dams. Among them, the distance between two adjacent dams in the non-display area NA is greater than the distance between two adjacent dams in the display area AA; the cathode layer 40 covers the metal transfer layer 20 and the pixel definition layer 30. This array substrate can reduce the lap impedance between the metal transfer layer 20 and the cathode layer 40 and improve the current resistance of the panel.

[0056] The above has introduced in detail an array substrate and a display panel provided by the embodiments of the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. An array substrate, characterized in that, Comprising: A substrate, the substrate having a display area and a non-display area surrounding the display area; A metal transfer layer, the metal transfer layer being disposed on the substrate and located in the non-display area; A pixel definition layer, the pixel definition layer being disposed on a side of the metal transfer layer away from the substrate, the pixel definition layer including a plurality of spaced dams, the metal transfer layer being located between two adjacent dams, wherein a spacing between two adjacent dams in the non-display area is greater than a spacing between two adjacent dams in the display area; A cathode layer, the cathode layer covering the metal transfer layer and the pixel definition layer; The array substrate further includes a power supply trace layer and a passivation layer, the power supply trace layer being disposed on the substrate and located in the non-display area; the passivation layer being disposed on a side of the power supply trace layer away from the substrate and located in the non-display area, a first via hole being provided on the passivation layer, and the metal transfer layer covering the first via hole; In the non-display area, the array substrate further includes a data trace layer, a buffer layer, and an interlayer dielectric layer, the data trace layer being disposed on the substrate and located between two adjacent dams, the buffer layer being disposed on a side of the data trace layer away from the substrate, the interlayer dielectric layer being disposed on a side of the buffer layer away from the substrate, and the power supply trace layer being disposed on a side of the interlayer dielectric layer away from the substrate; A plurality of second via holes are further provided on the power supply trace layer, the data trace layer includes a plurality of data signal lines arranged at intervals in a first direction, and a positive projection of the second via hole on the substrate at least partially overlaps a positive projection of the data signal line on the substrate.

2. The array substrate according to claim 1, wherein The plurality of second via holes are arranged at intervals in a second direction, and a positive projection of the second via hole on the substrate at least partially overlaps positive projections of the plurality of data signal lines on the substrate.

3. The array substrate according to claim 2, wherein, A cross-sectional width of the first via hole extending in the first direction is greater than or equal to a cross-sectional width of the second via hole extending in the first direction.

4. The array substrate according to claim 1, characterized in that, The plurality of second via holes are arranged at intervals in the first direction, and a positive projection of the second via hole on the substrate at least partially overlaps a positive projection of the data signal line on the substrate.

5. The array substrate according to claim 4, wherein A cross-sectional length of the first via hole extending in the second direction is greater than or equal to a cross-sectional length of the second via hole extending in the second direction.

6. The array substrate according to claim 1, wherein The plurality of second via holes are arranged in an array, and a cross-sectional area of the first via hole is greater than a sum of cross-sectional areas of the plurality of second via holes.

7. A display panel, characterized in that, Including the array substrate according to any one of claims 1-6.

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