Field plate structure for GaN high voltage transistors

Abstract

Field plate structures for gallium nitride (GaN) high voltage transistors are disclosed. In one aspect, a transistor includes a GaN substrate, a source region formed on the GaN substrate, a drain region formed on the GaN substrate and separated from the source region, a gate region formed between the source region and the drain region, a pedestal formed on the GaN substrate and positioned between the gate region and the drain region, and a field plate electrically coupled to the source region, wherein the field plate extends from a proximal region positioned between the source region and the pedestal toward the drain region, wherein at least a portion of the field plate overlaps at least a portion of the pedestal.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 195,652, “Field Plate for GaN High Voltage Transistors,” filed June 1, 2021, the entirety of which is incorporated herein by reference for all purposes. TECHNICAL FIELD

[0003] The described embodiments relate generally to high voltage transistors, and more specifically, embodiments of the invention relate to field plates for gallium nitride (GaN) high voltage transistors. BACKGROUND

[0004] In semiconductor technology, gallium nitride (GaN) is a compound semiconductor material used to form various devices such as high power and / or high voltage transistors. These devices can be formed by growing epitaxial layers on silicon, silicon carbide, sapphire, gallium nitride, or other substrates. Often, heteroepitaxial junctions of aluminum gallium nitride (AlGaN) and GaN are used to form these devices. This structure is known to form a high electron mobility two-dimensional electron gas (2DEG) at the interface of the two materials. High voltage GaN transistors can utilize a field plate to increase their operating voltage. In many applications, it can be desirable to control the strength of the electric field in a high voltage transistor. SUMMARY

[0005] In some embodiments, a transistor is disclosed. The transistor includes a gallium nitride (GaN) substrate, a source region formed on the GaN substrate, a drain region formed on the GaN substrate and separated from the source region, a gate region formed between the source region and the drain region, a pedestal formed on the GaN substrate and positioned between the gate region and the drain region, and a field plate electrically coupled to the source region, wherein the field plate extends from a proximal region positioned between the source region and the pedestal toward the drain region, wherein at least a portion of the field plate overlaps at least a portion of the pedestal.

[0006] In some embodiments, the transistor further includes a dielectric layer extending across at least a portion of the GaN substrate and across at least a portion of the pedestal, wherein the dielectric layer is positioned between the pedestal and the field plate.

[0007] In some embodiments, the proximal region of the field plate is separated from the GaN substrate by a thickness of the dielectric layer, and the distal region of the field plate is separated from the GaN substrate by the thickness of the dielectric layer and a thickness of the pedestal.

[0008] In some embodiments, a ratio of a distance between a distal region of the field plate and the GaN substrate to a distance between a proximal region of the field plate and the GaN substrate is between 1.05 and 10.0.

[0009] In some embodiments, the pedestal is a first pedestal of a plurality of pedestals.

[0010] In some embodiments, each pedestal of the plurality of pedestals is formed in a shape of an island.

[0011] In some embodiments, the pedestal is formed of a P-type GaN layer.

[0012] In some embodiments, the pedestal is formed of a dielectric layer.

[0013] In some embodiments, the dielectric layer comprises silicon nitride.

[0014] In some embodiments, a portion of the field plate is formed at an angle relative to the GaN substrate.

[0015] In some embodiments, a value of the angle is determined by a ratio of a distance between a distal region of the field plate and the GaN substrate to a distance between a proximal region of the field plate and the GaN substrate.

[0016] In some embodiments, the value of the angle is between 5 and 175 degrees.

[0017] In some embodiments, a transistor is disclosed. The transistor includes a substrate; a source region formed on the substrate; a drain region formed on the substrate and separated from the source region; a gate region formed between the source region and the drain region; a pedestal formed on the substrate and positioned between the gate region and the drain region; a field plate electrically coupled to the source region, the field plate extending across a portion of the substrate and across at least a portion of the pedestal toward the drain region; and a dielectric layer extending across at least a portion of the substrate and extending across at least a portion of the pedestal, the dielectric layer positioned between the pedestal and the field plate.

[0018] In some embodiments, a proximal region of the field plate is separated from the substrate by a thickness of the dielectric layer, and wherein a distal region of the field plate is separated from the substrate by the thickness of the dielectric layer and a thickness of the pedestal.

[0019] In some embodiments, a ratio of a distance between a distal region of the field plate and the substrate to a distance between a proximal region of the field plate and the substrate is between 1.02 and 10.0.

[0020] In some embodiments, the transistor further includes two or more pedestals.

[0021] In some embodiments, the pedestal is formed in a shape of an island.

[0022] In some embodiments, a portion of the field plate is shaped at an angle relative to the GaN substrate.

[0023] In some embodiments, the value of the angle is determined by a ratio of a distance between a distal region of the field plate and the substrate to a distance between a proximal region of the field plate and the substrate.

[0024] In some embodiments, the value of the angle is between 5 and 175 degrees. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1A shows a cross-sectional view of a GaN transistor having a field plate structure with a pedestal according to embodiments of the disclosure;

[0026] Figure 1B is a plot showing an electric field as a function of a gate-to-drain distance of a GaN transistor; Figure 1A

[0027] Figure 2 shows a cross-sectional view of a GaN transistor having a field plate structure according to embodiments of the disclosure;

[0028] Figure 3A shows a cross-sectional view of a GaN transistor having a field plate structure using a dielectric layer according to embodiments of the disclosure;

[0029] Figure 3B shows a cross-sectional view of a GaN transistor having a field plate structure using a dielectric layer according to embodiments of the disclosure;

[0030] Figure 3C shows a cross-sectional view of a GaN transistor having a field plate structure using a dielectric layer according to embodiments of the disclosure;

[0031] Figure 4 shows a plan view of a GaN transistor according to embodiments of the disclosure;

[0032] Figure 5A shows a plan view of a GaN transistor having a field plate structure according to embodiments of the disclosure;

[0033] Figure 5B shows a cross-sectional view of a pedestal island in Figure 5A

[0034] Figure 6A shows a cross-sectional view of a GaN transistor having multiple pedestals and having additional layers for adjusting thickness of the pedestals according to embodiments of the disclosure; and

[0035] Figures 6B-6F shows a cross-sectional view of a GaN transistor having a field plate structure according to embodiments of the disclosure; Figure 6A ​​variations of GaN transistors in which additional layers can be patterned in various locations. DETAILED DESCRIPTION

[0036] The structures and related technology disclosed herein generally relate to lateral transistors. More specifically, the devices, structures, and related technology disclosed herein relate to gallium nitride (GaN) high voltage lateral transistors in which a field plate structure can be utilized to reduce peak electric fields, thereby improving the reliability of the transistor. In lateral high voltage transistors, it is advantageous to reduce the electric field, particularly at the field plate edge. The reduced electric field can allow for the use of a relatively smaller high voltage lateral transistor, thereby reducing die size and saving system cost. In addition, the reduced electric field can improve the reliability of the lateral high voltage transistor and extend the operational life of the high voltage transistor. Embodiments of the present disclosure can tailor the structure of the field plate such that the distance of the field plate to the substrate can be increased, thereby reducing the electric field within the substrate.

[0037] In some embodiments, various layers can be formed in the shape of pedestals and positioned under the field plate edge in order to increase the distance between the field plate to the substrate, thereby reducing the electric field in the substrate. These layers can include, but are not limited to, GaN layers, such as P-type GaN layers, or any suitable dielectric, such as silicon nitride or silicon oxide, or any other suitable material. In various embodiments, the tailored field plate structure can enable a reduction in the size of GaN high voltage transistors and / or enable a relatively higher operational voltage for GaN high voltage transistors in the same die area. Various inventive embodiments are described herein, including methods, processes, systems, devices, etc.

[0038] A number of illustrative embodiments will now be described with respect to the drawings, which form a part of this disclosure. The following description provides exemplary embodiments and is not meant to limit the scope or applicability of the disclosure. Rather, the following description will provide those skilled in the art with an enabling description of the illustrative embodiments. Embodiments can be used in a variety of applications including, for example, those described herein. It is to be understood that the functionality and layout of the elements can be varied and that various changes can be made without departing from the spirit and scope of the present disclosure. In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the particular embodiments. However, it will be apparent to one skilled in the art that the various embodiments can be practiced without these specific details. The drawings and description are not intended to be restrictive in nature. The use of the term "example" or "exemplary" herein to refer to an embodiment or a design does not necessarily mean that the embodiment or design is preferred or advantageous over other embodiments or designs.

[0039] Figure 1A A cross-sectional view of a GaN transistor 100A having a field plate structure in accordance with embodiments of the present disclosure is shown. Figure 1BA plot 100B is shown illustrating the electric field within the transistor 100A as a function of distance from the gate region 104 to the drain 112. As shown Figure 1A The GaN transistor 100A can include a source region 102, a gate region 104, and a drain region 112, as shown Figure 1B A plot 100B is shown illustrating the electric field within the transistor 100A as a function of distance from the gate region 104 to the drain 112. As shown Figure 1B The first electric field 116 includes the pedestal 108 and exhibits a much lower peak at the distal region 129 of the field plate 106 than the second electric field 118 of a transistor without a pedestal.

[0040] In some embodiments, the gate region 104 can be an electrode formed across a P-type GaN layer and can form an ohmic contact with the P-type GaN layer. In various embodiments, the gate region can be formed from a P-type GaN layer that forms a Schottky contact with the substrate. In some embodiments, a direct Schottky gate can be used to form the gate region. The gate region 104 can be formed between the source region 102 and the drain region 112. The transistor structure can be fabricated on a substrate 114. In some embodiments, the transistor 100A can be formed on a substrate that can include gallium nitride, gallium nitride on silicon, silicon carbide, gallium arsenide, indium phosphide, or any other suitable semiconductor material.

[0041] In some embodiments, the transistor 100A can include a GaN-based substrate 114, a source region 102 formed on the substrate, a drain region 112 formed on the substrate and separated from the source region, a gate region 104 formed between the source region and the drain region, a pedestal 108 formed on the substrate and positioned between the gate region and the drain region, and a field plate 106 electrically coupled to the source region, the field plate extending from a proximal region positioned between the source region and the pedestal toward the drain region, wherein at least a portion of the field plate overlaps at least a portion of the pedestal.

[0042] In various embodiments, the substrate can include a first layer, which can include silicon, silicon carbide, sapphire, aluminum nitride, or other materials. A second layer can be disposed on the first layer and can include gallium nitride or other materials. A third layer can be disposed on the second layer and can include, for example, but not limited to, a composite stack of other Group III nitrides such as aluminum nitride, indium nitride, and the like, as well as Group III nitride alloys such as aluminum gallium nitride and indium gallium nitride. In some embodiments, the third layer can be Al 0.20 Ga 0.80N. In various embodiments, a two-dimensional electron gas (2DEG) can be formed at the interface of the second layer and the third layer. In some embodiments, the third layer can include a thin boundary layer with a high Al content and a relatively thicker layer with less Al content. In various embodiments, the third layer can have a GaN top cap layer, while in other embodiments, the third layer can not have a GaN top cap layer.

[0043] In some embodiments, GaN transistor 100A can be a relatively high voltage lateral transistor that can include a field plate 106. For example, GaN transistor 100A can have a working voltage of 600 V or more. In some embodiments, GaN transistor 100A can have a working voltage of 5 V to 100 V, while in other embodiments, GaN transistor 100A can have a working voltage of 150 V to 800 V. Field plate 106 can be positioned between gate region 104 and drain region 112. In some embodiments, a dielectric layer 110 can be positioned between field plate 106 and substrate 114. Dielectric layer 110 can be formed of silicon nitride (SiN), silicon oxide (Si02), or other suitable material. In various embodiments, a pedestal structure 108 can be added to transistor 100A below a distal region 129 of the field plate, with a proximal region 121 of field plate 106 electrically coupled to source region 102. Field plate 106 can extend across at least a portion of pedestal 108. In some embodiments, field plate 106 can extend across pedestal 108 from beginning to end. In various embodiments, the field plate can extend across 75% of pedestal 108, while in other embodiments, it can extend across 50% of pedestal 108, while in other embodiments, it can extend less than 50% across pedestal 108.

[0044] Proximal region 121 of field plate 106 can be separated from substrate 114 by a thickness of dielectric layer 122, and distal region 129 of the field plate can be separated from the substrate by the thickness of dielectric layer 122 and the thickness 124 of pedestal 108. Thus, a portion of field plate 106 beginning at location 128 can be angled at angle 126, such that the distance between field plate 106 and substrate 114 increases in the direction of distal region 125 of the field plate. The increase in separation between field plate 106 and substrate 114 in distal region 125 can result in a decrease in electric field (see, e.g., FIG. 2B). Figure 1BThe width 127 of the pedestal 108 may, for example, be between 1.0 um and 2.0 um. In some embodiments, the width 127 of the pedestal can be between 0.6 um and 0.8 um, while in other embodiments, the width can be between 0.5 um and 1.0 um, and in various embodiments, the width can be between 0.1 um and 5.0 um. The thickness 124 of the pedestal 108 may, for example, be between 50 nm and 100 nm. In some embodiments, the thickness 124 can be between 60 nm and 80 nm, while in other embodiments, the thickness can be between 30 nm and 200 nm, and in various embodiments, the thickness can be between 10 and 500 nm. In some embodiments, the ratio of the distance between the distal region 129 of the field plate 106 and the substrate 114 to the distance between the proximal region 121 of the field plate and the substrate can be between 1.1 and 3.0, while in other embodiments, the ratio can be between 1.05 and 5.0, and in various embodiments, the ratio can be between 1.01 and 10.0. As will be appreciated by one of ordinary skill in the art having the benefit of the instant disclosure, the width and thickness of the pedestal, as well as the ratio of the distance between the distal region of the field plate and the substrate to the distance between the proximal region of the field plate and the substrate can be set to any suitable value. Furthermore, as will be appreciated by one of ordinary skill in the art, the disclosed field plate structure can have one or more pedestals, pedestals of different sizes, and other characteristics that can differ from those described herein. Furthermore, as will be appreciated by one of ordinary skill in the art, the dielectric layer can be comprised of one or more dielectric layers.

[0045] The pedestal 108 can cause the field plate 106 to form an angled shape from the proximal region 121 to the distal region 125. In some embodiments, the angle 126 between the proximal region 121 and the distal region 125 can have a value of, for example, between 20 and 60 degrees, while in other embodiments, the value of the angle can be between 10 and 70 degrees, and in various embodiments, the value can be between 5 degrees and 85 degrees. As will be appreciated by one of ordinary skill in the art having the benefit of the instant disclosure, the value of the angle 126 can be set to any suitable value by setting the value of the thickness 124 of the pedestal 108.

[0046] A reduction in the peak of the second electric field 118 can improve the characteristics of the GaN transistor 100A, such as increasing reliability, increasing operating voltage, and / or reducing transistor size. In some embodiments, the reduction in the second electric field 118 can result from an increase in the separation between the distal region 125 of the field plate 106 and the substrate 114. In various embodiments, by changing the fabrication process of the transistor 100A, the thickness of the dielectric 110 under the field plate 106 can be increased in the distal region compared to the proximal region 121. At location 128, the value of the first electric field 116 can increase slightly relative to the second electric field 118 due to the accumulation of the peak electric field of the field plate at the end region near the substrate 114, however, the total peak of the first electric field is reduced with the addition of the pedestal 108 because the electric field is also spread along the distal region 125.

[0047] As described above, the use of a field plate 106 with a pedestal 108 can be able to reduce the electric field, thereby improving the performance of the transistor over time, improving reliability, and / or reducing the size of the transistor. In some embodiments, the field plate structure 106 with a pedestal 108 can achieve a higher operating voltage of the transistor in the same area as a transistor without a pedestal. In various embodiments, the pedestal 108 can be formed of, for example, but not limited to, P-type gallium nitride, by any suitable dielectric such as silicon nitride or silicon oxide, or by any other suitable material. In various embodiments, the pedestal 108 can be formed of, for example, a suitable semiconductor or dielectric or non-conductive material.

[0048] In some embodiments, the value of the angle 126 can contribute to the peak electric field distribution along the active region. A relatively smaller angle can reduce the first peak electric field at location 128 and increase the second peak electric field at the distal region 129. A relatively larger angle can increase the first peak electric field at location 128 and reduce the second peak electric field at the distal region 129. For all angle values, the highest electric field is lower than that of a transistor without a pedestal. The value of the angle 126 can be determined by the conformal deposition of the dielectric layer and by the thickness of the pedestal layer and the subsequent thickness of the dielectric layer.

[0049] Figure 2A cross-sectional view of a GaN transistor 200 having a field plate structure according to embodiments of the present disclosure is shown. GaN transistor 200 is similar to GaN transistor 100A, however, GaN transistor 200 can have multiple field plates. In this embodiment, GaN transistor 200 can include a first field plate 206 shaped by a pedestal 208, and can include a second field plate 220 shaped by a respective pedestal 222. As will be appreciated by one of ordinary skill in the art having the benefit of the present disclosure, transistor 200 can have a third field plate (not shown) or a fourth field plate (not shown) or up to an nth field plate with respective pedestal structures (not shown). In some embodiments, first field plate 206 can be electrically coupled to gate 211, while second field plate 220 can be electrically coupled to source 207 of transistor 200. First field plate 206 can be connected to gate 211 to reduce the capacitance between gate 211 and drain 215. In various embodiments, multiple pedestals can be added to the multiple field plate structures in the disclosed lateral high voltage GaN transistors to reduce the electric field, to increase the reliability, to increase the operating voltage, and / or to reduce the transistor size, as described above. GaN transistor 200 can further include a dielectric layer 240 disposed on pedestals 208 and 222, a dielectric layer 242 disposed on first plate 206, and a dielectric layer 244 disposed on second field plate 220.

[0050] In some embodiments, the pedestals (208 and 222) can be fabricated from, for example, but not limited to, gallium nitride of the P-type, or from a dielectric such as silicon nitride or silicon oxide, or from any other suitable material. In various embodiments, the pedestals (208 and 222) can be formed from, for example, a conductive or non-conductive material. The width 227 of the pedestal 208 can be in a range of, for example, 1.0 um to 2.0 um. In some embodiments, the width of the pedestal can be between 0.6 um and 0.8 um, while in other embodiments, the width can be between 0.5 um and 1.0 um, and in various embodiments, the width can be between 0.1 um and 5.0 um. The thickness 224 of the pedestal can be, for example, 50 nm to 100 nm. In some embodiments, the thickness can be between 60 nm and 80 nm, while in other embodiments, the thickness can be between 30 nm and 200 nm, and in various embodiments, the thickness can be between 10 and 500 nm. As will be appreciated by one of ordinary skill in the art having access to the present disclosure, the width and thickness of the pedestal can be set to any suitable value. Moreover, as will be appreciated by one of ordinary skill in the art, the disclosed field plate structure can have a smaller or larger number of pedestals, different sizes of pedestals, and other characteristics that can differ from those described herein. The width 217 of the pedestal 222 can be in a range of, for example, 1.0 um to 2.0 um. In some embodiments, the width of the pedestal can be between 0.6 um and 0.8 um, while in other embodiments, the width can be between 0.5 um and 1.0 um, and in various embodiments, the width can be between 0.1 um and 5.0 um. The thickness 214 of the pedestal can be, for example, 50 nm to 100 nm. In some embodiments, the thickness can be between 60 nm and 80 nm, while in other embodiments, the thickness can be between 30 nm and 200 nm, and in various embodiments, the thickness can be between 10 and 500 nm. As will be appreciated by one of ordinary skill in the art having access to the present disclosure, the width and thickness of the pedestal can be set to any suitable value. Moreover, as will be appreciated by one of ordinary skill in the art, the disclosed field plate structure can have a smaller or larger number of pedestals, different sizes of pedestals, and other characteristics that can differ from those described herein.

[0051] Figure 3A A cross-section of a GaN transistor 300A similar to the transistor 100A shown in Figure 1A However, the transistor 300A has a plurality of pedestals formed at a first dielectric layer 340. As Figure 3AThe transistor 300A can include a plurality of pedestals 306a, 306b formed by the first dielectric layer 340 positioned between the gate and the drain of the transistor, as shown. A second dielectric layer 308 can be positioned on top of the pedestals, and a first field plate 310 can be disposed on top of the second dielectric layer. A third dielectric layer 314 can be positioned on top of the second dielectric layer, and a second field plate 312 can be disposed on top of the second dielectric layer. The second field plate can be electrically coupled to the source 342. In some embodiments, a plurality of field plates can be utilized to fine tune the electric field in the drift region 345 of a GaN transistor as shown. Figure 1B In various embodiments, the pedestals can be formed of a dielectric, such as silicon nitride or silicon oxide, or of any other suitable material.

[0052] Figure 3B A cross-section of a GaN transistor 300B similar to the transistor 100A shown in Figure 1A However, the transistor 300B has a plurality of pedestals formed at the second dielectric layer 350. As shown in Figure 3B The transistor can include a plurality of pedestals 316a and 316b formed by the second dielectric layer 350 positioned between the gate and the drain of the transistor, as shown in. In the transistor 300B, a third dielectric layer 318 can be positioned on the pedestals 316a and 316b, as well as on a first field plate 309. A fourth dielectric layer 315 can be positioned on the third dielectric layer 318, as well as on a second field plate 311. In various embodiments, a plurality of field plates can be utilized to fine tune the electric field in the drift region of a GaN transistor as shown. Figure 1B The plurality of field plates can be electrically coupled to the source 355. In some embodiments, the pedestals can be formed of a dielectric, such as silicon nitride or silicon oxide, or of any other suitable material. In various embodiments, the pedestals can be formed of a conductive or non-conductive material. In some embodiments, the pedestals can be formed of GaN and / or AlGaN.

[0053] Figure 3C A cross-section of a GaN transistor 300C similar to the transistor 300B is shown, however, the transistor 300C can have a plurality of pedestals that can be formed at various dielectric layers. As shown in Figure 3CThe transistor 300C can include a plurality of pedestals 326a, 326b positioned between the gate and the drain that can be formed at any dielectric layer, as shown. For example, the pedestal 326a can be formed at the dielectric layer 340, while the pedestal 326b can be formed at the dielectric layer 358. This technique can be extended to any dielectric layer and various other dielectric layers up to the nth layer, as appreciated by one of ordinary skill in the art having the benefit of the disclosure. The nth dielectric layer 328 can be positioned on the pedestals as well as the nth field plate 359. The nth field plate and / or a plurality of field plates can be electrically coupled to the source 357. The transistor 300C can include the dielectric layers 338 and 348. In some embodiments, a plurality of field plates can be utilized to fine tune the electric field in the drift region of a GaN transistor as shown. Figure 1B In various embodiments, the pedestals can be formed of a dielectric, such as silicon nitride or silicon oxide, or any other suitable material.

[0054] Figure 4 A plan view of a GaN transistor 400 similar to the transistor 100A shown in FIG. 1 is shown, according to an embodiment of the disclosure. The transistor 400 can include a substrate 414, a source region 402, a gate region 404, and a drain region 412. The transistor 400 can further include a field plate 406 and a pedestal 408. The pedestal can have a rectangular shape and can be positioned at the edge of the field plate. The use of the pedestal can reduce the electric field and improve transistor performance, as discussed in detail above in Figure 1A In various embodiments, the pedestal 408 can be formed of, for example, but not limited to, P-type gallium nitride, or a dielectric, such as silicon nitride or silicon oxide, or any other suitable material. In various embodiments, the pedestal can be formed of, for example, a conductive or non-conductive material.

[0055] Figure 5A A plan view of a GaN transistor 500A similar to the transistor 400 shown in Figure 4 FIG. 1 is shown, according to an embodiment of the disclosure. The transistor 500A is similar to the transistor 400, however, the pedestal 508 can be in the shape of individual islands. The island configuration can include any of the features, aspects, or materials previously described, and can be included in any of the transistor structures discussed above. More specifically, any of the pedestal structures described above can be solid, as shown in Figure 4 or divided into islands as shown in Figure 5A FIG. 1.

[0056] The island width 519 can vary, for example, in the range of 0.1 um to 1.0 um. The spacing between individual islands can also vary. As will be appreciated by one of ordinary skill in the art having the benefit of the instant disclosure, the width of the base islands and the spacing therebetween can be set to any suitable value to adjust the strength of the electric field, as described in greater detail below. Further, as will be appreciated by one of ordinary skill in the art, the disclosed field plate structure can have a smaller or larger number of bases, different sizes of bases, and other characteristics that can differ from those described herein.

[0057] Figure 5B A cross-sectional 5B-5B view 500B of the base islands of 500A is shown. As Figure 5B shown, as the spacing between the base islands 518 increases, a recessed dielectric layer 520 can be formed. As the spacing between the base islands decreases, a protruding dielectric layer 522 can be formed due to, for example, a deposition fabrication process. A field plate extending above the dielectric layer can follow the contours of the dielectric layer, imparting recesses or protrusions thereto, where the recesses can decrease the distance between the field plate and the substrate, and where the protrusions can increase the distance between the field plate and the substrate. This method can be utilized to shape the dielectric layer and configure the field plate to a desirable shape in order to optimize the electric field and improve transistor performance. As will be appreciated by one of ordinary skill in the art having the benefit of the instant disclosure, the spacing of the base islands can be set to any suitable value in order to achieve an optimized shape of the field plate, thereby reducing the peak electric field at the edges of the field plate.

[0058] Figure 6AA cross-sectional view of an embodiment of a GaN transistor 600A having multiple pedestals and having an additional layer for adjusting the thickness of the pedestals according to embodiments of the disclosure is shown. GaN transistor 600A is similar to GaN transistor 200, however, GaN transistor 600A can include an additional layer 640 that can be patterned. Layer 640 is formed of, for example, but not limited to, GaN or AlGaN, or a dielectric such as silicon nitride or silicon oxide, or any other suitable material. In various embodiments, layer 640 can be formed of, for example, a conductive or non-conductive material. Layer 640 can be used to control the shape of the field plate structure by increasing the thickness of the pedestals used in GaN transistor 600A. Each individual pedestal thickness can be controlled by the patterning of layer 640. GaN transistor 600A can include a first field plate 206 shaped by pedestal 208, and can include a second field plate 220 shaped by respective pedestal 222. GaN transistor 600A can further include gate 211, source 207, and drain 215. GaN transistor 600A can be formed on substrate 114. In some embodiments, first field plate 206 can be electrically coupled to gate 211, while second field plate 220 can be electrically coupled to source 207 of the transistor. First field plate 206 can be connected to gate 211 to reduce the capacitance between gate 211 and drain 215. In various embodiments, multiple pedestals can be added to multiple field plate structures in lateral high voltage GaN transistors to reduce the electric field, to increase the reliability, to increase the operating voltage, and / or to reduce the transistor size, as described above.

[0059] In some embodiments, the bases (208 and 222) can be fabricated from, for example, but not limited to, gallium nitride of type P, or a dielectric such as silicon nitride or silicon oxide, or any other suitable material. In various embodiments, the bases (208 and 222) can be formed from, for example, a conductive or non-conductive material. The width 627 of the base 208 can be in a range of, for example, 1.0 um to 2.0 um. In some embodiments, the width of the base can be between 0.6 um and 0.8 um, while in other embodiments, the width can be between 0.5 um and 1.0 um, and in various embodiments, the width can be between 0.1 um and 5.0 um. The thickness 624 of the base can be, for example, 50 nm to 100 nm. In some embodiments, the thickness can be between 60 nm and 80 nm, while in other embodiments, the thickness can be between 30 nm and 200 nm, and in various embodiments, the thickness can be between 10 and 500 nm. As will be appreciated by one of ordinary skill in the art having access to the present disclosure, the width and thickness of the base can be set to any suitable value. Moreover, as will be appreciated by one of ordinary skill in the art, the disclosed field plate structure can have a smaller or larger number of bases, different sizes of bases, and other characteristics that can differ from those described herein. The width 617 of the base 222 can be in a range of, for example, 1.0 um to 2.0 um. In some embodiments, the width of the base can be between 0.6 um and 0.8 um, while in other embodiments, the width can be between 0.5 um and 1.0 um, and in various embodiments, the width can be between 0.1 um and 5.0 um. The thickness 614 of the base can be, for example, 50 nm to 100 nm. In some embodiments, the thickness can be between 60 nm and 80 nm, while in other embodiments, the thickness can be between 30 nm and 200 nm, and in various embodiments, the thickness can be between 10 and 500 nm. The thickness 629 of the layer 640 can be in a range of, for example, 1.0 um to 2.0 um. In some embodiments, the thickness of the layer 640 can be between 0.6 and 0.8 um, while in other embodiments, the thickness can be between 0.5 and 1.0 um, and in various embodiments, the width can be between 0.1 and 5.0 um. As will be appreciated by one of ordinary skill in the art having access to the present disclosure, the width and thickness of the base can be set to any suitable value. Moreover, as will be appreciated by one of ordinary skill in the art, the disclosed field plate structure can have a smaller or larger number of bases, different sizes of bases, and other characteristics that can differ from those described herein.

[0060] Figures 6B-6FSeveral variations of GaN transistor 600A are shown, in accordance with embodiments of the disclosure, in which layer 640 can be patterned in various locations. Layer 640 can be used to control the shape of the field plate structure by increasing the thickness of the pedestals in GaN transistor 600A. Each individual pedestal thickness can be controlled by the patterning of layer 640. Figure 6B An embodiment is shown in which layer 640 has been removed from pedestal 222, but remains on pedestal 208. In this way, the thickness of each individual pedestal can be controlled. Figure 6B In this embodiment, layer 640 remains in the region proximal to gate 211 and source 207. Figure 6C An embodiment is shown in which layer 640 remains on pedestal 222, and in which layer 640 has been removed from pedestal 208. Figure 6C In this embodiment, layer 640 remains in the region proximal to the drain. Figure 6D An embodiment is shown in which layer 640 has been removed in all regions, but remains on pedestals 208 and 222. Figure 6E An embodiment is shown in which layer 640 has been removed in all regions, but remains on pedestal 222. Figure 6F An embodiment is shown in which layer 640 has been removed in all regions, but remains on pedestal 208. Other combinations of regions with layer 640 and regions without layer 640 are possible, and are within the scope of the disclosure.

[0061] Although the field plate structure of a GaN transistor (see FIG. 1) is described and shown in one particular configuration of a GaN high voltage transistor, embodiments of the disclosure are suitable for use with other configurations of GaN transistors and non-GaN transistors. For example, any semiconductor device can be used with embodiments of the disclosure. In some instances, embodiments of the disclosure are particularly suitable for use with silicon and other compound semiconductor high voltage transistors.

[0062] For simplicity, various internal components, such as details of the substrate, various dielectric and metal layers, contacts, other components of GaN transistor 100A (see FIG. 1) are not shown in the figures.

[0063] In the foregoing specification, embodiments of the disclosure have been described with reference to numerous specific details that can vary from implementation to implementation. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. The sole and exclusive indicator of the scope of the disclosure, and what is intended by the applicants to be the scope of the disclosure, is the literal and equivalent scope of the claims that issue from this application, in whatever form it can be issued, including any subsequent correction. Specific details can be combined in any suitable manner without departing from the spirit and scope of the disclosure.

[0064] Furthermore, spatially relative terms such as “bottom” or “top” may be used to describe the relationship of an element and / or feature to another element(s) and / or feature, as illustrated in the figures. It should be understood that, in addition to the orientation depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use and / or operation. For example, if the device in the figures is flipped, an element described as the “bottom” face may be oriented “above” other elements or features. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein shall be interpreted accordingly.

[0065] As used herein, the terms “and,” “or,” and “one / or” can have a variety of meanings, which are expected to depend at least in part on the context in which such terms are used. Generally, “or,” when used to relate a list such as, for example, A, B, or C, implies A, B, and C, used here in an inclusive sense, and A, B, or C, used here in an exclusive sense. Additionally, the term “one or more,” as used herein, can be used to describe any feature, structure, or property in the singular, or to describe some combination of features, structures, or properties. However, it should be noted that this is merely an illustrative example, and the subject matter claimed is not limited to this example. Furthermore, if the term “at least one of” is used to relate a list (e.g., A, B, or C), it can be interpreted as referring to any combination of A, B, and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

[0066] Throughout this specification, references to “an example,” “an instance,” “some instances,” or “exemplary embodiments” imply that a particular feature, structure, or characteristic described with respect to a feature and / or instance may be included in at least one feature and / or instance of the claimed subject matter. Therefore, the appearance of the phrases “in an example,” “an instance,” “in some instances,” or “in some embodiments,” or other similar phrases throughout this specification, does not necessarily refer to the same feature, instance, and / or limitation. Furthermore, a particular feature, structure, or characteristic may be combined in one or more instances and / or features.

[0067] In the preceding detailed description, numerous specific details have been set forth to provide a thorough understanding of the claimed subject matter. However, those skilled in the art will understand that the claimed subject matter can be practiced without these specific details. In other instances, methods and apparatus originally known to a person of ordinary skill have not been described in detail so as not to obscure the claimed subject matter. Therefore, it is intended that the claimed subject matter be limited to the specific instances disclosed, but rather that such claimed subject matter may also encompass all aspects falling within the scope of the appended claims and their equivalents.

Claims

1. A transistor comprising: Gallium nitride (GaN) substrate; The source region is formed on the GaN substrate; The drain region is formed on the GaN substrate and is separated from the source region; A gate region is formed between the source region and the drain region; A base formed on the GaN substrate and positioned between the gate region and the drain region, wherein the base is not located between the gate region and the source region; and A field plate electrically connected to the source region, the field plate extending from a proximal region located between the source region and the base toward the drain region, wherein the starting position of the field plate is disposed between the gate region and the base, and the starting position of the field plate is separated from the GaN substrate by the thickness of a dielectric layer, the dielectric layer extending across at least a portion of the GaN substrate and at least a portion of the base, wherein a portion of the field plate is tilted at an angle such that the distance between the field plate and the GaN substrate increases in the direction of the distal region of the field plate, wherein the dielectric layer is located between the base and the field plate, and wherein at least a portion of the field plate overlaps at least a portion of the base.

2. The transistor of claim 1, wherein the near-side region of the field plate separates the thickness of the dielectric layer from the GaN substrate, and wherein the far-side region of the field plate separates the thickness of the dielectric layer and the thickness of the base from the GaN substrate.

3. The transistor of claim 2, wherein the ratio of the distance between the distal region of the field plate and the GaN substrate to the distance between the proximal region of the field plate and the GaN substrate is between 1.05 and 10.

0.

4. The transistor of claim 1, wherein the base is a first base of a plurality of bases.

5. The transistor of claim 4, wherein each of the plurality of bases is formed in the shape of an island.

6. The transistor of claim 1, wherein the base is formed of a P-type GaN layer.

7. The transistor of claim 1, wherein the base is formed of the dielectric layer.

8. The transistor of claim 7, wherein the dielectric layer comprises silicon nitride.

9. The transistor of claim 1, wherein the value of the angle is determined by the ratio of the distance between the far side region of the field plate and the GaN substrate to the distance between the near side region of the field plate and the GaN substrate.

10. The transistor of claim 1, wherein the value of the angle is between 5 and 175 degrees.

11. A transistor comprising: Substrate; The source region is formed on the substrate; A drain region is formed on the substrate and is separated from the source region; A gate region is formed between the source region and the drain region; A base formed on the substrate and positioned between the gate region and the drain region, wherein the base is not located between the gate region and the source region; A field plate electrically connected to the source region, the field plate extending across a portion of the substrate and at least a portion of the base toward the drain region; and A dielectric layer extending across at least a portion of the substrate and at least a portion of the base, the dielectric layer being positioned between the base and the field plate, wherein a portion of the field plate is tilted at an angle such that the distance between the field plate and the substrate increases in a direction toward the distal region of the field plate. The starting position of the field plate is located between the gate region and the base, and the starting position of the field plate is separated from the substrate by the thickness of the dielectric layer.

12. The transistor of claim 11, wherein the proximal region of the field plate separates the thickness of the dielectric layer from the substrate, and wherein the distal region of the field plate separates the thickness of the dielectric layer and the thickness of the base from the substrate.

13. The transistor of claim 12, wherein the ratio of the distance between the distal region of the field plate and the substrate to the distance between the proximal region of the field plate and the substrate is between 1.02 and 10.

0.

14. The transistor of claim 11, further comprising two or more bases.

15. The transistor of claim 14, wherein the base is formed in the shape of an island.

16. The transistor of claim 11, wherein the value of the angle is determined by the ratio of the distance between the far side region of the field plate and the substrate to the distance between the near side region of the field plate and the substrate.

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