Memory-enhanced computer crossbar array in neural networks

Abstract

In a method for operating a hardware implementation of a neural network system, a neural network system is provided that includes a controller, a memory, and an interface connecting the controller to the memory, where the controller includes a processing unit configured to execute a neural network and the memory includes a neuromorphic memory device having a crossbar array structure including input lines and output lines interconnected at cross points via electronics. The electronics of the neuromorphic memory device are programmed to incrementally change states by coupling write signals to the input lines based on write instructions received from the controller and write vectors generated by the interface. Data is retrieved from the neuromorphic memory device by coupling read signals to one or more of the input lines of the neuromorphic memory device based on read instructions from the controller and read vectors generated by the interface in accordance with a multiply-accumulate operation.

Description

Background Technology

[0001] This invention generally relates to the field of neural network systems, and more specifically to memory-enhanced neural network systems that use neuromorphic memory devices with a crossbar array structure as external memory.

[0002] Machine learning typically relies on artificial neural networks (ANNs), which are computational models inspired by biological neural networks in the human or animal brain. Such systems learn tasks progressively and autonomously through examples and have been successfully applied to areas such as speech recognition, text processing, and computer vision.

[0003] Neural networks include feedforward neural networks, such as multilayer perceptrons, deep neural networks, and convolutional neural networks. Neural networks are typically implemented in software. However, neural networks can also be implemented in hardware, for example, as resistive processing units (crossbar array structures) or optical neuromorphic systems.

[0004] Various types of hardware systems can be used to execute neural networks. Memory-enhanced neural network systems are particularly advantageous. The basic idea of ​​a memory-enhanced neural network is to enhance a neural network with external memory. Memory-enhanced neural networks (MANNs) benefit from a robust architecture that combines the advantages of neural network data processing and persistent storage. Summary of the Invention

[0005] Embodiments of the present invention disclose a hardware implementation method and a neural network system. A neural network system is provided, including a controller, a memory, and an interface connecting the controller to the memory. The controller includes a processing unit configured to execute a neural network, and the memory includes a neuromorphic memory device having a crossbar array structure, the crossbar array structure including input lines and output lines interconnected at intersections via electronics. The electronics of the neuromorphic memory device are programmed to incrementally change their state based on (i) a write instruction received from the controller, and (ii) a write vector generated by the interface according to the write instruction. Data is retrieved from the neuromorphic memory device according to a multiplication-accumulation operation by coupling a read signal to one or more input lines of the neuromorphic memory device based on (i) a read instruction from the controller, and (ii) a read vector generated by the interface according to the read instruction. Attached Figure Description

[0006] Figure 1 This is a block diagram schematically illustrating selected components of a neural network system according to an embodiment of the present invention.

[0007] Figure 2AThe following is a schematic illustration of an embodiment of the present invention. Figure 1 Memristor crossbar arrays for neuromorphic memory devices in a system.

[0008] Figure 2B The following is a schematic illustration of an embodiment of the present invention. Figure 1 The neuromorphic memory device for a neural network system, wherein the memory device includes a pulse width modulation circuit and a readout circuit.

[0009] Figure 3 This illustrates the operation according to an embodiment of the present invention. Figure 1 A flowchart of the advanced steps of the method for neural network systems.

[0010] Figure 4 This is a flowchart illustrating the sub-steps of a write memory access according to an embodiment of the present invention.

[0011] Figure 5 This is a flowchart illustrating how the electronics of a neuromorphic memory device according to an embodiment of the present invention are programmed to incrementally change the state of the electronics, wherein the incremental value is first accumulated in an additional memory before the accumulated value is written to the electronics.

[0012] Figure 6 The exemplary embodiments shown according to the present invention can be included as Figure 1 A block diagram of the components of a computer system, which is part of a neural network system 1. Detailed Implementation

[0013] Embodiments of the present invention recognize that in conventional neural network systems, information can only be stored in its internal state (e.g., if the network consists of Long-Term Short-Term Memory (LSTM) units, the information must be stored in the state of that unit). Embodiments of the present invention recognize that this has the disadvantage that if new input arrives at the unit, the stored information may be overwritten and can only be retained for a limited amount of time. Embodiments of the present invention also recognize that if the same network is extended with external memory, as in memory-enhanced neural network systems, the network can utilize this memory and use it to retain information for a longer period.

[0014] Memory-enhanced neural networks offer several advantages. Embodiments of this invention utilize neuromorphic devices (e.g., crossbar array structures) as external memory for neural network systems.

[0015] To extend a neural network with external memory, an interface is necessary. This interface may include, for example, read heads and write heads (there may be several read heads and several write heads). The purpose of these heads is to retrieve data from external memory and write information to external memory.

[0016] A controller (also called a controller network) is a unit that includes processing units that execute a neural network. The controller can be thought of as a unit that executes a regular neural network, receiving some input and producing some output. Without external memory, this is equivalent to a standard neural network used to solve any particular task. In an embodiment, the controller is coupled to a feature extraction unit (not shown) for extracting features from input data (e.g., an image), thereby providing the extracted features to the controller for executing the neural network based on these extracted features (whether for training or inference purposes). Any suitable feature extraction scheme can be envisioned, for example, relying on principal component analysis or convolutional neural networks. Other preprocessing entities may be involved if desired. Such preprocessing entities can now be integrated into the controller. Therefore, various architectures can be envisioned for the controller network (e.g., the controller may be essentially designed to execute a simple feedforward neural network or a complex recurrent neural network with multiple layers). For simplicity, the network can be viewed, for example, as a single-layer recurrent LSTM unit.

[0017] Typically, the structure of the read and write heads depends on the type of memory-enhancing neural network system chosen. Many variations are available. The read and write heads can be represented, for example, by shallow neural networks. The read head receives input from the controller. The structure of this input also depends on the type of memory-enhancing neural network. In a simple case, the input to the read head is exactly the same as the input to the controller network itself. Based on this input, the read head generates a read vector w. r It is used to access external memory M[i,j]:

[0018]

[0019] In a very simple case, the input to the read head is passed through a shallow neural network, and the result of this operation forms the read vector w. r More complex read-head architectures exist, such as those involving attention mechanisms. Essentially, the read vector is used to access external memory, regardless of how the read vector is generated. The result *r* (from the memory access) is returned to the controller network, which can then use *r* to generate an output to an initially given input.

[0020] The write head operates in a similar manner to the read head. The write head receives input from the controller network; in simple cases, this input is simply input to the controller network itself. However, unlike the read head, the write head's task is to store information in external memory, not to read information. Essentially, the write head generates a write vector w for writing to memory. wAnd v is used to achieve this. Again, the exact process of how to generate such a vector is specific to the type of memory-enhancing neural network. In a simple case, the input to the head is passed through two shallow neural networks and the result is w. w And v. Then modify the memory contents according to the following formula:

[0021] M[i,j]=M[i,j](1-w w [i]e T [j])+w w [i]v T [j]

[0022] Embodiments of the present invention rely on external memory, such as phase-change memory (PCM) cells, that have a crossbar array structure and use electronics such as memristors. This type of memory device cannot be used as readily as conventional memory (e.g., SRAM or DRAM). It is understood that memristor cells support a specific way of writing to memory; that is, values ​​can be incrementally added to the cell, and if a value needs to be subtracted, the cell can be reset to zero. To address this limitation, embodiments of the present invention propose modifications to the write head. Embodiments of the present invention program the electronics (cells) of the external memory device to incrementally change their state by coupling write signals to the input lines of the external memory based on write instructions from the controller and write vectors generated by the interface according to these write instructions. In a particular embodiment, the write head may maintain the cell's previous state or completely reset the cell's state to zero. Note that this modification is irrelevant to how the write vectors are obtained and can therefore be applied to different types of memory-enhanced neural networks. Embodiments of the invention will be discussed in more detail with reference to the accompanying drawings.

[0023] refer to Figures 1-3 First, one aspect of an embodiment of the present invention is described, relating to a hardware implementation method for operating a neural network system 1 based on received input (S10) and generating output (S30). This method and its variations are collectively referred to as "this method". All references to "Sij(k)" refer to... Figures 3-5 The method steps described in the flowchart rely on a neural network system 1, which further relates to another aspect of embodiments of the invention. Essentially, system 1 includes a controller 10, a memory 30, and an interface 20. The interface 20 connects the controller 10 to the memory 30. The controller 10 includes processing units configured to execute a neural network; therefore, the controller can be considered a controller network. The memory 30 includes a neuromorphic memory device with a crossbar array structure. This structure includes input lines 31 and output lines 32, wherein lines 31 and 32 are interconnected at intersections via electronic devices 33 (e.g., memristor devices).

[0024] In steps S21-S23, the electronics 33 of the neuromorphic storage device 30 are programmed to incrementally change the state of the device 33 (S23). This is achieved by coupling a write signal to one or more input lines 31 of the crossbar array structure 30, generating the write signal based on a write vector generated by the interface 20 (S22), which itself is generated according to a write instruction from the controller 10 (S21).

[0025] When needed, the electronic device 33 can retrieve data S24-S26 from the neuromorphic memory device 30 according to a multiplication-accumulation operation. This is achieved by coupling a read signal to one or more input lines 31 of the neuromorphic memory device 30 based on a read vector generated by the interface 20 in S25, the read vector itself being generated according to a read instruction S24 from the controller 10.

[0026] The processing unit of controller 10 is configured to implement and execute neural networks. Note that the processing unit may be, for example, a general-purpose processing unit (e.g., the central processing unit of a standard computer) or may include analog circuitry. The processing unit may specifically include another neuromorphic device (not shown). However, in the depicted embodiment, the neuromorphic memory device 30 does not form part of the processing unit. Instead, the neuromorphic device 30 is configured to serve as external memory for controller 10 and its processing unit; therefore, the neuromorphic device 30 is used as external memory and should not be confused with other neuromorphic devices that may form part of controller 10 (or write head and read head).

[0027] The neural network system 1 can therefore be considered a memory-enhanced system, wherein the external memory 30 is implemented as a crossbar array structure. The latter is preferably a memristor crossbar structure, which may use low precision (i.e., a single memristor element can be used to represent a memory element).

[0028] However, more generally, each electronic component 33 of the neuromorphic device 30 may include one or more memristor devices. Furthermore, dual output lines (columns) may be included, one for storing positive values ​​and the other for storing negative values, as is common in the art. Several types of memristor devices are contemplated, such as PCM cells, resistive random access memory (RRAM), static random access memory (SRAM) cells, or electrochemical random access memory (ECRAM) cells. In other variations, flash memory cells may be used.

[0029] Interface 20 typically includes multiple read / write heads (24 / 22) that connect controller 10 to memory 30. These heads can be implemented in different ways. They can, in particular, be implemented as shallow neural networks, as discussed later with reference to another aspect of the invention.

[0030] According to this method, the write process is simplified to an incremental write process, eliminating the need to read the contents of external memory 30 before writing (at least for the purpose of programming the cell). As in the embodiments discussed below, only a complete memory reset of the electronics may be required, while incremental writing is implemented separately. That is, programming the electronics 33 causes the state of the device 33 to change incrementally (e.g., changing the conductance of the device 33). The state of the electronics 33 corresponds to certain values ​​that determine data such as that stored on the neuromorphic device 30.

[0031] Note that the incremental write process, as anticipated herein, can significantly involve an incremental programming process, whereby the conductivity state of the electronic device increases in small, constant steps. In variations, the incremental write process relies on iterative programming, thereby programming the electronic device iteratively using multiple pulses. In other variations, the incremental value is accumulated and stored in additional memory 23 before writing such a value, as in the embodiments discussed later.

[0032] Reading from memory is achieved via vector-matrix multiplication, which can be performed in constant time, meaning data can be retrieved during any operating cycle. However, in practice, the read operation will only be performed at specific times (according to a general algorithm running at the controller) and not necessarily in every operating cycle. In all cases, data can be retrieved via a multiplication-accumulation operation parameterized by values ​​corresponding to the state of the electronics 33, so that data can be stored on external memory formed by the neuromorphic device, and such data can be invoked by the controller 10, as required to perform the S20 task supervised by the controller 10.

[0033] Read / write memory accesses are determined by corresponding read / write vectors based on inputs from controller 10, and such vectors can be compared with memory addresses. However, while memory addresses correspond to specific locations in typical hardware memory, here the read / write vectors determine the necessary signals and where to apply them to write to or read from memory 30 based on a given operation (e.g., multiplication-accumulation of a read operation). Note that physical addresses of electronics 33 are also required in this case, as read / write operations require individual access to each electronics 33. Inputs to the crossbar array structure 30 can be implemented, for example, using a digital-to-analog converter (DAC), pulse-width modulation (PWM) circuit 35, or optionally a time-to-spiking method, as discussed in detail later.

[0034] This method offers several advantages. First, memory-enhanced neural network systems such as the one disclosed herein can effectively utilize crossbar structures, where the computational power in the memory allows read and write operations from the memory to be performed in constant time. Second, the proposed method is not limited to memristor technology; other technologies such as flash memory cells can be considered. Third, the proposed write access eliminates the need to read external memory before the write cycle (eliminating the need for partial reset of the memory cell). This makes it fully compatible with known crossbar structures based on memristor devices (e.g., PCM devices). Therefore, the proposed solution allows memory access to be significantly accelerated while reducing energy consumption in memory-enhanced neural networks.

[0035] Although incremental write methods exist, the differentiability of the system can be recovered if necessary by utilizing pseudo-derivatives, as in the embodiments discussed below. As previously mentioned, memory contents can be represented with low precision (e.g., 4 bits are sufficient). This approach allows for efficient implementation of the memory area, as a single electronics element is sufficient for each intersection. However, if desired, the precision of the memory can be improved by using multiple memristor elements at each intersection.

[0036] All of these will now be described in detail with reference to specific embodiments of the invention. Figures 3-4 The programming S21-S23 of the electronic device 33 may further include performing an erase operation (e.g., reset) before incrementally changing the state of one or more of the electronic devices 33. In embodiments of the invention, this erase operation may simply involve completely erasing the electronic device 33 to reset its state; several electronic devices 33 may require this erase operation based on the data to be written to the memory 30, determined by the write vector. In operation, during each write cycle, other electronic devices 33 (typically most such devices) can be simply incremented without resetting the corresponding electronic devices 33; in other words, a binary type of erase operation can be considered, which may completely erase or not erase the values ​​stored on the electronic devices 33, the values ​​corresponding to the states of those devices. To erase a cell, a reset pulse is applied, for example, the amorphization pulse of a PCM cell. For example, when a value needs to be subtracted, it may be necessary to reset the electronic device 33 to zero. Next, an additive term is written to the cell, which is calculated as the final value, i.e., the difference between the initial value and the subtrahend.

[0037] In practice, at least for the purpose of programming electronic device 33 in S21-S23 (i.e., for writing to it), this method can be designed and implemented to prevent any part of electronic device 33 from being erased. That is, the method can be designed to guarantee that no memory read access is required for the purpose of writing to the cell. However, note that the entire algorithm run by controller 10 may require reading data from memory before writing data to memory, depending on variations of the algorithm. However, the basic memory write process can still be designed so that no reading of memory contents (to update memory contents) is required before writing to the cell. In particular, the write vector can be generated by interface 20 in S22 without any memory read access, i.e., data does not need to be retrieved from neuromorphic memory device 30 first, i.e., step S22 itself can be independent of steps S24-S26.

[0038] like Figure 1 As shown in Figure 2, the crossbar array structure 30 of the neural network system 1 can, for example, include N input lines 31 and W output lines 32, where N > 1 and W > 1. In this case, the memory capacity of the neuromorphic memory device 30 is determined by a memory matrix M of dimension N × W. Note that in variations, this method can also be applied to a single input line and / or a single output line. Furthermore, as mentioned earlier, dual output lines may be required.

[0039] In this embodiment, write signals are generated based on two operations using two types of write vectors. The first operation determines the extent of the erase operation (i.e., whether it's a complete reset or no reset at all), while the second operation is performed to incrementally change the state of the electronic device 33, such as... Figure 4 As assumed in the text, if a write vector of the first type implies that a reset S231 is required for a given device 33, then the device is reset S232 before its state is incrementally changed according to the write vector of the second type. Otherwise, if a reset is not required, the state of the device 33 is directly incremented in S233. In other words, the write access is divided into an erase portion and an accumulation portion.

[0040] For example, the first operation could involve multiplying the memory matrix by a binary value vector, where the binary value vector determines the extent of the binary erase operation (i.e., no erase or complete erase), while the second operation involves accumulating terms to incrementally change the state of the electronic device 33, i.e., using two types of vectors, namely, referred to as vector e. T and v T This makes it possible to perform two operations (the sum of operations).

[0041] Furthermore, this programming may also involve vector e T The values ​​of the components are binarized. This can be written as: M[i,j]=M[i,j](1-Ee′) T[j])+Ev T [j], where E∈1 Nx1 And e′[j]∈(0,1) Wx1 Note that e′ represents a binary vector. By binarizing the ordinary vector component e[j], we can obtain the binary vector component e′[j]. ​​The term Ee′ T and Ev T It can be considered a modified write key, which can be generated in different ways depending on the architecture at hand (e.g., differentiable neural computer [DNC], neural Turing machine [NTM], etc.).

[0042] In an embodiment, by using vector e T Binarization is achieved using a Heaviside function that calculates the values ​​of the vector components as shift values. For example, one approach is to use e′[j] = Θ(e[j] - 0.5). In variations, two Heaviside functions, or even comparator circuits, can be used to achieve similar results, as will be understood by those skilled in the art.

[0043] Note that a direct implementation of this method may come at the cost of differentiability, which could impair training (e.g., for supervised learning applications based on backpropagation). Differentiability can still be recovered by relying on pseudo-derivatives, thus restoring the error backpropagation algorithm. For example, an analytical approximation of the Heaviside function, such as Θ(x)≈(1+tanh(kx)) / 2, with a sufficiently large k value, can be considered to produce a derivative. In deformation, for example, it can be used

[0044] Therefore, a simplified write method can be included, wherein either no erasure or a complete erasure is performed before the state of device 33 is incremented, and the memory contents do not need to be read before writing. Furthermore, a thresholding method can be used to recover differentiability (using pseudo-derivatives).

[0045] As described, the general algorithm run by controller 10 may still require reading content from device 30 (rather than writing content to it). Figure 3 As shown, controller 10 retrieves data from neuromorphic memory device 30 according to multiplication-accumulation operations (S24). For example, interface 20 generates read vector w. r (S25) and read vector w r Multiply by the storage matrix M. Similarly, vector w r The read key can be generated in different ways depending on the available architecture. Each read result r is transmitted through a vector w. r It is obtained by multiplying with the storage matrix M, and this operation can be written as In other words, a read access to memory can be formulated as a vector-matrix multiplication, where the memory M is represented by a crossbar array of dimension N×W. Vector w r It can be represented by a digital-to-analog converter (DAC) or a simple PWM circuit 35, which is clearly represented as a crossbar structure 30. In further variations, it can be implemented using time-to-spiking (TTS), as discussed later.

[0046] As mentioned earlier, incremental write methods are incompatible with cumulative programming. For example, refer to... Figure 5 It can be done in a different external memory 30 (see Figure 1 The accumulated value v of the accumulated item is accumulated in the additional memory 23 of the second operation to perform the accumulation item involved in the second operation. Similarly, such an accumulated value is determined by a write vector of the second type. In the operation, after checking the current value v of the given accumulated value (S224): if the accumulated value v exactly exceeds the given threshold v (S225)... T The algorithm then instructs (S226) to incrementally change the state of the given electronic device 33 according to the accumulated value v. Therefore, for smaller values ​​of v, there is a possibility that v is locally accumulated (in the additional memory 23) and applied only in subsequent steps. Figure 5 As shown, the accumulation process can be performed as part of the write vector generation (S22), and then the algorithm is as previously referenced. Figure 4 Continue as explained.

[0047] Note that in this variant, updates can also be applied at a certain granularity during the write process. Such updates may be useful for hardware architectures that only support fixed-size updates, such as PCM devices. In this case, the difference may need to be stored in additional memory 23. This variant may be beneficial for certain types of hardware, such as PCM-based implementations, or any other hardware that only allows the application of pulses with a fixed power corresponding to a fixed increment.

[0048] In a typical application, the processing unit of controller 10 runs algorithm S20, which causes system 1 to interleave steps S21-S23 (electronic device 33) and retrieving data from neuromorphic memory device 30 in steps S24-S26. In operation, this causes the processing unit to execute the neural network multiple times. For example, before executing the neural network, inputs such as those stored on neuromorphic memory device 30 can be fed into the input nodes of the neural network. Executing the neural network results in outputs stored on neuromorphic memory device 30, and so on.

[0049] See again Figure 1Figure 2 illustrates another aspect of the invention, relating to the neural network system 1 itself. As previously described, system 1 includes a controller 10, which itself includes a processing unit. The processing unit is configured to execute the neural network. System 1 also includes a memory 30 (i.e., external memory), which includes neuromorphic memory devices. As described, the neuromorphic memory devices of memory 30 have a crossbar array structure including input lines 31 and output lines 32. These lines are interconnected at the intersections via electronics 33. System 1 also includes an interface 20 that connects the controller 10 to memory 30.

[0050] System 1 is typically configured to program the electronic device 33 to incrementally change its state. This is achieved, as explained with reference to this method, by coupling write signals to one or more input lines 31, which are generated based on write instructions from controller 10 and write vectors generated by interface 20 in operation according to these write instructions. Furthermore, read signals are generated by coupling read signals to one or more of the input lines 31 of the neuromorphic memory device 30, based on read instructions from controller 10 and read vectors generated by interface 20 according to such read instructions, to retrieve data from the neuromorphic memory device 30 according to a multiplication-accumulation operation.

[0051] In an embodiment, system 1 is also configured to perform an erase operation before incrementally changing the state of electronic device 33. As already explained, the erase operation is determined by a write vector, whereby each erase operation may only include: (i) completely erasing one of the electronic devices 33 or (ii) not erasing the electronic device 33 at all. Completely erasing an electronic device resets its state during operation. Even more so, neural network system 1 may be configured to prevent any part of any electronic device 33 from being erased (at least for programming purposes, i.e., written to such electronic device 33) during the operation of the system.

[0052] like Figure 1 As shown in Figure 2, the crossbar array structure typically includes N input lines 31 and W output lines 32, where N > 1 and W > 1. Thus, the memory capacity of the neuromorphic memory device 30 is determined by a memory matrix M of dimension N × W. The contents of the memory can actually be represented with finite precision (e.g., 4 bits), which allows full utilization of the advantages of memristor crossbar implementation.

[0053] As previously mentioned, interface 20 may include a read head 24 connected to input line 31 and output line 32, and a write head 22 connected to input line 31. Various configurations of the read head 24 and write head 22 may be considered as previously mentioned.

[0054] In this embodiment, the crossbar array structure further includes a PWM circuit 35, such as... Figure 2BAs shown. The PWM circuit is used to controllably generate the signals required for writing to and reading from the memory device 30. Both the read head 24 and the write head 22 are connected to the input line 31 via their respective PWM circuits 35. In various variations, the Time-to-Spirit (TTS) method can be used. That is, a low latency TTS integrator can be used, which utilizes the timing of the signal to send information more efficiently.

[0055] The read head 24 is also connected to the output of the crossbar structure to read the result from the multiplication-accumulation operation and return this result to the controller 10. The standard readout circuit 36 ​​can be used to read the output current from the output line 32.

[0056] Interestingly, the read head 24 can be implemented as a module implementing a shallow neural network, for example, a two-layer network. That is, the network can include an input layer and an output layer, with the input nodes of the input layer mapped to the output from the controller 10, and the output nodes of the output layer mapped to the input line 31 of the crossbar array structure. Similarly, the write head 22 can be implemented as a module implementing two shallow neural networks. Each network includes an input layer and an output layer, with the input nodes of the input layer mapped to the output from the controller 10, and the output nodes of the output layer mapped to the input line 31 of the crossbar array structure 30. This allows for the output of two types of write vectors, based on which the system 1 can perform the two operations described above. That is, the first type of operation determines the erase operation, while the second type of operation aims to incrementally change the state of the electronic device 33. Note that the read head / write head (24 / 22) can also be implemented as a neuromorphic device, each with a crossbar array structure. Such a neuromorphic device can be adequately used to implement the shallow networks required to generate read and write signals.

[0057] The above embodiments have been briefly described with reference to the accompanying drawings, and various variations of the above embodiments are possible. Several combinations of the above features can be considered. For example, in one embodiment, the memristor crossbar structure 30 (with PCM cells) is used with an optimized read / write head (24 / 22) to implement external memory for the controller 10 and its processing unit. The controller aims to execute a neural network to train the neural network or to perform inference based on the trained network. Therefore, such a neural network can be enhanced with memory built on the memristor device 33, and the memory contents can be represented with low precision or even with binary values ​​stored in the memristor device. Memory write access is performed using a simplified write method without reading the current contents of the memory array 30 and without partially resetting the memristor device 33.

[0058] This method can be applied, for example, to so-called copy repetition tasks (as used by A. Graves and G. Wayne et al. in Nature 2016, mentioned in the background section). The architecture employed can be, for example, as follows: A recurrent controller network 10 (comprising 10 LSTM units instead of 64 LSTM units) can be used, along with an external memory device of 16×16 size, and four read heads 24 and one write head 22. The network structure and the operation of the read and write heads 22 can be similar to those described in the aforementioned articles. As observed by the inventors, the previously described simplified memory access does not affect network performance, and the limited precision used to represent memory contents does not cause any loss of accuracy.

[0059] As another example of application, similarity measurement can be calculated using a simple PWM circuit 35. The generation of read / write weights may require calculating the dot product and norm, i.e., measuring distance according to the following formula:

[0060]

[0061] Let k represent the input vector and M represent the memory. This calculation can potentially be performed using a single generation of the PWM input signal. A fixed portion representing 1 is added to the PWM signal corresponding to the value of k to calculate the norm ‖M‖1. Two read accesses from device 30 are required, where the first access corresponds to the norm ‖M‖1 and the second access corresponds to the vector-matrix multiplication kM. One method to obtain the two results separately is to reset the integrator after ‖M‖1 is calculated. In various variations, the integrator operates continuously, and the current value is stored in auxiliary memory after the fixed portion is processed at the input. After all inputs have been processed, the previously stored value needs to be subtracted from the total result to obtain ‖M‖1 and kM.

[0062] Note that the time-to-spiking scheme can be used to represent the input vector at the row / column of the crossbar array 30 instead of using a DAC or PWM circuit, which allows for a reduction in the energy required to transmit the input. Also in this case, the process of calculating the similarity metric can potentially be implemented in a single crossbar operation. The pulse sent as a reference point in the TTS scheme can be used for L1 norm parallel readout (the input vector contains all 1s). Dot product parallel readout can be implemented using a second pulse and TTS integrator scheme. Instead of a reference signal that activates the modulation terms of the TTS integrator to their initial values, the current is read out during the reference signal period to obtain ‖M‖1. Therefore, a single TTS readout returns the norm of M and the value of kM.

[0063] Although the invention has been described with reference to a limited number of embodiments, variations, and drawings, those skilled in the art will understand that various changes can be made and equivalents can be substituted without departing from the scope of the invention. In particular, features (of similar devices or methods) described in a given embodiment or variation or shown in the drawings may be combined with or replace another feature in another embodiment, variation, or drawing without departing from the scope of the invention. Therefore, various combinations of features described with respect to any of the foregoing embodiments or variations are contemplated, which remain within the scope of the appended claims. Furthermore, many minor modifications can be made to adapt particular situations or materials to the teachings of the invention without departing from the scope of the invention. Therefore, the invention is not limited to the specific embodiments disclosed, but rather will include all embodiments falling within the scope of the appended claims. In addition, many other variations besides those explicitly mentioned above are contemplated.

[0064] Figure 6 A block diagram is shown of components of a computer system 500 that may be included as part of a neural network system 1, according to an exemplary embodiment of the present invention. It should be understood that... Figure 6 This is merely an illustration of an implementation and does not imply any limitation on the environments in which different embodiments may be implemented. Many modifications can be made to the described environment.

[0065] Computer system 500 includes a communication structure 502 that provides communication between cache 516, memory 506, persistent storage device 508, communication unit 510, and input / output (I / O) interface 512. Communication structure 502 can be implemented using any architecture designed to transfer data and / or control information between processors (such as microprocessors, communication and network processors), system memory, peripheral devices, and any other hardware components within the system. For example, communication structure 502 can be implemented using one or more buses or crossbars.

[0066] Memory 506 and persistent storage device 508 are computer-readable storage media. In this embodiment, memory 506 includes random access memory (RAM). Typically, memory 506 may include any suitable volatile or non-volatile computer-readable storage medium. Cache 516 is a fast memory that enhances the performance of computer processor 504 by storing recently accessed data and data near data accessed from memory 506.

[0067] The program can be stored in persistent storage device 508 and memory 506 for execution by one or more corresponding computer processors 504 via cache 516. In one embodiment, persistent storage device 508 includes a magnetic hard disk drive. As an alternative to or supplement to a magnetic hard disk drive, persistent storage device 508 may include a solid-state drive, semiconductor storage device, read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, or any other computer-readable storage medium capable of storing program instructions or digital information.

[0068] The media used in persistent storage device 508 can also be removable. For example, a removable hard disk drive can be used for persistent storage device 508. Other examples include optical discs and disks, thumb drives, and smart cards, which are inserted into the drive for transfer to another computer-readable storage medium that is also part of persistent storage 508.

[0069] In these examples, communication unit 510 provides communication with other data processing systems or devices. In these examples, communication unit 510 includes one or more network interface cards. Communication unit 510 can provide communication by using one or both of physical and wireless communication links. Programs can be downloaded to permanent memory 508 via communication unit 510.

[0070] I / O interface 512 allows data input and output to other devices that can be connected to computer system 500. For example, I / O interface 512 can provide connectivity to external devices 518, such as keyboards, keypads, touchscreens, and / or other suitable input devices. External devices 518 may also include portable computer-readable storage media, such as thumb drives, portable optical discs or disks, and memory cards. Software and data used to practice embodiments of the invention can be stored on such portable computer-readable storage media and can be loaded onto persistent storage device 508 via I / O interface 512. I / O interface 512 is also connected to display 520.

[0071] The display 520 provides a mechanism for displaying data to the user and can be, for example, a computer monitor.

[0072] The programs described herein are identified based on applications that implement them in specific embodiments of the invention. However, it should be understood that any particular program terminology used herein is for convenience only, and therefore the invention should not be limited to use only in any particular application identified and / or implied by such terminology.

[0073] This invention can be a system, method, and / or computer program product at any possible level of technical detail integration. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to perform aspects of the invention.

[0074] Computer-readable storage media can be tangible means for retaining and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital universal disk (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards or protrusions in slots having instructions recorded thereon, and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through fiber optic cables), or electrical signals transmitted through wires.

[0075] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a suitable computing / processing device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network), or to an external computer or external storage device. The network may include copper cables, optical fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the suitable computing / processing device.

[0076] Computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as the "C" programming language or similar programming languages). The computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as a standalone software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may execute computer-readable program instructions by utilizing state information from the computer-readable program instructions to personalize the electronic circuitry in order to perform aspects of this invention.

[0077] The present invention will be described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0078] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner, such that the computer-readable storage medium storing the instructions includes an article of manufacture containing instructions that implement aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0079] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce computer-implemented processing, such that the instructions executed on the computer, other programmable apparatus, or other device perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0080] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions indicated in the blocks may occur in a different order than indicated in the figures. For example, two blocks shown consecutively may actually be implemented as a single step, executed simultaneously, substantially simultaneously, with partial or complete time overlap, or these blocks may sometimes be executed in reverse order, depending on the functions involved. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0081] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the invention. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or improvements to existing technologies in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for hardware implementation of operating a neural network system, the method comprising: A neural network system is provided, the neural network system including a controller, a memory and an interface for connecting the controller to the memory, wherein the controller includes a processing unit configured to execute a neural network, and the memory includes a neuromorphic memory device having a crossbar array structure, the crossbar array structure including input lines and output lines interconnected at crossbars via memristor devices, and the memristor device at each crossbar includes a phase-change memory (PCM) cell; In response to a write operation to the memory: receiving a write instruction from the controller, generating a write vector from the interface according to the write instruction, generating a write signal according to the write vector, and programming the memristor device of the neuromorphic memory device to incrementally change its state by coupling the write signal to one or more input lines in the input lines; as well as In response to a read operation on the memory: a read instruction is received from the controller, a read vector is generated by the interface according to the read instruction, a read signal is generated according to the read vector, and data is retrieved from the neuromorphic memory device by coupling the read signal to one or more input lines of the neuromorphic memory device according to a multiplication-accumulation operation; The controller enables the neural network system to interleave the steps of programming the memristor device and retrieving data from the neuromorphic memory device.

2. The method according to claim 1, wherein: Programming the memristor device further includes performing an erase operation before incrementally changing the state of one or more of the memristor devices, and The erase operation is determined by the write vector, thereby completely erasing one or more of the memristor devices in order to reset their respective states.

3. The method according to claim 1, wherein: The write vector is generated by the interface, which does not retrieve any data from the neuromorphic memory device.

4. The method according to claim 2, wherein: The crossbar array structure of the provided neural network system includes N input lines and W output lines, where N > 1 and W > 1; as well as The memory capacity of a neuromorphic memory device is determined by a memory matrix M of dimension N×W.

5. The method according to claim 4, wherein: The write signal is generated based on two types of write vectors according to two operations, the two operations including a first operation for determining the erase operation and a second operation for incrementally changing the state of the memristor device.

6. The method according to claim 5, wherein: The second operation involves an accumulation term and is performed through the following steps: Accumulate the accumulated value of the accumulated terms, the accumulated value being determined by the second type of the two types of write vectors; and; In response to the accumulated value exceeding a given threshold, the state of the memristor device is incrementally changed according to such accumulated value.

7. The method according to claim 5, wherein: Programming the memristor device also includes binarizing the values ​​of the components of one of the two types of vectors.

8. The method according to claim 7, wherein: Binarizing the value includes using a Heaviside function to calculate the value as a shift value of the vector component.

9. The method according to claim 4, wherein: According to the multiplication-accumulation operation, a second dataset is retrieved from the neuromorphic memory device, thereby multiplying the read vector generated by the interface by the memory matrix M.

10. A neural network system, comprising: The controller includes processing units configured to execute a neural network. The memory includes a neuromorphic memory device with a crossbar array structure, the crossbar array structure including input and output lines interconnected at the crossbars via memristor devices, and each memristor device at the crossbars comprising a phase-change memory (PCM) cell. An interface that connects the controller to the memory. The system is configured as follows: In response to a write operation on the memory: receiving a write instruction from the controller, generating a write vector from the interface according to the write instruction, generating a write signal according to the write vector, and programming the memristor device of the neuromorphic memory device to incrementally change its state by coupling the write signal to one or more input lines; and In response to a read operation on the memory: receiving a read instruction from the controller, generating a read vector from the interface according to the read instruction, generating a read signal according to the read vector, and retrieving data from the neuromorphic memory device by coupling the read signal to one or more input lines of the neuromorphic memory device based on a multiplication-accumulation operation; The controller enables the neural network system to interleave the steps of programming the memristor device and retrieving data from the neuromorphic memory device.

11. The neural network system according to claim 10, wherein: The system is further configured to perform an erase operation before incrementally changing the state of the memristor device, and The erase operation is determined by the write vector, and thus each such erase operation can only perform an action selected from the group consisting of: (i) completely erasing one of the memristor devices, and (ii) not erasing one of the memristor devices at all during the operation.

12. The neural network system according to claim 11, wherein: The crossbar array structure includes N input lines and W output lines, where N > 1 and W > 1; and The memory capacity of a neuromorphic memory device is determined by a memory matrix M of dimension N×W.

13. The neural network system according to claim 12, wherein: The interface includes a read head connected to the input line and the output line, and a write head connected to the input line.

14. The neural network system according to claim 13, wherein: The crossbar array structure also includes a pulse width modulation circuit, through which the read head and the write head are connected to the input line via a corresponding pulse width modulation circuit in the pulse width modulation circuit.

15. The neural network system according to claim 13, wherein: The read head is implemented as a module for a two-layer neural network, the two-layer neural network comprising: The input layer, whose input nodes are mapped to the output from the controller; and The output layer has its output nodes mapped to the input lines of the crossbar array structure.

16. The neural network system according to claim 14, wherein The write head is implemented as a module for implementing two neural networks, each neural network including: The input layer has its input nodes mapped to the output from the controller. as well as The output layer, whose output nodes are mapped to the input lines of the crossbar array structure, is used to output two types of write vectors respectively. Based on this, the system is adapted to perform two operations, including a first operation to determine the erase operation and a second operation to incrementally change the state of the memristor device.

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