Method for identifying die, wafer and die position on wafer

Abstract

Embodiments of the present application provide a die, a wafer and a method for identifying a position of a die on a wafer, and relate to the field of chips. A novel method for identifying a position of a die on a wafer is provided. The method comprises a position identifier made on the die; the position identifier is used to indicate a position of the die on the wafer; the position identifier comprises a first position identifier and a second position identifier; the first position identifier is used to indicate a position of a coverage area of a second mask on the wafer, wherein the second position identifier is made on the die in the coverage area by the second mask; the second position identifier is used to indicate a position of the die in the coverage area; wherein the first position identifier is made by a one-time exposure process using a first mask, and the second position identifier on the die in the same coverage area is made by a one-time exposure process using a second mask; and the first position identifier and the second position identifier are made on different material layers of the die, respectively.

Description

Technical Field

[0001] This application relates to the field of chips, and more particularly to a method for identifying a die, a wafer, and the location of a die on a wafer. Background Technology

[0002] In integrated circuit manufacturing, a single wafer typically contains tens of thousands of dies (or bare dies). The wafer is thinned and diced to form dies, which are then packaged into integrated circuit chips. Chips usually undergo testing to distinguish between good and defective products. Good chips must meet certain reliability standards before being released to the market, while defective chips are ultimately scrapped. The integrated circuit industry not only needs to ensure chip quality and reliability but also needs to continuously improve yield and reduce costs. Therefore, it is necessary to analyze and locate defective or failed chips to find the root cause of failure, providing feedback and driving continuous improvement in wafer fabs and packaging / testing plants. Thus, failure analysis (FA) of defective products (or failed chips) is a crucial step in chip manufacturing.

[0003] In failure analysis of defective products (or failed chips), data screening is often the first step. This involves analyzing the processing and testing data of each stage of chip manufacturing (wafer testing, chip packaging, chip testing) to determine if any anomalies were introduced at each stage. For a failed chip, the first step is to check for anomalies in its final test data, followed by anomalies in the upstream packaging process, and finally, checking whether the chip's packaged die is a good die on the wafer. However, as mentioned earlier, a wafer often contains tens of thousands of dies, necessitating the identification and differentiation of the die's location on the wafer.

[0004] Typically, when a die contains memory cells (such as register circuit units), the die's location information data can be directly programmed into the memory cells. When needed later, the previously programmed location information data can be read through an interface. Alternatively, optically visible location markers can be physically fabricated on the die. The latter usually requires improvements to existing chip manufacturing processes to create location markers on the die. The fabrication process for patterns on the die primarily uses photolithography, a method similar to photography, to transfer the pattern from a mask onto the die. Fabricating a separate mask to create location markers on the die typically increases costs, especially for high-resolution masks. Therefore, how to fabricate location markers on the die while remaining compatible with existing manufacturing processes requires further research. Summary of the Invention

[0005] This application provides a method for marking the location of a die, a wafer, and the die location on the wafer. This method can mark the location on the die while being compatible with existing manufacturing processes, effectively controlling costs.

[0006] In a first aspect, a die is provided. The die includes a position mark fabricated on the die; the position mark is used to indicate the position of the die on a wafer; the position mark includes a first position mark and a second position mark; the first position mark is used to indicate the position of a second photomask covering an area on the wafer, wherein the second position mark is fabricated on the die within the covered area by the second photomask; the second position mark is used to indicate the position of the die within the covered area; wherein the first position mark is fabricated using the first photomask through a single exposure process, and the second position mark on the die within the same covered area is fabricated using the second photomask through a single exposure process; the first position mark and the second position mark are respectively fabricated on different material layers on the die.

[0007] In the embodiments of this application, since the position of each die within the coverage area of ​​the second photomask is relatively fixed, a photomask with a certain material layer can be selected as the second photomask. A second position mark of the die within the coverage area is made on the second photomask at the position corresponding to each die. Then, the second position mark can be made by exposing the die within the coverage area through the second photomask. However, the coverage area of ​​the second photomask on the wafer is different for each exposure. Thus, the first position mark of the die in different coverage areas must be different to distinguish the position of each coverage area. Therefore, the same second photomask cannot be used to make the first position mark. The reason is that if the first position mark is made in a similar way as using the second photomask to make the second position mark, since each first position mark is different, that is, each coverage area requires a separate second photomask, multiple second photomasks need to be made, and the second photomask needs to be replaced for each exposure. The efficiency is very low, the cost is very high, and it has no value for mass production. Therefore, in the embodiments of this application, a first photomask is used to create a first position mark on all dies on the wafer through a single exposure process; thus, the first position marks on dies within the same coverage area are all identical; for dies in different coverage areas, the first position marks are different. Furthermore, a second photomask is used to sequentially expose different coverage areas on the entire wafer to create a second position mark on the die. The first and second position marks are combined to form a position mark to identify the die's position on the wafer. The first and second position marks are respectively fabricated on different material layers on the die, which is compatible with existing manufacturing processes while effectively controlling cost increases.

[0008] In one possible implementation, the first location marker is a graphic; the second location marker is letters and / or numbers; the precision of the exposure process for the first photomask is lower than that for the second photomask. For example, the exposure process for the first photomask can be contact exposure or proximity exposure; the exposure process for the second photomask can be projection exposure. Because projection exposure has high precision, typically with a resolution <0.1µm, it can effectively reduce the area occupied by the location markers, and letters and / or numbers produced using a high-precision exposure process can be used as the second location markers. In a single exposure, the coverage area of ​​the second photomask can include tens to hundreds of grains; therefore, a high-precision second exposure process can distinguish the position of each grain within the coverage area of ​​the second photomask, but cannot distinguish which coverage area it represents. As mentioned above, the first position mark is made on all the dies on the entire wafer through a single exposure process. Therefore, compared to the second photomask, the first position mark requires a larger area of ​​first photomask. Generally, due to the influence of gravity, the larger the area of ​​the photomask, the greater the deformation of the photomask, and the higher the distortion of the pattern produced. In addition, the production cost of a large-area high-precision photomask is also high. Therefore, the first position mark adopts a lower precision pattern, so that the first photomask can use a lower precision photomask to achieve low-precision exposure.

[0009] In one possible implementation, a first position identifier is used to indicate a digital sequence of covered areas, which are then stitched together to cover the entire wafer. For example, when exposing the wafer using a second photomask, the digital sequence changes each time the second photomask is moved; that is, each covered area corresponds to a unique digital sequence. For example, each time the second photomask is moved, the digital sequence is incremented by 1.

[0010] In one possible implementation, the second location identifier is used to indicate the row and column information of the grain in all grains within the coverage area, the row and column information including the row sequence and the column sequence.

[0011] In one possible implementation, the first position identifier is encoded using an array of patterns, wherein if an element in the array is filled with the pattern, it is decoded as a binary 1; if an element in the array is not filled with the pattern, it is decoded as a binary 0; or, if an element in the array is filled with the pattern, it is decoded as a binary 0; if an element in the array is not filled with the pattern, it is decoded as a binary 1. The second position identifier is filled within the elements of the array.

[0012] In one possible implementation, to make the position markers easier to identify, the die also includes a border around the element, or the die also includes a border around the array. The border and the second position marker are fabricated using the same exposure process.

[0013] Secondly, a wafer is provided. It includes a plurality of the aforementioned grains, which are distributed on the wafer in an array.

[0014] Thirdly, a method for marking the position of a die on a wafer is provided. This includes the following steps: determining a first position mark based on the position of the area covered by the second photomask on the die within the coverage area of ​​the second photomask on the wafer; the first position mark indicating the position of the area covered by the second photomask on the wafer; the second position mark indicating the position of the die within the coverage area; using the first photomask to create the first position mark on all dies of the wafer in a single exposure process, wherein dies within the same coverage area have the same first position mark; using the second photomask to create the second position mark on the die within the coverage area of ​​the second photomask in a single exposure process; the position mark composed of the first and second position marks indicating the position of the die on the wafer; and the second and first position marks being fabricated on different material layers on the die.

[0015] In one possible implementation, the first position identifier is a graphic; the second position identifier is a letter and / or number; and the exposure process precision of the first photomask is less than that of the second photomask.

[0016] In one possible implementation, a first location identifier is used to indicate a digital sequence of the covered area, which is spliced ​​to cover the entire wafer. For example, when exposing the wafer using a second photomask, the digital sequence changes once each time the second photomask is moved; that is, each covered area corresponds to a unique digital sequence. For example, each time the second photomask is moved, the digital sequence is incremented by 1.

[0017] In one possible implementation, the second location identifier is used to indicate the row and column information of all grains in the covered area, the row and column information including row sequence and column sequence.

[0018] In one possible implementation, the first position identifier is encoded using an array of patterns, wherein if an element in the array is filled with the pattern, it is decoded as a binary 1; if an element in the array is not filled with the pattern, it is decoded as a binary 0; or, if an element in the array is filled with the pattern, it is decoded as a binary 0; if an element in the array is not filled with the pattern, it is decoded as a binary 1.

[0019] In one possible implementation, the second position identifier is filled into the elements in the array.

[0020] One possible implementation also includes creating a border around the element using an exposure process that creates a second position identifier.

[0021] In one possible implementation, the outer border of the array is created using an exposure process that produces a second position marker.

[0022] Fourthly, a method for identifying the location of a die is provided, comprising the following steps: obtaining a first location identifier fabricated on the die; the first location identifier is used to indicate the location of a second photomask covering an area on a wafer; obtaining a second location identifier fabricated on the die; the second location identifier is fabricated by the second photomask on the die within the covered area, and the second location identifier is used to indicate the location of the die within the covered area; determining a location identifier based on the first location identifier and the second location identifier, wherein the location identifier is used to indicate the location of the die on the wafer.

[0023] Fifthly, an electronic device is provided, including a circuit board and a die connected to the circuit board, the die including the aforementioned die. The die is packaged as a chip, and the circuit board is connected to the die through the pins of the chip.

[0024] The technical effects of any of the possible implementations in aspects two through five can be found in the technical effects of different implementations in aspect one above, and will not be repeated here. Attached Figure Description

[0025] Figure 1 A schematic diagram of a grain structure provided for an embodiment of this application;

[0026] Figure 2 A schematic diagram of an encoding scheme for a reticle provided for an embodiment of this application;

[0027] Figure 3 A schematic diagram illustrating the positional identification of each grain in a reticle, provided for an embodiment of this application;

[0028] Figure 4 A schematic diagram illustrating the location of a grain provided for an embodiment of this application;

[0029] Figure 5 A schematic diagram illustrating the location of a grain provided in another embodiment of this application;

[0030] Figure 6 A schematic diagram illustrating the location of a grain provided in yet another embodiment of this application;

[0031] Figure 7 A schematic diagram illustrating the location of a grain provided in yet another embodiment of this application;

[0032] Figure 8 A schematic diagram illustrating the location of a grain provided in another embodiment of this application;

[0033] Figure 9A flowchart illustrating a method for identifying the location of a die on a wafer, provided for an embodiment of this application;

[0034] Figure 10 A schematic diagram of an encoding scheme for a reticle provided for another embodiment of this application;

[0035] Figure 11 A schematic diagram illustrating the encoding of grains on a reticle, provided for an embodiment of this application;

[0036] Figure 12 A schematic diagram illustrating the location of a grain provided in yet another embodiment of this application;

[0037] Figure 13 A flowchart illustrating a method for identifying the location of a die on a wafer, provided for embodiments of this application;

[0038] Figure 14 A schematic diagram of a photolithography process provided for an embodiment of this application;

[0039] Figure 15 A schematic diagram of a photolithography process provided for another embodiment of this application;

[0040] Figure 16 This is a schematic flowchart of a photolithography process provided for another embodiment of this application. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0042] The technical terms used in the embodiments of this application are described below:

[0043] Photolithography is a process in integrated circuit manufacturing that uses optical-chemical reaction principles and chemical and physical etching methods to transfer circuit patterns onto the surface of a wafer (e.g., a silicon wafer) or a material layer, forming effective pattern windows or functional patterns. Conventional photolithography uses ultraviolet light with wavelengths of 2000–4500 angstroms as the carrier of the circuit pattern, and a thin layer of photoresist (also called photoresist) as an intermediate medium (image recording) to transform, transfer, and process the circuit pattern, ultimately transferring it onto the wafer or material layer. In a broad sense, it includes two main aspects: exposure and etching processes. Photocopying is a process where an exposure system precisely transfers the device or circuit pattern pre-fabricated on a photomask (also called a photomask) to the required position onto a thin layer of photoresist pre-coated on the wafer surface or a material layer. Etching process: Using chemical or physical methods, the unmasked areas of the wafer surface or material layer covered by the photoresist layer are removed, thereby obtaining a pattern on the wafer surface or material layer that perfectly matches the pattern of the photoresist layer. Since the functional layers of an integrated circuit are three-dimensionally overlapping, the photolithography process is always repeated multiple times. For example, large-scale integrated circuits require approximately dozens of photolithography steps to complete the transfer of patterns across all layers.

[0044] Exposure process: also known as optical copying process. It typically includes contact exposure, proximity exposure, and projection exposure. Contact exposure: Uses a photomask to expose an entire wafer at a time, contacting the photoresist. Resolution is generally low (micrometer level). Because the photomask is in direct contact with the photoresist, secondary contamination of the photoresist is likely, and the photomask lifespan is short. Proximity exposure: Uses a photomask to expose an entire wafer at a time, without contacting the photoresist. Due to the gap between the photomask and the photoresist and the diffraction effect of light, the resolution is lower (usually below 3µm), but it does not cause photoresist contamination. Projection exposure: The photomask used can only cover a small square area on the wafer at a time (the coverage area of ​​the photomask can be square or rectangular). After exposing one area, it moves to the next adjacent area to continue exposure, covering the entire wafer through S-shaped scanning or stepping exposure. For a given product, the effective area for each exposure is fixed and repeated in the vertical and horizontal directions of the wafer; each exposure area (or coverage area) is called a reticle. In projection exposure, each photomask layer is aligned with the previous photomask, requiring high-precision overlap of the exposure areas. Since the circuitry of each die is identical, the pattern on the photomask is also identical. By strategically designing the number of dies within a reticle, the entire wafer can be exposed sequentially using this photomask. Furthermore, since only one photomask is needed, cost can be effectively controlled. Efficiency can be balanced by strategically designing the number of dies covered by the photomask. Projection exposure offers extremely high resolution, resulting in higher photomask costs, making it the mainstream exposure method. Typically, to save costs, contact or proximity exposure is used for low-precision applications, while projection exposure is used for high-precision applications. With the miniaturization and micro-miniaturization of chips, the size of circuit patterns is decreasing, and the precision requirements for exposure processes are increasing. Currently, the mainstream photolithography process primarily employs projection exposure.

[0045] The following sections will discuss the fabrication and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided in this application can be implemented in a variety of specific environments. The specific embodiments discussed are merely illustrative of specific ways of implementing and using this description and technology, and do not limit the scope of this application.

[0046] Unless otherwise defined, all technical terms used herein have the same meaning as commonly known to one of ordinary skill in the art.

[0047] The technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings. In this application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, in the embodiments of this application, the words "first," "second," etc., do not limit the quantity or order.

[0048] Furthermore, in this application, directional terms such as "upper" and "lower" are defined relative to the orientation of the components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings.

[0049] In this application, unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. It can be a direct electrical connection or an indirect electrical connection through an intermediate medium.

[0050] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0051] The technical solution of this application can be applied to electronic devices, which can be various types of user equipment or terminal devices such as computers, mobile phones, tablets, wearable devices, and vehicle-mounted devices; the electronic device can also be network equipment such as base stations. The electronic device can also be a radio frequency power amplifier, analog driver, discrete device, or other similar device used in the aforementioned electronic devices. The embodiments of this application do not impose any special limitations on the specific form of the aforementioned electronic devices.

[0052] This application provides an electronic device including a circuit board and a die connected to the circuit board. The circuit board can be a printed circuit board (PCB), or a flexible printed circuit board (FPC), etc.; this embodiment does not limit the type of circuit board. The die can be packaged into a chip, and the circuit board is connected to the die through the chip's pins. Optionally, the electronic device also includes a packaging substrate, which is fixed to the printed circuit board (PCB) by solder balls, and the chip is fixed to the packaging substrate by solder balls.

[0053] In this application, the die provided in the embodiments has a position marker to identify the die's location on the wafer, thus distinguishing the die's position on the wafer. Typically, in integrated circuits using complementary metal-oxide-semiconductor (CMOS) technology, the die design incorporates special register circuit units, such as OTPROM (one-time programmable read-only memory). OTPROM has the characteristic of being programmable only once; this step is called programming. After programming, it becomes read-only memory and no longer allows new information to be written, making it suitable for use as a die identifier. During the wafer testing process, various necessary information, including wafer batch information and die position markers, is written to the register unit all at once through the die's digital interface; when needed later, the previously programmed information can be read through the chip's interface. For non-CMOS integrated circuits, special processes that cannot use registers (such as III-V compound semiconductor processes, typically used to manufacture RF power amplifiers, analog drivers, discrete devices, etc.), while requiring die identification to support the acquisition of the die's physical location on the wafer, only physical methods can be chosen. Physical methods involve directly fabricating optically visible markings on the die using physical methods to indicate the die's location on the wafer. The location markings provided in the embodiments of this application primarily refer to physical location markings. Of course, the location markings provided in the embodiments of this application can mainly be applied to the aforementioned non-CMOS integrated circuits. However, since the die location markings provided in the embodiments of this application are mainly fabricated using photolithography, and since CMOS integrated circuits also use photolithography, the die location markings provided in the embodiments of this application can also be used for CMOS integrated circuits.

[0054] The structure of the above-mentioned grains is described below.

[0055] Reference Figure 1As shown, grains typically have... Figure 1 The pins 11 shown are distributed around the die and are connected to the integrated circuit inside the die through traces to connect with other external devices or circuits to realize the function of the integrated circuit in the die.

[0056] In addition, such as Figure 1 As shown, the die provided in the embodiments of this application further includes a position identifier 12 fabricated on the die; the position identifier 12 is used to indicate the position of the die on the wafer; the position identifier 12 includes a first position identifier and a second position identifier. The position identifier can be at any position on the die, but for a specific product, the position is fixed.

[0057] The first position marker indicates the position of the area covered by the second photomask on the wafer. The second position marker is fabricated by the second photomask on the die within the covered area. That is, the first position marker indicates the position of each reticle on the wafer. In the following description, the covered area is uniformly illustrated using a reticle. The second position marker indicates the position of the die within the reticle.

[0058] Furthermore, the first position marker is fabricated using a first photomask through a single exposure process, and the second position marker is fabricated using a second photomask through a single exposure process. The position markers can be formed on a material layer inside the die using a photolithography process. For example, the first and second position markers are fabricated on different material layers on the die. These material layers can be any non-transparent material layer requiring exposure using a photomask, such as the first position marker being fabricated on a first metal layer and the second position marker being fabricated on a second metal layer. The first and second metal layers can be material layers located on different layers and can be reused to fabricate metal traces with different functions on the die.

[0059] In the embodiments of this application, since the position of each die within the reticle is relatively fixed, a photomask of a certain material layer can be selected as the second photomask. A second position mark corresponding to each die is made on the second photomask at the position corresponding to each die. Then, by exposing the die within the reticle through the second photomask, the second position mark can be made. However, the reticle on the wafer is different for each exposure. Thus, the first position mark of the die within different reticles must be different to distinguish the position of each reticle. Therefore, the same second photomask cannot be used to make the first position mark. The reason is that if the first position mark is made in a similar way as using the second photomask to make the second position mark, since each first position mark is different, that is, each reticle requires a separate second photomask, multiple second photomasks need to be made, and the second photomask needs to be replaced for each exposure. The efficiency is very low, the cost is very high, and it has no value for mass production. Therefore, in the embodiments of this application, a first photomask is used to create a first position mark on all dies on the wafer through a single exposure process; special coding and layout ensure that all first position marks on dies within the same reticle are identical; for dies in different reticles, the first position marks are different. Furthermore, a second photomask is used to sequentially expose different reticles on the entire wafer to create a second position mark on the die. The first and second position marks are combined to form a position mark to identify the die's position on the wafer. The first and second position marks are respectively fabricated on different material layers on the die, which is compatible with existing manufacturing processes while effectively controlling cost increases.

[0060] In one embodiment, the first position identifier is a graphic; the second position identifier is letters and / or numbers; the precision of the exposure process for the first photomask is lower than the precision of the exposure process for the second photomask. For example, the exposure process for the first photomask can be contact exposure or proximity exposure; the exposure process for the second photomask can be projection exposure. Because projection exposure has higher precision, typically a resolution > 0.1µm, it can effectively reduce the area occupied by the position identifier, and letters and / or numbers produced using a high-precision exposure process can be used as the second position identifier. In a single exposure, the reticle of the second photomask can include tens to hundreds of grains; therefore, a high-precision second exposure process can distinguish the position of each grain within the reticle of the second photomask, but cannot distinguish which reticle it is. As mentioned above, the first position marker is created on all the dies on the entire wafer using a single exposure process. Therefore, compared to the second photomask, creating the first position marker requires a larger area of ​​the first photomask. Due to gravity, the larger the photomask area, the greater the deformation, resulting in higher pattern distortion. Furthermore, the cost of creating a large-area, high-precision photomask is also high. Therefore, the first position marker uses a lower-precision pattern, allowing for lower-precision exposure using a lower-precision photomask. For example, the first position marker can be a circle, triangle, square, rhombus, or other polygonal shape, with a width controlled at around 15μm. Therefore, to distinguish reticles, global exposure (i.e., one photomask covering the entire wafer in a single exposure) is required, i.e., contact exposure or proximity exposure. Each die on the first photomask must be marked with its corresponding reticle. Since the second photomask used for projection exposure on the wafer typically has dozens to hundreds of reticles, creating a first position marker corresponding to the number of reticles on the first photomask is sufficient for differentiation.

[0061] In one embodiment, the specific forms of the first location identifier and the second location identifier are described as follows:

[0062] The first position identifier can be an encoding of the reticle, and the encoding corresponding to each reticle is different.

[0063] For example: the first position identifier is used to indicate the digital sequence of reticles; all reticles are stitched together to cover the entire wafer. When the wafer is exposed using the second photomask, the digital sequence of the second photomask changes once each time it is moved; for example, each time the second photomask is moved, the corresponding reticle digital sequence is incremented by 1.

[0064] The second location identifier can be the code of the grain among all grains within the reticle, and the code of each grain is different within the same reticle.

[0065] For example, the second position identifier is used to indicate the row and column information of all grains within the reticle, including the row sequence X and the column sequence Y.

[0066] like Figure 2 As shown, according to the exposure sequence of the wafer using the second photomask, the reticles formed on the wafer by the second photomask are encoded according to a digital sequence, such as... Figure 2 As shown, the codes include 001-016. (Refer to...) Figure 3 As shown, each reticle comprises six grains arranged in an array, to Figure 3 For example, the six grains are arranged in a 3x2 grid, where... Figure 3 The image shows the position identifiers on each grain in reticle numbered 010. In each grain, 010 is the code of the reticle, and 11 (12, 13, 21, 22, 23) are the row and column information of the grain in all grains in the reticle. 11 is used to indicate that the grain is located in the 1st row and 1st column of reticle 101.

[0067] Furthermore, as described above, the first position identifier is encoded using an array of graphics, wherein if an element in the array is filled with a graphic, it is decoded as a binary code 1; if an element in the array is not filled with the graphic, it is decoded as a binary code 0; or, if an element in the array is filled with the graphic, it is decoded as a binary code 0; if an element in the array is not filled with the graphic, it is decoded as a binary code 1.

[0068] The following explanation illustrates the encoding scheme for reticles. If an element in the array is filled with a pattern, it is decoded as a binary 1; otherwise, it is decoded as a binary 0. This is equivalent to encoding reticles using binary. A 7-bit scheme (0000000~1111111) supports a maximum of 128 reticles, meaning the wafer can be exposed a maximum of 128 times using the same second photomask. An 8-bit scheme (00000000~11111111) supports a maximum of 256 reticles, meaning the wafer can be exposed a maximum of 256 times using the same second photomask. Taking the 8-bit scheme (00000000~11111111) supporting 256 reticles as an example, the reticle encoding scheme is shown in Table 1 below.

[0069]

[0070] Table 1

[0071] Then refer to as follows Figure 4As shown, taking a 3x3 array as an example, and using black squares to fill the elements in the array as an example, the pattern can be achieved in the exposure process by retaining the material layer at the position of the black square. Each element in the 3x3 array is represented by a filled pattern (1) and an unfilled pattern (0). For example, if a reticle of the second photomask is encoded as 171 to indicate its position, the encoding is as follows: 171 = 1*1 + 1*2 + 0*4 + 1*8 + 0*16 + 1*32 + 0*64 + 1*128, i.e., 171 = 11010101. Taking 8 bits supporting 256 reticles as an example, the first position identifier needs to be identified using 8 elements in the 3x3 array. This application uses the 1st to 8th elements as examples for illustration. If bits 1, 2, 4, 6, and 8 are 1, then the 1st, 2nd, 4th, 6th, and 8th elements in the 3x3 array will be filled with a graphic; if all other bits are 0, then the 3rd, 5th, 7th, and 9th elements in the 3x3 array will remain blank.

[0072] The position of the grain within the reticle, i.e., the second position identifier, uses the row and column information of the grain among all grains in the reticle. The row and column information includes the row sequence X and column sequence Y, i.e., the (X, Y) coordinates. Two characters represent X and Y respectively; decimal numbers can be used, and letters are used for values ​​greater than 10. For example... Figure 5 As shown, if the 9th element of the 3*3 array is 35, it means that the position of the grain in the reticle is (3, 5); if it is A8, it means that the position of the grain in the reticle is (10, 8); if it is CB, it means that the position of the grain in the reticle is (12, 11), and so on. The correspondence between the decimal numbers and letters represented by X or Y is shown in Table 2 below.

[0073]

[0074] Table 2

[0075] In one implementation, to make the location identifier easier to identify, such as Figure 5 As shown, the grain also includes a border around the element, wherein border 13 and the second position marker are fabricated using the same exposure process. Alternatively, as... Figure 6 As shown, the die also includes a border 14 around the array, wherein the border and the second position marker are fabricated using the same exposure process. Of course, the embodiments of this application do not limit the specific form of the border, and the border around the element can be as follows: Figure 5 The separated form shown means that each element has its own border, or as... Figure 7As shown, adjacent elements share a border. This border can be continuous or discontinuous. The border can also be on a different layer than the second position identifier; for example, it can be created using a different material layer and high-precision projection exposure. Since the border on each die on the wafer is identical, no new photomask is needed. Any opaque layer can be chosen, and the top visible material layer can be achieved during the exposure process.

[0076] Taking a 3x3 array as an example, if the entire wafer can be covered by 128 exposures using the second photomask, then a 7-bit array can be used to support a maximum of 128 reticles. This requires using 7 elements in the 3x3 array to identify the first position. In this case, the remaining two elements in the 3x3 array—the 8th and 9th primary colors—are used to identify the second position. Figure 8 As shown, if a reticle of the second photomask is encoded as 107 to indicate its position, the encoding is as follows: 107 = 1*1 + 1*2 + 0*4 + 1*8 + 0*16 + 1*32 + 1*64, i.e., 107 = 1101011. Taking 7 bits supporting 128 reticles as an example, 7 elements in a 3*3 array are needed to identify the first position. This application uses the 1st to 7th elements as an example. If bits 1, 2, 4, 6, and 7 are 1, then the 1st, 2nd, 4th, 6th, and 7th elements in the 3*3 array are filled with graphic elements; if all other bits are 0, then the 3rd, 5th, 8th, and 9th elements in the 3*3 array remain blank. Figure 8 As shown, the 8th element of the 3*3 array is 3 and the 9th element is 5, which means that the position of the grain in the reticle is (3, 5).

[0077] Thus, as long as the aforementioned positional markers are fabricated on the die, the positional marker on each die on the wafer is unique. Therefore, by obtaining the positional marker on the die, the precise location of that die on the wafer can be identified. Specifically, as follows... Figure 9 As shown, based on the aforementioned location markers on the die, embodiments of this application also provide a method for identifying the location of a die on a wafer, comprising the following steps:

[0078] 101. Obtain the first location identifier fabricated on the die.

[0079] The first position marker is used to indicate the position of the area covered by the second photomask on the wafer.

[0080] The first position identifier is used to indicate the position of each reticle on the wafer.

[0081] 102. Obtain the second location identifier fabricated on the grain.

[0082] The second position marker is made on the die within the coverage area by the second photomask, and the second position marker is used to indicate the position of the die within the reticle.

[0083] 103. Determine the position identifier based on the first position identifier and the second position identifier, wherein the position identifier is used to indicate the position of the die on the wafer.

[0084] For example: For a wafer, the encoding rules for the location identifiers of the grains on that wafer are as follows: Figure 10 As shown, the reticles of the second photomask are sequentially encoded on the wafer in ascending order as (001~042), for a total of 42 reticles (of course...). Figure 10 In the diagram, 001, 006, 037, and 042 are not covered by the wafer and can be removed; while the dies on the reticle are coded from (1,1) to (7,A), as shown below. Figure 11 As shown, there are a total of 70 grains; the location marker of one grain is known, as shown below. Figure 12 As shown, the process of identifying the die's position on the wafer is as follows: The number 35 in the 9th element of the 3x3 array indicates that the die's coordinates on the coverage area of ​​the second photomask are (3, 5); the 1st to 8th elements of the 3x3 array are arranged sequentially from top to bottom and left to right, with 1 for a pattern and 0 for no pattern, resulting in 110 110 00, which is the code of the reticle of the second photomask. 110 11000 = 1*1+1*2+0*4+1*8+1*16+0*32+0*64+0*128=27, which is the 027 coverage area. Therefore, it can be confirmed that the die's position on the wafer is (3, 5) in the reticle numbered 27.

[0085] Reference Figure 13 As shown in the figure, embodiments of this application also provide a method for identifying the location of a die on a wafer, comprising the following steps:

[0086] 201. Determine the first position mark based on the position of the covered area when a second position mark is made on a die within the covered area of ​​the second photomask on the wafer using the second photomask.

[0087] The first position marker is used to indicate the position of the area covered by the second photomask on the wafer, wherein the second position marker is made by the second photomask on the die within the covered area; the second position marker is used to indicate the position of the die within the covered area. That is, the first position marker is used to indicate the position of each reticle on the wafer.

[0088] 202. Using a first photomask, a first position mark is created on all the dies of the wafer through a single exposure process. Dies within the same reticle have the same first position mark.

[0089] 203. Using a second photomask, a second position mark is created on the die within the reticle area of ​​the second photomask through a single exposure process.

[0090] The position identifier, consisting of a first position identifier and a second position identifier, is used to indicate the position of the die on the wafer; the first position identifier and the second position identifier are respectively fabricated on different material layers on the die.

[0091] In this application, since the position of each die within a reticle is relatively fixed, a photomask of a certain material layer can be selected as the second photomask. A second position marker corresponding to each die is created on the second photomask at the corresponding position. Then, by exposing the die within the reticle using this second photomask, the second position marker can be created. However, with each exposure, the reticle on the wafer is different. Therefore, the first position markers of the dies within different reticles must be different to distinguish the positions of each reticle. Thus, the same second photomask cannot be used to create the first position marker because if a similar method were used, multiple second photomasks would need to be created, and each exposure would require replacing the second photomask, resulting in low efficiency and high cost, making mass production impractical. Therefore, in the embodiments of this application, a first photomask is used to create the first position marker on all dies on the wafer through a single exposure process. This ensures that the first position markers on dies within the same reticle are identical, while the first position markers are different for dies in different reticles. Furthermore, by sequentially exposing different reticles on the entire wafer using a second photomask, a second position mark is created on the die. The first and second position marks are combined to form a position mark to identify the die's position on the wafer. The first and second position marks are respectively fabricated on different material layers on the die, which is compatible with existing manufacturing processes while effectively controlling the increase in costs.

[0092] Taking the example where the first location marker is located in the first metal layer and the second location marker is located in the second metal layer:

[0093] Typically, the photolithography process for the first and second metal layers refers to... Figure 14 As shown, it includes the following steps:

[0094] 301. Deposited metal layer.

[0095] First, a metal layer is formed by depositing a metal material on a substrate, which can be a silicon wafer or a substrate after a functional layer has been fabricated in an integrated circuit manufacturing process. Depending on the specific product form of the integrated circuit, this metal layer can be used to fabricate RF power amplifiers, analog drivers, and metal traces in discrete devices (any metal layer in the process can be selected, as long as it is visible on the surface after wafer fabrication, such as aluminum, aluminum-copper alloys, or copper as the top layer in silicon processes; in special III-V compound processes, since there are only two or three metal layers, almost any metal layer can be used). In step 401, a metal layer is formed by depositing a metal material on the substrate using a physical vapor deposition (PVD) process. In some embodiments, the following metals are selected: tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), ruthenium (Ru), iridium (Ir), cobalt (Co), aluminum (Al), copper (Cu), etc., or alloys thereof. The process for fabricating the metal layer is not limited to PVD; it can also be chemical vapor deposition (CVD), evaporation, or electroplating.

[0096] 302. Coat the metal layer with photoresist.

[0097] Specifically, a photoresist layer can be formed on the metal layer using static coating or dynamic spin coating methods. For example, it can be an olefin monomer, polyvinyl alcohol laurate, etc. The photoresist can be positive or negative.

[0098] 303. Expose the photoresist using a photomask.

[0099] In this process, the photoresist is mainly exposed to transfer the pattern to be created on the metal layer onto the photoresist. After step 303, the photoresist that does not need to be retained is developed with a solvent, and the remaining photoresist protects the pattern that needs to be retained on the metal layer.

[0100] 304. Etch the metal layer.

[0101] Finally, dry or wet etching processes are used to remove the metal layer not covered by photoresist to form a pattern.

[0102] Steps 301-304 above describe a standard photolithography process for the metal layer. The above process can be used to create patterns on both the first and second metal layers. In this application, to create a first position marker on the first metal layer, an additional exposure process (such as...) can be added after step 303 in the photolithography process for the first metal layer. Figure 15As shown in the figure, the first photomask exposure process described above uses the first photomask to expose the photoresist. After step 304, the first position mark can be made on all the dies of the wafer.

[0103] In another embodiment, a photolithography process for the first and second metal layers using a liftoff process is also provided, referring to... Figure 16 As shown, it includes the following steps:

[0104] 401. Coat the substrate with photoresist.

[0105] First, photoresist is coated onto a substrate, which can be a silicon wafer or a substrate after a functional layer has been fabricated in an integrated circuit manufacturing process. Specifically, a layer of photoresist can be formed on the metal layer using static coating or dynamic spin coating methods. For example, it can be an olefin monomer, polyvinyl alcohol laurate, etc. The photoresist can be positive or negative.

[0106] 402. Expose the photoresist using a photomask.

[0107] In this process, the photoresist is mainly exposed to transfer the pattern to be created on the metal layer onto the photoresist. After step 402, the photoresist that does not need to be retained is developed with a solvent, and the remaining photoresist protects the substrate to create patterns on the areas of the substrate not covered by the photoresist.

[0108] 403. Deposited metal layer.

[0109] In step 403, a metal layer can be formed by depositing a metal material using the physical or chemical methods mentioned in step 301. In some embodiments, the following metals are selected: tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), ruthenium (Ru), iridium (Ir), cobalt (Co), aluminum (Al), copper (Cu), etc., or alloys thereof.

[0110] 404. Remove the photoresist and the metal layer on it.

[0111] After step 404, what remains on the substrate is the pattern of the metal layer deposited in step 403 at the location where the photoresist was not retained in step 402.

[0112] Steps 401-404 above describe the liftoff photolithography process for the metal layer. The above process can be used to create patterns on both the first and second metal layers. In this application, to create the first position marker on the first metal layer, an exposure process can be added after step 402 in the photolithography process for the first metal layer. This exposure process corresponds to the first photomask mentioned above, where the first photomask is used to expose the photoresist. Thus, after step 402, the first position marker can be created on all the dies of the wafer.

[0113] In order to realize the fabrication of the second position mark in the second metal layer, the photomask in step 303 can be directly reused in the photolithography process of fabricating the second metal layer, and the pattern of the second position mark can be added to the photomask. In this way, after step 304, the second position mark can be fabricated on the die of the wafer.

[0114] In addition, optionally, the first position identifier is a graphic; the second position identifier is a letter and / or number; the precision of the first exposure process is less than the precision of the second exposure process.

[0115] Optionally, the first position identifier is used to indicate the digital sequence of the reticle, which covers the entire wafer; wherein, the reticle contains multiple dies. The digital sequence changes once each time the second photomask is moved, meaning that each covered area corresponds to a unique digital sequence. For example, the digital sequence increments by 1 each time the second photomask is moved.

[0116] Optionally, the second position identifier is used to indicate the row and column information of the grain in all grains within the reticle, the row and column information including the row sequence and column sequence.

[0117] Optionally, the first position identifier is encoded using an array of patterns, wherein if the elements in the array are filled with the patterns, they are decoded as binary code 1; if the elements in the array are not filled with patterns, they are decoded as binary code 0; or, if the elements in the array are filled with patterns, they are decoded as binary code 0; if the elements in the array are not filled with patterns, they are decoded as binary code 1.

[0118] Optionally, the second position identifier is filled in the elements of the array.

[0119] Optionally, the border around the element can be created using an exposure process that produces a second position marker.

[0120] Optionally, the outer border of the array can be created using an exposure process that produces a second position marker.

[0121] It is immediately apparent that in the embodiments corresponding to the method for identifying the grain position, each step is for creating a position marker on the grain. Therefore, the technical effects that can be achieved in the various optional implementations described above are the same as the corresponding structures in the above-mentioned grain structure, and will not be repeated here.

[0122] In another aspect of this application, a non-transitory computer-readable storage medium for use with a computer having software for creating integrated circuits is also provided. The computer-readable storage medium stores one or more computer-readable data structures having photomask data for manufacturing the location identifiers on the die provided above.

[0123] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A crystal grain, characterized by, The crystal grain comprises a position mark made on the crystal grain; the position mark is used to indicate the position of the crystal grain on the wafer; The position mark comprises a first position mark and a second position mark; The first position mark is used to indicate the position of a second mask on a covering area on the wafer; the second position mark is made on the crystal grain in the covering area by the second mask; the second position mark is used to indicate the position of the crystal grain in the covering area; The first position mark is made by a first mask through a one-time exposure process; the second position mark on the crystal grain in the same covering area is made by a second mask through a one-time exposure process; the first position mark and the second position mark are made on different material layers on the crystal grain; the first position mark is encoded by an arrayed pattern; the second position mark is encoded by letters and / or numbers; The exposure process precision of the first mask is less than the exposure process precision of the second mask; If the element in the array is filled with the pattern, it is decoded as 1 in binary code; if the element in the array is not filled with the pattern, it is decoded as 0 in binary code. Or, if the element in the array is filled with the pattern, it is decoded as 0 in binary code; if the element in the array is not filled with the pattern, it is decoded as 1 in binary code.

2. The grain of claim 1, wherein The first position mark is used to indicate a digital sequence of the covering area; the covering areas are spliced to cover the whole wafer.

3. The crystal grain according to claim 1 or 2, characterized by The second position mark is used to indicate the row and column information of the crystal grain in all the crystal grains in the covering area; the row and column information comprises a row sequence and a column sequence.

4. The die of claim 1 wherein, The second position mark is filled in the element in the array.

5. The grain of claim 1 or 4, wherein The crystal grain further comprises a frame outside the element; the frame and the second position mark are made by the same exposure process.

6. The grain of claim 1 or 4, wherein The crystal grain further comprises a frame outside the array; the frame and the second position mark are made by the same exposure process.

7. A wafer, characterized by The wafer comprises a plurality of crystal grains as claimed in any one of claims 1-6; the crystal grains are distributed in an array on the wafer.

8. A method for marking the position of a crystal grain on a wafer, characterized in that, a first position mark is determined according to the position of a covering area of a second mask on the wafer when the second position mark is made on the crystal grain in the covering area of the second mask on the wafer by the second mask; the first position mark is used to indicate the position of the second mask on the covering area on the wafer; the second position mark is used to indicate the position of the crystal grain in the covering area; a first position mark is made on all the crystal grains on the wafer by a first mask through a one-time exposure process; the crystal grains in the same covering area have the same first position mark. a second position mark is made on the die within the coverage area of the second mask by a one-time exposure process using the second mask; the first position mark and the second position mark are used to indicate the position of the die on the wafer; the first position mark and the second position mark are made on different layers of material on the die respectively; the first position mark is encoded by an array-arranged pattern; the second position mark is encoded by letters and / or numbers; the accuracy of the exposure process of the first mask is less than the accuracy of the exposure process of the second mask; wherein, if an element in the array is filled with the pattern, it is decoded as 1 in binary code; if an element in the array is not filled with the pattern, it is decoded as 0 in binary code; or, if an element in the array is filled with the pattern, it is decoded as 0 in binary code; if an element in the array is not filled with the pattern, it is decoded as 1 in binary code.

9. The method of claim 8, wherein, the first position mark is used to indicate a numerical sequence of the coverage area; all the coverage areas are spliced to cover the entire wafer.

10. The method of claim 8 or 9, wherein the second position mark is used to indicate the row and column information of the die within all the dies in the coverage area, the row and column information including a row sequence and a column sequence.

11. The method of claim 8, wherein: the second position mark is filled in the elements in the array.

12. The method of claim 8 or 11, wherein It also includes a frame outside the elements made by the exposure process of making the second position mark.

13. The method of claim 8 or 11, wherein a frame outside the array is made by the exposure process of making the second position mark.

14. A die position identification method, characterized in that, a first position mark made on the die is obtained; the first position mark is used to indicate the position of a coverage area on a wafer by a second mask, and the first position mark is made by a one-time exposure process using a first mask; a second position mark made on the die is obtained; the second position mark is used to indicate the position of the die within the coverage area, wherein the second position mark is made on the die within the coverage area by the second mask; a position mark is determined according to the first position mark and the second position mark, wherein the position mark is used to indicate the position of the die on the wafer; the first position mark and the second position mark are made on different layers of material on the die respectively; the first position mark is encoded by an array-arranged pattern; the second position mark is encoded by letters and / or numbers; the accuracy of the exposure process of the first mask is less than the accuracy of the exposure process of the second mask; wherein, if an element in the array is filled with the pattern, it is decoded as 1 in binary code; if an element in the array is not filled with the pattern, it is decoded as 0 in binary code; or, if an element in the array is filled with the pattern, it is decoded as 0 in binary code; if an element in the array is not filled with the pattern, it is decoded as 1 in binary code.

15. An electronic device, comprising: It includes a circuit board and a die connected with the circuit board, the die includes any one of the dies in claims 1-6, the die is packaged as a chip, and the circuit board is connected with the die through the pins of the chip.

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