Signal processing circuit

Abstract

The signal processing circuit includes: a first sampling capacitor and a second sampling capacitor connected to the input signal path of an analog signal; and a signal processing unit that performs prescribed processing on the analog signal sampled by the first sampling capacitor and the analog signal sampled by the second sampling capacitor. The signal processing circuit performs sampling of the analog signal of one of the first sampling capacitor and the second sampling capacitor, and performing prescribed processing on the analog signal sampled by the other of the first sampling capacitor and the second sampling capacitor based on the signal processing unit in parallel.

Description

Technical Field

[0001] This invention relates to signal processing circuits. Background Technology

[0002] Previously, a technique related to switched capacitor circuits (for example, see Patent Documents 1 and 2 below) was proposed, in which analog differential signals are sampled by capacitors and the sampled analog differential signals are amplified by amplifiers.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2006-33304

[0006] Patent Document 2: Japanese Patent Application Publication No. 11-298328 Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] However, in existing technologies, to double the data rate of the analog signal for output, two amplifiers are required, with the amplified analog signal being output alternately from the two amplifiers. Therefore, in existing technologies, driving two amplifiers may lead to increased power consumption.

[0009] Methods for solving problems

[0010] One embodiment of the signal processing circuit includes: a first sampling capacitor and a second sampling capacitor connected to an input signal path of an analog signal; and a signal processing unit that performs predetermined processing on the analog signal sampled by the first sampling capacitor and the analog signal sampled by the second sampling capacitor, wherein the signal processing circuit performs sampling of the analog signal of one of the first sampling capacitor and the second sampling capacitor, and predetermined processing based on the signal processing unit on the analog signal sampled by the other of the first sampling capacitor and the second sampling capacitor in parallel.

[0011] Invention Effects

[0012] According to one embodiment of the signal processing circuit, the increase in power consumption can be suppressed and the data rate of analog signals can be increased. Attached Figure Description

[0013] Figure 1 This is a diagram showing the structure of the detection system and IC according to the first embodiment.

[0014] Figure 2 This is a diagram showing the circuit structure of the amplifier circuit in the first embodiment.

[0015] Figure 3 This is a diagram showing the state of the amplifier circuit in the first embodiment during the first period.

[0016] Figure 4 This is a diagram showing the state of the amplifier circuit in the second period of the first embodiment.

[0017] Figure 5 This is a timing diagram showing the operation timing of the amplifier circuit in the first embodiment.

[0018] Figure 6 This is a diagram showing the circuit structure of the averaging filter circuit in the second embodiment.

[0019] Figure 7 This is a timing diagram showing the operation timing of the averaging filter circuit in the second embodiment.

[0020] Figure 8 This is a diagram showing the circuit structure of the amplifier circuit in the third embodiment.

[0021] Figure 9 This is a diagram showing the circuit structure of the DAC in the third embodiment.

[0022] Figure 10 This is a diagram illustrating an example of the binary code used in the DAC of the third embodiment.

[0023] Figure 11 This is a diagram illustrating an example of the thermometer code used in the DAC of the third embodiment.

[0024] Figure 12 This is a timing diagram showing the operation timing of the DA converter in the third embodiment.

[0025] Figure 13 This diagram is used to explain the operating principle of the DA converter in the third embodiment.

[0026] Figure 14 This is a graph showing an example of the output voltage value of the analog signal output from the amplifier when the DAC of the third embodiment is not provided.

[0027] Figure 15 This is a graph showing an example of the output voltage value of the analog signal output from the amplifier when the DAC of the third embodiment is not provided.

[0028] Figure 16 This is a graph showing an example of the output voltage value of the analog signal output from the amplifier when the DAC of the third embodiment is provided.

[0029] Figure 17 This is a diagram showing the structure of a load detection device according to one embodiment. Detailed Implementation

[0030] Hereinafter, one embodiment will be described with reference to the accompanying drawings.

[0031] [First Implementation Method]

[0032] (Structure of detection system 10)

[0033] Figure 1 This is a diagram showing the structure of the detection system 10 and IC20 according to the first embodiment. Figure 1 The detection system 10 shown includes: a sensor 12, an IC (Integrated Circuit) 20, and an MCU (Micro Controller Unit) 30.

[0034] Sensor 12 detects various objects (e.g., temperature, strain, etc.). Sensor 12 is a differential sensor, outputting two sensor signals (analog signals) that represent the detected value differentially.

[0035] IC20 is an integrated circuit that performs specified processing on the sensor signal (analog signal) output from sensor 12. For example, IC20 amplifies and performs AD conversion on the sensor signal output from sensor 12. Furthermore, IC20 outputs the amplified and AD-converted sensor signal (digital signal) to MCU30.

[0036] MCU30 obtains the amplified and AD-converted sensor signal (digital signal) from IC20 via communication with IC20. Furthermore, MCU30 performs the prescribed digital processing using the sensor signal obtained from IC20.

[0037] (Structure of IC20)

[0038] like Figure 1 As shown, IC20 includes: an amplifier circuit 22, an AD converter 24, and a digital processing circuit 26.

[0039] Amplifier circuit 22 is an example of a "signal processing circuit". Amplifier circuit 22 is connected to the input terminal of IC 20. Amplifier circuit 22 amplifies the sensor signal (analog signal) input from sensor 12 via the input terminal of IC 20 and outputs it to AD converter 24. Furthermore, as in... Figure 2 As will be explained later, the amplifier circuit 22 is able to output an amplified sensor signal with a data rate twice that of the input sensor signal by outputting the amplified sensor signal in each of the first and second periods that are alternately generated in the amplifier circuit 22.

[0040] The AD converter 24 is connected to the output terminal of the amplifier circuit 22. The AD converter 24 converts the amplified sensor signal output from the amplifier circuit 22 from an analog signal to a digital signal and outputs it to the digital processing circuit 26.

[0041] Digital processing circuit 26 is connected to the output terminal of AD converter 24. Digital processing circuit 26 performs prescribed digital signal processing (e.g., digital filtering) on ​​the sensor signal (digital signal) output from AD converter 24. In addition, digital processing circuit 26 sends the sensor signal after prescribed digital signal processing to MCU 30 via communication (e.g., I2C communication).

[0042] (Circuit structure of amplifier circuit 22)

[0043] Figure 2 This is a diagram showing the circuit structure of the amplifier circuit 22 in the first embodiment. (Example) Figure 2 As shown, the amplifier circuit 22 includes: input terminal VIN_P, input terminal VIN_M, amplifier AMP, output terminal VOUT_P, output terminal VOUT_M, first processing unit S / H1, second processing unit S / H2, multiple first switches PP1 and multiple second switches PP2.

[0044] The input terminals VIN_P and VIN_M are each of the two analog signals (non-inverting signal and inverting signal) that constitute the differential signal output from sensor 12.

[0045] The amplifier AMP is an example of a "signal processing unit". During the second period, it is able to amplify each of the two analog signals sampled by the sampling capacitors Cs11 and Cs12 of the first processing unit S / H1 (described later) with a specified gain, and output each of the two amplified analog signals.

[0046] Furthermore, during the first period, the amplifier AMP is able to amplify each of the two analog signals sampled by the sampling capacitors Cs21 and Cs22 of the second processing unit S / H2 (described later) with a predetermined gain, and output each of the two amplified analog signals.

[0047] The output terminals VOUT_P and VOUT_M output each of the two amplified analog signals (non-inverting signal and inverting signal) from the amplifier AMP to the external amplifier circuit 22.

[0048] The first processing unit S / H1 has a sampling capacitor Cs11 and a feedback capacitor Cf11 connected in series, and a sampling capacitor Cs12 and a feedback capacitor Cf12 connected in series.

[0049] Sampling capacitor Cs11 is connected to input terminal VIN_P via first switch PP1 during the first period to sample the analog signal (non-inverting signal) input from input terminal VIN_P. Sampling capacitor Cs12 is connected to input terminal VIN_M via first switch PP1 during the first period to sample the analog signal (inverting signal) input from input terminal VIN_M.

[0050] The analog signal (non-inverting signal) sampled by the sampling capacitor Cs11 is amplified by the amplifier AMP by being transmitted to the feedback capacitor Cf11 in the second period following the first period in which the analog signal (non-inverting signal) was sampled, and is output from the output terminal VOUT_P.

[0051] The analog signal (inverted signal) sampled by the sampling capacitor Cs12 is amplified by the amplifier AMP by being transmitted to the feedback capacitor Cf12 in the second period following the first period of sampling of the analog signal (inverted signal), and is output from the output terminal VOUT_M.

[0052] The second processing unit S / H2 has a sampling capacitor Cs21 and a feedback capacitor Cf21 connected in series, and a sampling capacitor Cs22 and a feedback capacitor Cf22 connected in series.

[0053] During the second period, sampling capacitor Cs21 is connected to input terminal VIN_P via second switch PP2 to sample the analog signal (non-inverting signal) input from input terminal VIN_P. During the second period, sampling capacitor Cs22 is connected to input terminal VIN_M via second switch PP2 to sample the analog signal (inverting signal) input from input terminal VIN_M.

[0054] The analog signal (non-inverting signal) sampled by the sampling capacitor Cs21 is amplified by the amplifier AMP by being transmitted to the feedback capacitor Cf21 in the first period following the second period in which the analog signal (non-inverting signal) was sampled, and is output from the output terminal VOUT_P.

[0055] The analog signal (inverted signal) sampled by the sampling capacitor Cs22 is amplified by the amplifier AMP by being transmitted to the feedback capacitor Cf22 in the first period following the second period in which the analog signal (inverted signal) is sampled, and is output from the output terminal VOUT_M.

[0056] Furthermore, in amplifier circuit 22, multiple first switches PP1 switch to the ON state during the first period and switch to the OFF state during the second period. Additionally, in amplifier circuit 22, multiple second switches PP2 switch to the OFF state during the first period and switch to the ON state during the second period.

[0057] Therefore, in the amplifier circuit 22, during the first period, the analog signals input to the input terminals VIN_P and VIN_M are sampled by the sampling capacitors Cs11 and Cs12, and the analog signals sampled by the sampling capacitors Cs21 and Cs22 are amplified by the amplifier AMP and output from the output terminals VOUT_P and VOUT_M.

[0058] In addition, in the amplifier circuit 22, during the second period, the analog signals input to the input terminals VIN_P and VIN_M are sampled by the sampling capacitors Cs21 and Cs22, and the analog signals sampled by the sampling capacitors Cs11 and Cs12 are amplified by the amplifier AMP and output from the output terminals VOUT_P and VOUT_M.

[0059] As a result, the amplifier circuit 22 is able to output the amplified analog signal in each of the alternately generated first and second periods, that is, it is able to double the data rate of the analog signal.

[0060] (Operation of amplifier circuit 22)

[0061] Next, refer to Figures 3-5 The operation of the amplifier circuit 22 in the first embodiment will be explained. Figure 3 This is a diagram showing the state of the amplifier circuit 22 in the first embodiment during the first period. Figure 4 This is a diagram showing the state of the amplifier circuit 22 in the second period of the first embodiment. Figure 5 This is a timing diagram showing the operation timing of the amplifier circuit 22 in the first embodiment.

[0062] like Figure 5 As shown, amplifier circuit 22 alternately generates the first period and the second period.

[0063] like Figure 3 and Figure 5 As shown, during the first period, all the first switches PP1 are switched to the ON position, and all the second switches PP2 are switched to the OFF position.

[0064] Therefore, during the first period, sampling capacitors Cs11 and Cs12 are connected to input terminals VIN_P and VIN_M, and the analog signals input from input terminals VIN_P and VIN_M are sampled by sampling capacitors Cs11 and Cs12.

[0065] Meanwhile, during the first period, sampling capacitors Cs21 and Cs22 are short-circuited to each other. The analog signals sampled by the sampling capacitors Cs21 and Cs22 are amplified by the amplifier AMP by being transmitted to the feedback capacitors Cf21 and Cf22, and output from the output terminals VOUT_P and VOUT_M.

[0066] On the other hand, such as Figure 4 as well as Figure 5 As shown, during the second period, all of the first switches PP1 are switched to open, and all of the second switches PP2 are switched to close.

[0067] Therefore, during the second period, sampling capacitors Cs21 and Cs22 are connected to input terminals VIN_P and VIN_M, and the analog signals input from input terminals VIN_P and VIN_M are sampled by sampling capacitors Cs21 and Cs22.

[0068] Meanwhile, during the second period, sampling capacitors Cs11 and Cs12 are short-circuited to each other. The analog signals sampled by the sampling capacitors Cs11 and Cs12 are amplified by the amplifier AMP by being transmitted to the feedback capacitors Cf11 and Cf12, and output from the output terminals VOUT_P and VOUT_M.

[0069] As a result, the amplifier circuit 22 is able to output the amplified analog signal in each of the alternately generated first and second periods, that is, it is able to double the data rate of the analog signal.

[0070] For example, in Figure 5 The example shown illustrates the situation where, during the initial first period, the analog signal ΔVIN1 input from the input terminal ΔVIN is sampled by the sampling capacitors Cs11 and Cs12.

[0071] In addition, Figure 5 In the example shown, it is illustrated that during the next second period, the analog signal ΔVIN2 input from the input terminal ΔVIN is sampled by sampling capacitors Cs21 and Cs22, and the analog signal ΔVIN1 sampled by sampling capacitors Cs11 and Cs12 is amplified and output from the output terminal ΔVOUT.

[0072] Furthermore, in Figure 5 In the example shown, it is illustrated that during the next first period, the analog signal ΔVIN3 input from the input terminal ΔVIN is sampled by the sampling capacitors Cs11 and Cs12, and the analog signal ΔVIN2 sampled by the sampling capacitors Cs21 and Cs22 is amplified and output from the output terminal ΔVOUT.

[0073] In addition, Figure 5In this context, the input terminal ΔVIN represents the difference between input terminals VIN_P and VIN_M. Similarly, the output terminal ΔVOUT represents the difference between output terminals VOUT_P and VOUT_M. Furthermore, the analog signal ΔVIN represents the difference between the analog signal (non-inverting signal) and the analog signal (inverting signal) that constitute the differential signal.

[0074] In addition, such as Figure 5 As shown, during the transition from the first period to the second period, there is a non-overlapping period in which PP1 and PP2 are not simultaneously activated.

[0075] As described above, the amplifier circuit 22 of the first embodiment includes: first sampling capacitors Cs11 and Cs12 and second sampling capacitors Cs21 and Cs22, which are connected to the input signal path of the analog signal; and an amplifier AMP, which performs amplification processing on the analog signal sampled by the first sampling capacitors Cs11 and Cs12 and the analog signal sampled by the second sampling capacitors Cs21 and Cs22. The amplifier circuit 22 is capable of performing parallel sampling of the analog signal of one of the first sampling capacitors Cs11 and Cs12 and the second sampling capacitors Cs21 and Cs22, as well as amplification processing based on the amplifier AMP on the analog signal sampled by the other of the first sampling capacitors Cs11 and Cs12 and the second sampling capacitors Cs21 and Cs22.

[0076] Therefore, by alternately setting the second period for outputting the analog signal sampled by the first sampling capacitors Cs11 and Cs12 and the first period for outputting the analog signal sampled by the second sampling capacitors Cs21 and Cs22, the amplifier circuit 22 of the first embodiment can output an amplified analog signal based on an amplifier AMP in each of the first and second periods. Thus, according to the amplifier circuit 22 of the first embodiment, only one amplifier is needed instead of two in the usual way, the increase in power consumption can be suppressed, and the data rate of the analog signal can be doubled.

[0077] Furthermore, the amplifier circuit 22 of the first embodiment alternately generates a first period and a second period. In the first period, the analog signal is sampled by the first sampling capacitors Cs11 and Cs12, and the amplifier AMP performs amplification processing on the analog signal sampled by the second sampling capacitors Cs21 and Cs22. In the second period, the analog signal is sampled by the second sampling capacitors Cs21 and Cs22, and the amplifier AMP performs amplification processing on the analog signal sampled by the first sampling capacitors Cs11 and Cs12.

[0078] Therefore, the amplifier circuit 22 of the first embodiment can output an amplified analog signal based on an amplifier AMP in each of the first and second periods. Thus, according to the amplifier circuit 22 of the first embodiment, the increase in power consumption can be suppressed, and the data rate of the analog signal can be doubled.

[0079] Furthermore, regarding the amplifier circuit 22 of the first embodiment, during the first period, multiple first switches PP1 are switched on, thereby connecting the input signal path of the analog signal to the first sampling capacitors Cs11 and Cs12, and the second sampling capacitors Cs21 and Cs22 are connected to the amplifier AMP. During the second period, multiple second switches PP2 are switched on, thereby connecting the input signal path of the analog signal to the second sampling capacitors Cs21 and Cs22, and the first sampling capacitors Cs11 and Cs12 are connected to the amplifier AMP.

[0080] Thus, the amplifier circuit 22 of the first embodiment can alternately switch the operation of the first period and the operation of the second period by simply controlling the multiple first switches PP1 and multiple second switches PP2 to be turned on.

[0081] [Second Implementation]

[0082] Next, refer to Figure 6 as well as Figure 7 The second embodiment will now be described. In the second embodiment, an example will be described of applying the structure described in the first embodiment, which doubles the data rate of the analog signal, to the averaging filter circuit 40.

[0083] (Circuit structure of averaging filter circuit 40)

[0084] Figure 6 This is a diagram showing the circuit structure of the averaging filter circuit 40 in the second embodiment. (See diagram for example.) Figure 6 As shown, the averaging filter circuit 40 (another example of a “signal processing circuit”) has: input terminal INP, input terminal INM, first processing unit AVG_FLT1, second processing unit AVG_FLT2, averaging filter 42, output terminal OUTP, and output terminal OUTM.

[0085] The input terminals INP and INM are each of the two analog signals (non-inverting signal and inverting signal) that constitute the differential signal.

[0086] The averaging filter 42 is another example of the "signal processing unit". It can output an analog signal (non-inverted signal) representing the average value of the four analog signals (non-inverted signals) sampled by the first sampling capacitors Cs1 to Cs4 on the positive side of the first processing unit AVG_FLT1 described later, and output an analog signal (inverted signal) representing the average value of the four analog signals (inverted signals) sampled by the first sampling capacitors Cs1 to Cs4 on the negative side of the first processing unit AVG_FLT1 described later.

[0087] In addition, the averaging filter 42 can output an analog signal (non-inverting signal) representing the average value of the four analog signals (non-inverting signals) sampled by the second sampling capacitors Cs5 to Cs8 on the positive side of the second processing unit AVG_FLT2 (described later), and output an analog signal (inverting signal) representing the average value of the four analog signals (inverting signals) sampled by the second sampling capacitors Cs5 to Cs8 on the negative side of the second processing unit AVG_FLT2 (described later).

[0088] The output terminals OUTP and OUTM output each of the two analog signals (non-inverted signal and inverted signal) after averaging and filtering from the averaging filter 42 to the outside of the averaging filter circuit 40.

[0089] Each first processing unit AVG_FLT1 has four first sampling capacitors Cs1 to Cs4 (denoted as "+-side first sampling capacitors Cs1 to Cs4") connected between the input terminal INP and the common voltage VCM. Additionally, each first processing unit AVG_FLT1 has four first sampling capacitors Cs1 to Cs4 (denoted as "-side first sampling capacitors Cs1 to Cs4") connected between the input terminal INM and the common voltage VCM.

[0090] Each of the first sampling capacitors Cs1 to Cs4 on the + side is provided with a switch SW1 to SW4 between it and the input terminal INP. Similarly, each of the first sampling capacitors Cs1 to Cs4 on the - side is provided with a switch SW1 to SW4 between it and the input terminal INM.

[0091] Each of the first sampling capacitors Cs1 to Cs4 on the + side is sequentially connected to the input terminal INP via switches SW1 to SW4 during the first period, and samples the analog signal (non-inverting signal) input from the input terminal INP. Each of the first sampling capacitors Cs1 to Cs4 on the - side is sequentially connected to the input terminal INM via switches SW1 to SW4 during the first period, and samples the analog signal (inverting signal) input from the input terminal INM.

[0092] The four analog signals (non-inverting signals) sampled by the first sampling capacitors Cs1 to Cs4 on the + side are transmitted to the averaging filter 42 via the second switch PP5678 during the second period following the first period of sampling of the analog signals (non-inverting signals), where they are averaged. As a result, an analog signal (non-inverting signal) representing the average value of the four analog signals (non-inverting signals) is output from the output terminal OUTP.

[0093] The four analog signals (inverted signals) sampled by the first sampling capacitors Cs1 to Cs4 are transmitted to the averaging filter 42 via the second switch PP5678 during the second period following the first period of sampling of the analog signals (inverted signals), where they are averaged. As a result, an analog signal (inverted signal) representing the average value of the four analog signals (inverted signals) is output from the output terminal OUTM.

[0094] Each of the second processing units AVG_FLT2 has four second sampling capacitors Cs5 to Cs8 (referred to as "second sampling capacitors Cs5 to Cs8 on the + side") connected between the input terminal INP and the common voltage VCM. Additionally, each of the second processing units AVG_FLT2 has four second sampling capacitors Cs5 to Cs8 (referred to as "second sampling capacitors Cs5 to Cs8 on the - side") connected between the input terminal INM and the common voltage VCM.

[0095] Furthermore, each of the second sampling capacitors Cs5 to Cs8 on the + side is provided with a switch SW5 to SW8 between it and the input terminal INP. Additionally, each of the second sampling capacitors Cs5 to Cs8 on the - side is provided with a switch SW5 to SW8 between it and the input terminal INM.

[0096] Each of the second sampling capacitors Cs5 to Cs8 on the + side is sequentially connected to the input terminal INP via switches SW5 to SW8 during the second period to sample the analog signal (non-inverting signal) input from the input terminal INP. Each of the second sampling capacitors Cs5 to Cs8 on the - side is sequentially connected to the input terminal INM via switches SW5 to SW8 during the second period to sample the analog signal (inverting signal) input from the input terminal INM.

[0097] The four analog signals (non-inverting signals) sampled by the second sampling capacitors Cs5 to Cs8 on the + side are transmitted to the averaging filter 42 via the first switch PP1234 during the first period following the second period in which the analog signals (non-inverting signals) are sampled, and are averaged by the averaging filter 42. As a result, an analog signal (non-inverting signal) representing the average value of the four analog signals (non-inverting signals) is output from the output terminal OUTP.

[0098] The four analog signals (inverted signals) sampled by the second sampling capacitors Cs5 to Cs8 on the - side are transmitted to the averaging filter 42 via the first switch PP1234 during the first period following the second period of sampling of the analog signals (inverted signals), where they are averaged. As a result, an analog signal (inverted signal) representing the average value of the four analog signals (inverted signals) is output from the output terminal OUTM.

[0099] Furthermore, in the averaging filter circuit 40, the plurality of first switches PP1234 are switched to the on state during the first period and to the off state during the second period. Additionally, in the averaging filter circuit 40, the plurality of second switches PP5678 are switched to the off state during the first period and to the on state during the second period.

[0100] Therefore, in the averaging filter circuit 40, during the first period, the analog signal (non-inverted signal) input to the input terminal INP is sequentially sampled by each of the first sampling capacitors Cs1 to Cs4 on the + side, and the analog signal (inverted signal) input to the input terminal INM is sequentially sampled by each of the first sampling capacitors Cs1 to Cs4 on the - side. Simultaneously, the four analog signals (non-inverted signals) sampled by each of the second sampling capacitors Cs5 to Cs8 on the + side are averaged by the averaging filter 42, and an analog signal (non-inverted signal) representing the average value of these four analog signals is output from the output terminal OUTP. Furthermore, simultaneously, the four analog signals (inverted signals) sampled by each of the second sampling capacitors Cs5 to Cs8 on the - side are averaged by the averaging filter 42, and an analog signal (inverted signal) representing the average value of these four analog signals is output from the output terminal OUTM.

[0101] Furthermore, in the averaging filter circuit 40, during the second period, the analog signal (non-inverted signal) input to the input terminal INP is sequentially sampled by each of the second sampling capacitors Cs5 to Cs8 on the + side, and the analog signal (inverted signal) input to the input terminal INM is sequentially sampled by each of the second sampling capacitors Cs5 to Cs8 on the - side. Simultaneously, the four analog signals (non-inverted signals) sampled by each of the first sampling capacitors Cs1 to Cs4 on the + side are averaged by the averaging filter 42, and an analog signal (non-inverted signal) representing the average value of these four analog signals is output from the output terminal OUTP. Also simultaneously, the four analog signals (inverted signals) sampled by each of the first sampling capacitors Cs1 to Cs4 on the - side are averaged by the averaging filter 42, and an analog signal (inverted signal) representing the average value of these four analog signals is output from the output terminal OUTM.

[0102] As a result, the averaging filter circuit 40 can output the averaged filtered analog signal (non-inverted signal and inverted signal) in each of the alternately generated first and second periods, that is, it can make the data rate of the analog signal double.

[0103] In addition, such as Figure 7 As shown, during the transition from the first period to the second period, a non-overlapping period is provided where PP1234 and PP5678 are not simultaneously turned on.

[0104] (Operation of the averaging filter circuit 40)

[0105] Figure 7 This is a timing diagram showing the operation timing of the averaging filter circuit 40 in the second embodiment.

[0106] like Figure 7 As shown, the averaging filter circuit 40 alternately generates the first period and the second period.

[0107] like Figure 7 As shown, during the first period, all first switches PP1234 are switched to ON, and all second switches PP5678 are switched to OFF. Additionally, as... Figure 7 As shown, during the first period, each of switches SW1 to SW4 is switched on in sequence.

[0108] Therefore, during the first period, each of the first sampling capacitors Cs1 to Cs4 on the + side is sequentially connected to the input terminal INP, and the analog signal (non-inverting signal) input from the input terminal INP is sampled by each of the first sampling capacitors Cs1 to Cs4 on the + side. Additionally, each of the first sampling capacitors Cs1 to Cs4 on the - side is sequentially connected to the input terminal INM, and the analog signal (inverting signal) input from the input terminal INM is sampled by each of the first sampling capacitors Cs1 to Cs4 on the - side.

[0109] Simultaneously, during the first period, the four analog signals (non-inverted signals) sampled by the second sampling capacitors Cs5 to Cs8 on the + side are transmitted to the averaging filter 42 and averaged by the averaging filter 42. As a result, an analog signal (non-inverted signal) representing the average value of the four analog signals (non-inverted signals) is output from the output terminal OUTP.

[0110] Additionally, during the first period, the four analog signals (inverted signals) sampled by the second sampling capacitors Cs5 to Cs8 on the side are transmitted to the averaging filter 42 and averaged. As a result, an analog signal (inverted signal) representing the average value of the four analog signals (inverted signals) is output from the output terminal OUTM.

[0111] On the other hand, such as Figure 7 As shown, during the second period, all first switches PP1234 are switched to open, and all second switches PP5678 are switched to close. Additionally, as... Figure 7 As shown, during the second period, each of switches SW5 to SW8 is switched on in sequence.

[0112] Therefore, during the second period, each of the second sampling capacitors Cs5 to Cs8 on the + side is sequentially connected to the input terminal INP, and the analog signal (non-inverting signal) input from the input terminal INP is sampled by each of the second sampling capacitors Cs5 to Cs8 on the + side. Additionally, each of the second sampling capacitors Cs5 to Cs8 on the - side is sequentially connected to the input terminal INM, and the analog signal (inverting signal) input from the input terminal INM is sampled by each of the second sampling capacitors Cs5 to Cs8 on the - side.

[0113] Simultaneously, during the second period, the four analog signals (non-inverted signals) sampled by the first sampling capacitors Cs1 to Cs4 on the + side are transmitted to the averaging filter 42 and averaged by the averaging filter 42. As a result, an analog signal (non-inverted signal) representing the average value of the four analog signals (non-inverted signals) is output from the output terminal OUTP.

[0114] Additionally, during the second period, the four analog signals (inverted signals) sampled by the first sampling capacitors Cs1 to Cs4 on the side are transmitted to the averaging filter 42 and averaged by the averaging filter 42. As a result, an analog signal (inverted signal) representing the average value of the four analog signals (inverted signals) is output from the output terminal OUTM.

[0115] As a result, the averaging filter circuit 40 is able to output the averaged filtered analog signal in each of the alternately generated first and second periods, that is, it is able to double the data rate of the analog signal.

[0116] For example, in Figure 5 In the example shown, it is illustrated that during the initial first period, each of the analog signals ΔVIN1 to ΔVIN4 input from the input terminal ΔVIN is sequentially sampled by each of the first sampling capacitors Cs1 to Cs4.

[0117] In addition, Figure 5 In the example shown, it is illustrated that during the next second period, each of the analog signals ΔVIN5 to ΔVIN8 input from the input terminal ΔVIN is sequentially sampled by each of the second sampling capacitors Cs5 to Cs8, and an analog signal representing the average value of the analog signals ΔVIN1 to ΔVIN4 sampled by each of the first sampling capacitors Cs1 to Cs4 is output from the output terminal ΔVOUT.

[0118] Furthermore, in Figure 5 In the example shown, it is illustrated that during the next first period, each of the analog signals ΔVIN9 to ΔVIN12 input from the input terminal ΔVIN is sequentially sampled by each of the first sampling capacitors Cs1 to Cs4, and an analog signal representing the average value of the analog signals ΔVIN5 to ΔVIN8 sampled by each of the second sampling capacitors Cs5 to Cs8 is output from the output terminal ΔVOUT.

[0119] In addition, Figure 7 In this diagram, the input terminal ΔVIN represents the difference between input terminals INP and INM. Similarly, the output terminal ΔVOUT represents the difference between output terminals OUTP and OUTM. Furthermore, the analog signal ΔVIN represents the difference between the analog signal (non-inverting signal) and the analog signal (inverting signal) that constitute the differential signal.

[0120] As described above, the averaging filter circuit 40 of the second embodiment includes: first sampling capacitors Cs1 to Cs4 and second sampling capacitors Cs5 to Cs8, which are connected to the input signal path of the analog signal; and an averaging filter 42, which performs averaging filtering processing on the analog signals sampled by the first sampling capacitors Cs1 to Cs4 and the analog signals sampled by the second sampling capacitors Cs5 to Cs8. The averaging filter circuit 40 is capable of performing averaging filtering processing based on the averaging filter 42 on the analog signals sampled by one of the first sampling capacitors Cs1 to Cs4 and the second sampling capacitors Cs5 to Cs8, and on the analog signals sampled by the other of the first sampling capacitors Cs1 to Cs4 and the second sampling capacitors Cs5 to Cs8 in parallel.

[0121] Therefore, the averaging filter circuit 40 of the second embodiment, by alternately setting a second period for outputting the analog signal sampled by the first sampling capacitors Cs1 to Cs4 and a first period for outputting the analog signal sampled by the second sampling capacitors Cs5 to Cs8, can output an analog signal after averaging filtering based on an averaging filter 42 in each of the first and second periods. Thus, according to the averaging filter circuit 40 of the second embodiment, the increase in power consumption can be suppressed, and the data rate of the analog signal can be doubled.

[0122] Furthermore, the averaging filter circuit 40 of the second embodiment alternately generates a first period and a second period. In the first period, the analog signal is sampled by the first sampling capacitors Cs1 to Cs4, and the averaging filter 42 performs averaging filtering processing on the analog signal sampled by the second sampling capacitors Cs5 to Cs8. In the second period, the analog signal is sampled by the second sampling capacitors Cs5 to Cs8, and the averaging filter 42 performs averaging filtering processing on the analog signal sampled by the first sampling capacitors Cs1 to Cs4.

[0123] Therefore, the averaging filter circuit 40 of the second embodiment can output an analog signal after averaging and filtering based on an averaging filter 42 in each of the first and second periods. Thus, the averaging filter circuit 40 of the second embodiment can suppress the increase in power consumption and double the data rate of the analog signal.

[0124] Furthermore, regarding the averaging filter circuit 40 of the second embodiment, during the first period, multiple first switches PP1234 are switched on, thereby connecting the input signal path of the analog signal to the first sampling capacitors Cs1 to Cs4, and the second sampling capacitors Cs5 to Cs8 are connected to the averaging filter 42. During the second period, multiple second switches PP5678 are switched on, thereby connecting the input signal path of the analog signal to the second sampling capacitors Cs5 to Cs8, and the first sampling capacitors Cs1 to Cs4 are connected to the averaging filter 42.

[0125] Thus, the averaging filter circuit 40 of the second embodiment can alternately switch the operation of the first period and the operation of the second period by simply controlling the multiple first switches PP1234 and the multiple second switches PP5678 to be turned on.

[0126] [Third Implementation Method]

[0127] Next, refer to Figure 8 as well as Figure 9 The third embodiment will now be described. In the third embodiment, as a variation of the amplifier circuit 22 described in the first embodiment, an amplifier circuit 22A with offset adjustment function will be described.

[0128] (Circuit structure of amplifier circuit 22A)

[0129] Figure 8 This is a diagram showing the circuit structure of the amplifier circuit 22A in the third embodiment. (See diagram for example.) Figure 2 As shown, the amplifier circuit 22A differs from the amplifier circuit 22 described in the first embodiment in that it also has two DACs (Digital-to-Analog Converters) 50.

[0130] The two DA converters 50 have the same circuit structure. Both DA converters 50 are capacitor-type DA converters with multiple capacitors, functioning as an "offset adjustment circuit".

[0131] One of the two DA converters 50 (hereinafter referred to as "DA converter 50A") has its output terminal VOUTP connected to the connection point P1 between the sampling capacitor Cs11 and the feedback capacitor Cf11 of the first processing unit S / H1, and its output terminal VOUTM connected to the connection point P2 between the sampling capacitor Cs12 and the feedback capacitor Cf12 of the first processing unit S / H1. Thus, DA converter 50A can adjust the offset of each of the two analog signals (non-inverting signal and inverting signal) transmitted to the feedback capacitors Cf11 and Cf12.

[0132] The output terminal VOUTP of the other DA converter 50 (hereinafter referred to as "DA converter 50B") is connected to the connection point P3 between the sampling capacitor Cs21 and the feedback capacitor Cf21 of the second processing unit S / H2, and the output terminal VOUTM is connected to the connection point P4 between the sampling capacitor Cs22 and the feedback capacitor Cf22 of the second processing unit S / H2. Thus, DA converter 50B can adjust the offset of each of the two analog signals (non-inverting signal and inverting signal) transmitted to the feedback capacitors Cf21 and Cf22.

[0133] Furthermore, "offset adjustment" refers to reducing (preferably to 0) the voltage offset of the sensor signal before it is amplified by the amplifier AMP. By performing "offset adjustment," even when the sensor signal is amplified by the amplifier AMP at high gain, the voltage of the sensor signal output from the amplifier AMP can be kept within the specified upper and lower threshold values.

[0134] (Circuit structure of DA converter 50)

[0135] Figure 9 This is a diagram showing the circuit structure of the DA converter 50 according to the third embodiment.

[0136] like Figure 9 As shown, the DA converter 50 has a signal line 51P connected to the output terminal VOUTP and a signal line 51M connected to the output terminal VOUTM.

[0137] In the DA converter 50, five capacitors C1P, C2P, C3P, C4P, and C5P are connected to signal line 51P. These five capacitors are also connected to connection points VREFN, OSP, bit0P, bit1P, and bit2P, respectively. Switch SW1P connects these five capacitors to the common voltage VCM.

[0138] Additionally, eight capacitors C6P, C7P, C8P, C9P, C10P, C11P, C12P, and C13P are connected to signal line 51P. These eight capacitors are also connected to connection points bit3P, DEC1P, DEC2P, DEC3P, DEC4P, DEC5P, DEC6P, and DEC7P, respectively. Switch SW2P connects these eight capacitors to the common voltage VCM.

[0139] Switch SW3P is connected to the output terminal VOUTP, which allows it to be connected to the common voltage VCM.

[0140] Additionally, in signal line 51P, capacitor Csplit2 is positioned between capacitors C1P to C13P and the output terminal VOUTP. Therefore, the DA converter 50 performs weighting on capacitors C1P to C13P based on capacitor Csplit2.

[0141] Furthermore, in signal line 51P, capacitor Csplit1 is positioned between capacitors C1P to C5P and capacitors C6P to C13P. Therefore, the DA converter 50 further weights capacitors C1P to C5P based on capacitor Csplit1.

[0142] Additionally, in the DA converter 50, five capacitors C1M, C2M, C3M, C4M, and C5M are connected to signal line 51M. These five capacitors are also connected to connection points VREFN, OSM, bit0M, bit1M, and bit2M, respectively. Switch SW1M connects these five capacitors to the common voltage VCM.

[0143] Additionally, eight capacitors C6M, C7M, C8M, C9M, C10M, C11M, C12M, and C13M are connected to signal line 51M. These eight capacitors are also connected to connection points bit3M, DEC1M, DEC2M, DEC3M, DEC4M, DEC5M, DEC6M, and DEC7M, respectively. Switch SW2M connects these eight capacitors to the common voltage VCM.

[0144] The switch SW3M is connected to the output terminal VOUTM, which allows it to be connected to the common voltage VCM.

[0145] Additionally, in signal line 51M, capacitor Csplit2 is positioned between capacitors C1M to C13M and the output terminal VOUTM. Therefore, the DA converter 50 performs weighting on capacitors C1M to C13M based on capacitor Csplit2.

[0146] Furthermore, in signal line 51M, capacitor Csplit1 is positioned between capacitors C1M to C5M and capacitors C6M to C13M. Therefore, the DA converter 50 further weights capacitors C1M to C5M based on capacitor Csplit1.

[0147] Switches SW21 and SW22 are provided at each of the aforementioned connection points. Figure 9 As representative examples, switches SW21 and SW22 installed in connection section DEC2M and connection section DEC7M are shown. Each of these connection sections is switched on by switch SW21 to connect to the reference voltage VREFP. Furthermore, each of these connection sections is switched on by switch SW22 to connect to the reference voltage VREFN.

[0148] (An example of binary code used in DA converter 50)

[0149] Figure 10 This is a diagram illustrating an example of the binary code used in the DA converter 50 of the third embodiment.

[0150] In the DA converter 50 of the third embodiment, Figure 9 The four connection parts shown, bit0, bit1, bit2, and bit3, can be connected via... Figure 10 The binary code shown is used to switch whether to drive (i.e., whether to switch SW21 and SW22 during charge transfer).

[0151] like Figure 10 As shown, the binary code in this embodiment can use a numerical range of 0 to 15. Additionally, as... Figure 10 As shown, each binary code can be represented by a 4-bit binary number. Furthermore, in this embodiment, each of the 4 bits is assigned to each of the 4 connection parts bit0, bit1, bit2, and bit3.

[0152] In addition, Figure 10 In the diagram, the connection part with a corresponding bit of "0" indicates that the connection part is not driven (that is, the switches SW21 and SW22 are not switched during charge transfer, thereby keeping the potential of the capacitor connected to the connection part unchanged).

[0153] In addition, Figure 10 In the diagram, the connection part with a corresponding bit of "1" indicates that the connection part is driven (that is, the switches SW21 and SW22 are switched during charge transfer, thereby causing the potential of the capacitor connected to the connection part to change).

[0154] In addition, Figure 10 The diagram shows capacitors whose potentials change due to the switching of switches SW21 and SW22 for each of the four connection bits (bit0, bit1, bit2, and bit3). Figure 9The capacitance values ​​of capacitors C3P, C4P, C5P, C6P, or capacitors C3M, C4M, C5M, C6M are shown. However, capacitors C6P and C6M are weighted based on Csplit1 to obtain a capacitance value equivalent to 0.8pF.

[0155] For example, in Figure 10 In the example shown, the capacitance value of the capacitor whose potential changes is set to "0.1pF" by driving connection bit 0. Furthermore, the capacitance value of the capacitor whose potential changes is set to "0.2pF" by driving connection bit 1. Additionally, the capacitance value of the capacitor whose potential changes is set to "0.4pF" by driving connection bit 2. And, the capacitance value of the capacitor whose potential changes is set to 0.8pF by driving connection bit 3, weighted based on capacitor Csplit1.

[0156] Therefore, the DA converter 50 of the third embodiment can arbitrarily set the total capacitance value of the capacitor that causes the potential to change due to the four connection bits bit0, bit1, bit2, and bit3 during charge transfer by inputting binary code from an external controller, in units of 0.1pF or between 0.0pF and 1.5pF.

[0157] For example, the DA converter 50 of the third embodiment can drive two connection parts bit0 and bit1 during charge transfer by inputting the binary code "3" from an external controller, and can set the total capacitance value of the capacitor that changes during charge transfer to "0.3pF".

[0158] (An example of a thermometer code used in the DA converter 50)

[0159] Figure 11 This is a diagram illustrating an example of the thermometer code used in the DA converter 50 of the third embodiment.

[0160] In the DA converter 50 of the third embodiment, Figure 9 The seven connecting parts shown, DEC1, DEC2, DEC3, DEC4, DEC5, DEC6, and DEC7, can be connected via... Figure 11 Whether the temperature code switching shown is driven (i.e., whether the switching of switches SW21 and SW22 is performed during charge transfer).

[0161] like Figure 11 As shown, the temperature code in this embodiment can use a numerical range of 0 to 7. Furthermore, as... Figure 11 As shown, each thermometer code indicates the number of connections driven during charge transfer.

[0162] In addition, Figure 11The diagram shows a connection marked "0" indicating that the connection is not driven (i.e., the switches SW21 and SW22 are not switched during charge transfer, thereby preventing the potential of the capacitor connected to the connection from changing).

[0163] In addition, Figure 11 The diagram shows a connection marked "1" indicating that the connection is driven (i.e., the switching of switches SW21 and SW22 is performed during charge transfer, thereby changing the potential of the capacitor connected to the connection).

[0164] In addition, Figure 11 In the diagram, for each of the seven connection points DEC1 to DEC7, a capacitor whose potential changes due to the switching of switches SW21 and SW22 is shown (i.e., Figure 9 The capacitance value of each of capacitors C7P to C13P, or each of capacitors C7M to C13M, shown.

[0165] For example, in Figure 11 In the example shown, for each of the seven connection parts DEC1 to DEC7, the capacitance value of the capacitor connected to that connection part is "0.2pF". Therefore, the capacitance value of the capacitor that causes the potential to change by driving the connection part is "0.2pF".

[0166] Therefore, the DA converter 50 of the third embodiment can arbitrarily set the total capacitance value of the capacitors whose potential changes due to the seven connection parts DEC1 to DEC7 during charge transfer in units of 0.2pF, between 0.0pF and 1.4pF, by inputting thermometer code from an external controller.

[0167] For example, the DA converter 50 of the third embodiment can drive three connection parts DEC1, DEC2, and DEC3 during charge transfer by inputting the thermometer code "3" from an external controller, and can set the total capacitance value of the capacitor that changes during charge transfer to "0.6pF".

[0168] also, Figure 10 The binary code shown uses 4 bits of the 8-bit control code input from an external controller. Additionally, Figure 11 The thermometer code shown uses the other 3 bits of the 8-bit control code input from an external controller. That is, the 8-bit control code input from the external controller can simultaneously indicate binary code and thermometer code to the DA converter 50.

[0169] Using a binary code structure reduces the total area of ​​multiple capacitors, but the deviation between the capacitors is relatively large, which may reduce the accuracy of offset adjustment. On the other hand, using a thermometer code structure reduces the deviation between the capacitors, thus improving the accuracy of offset adjustment, but the total area of ​​the capacitors may increase. The DA converter 50 of the third embodiment has both a binary code structure and a thermometer code structure, thus suppressing the total area of ​​the capacitors and improving the accuracy of offset adjustment.

[0170] Furthermore, the 8-bit control code input from the external controller can also specify, through another 1 bit, that the potential of each of the multiple capacitors connected to the output terminal VOUTM and the multiple capacitors connected to the output terminal VOUTP be set to the reference voltage VREFP or the reference voltage VREFN.

[0171] For example, when one of the other bits in the 8-bit control code is "1", the DA converter 50 sets the potential of the multiple capacitors connected to the output terminal VOUTP (the potential of the first period described later) to the reference voltage VREFN by sampling under the VCM reference, and sets the potential of the multiple capacitors connected to the output terminal VOUTM (the potential of the first period described later) to the reference voltage VREFP by sampling under the VCM reference.

[0172] Conversely, when one of the other bits in the 8-bit control code is “0”, the DA converter 50 sets the potential of the multiple capacitors connected to the output terminal VOUTP (the potential of the first period described later) to the reference voltage VREFP by sampling under the VCM reference, and sets the potential of the multiple capacitors connected to the output terminal VOUTM (the potential of the first period described later) to the reference voltage VREFN by sampling under the VCM reference.

[0173] (Action of DA converter 50)

[0174] Figure 12 This is a timing diagram showing the operation timing of the DA converter 50 in the third embodiment. Figure 12 As representative examples, the operation of connecting parts DEC2M and DEC7M is shown. Additionally, in... Figure 12 The example shown illustrates the switching of the connection destination when charge transfer is performed on the connection part DEC2M according to the thermometer code input from the external controller, and the switching of the connection destination when no charge transfer is performed on the connection part DEC7M.

[0175] like Figure 12As shown, the DA converter 50 alternately generates a first period and a second period.

[0176] like Figure 12 As shown, during the first period, each of the connecting parts DEC2M and DEC7M connects via switch SW22 (see reference). Figure 9 Switch to ON and turn on switch SW21 (refer to) Figure 9 Switch to disconnect to switch the connection destination to the reference voltage VREFN.

[0177] Therefore, during the first period, the capacitor C8M (refer to) connected to the connecting part DEC2M Figure 9 ) and capacitor C13M connected to the connecting part DEC7M (see reference) Figure 9 All of these are sampled under the VCM reference to make the potential become the reference voltage VREFN.

[0178] In addition, such as Figure 12 As shown, during the second period, the connection destination of the connection part DEC7M remains at the reference voltage VREFN. Therefore, during the second period, the potential of the capacitor C13M connected to the connection part DEC7M remains at the reference voltage VREFN. As a result, during the second period, charge is not transferred from the capacitor C13M to the output terminal VOUTM.

[0179] On the other hand, during the second period, regarding the connection part DEC2M, by switching switch SW22 to open and switch SW21 to open, the connection destination is switched to the reference voltage VREFP. Therefore, during the second period, the potential of the capacitor C8M connected to the connection part DEC2M is switched to the reference voltage VREFP. As a result, during the second period, charge is transferred from the capacitor C8M to the output terminal VOUTM.

[0180] Thus, the DA converter 50 of the third embodiment can transfer charge from the capacitor to the output terminal VOUTM by shifting the potential of at least one of the three capacitors C3M to C5M connected to the signal line 51M and the eight capacitors C6M to C13M connected to the signal line 51M from the reference voltage VREFN to the reference voltage VREFP during charge transfer. Therefore, the DA converter 50 of the third embodiment can adjust the offset of the analog signal (inverting signal) input to the amplifier AMP through the output terminal VOUTM according to the total capacitance value of the capacitors transferring charge.

[0181] For example, if the offset of the analog signal output from sensor 12 is known in advance, an external controller uses an 8-bit control code (containing binary code and thermometer code) to instruct one or more capacitors for charge transfer to the DA converter 50 so that the offset becomes 0, thereby enabling the offset of the analog signal input to amplifier AMP to be 0.

[0182] In addition, Figure 12 The text describes the adjustment of the offset relative to the non-inverting signal in the output terminal VOUTM of the DA converter 50, but... Figure 9 As shown, the structures of the non-inverting signal side and the inverting signal side of the DA converter 50 are identical, therefore, the adjustment of the offset relative to the inverting signal in the output terminal VOUTP of the DA converter 50 is also identical.

[0183] That is, the DA converter 50 of the third embodiment can transfer charge from the capacitor to the output terminal VOUTP by shifting the potential of at least one of the three capacitors C3P to C5P connected to the signal line 51P and the eight capacitors C6P to C13P connected to the signal line 51P from the reference voltage VREFP to the reference voltage VREFN during charge transfer. Thus, the DA converter 50 of the third embodiment can adjust the offset of the analog signal (non-inverting signal) input to the amplifier AMP through the output terminal VOUTP according to the total capacitance value of the capacitors transferring charge.

[0184] In addition, such as Figure 12 As shown, in the DA converter 50, during the transition from the first period to the second period, there is a non-overlapping period in which switches SW21 and SW22 are not turned on at the same time.

[0185] In the first period of amplifier circuit 22, the analog signals input to input terminals VIN_P and VIN_M are sampled by sampling capacitors Cs11 and Cs12, and sampling at the VCM reference is performed in DA converter 50A during the first period. Additionally, in the first period of amplifier circuit 22, the analog signals sampled by sampling capacitors Cs21 and Cs22 are amplified by amplifier AMP and output from output terminals VOUT_P and VOUT_M, and charge transfer is performed in DA converter 50B during the second period.

[0186] In the second period of amplifier circuit 22, the analog signals input to input terminals VIN_P and VIN_M are sampled by sampling capacitors Cs21 and Cs22, and sampling at the VCM reference is performed in the first period of DA converter 50B. Additionally, in the second period of amplifier circuit 22, the analog signals sampled by sampling capacitors Cs11 and Cs12 are amplified by amplifier AMP and output from output terminals VOUT_P and VOUT_M, and charge transfer is performed in the second period of DA converter 50A.

[0187] (Operating principle of DA converter 50)

[0188] Figure 13 This is a diagram used to explain the operating principle of the DA converter 50 in the third embodiment.

[0189] exist Figure 13 In the circuit shown, the total capacitance of node Vx, including capacitors C0, C1, C2 and Csplit2, is 3.2pF (1.6pF + 0.1pF + 0.1pF + 1.4pF).

[0190] exist Figure 13 In the circuit shown, during the transfer of charge sampled by each capacitor, the amount of potential reduction in node Vx is calculated by the following mathematical formula (1) when the potential of capacitor C1 (0.1pF) is shifted from reference voltage VREFP to reference voltage VREFN.

[0191] 0.1pF / 3.2pF(VREFP-VREFN)...(1)

[0192] In addition, Figure 13 In the circuit shown, the change in output at the output terminal VOUT is determined by the ratio of the capacitors. Therefore, in Figure 13 In the circuit shown, the change in the output of the output terminal VOUT is obtained by the following mathematical formula (2).

[0193] ΔVOUT=0.1pF / 3.2pF×1.6pF / 4pF(VREFP-VREFN)=0.0125(VREFP-VREFN)...(2)

[0194] The DA converter 50 of the third embodiment utilizes this principle to adjust the output of the output terminal VOUT by changing the potential of one or more capacitors during the transmission of charge sampled by each capacitor; that is, it adjusts the offset of the analog signal. Furthermore, the operating principle is explained using specific numerical values, but this is only one example, and any numerical value can be used.

[0195] (An example of the output voltage value of an analog signal)

[0196] Figure 14 as well as Figure 15 This is a graph showing an example of the output voltage value of the analog signal output from the amplifier AMP when the DA converter 50 of the third embodiment is not provided. Figure 16 This is a graph showing an example of the output voltage value of the analog signal output from the amplifier AMP when the DA converter 50 of the third embodiment is provided.

[0197] Figure 14 This represents an example of the output voltage value of an analog signal when the gain of the amplifier AMP is set to 64 times. Figure 15 and Figure 16 This represents an example of the output voltage value of an analog signal when the gain of the amplifier AMP is set to 128 times.

[0198] like Figure 15 As shown, without offset adjustment based on DA converter 50, and with the analog signal amplified at high gain, the offset component is also amplified at high gain. Therefore, the output voltage value of the analog signal may exceed both the upper and lower thresholds.

[0199] On the other hand, such as Figure 16 As shown, when the offset component of the analog signal input to the amplifier AMP is set to 0 by performing offset adjustment based on the DA converter 50, the offset component will not be amplified even when the analog signal is amplified at high gain. Therefore, the output voltage value of the analog signal can be kept below the upper and lower threshold values.

[0200] As described above, the IC20 of the third embodiment includes: an amplifier AMP that amplifies an analog signal; and a DA converter 50 disposed in front of the amplifier AMP that adjusts the offset of the analog signal before it is amplified by the amplifier AMP.

[0201] Therefore, IC20 in the third embodiment can reduce the offset contained in the analog signal output from the amplifier. Thus, even when the analog signal is amplified at high gain by the amplifier AMP, IC20 in the third embodiment can ensure that the output voltage value of the analog signal output from the amplifier AMP does not exceed a threshold.

[0202] In particular, in the IC20 of the third embodiment, a capacitor-type DA converter 50 with multiple capacitors is used as the offset adjustment circuit. According to the control code input from the outside, the potential of at least one of the multiple capacitors is changed, thereby adjusting the offset of the analog signal.

[0203] Therefore, the IC20 in the third embodiment does not generate 1 / f noise that may occur when offset adjustment is performed using an operational amplifier and a current mirror circuit, and can adjust the offset of the analog signal.

[0204] The above describes one embodiment of the present invention in detail, but the present invention is not limited to these embodiments. Various modifications or alterations can be made within the scope of the spirit of the present invention as described in the claimed technical solution.

[0205] For example, in the third embodiment, a DA converter 50 is provided in the amplifier circuit 22 of the first embodiment, but it is not limited thereto. For example, the DA converter 50 of the third embodiment may also be provided in an amplifier circuit other than the amplifier circuit 22 of the first embodiment.

[0206] In addition, in the third embodiment, a DA converter 50 is provided as an example of an "offset adjustment circuit", but it is not limited to this. The "offset adjustment circuit" can be any structure as long as it is a structure that can at least adjust the offset of the analog signal in the preamplifier stage.

[0207] in addition, Figure 17 This is a diagram showing the structure of a load detection device 100 according to one embodiment. Figure 17 As shown, the IC20 described in the above embodiments, for example, in a load detection device 100 that detects the load applied to an object 150, serves as a strain gauge that outputs an analog signal. Figure 17 The strain sensors 112 and 114 shown are connected to a microcomputer that performs digital processing. Figure 17 The so-called AFE (Analog Front End) is connected between the signal processing circuit 130 shown. Figure 17 The AFE chip 120 shown is used. However, it is not limited to this; IC 20 can also be connected to sensors other than strain gauges, and can also be used in system structures other than the detection system 10 described in the above embodiments.

[0208] This international application claims priority based on Japanese Patent Application No. 2020-070473, filed on April 9, 2020, the entire contents of which are incorporated herein by reference.

[0209] Symbol Explanation

[0210] 10 Detection System

[0211] 12 sensors

[0212] 20 IC

[0213] 22, 22A Amplifier Circuit (Signal Processing Circuit)

[0214] AMP amplifier (signal processing unit)

[0215] Cf11 and Cf12 feedback capacitors

[0216] Cf21 and Cf22 feedback capacitors

[0217] Cs11 and Cs12 sampling capacitors (first sampling capacitor)

[0218] Cs21 and Cs22 sampling capacitors (second sampling capacitors)

[0219] PP1 First Switch

[0220] PP2 Second Switch

[0221] S / H1 First Processing Unit

[0222] S / H2 Second Processing Unit

[0223] VIN_P and VIN_M input terminals

[0224] VOUT_P and VOUT_M output terminals

[0225] 24 AD converter

[0226] 26 Digital Processing Circuits

[0227] 30 MCU

[0228] 40. Averaging Filter Circuit (Signal Processing Circuit)

[0229] 42. Averaging Filter (Signal Processing Unit)

[0230] AVG_FLT1 First Processing Unit

[0231] AVG_FLT2 Second Processing Unit

[0232] INP and INM input terminals

[0233] OUTP and OUTM output terminals

[0234] Cs1~Cs4 First sampling capacitor

[0235] Cs5~Cs8 Second sampling capacitor

[0236] PP1234 First Switch

[0237] PP5678 Second Switch

[0238] SW1~SW8 switches

[0239] 50 DA Converter (Offset Adjustment Circuit)

[0240] VOUTP and VOUTM output terminals

[0241] C1P~C13P, C1M~C13M capacitors

[0242] Csplit1 and Csplit2 capacitors

[0243] SW21 and SW22 switches

[0244] SW1P, SW2P, SW3P switches

[0245] SW1M, SW2M, SW3M switches

[0246] 51P, 51M signal lines

[0247] VREFN, OSP, OSM connection parts

[0248] bit0P, bit1P, bit2P, bit3P connection section

[0249] bit0M, bit1M, bit2M, bit3M connection section

[0250] Connecting parts for DEC1P~DEC7P and DEC1M~DEC7M.

Claims

1. A signal processing circuit, characterized in that, The signal processing circuit has: The first sampling capacitor (Cs11, Cs12) and the second sampling capacitor (Cs21, Cs22) are connected at one end to the input signal path of the analog signal and at the other end to a common voltage. as well as A first feedback capacitor (Cf11, Cf12) and a second feedback capacitor (Cf21, Cf22) are provided. One end of the first feedback capacitor is connected to the first sampling capacitor (Cs11, Cs12), and the other end of the first feedback capacitor is connected to the output terminal. One end of the second feedback capacitor is connected to the second sampling capacitor (Cs21, Cs22), and the other end of the second feedback capacitor is connected to the output terminal. A signal processing unit (AMP) includes an amplifier that performs prescribed processing on the analog signal sampled by the first sampling capacitor (Cs11, Cs12) and the analog signal sampled by the second sampling capacitor (Cs21, Cs22). Multiple first switches (pp1) are configured between the input signal and the first sampling capacitors (Cs11, Cs12), between the first feedback capacitors (Cf11, Cf12) and the common voltage, between the second feedback capacitors (Cf21, Cf22) and the output terminal, and between the second sampling capacitors (Cs21, Cs22) and the signal processing unit. Multiple second switches (pp2) are configured between the input signal and the second sampling capacitors (Cs21, Cs22), between the second feedback capacitors (Cf21, Cf22) and the common voltage, between the first feedback capacitors (Cf11, Cf12) and the output terminal, and between the first sampling capacitors (Cs11, Cs12) and the signal processing unit. The signal processing circuit alternately generates a first period and a second period. During the first period, by switching multiple first switches (pp1) to on, the input signal path is connected to the first sampling capacitor, and the second sampling capacitor is connected to the signal processing unit, which performs prescribed processing on the analog signal sampled by the second sampling capacitor. During the second period, by switching multiple second switches (pp2) to the on, the input signal path is connected to the second sampling capacitor, and the first sampling capacitor is connected to the signal processing unit, which performs prescribed processing on the analog signal sampled by the first sampling capacitor.

2. The signal processing circuit according to claim 1, characterized in that, The data rate of the output analog signal is twice that of the case where sampling is performed using only the first sampling capacitor or the second sampling capacitor.

3. The signal processing circuit according to claim 1, characterized in that, The signal processing circuit further includes an offset adjustment circuit disposed in front of the amplifier to adjust the offset of the analog signal before it is amplified by the amplifier.

4. The signal processing circuit according to any one of claims 1 to 3, characterized in that, The specified processing method is averaging filtering.

5. The signal processing circuit according to claim 4, characterized in that, The first sampling capacitor is composed of multiple first capacitors (Cs1 to Cs4). The first switch includes third switches (SW1 to SW4) respectively disposed between the plurality of first capacitors (Cs1 to Cs4) and the input signal path. The second sampling capacitor is composed of multiple second capacitors (Cs5 to Cs8). The second switch includes a fourth switch (SW5-SW8) respectively disposed between the plurality of second capacitors (Cs5-Cs8) and the input signal path. During the first period, the third switch is sequentially switched to ON. During the second period, the fourth switch is switched to ON in sequence.

6. The signal processing circuit according to claim 1, characterized in that, The signal processing circuit also has: The third sampling capacitor (Cs12) and the fourth sampling capacitor (Cs22) are connected at one end to the second input signal path of the second analog signal, and at the other end to the common voltage. A third feedback capacitor (Cf12) and a fourth feedback capacitor (Cf22) are used. One end of the third feedback capacitor is connected to the third sampling capacitor (Cs12), and the other end of the third feedback capacitor is connected to the second output terminal. One end of the fourth feedback capacitor is connected to the second sampling capacitor (Cs21), and the other end of the fourth feedback capacitor is connected to the second output terminal. The plurality of first switches (pp1) are configured between the input signal and the third sampling capacitor (Cs12), between the third feedback capacitor (Cf12) and the common voltage, between the fourth feedback capacitor (Cf22) and the output terminal, and between the fourth sampling capacitor (Cs22) and the signal processing unit. The plurality of second switches (pp2) are configured between the input signal and the fourth sampling capacitor (Cs22), between the fourth feedback capacitor (Cf22) and the common voltage, between the third feedback capacitor (Cf12) and the output terminal, and between the third sampling capacitor (Cs12) and the signal processing unit. During the first period, by switching the plurality of first switches (pp1) to on, the second input signal path is connected to the third sampling capacitor, and the fourth sampling capacitor is connected to the signal processing unit, which performs prescribed processing on the analog signal sampled by the fourth sampling capacitor. During the second period, by switching the plurality of second switches (pp2) to the on, the input signal path is connected to the fourth sampling capacitor, and the third sampling capacitor is connected to the signal processing unit, which performs prescribed processing on the analog signal sampled by the third sampling capacitor.

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