Methods, systems, and non-transitory computer storage media for use in memory devices

Abstract

This disclosure relates to scan segments in a memory device. A memory system includes a memory device and a processing means operatively coupled to the memory device. The processing means performs operations including: identifying one or more forced scan word lines and one or more remaining word lines of the memory device; performing multiple scan iterations relative to a plurality of pages of the memory device, such that performing each scan iteration includes: identifying one or more predetermined scan word lines of the memory device among the remaining word lines; scanning a subset of pages of the memory device that are addressable by the forced scan word lines and the predetermined scan word lines; wherein a combination of a first plurality of pages addressable by the predetermined scan word lines selected by the multiple scan iterations and a second plurality of pages addressable by the forced word lines includes the plurality of pages of the memory device.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to scan segment strategies based on memory degradation and system requirements. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, the host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, this disclosure provides a system comprising: a memory device; and a processing means operatively coupled to the memory device to perform operations including: identifying one or more forced scan word lines and one or more remaining word lines of the memory device; performing a plurality of scan iterations relative to a plurality of pages of the memory device, such that performing each scan iteration includes: identifying one or more predetermined scan word lines of the memory device among the remaining word lines; scanning a subset of pages of the memory device addressable by the forced scan word lines and the predetermined scan word lines; wherein a combination of a first plurality of pages addressable by the predetermined scan word lines selected by the plurality of scan iterations and a second plurality of pages addressable by the forced word lines comprises a plurality of pages of the memory device.

[0004] In another aspect, this disclosure further provides a method comprising: identifying one or more forced scan word lines and one or more remaining word lines of a memory device by a processing means; performing a plurality of scan iterations relative to a plurality of pages of the memory device, such that performing each scan iteration comprises: identifying one or more predetermined scan word lines of the memory device among the remaining word lines; scanning a subset of pages of the memory device addressable by the forced scan word lines and the predetermined scan word lines; wherein a combination of a first plurality of pages addressable by the predetermined scan word lines selected by the plurality of scan iterations and a second plurality of pages addressable by the forced word lines comprises a plurality of pages of the memory device.

[0005] In another aspect, this disclosure further provides a non-transitory computer-readable storage medium including instructions that, when executed by a processing means, cause the processing means to perform operations including: identifying one or more forced scan word lines and one or more remaining word lines of the memory means; performing a plurality of scan iterations relative to a plurality of pages of the memory means, such that performing each scan iteration includes: identifying one or more predetermined scan word lines of the memory means among the remaining word lines; scanning a subset of pages of the memory means that can be addressed by the forced scan word lines and the predetermined scan word lines; wherein a combination of a first plurality of pages that can be addressed by the predetermined scan word lines selected by the plurality of scan iterations and a second plurality of pages that can be addressed by the forced word lines includes a plurality of pages of the memory means. Attached Figure Description

[0006] This disclosure will be more fully understood from the embodiments given below and from the accompanying drawings of some embodiments thereof.

[0007] Figure 1 This describes an instance computing environment including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 A full scan of examples of operations performed by the memory subsystem controller according to various aspects of this disclosure is illustrated schematically.

[0009] Figure 3 A flowchart of an example method for performing a full scan of a memory device according to some embodiments of the present disclosure.

[0010] Figure 4 A flowchart of another example method for performing a full scan of a memory device according to some embodiments of the present disclosure.

[0011] Figure 5 A block diagram of an example computer system operable according to embodiments of the present disclosure. Detailed Implementation

[0012] Embodiments of this disclosure relate to scan segment strategies based on memory degradation and system requirements. One or more memory devices may be part of a memory subsystem, which may be a storage device, a memory module, or a hybrid of a storage device and a memory module. The following description is in conjunction with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request retrieval of data from the memory subsystem.

[0013] The memory subsystem can perform various data operations, such as host-initiated data operations. For example, the host system can initiate data operations (e.g., write, read, erase, etc.) on the memory subsystem. The host system can send access requests (e.g., write commands, read commands) to the memory subsystem to store data on memory devices located in the memory subsystem and to read data from memory devices on the memory subsystem. The data to be read or written as specified by the host request is referred to hereinafter as "host data". The host request may contain logical address information (e.g., logical block address (LBA), namespace) for the host data, which is the location associated between the host system and the host data. The logical address information (e.g., LBA, namespace) may be part of the metadata of the host data. The metadata may also include error handling data (e.g., error correction code (ECC) codeword, parity check code), data version (e.g., to distinguish between new and old data being written), validity bitmap (indicating that the LBA or logical transfer unit contains valid data), etc.

[0014] The memory subsystem may include high-density non-volatile memory devices, where data needs to be retained when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described.

[0015] A non-volatile memory device is a package of one or more memory dies. Each die may contain two or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane contains a set of physical blocks. In some embodiments, each block may contain multiple sub-blocks. Each plane carries a matrix of memory cells formed on a silicon wafer and connected by conductors called word lines and bit lines, such that word lines connect multiple memory cells forming rows of the memory cell matrix, while bit lines connect multiple memory cells forming columns of the memory cell matrix.

[0016] Depending on the cell type, each memory cell can store one or more bits of binary information and has various logical states related to the number of bits being stored. Logical states can be represented by binary values ​​(such as "0" and "1") or combinations of such values. A set of memory cells called a memory page can be programmed in a single operation, for example, by selecting consecutive bit lines together.

[0017] Memory cells can be programmed (written to) by applying a voltage to them, which keeps the cells charged, thus allowing modulation of the voltage distribution generated by the memory cells. Furthermore, precise control over the amount of charge stored in a memory cell allows for the establishment of multiple threshold voltage levels corresponding to different logic levels, effectively allowing a single memory cell to store multiple bits of information: with 2...n A memory cell operating at different threshold voltage levels can store n bits of information. Therefore, a read operation can be performed by comparing the measured voltage exhibited by the memory cell with one or more reference voltage levels to distinguish between two logic levels in a single-level cell and multiple logic levels in a multi-level cell.

[0018] The charge level of a memory cell can degrade over time due to various physical phenomena and operational processes (such as slow charge loss and read interference), thus causing a higher error rate in memory read operations. This memory degradation can be measured by various data state metrics. In this document, "data state metric" refers to a quantity measured or inferred from the state of the data stored on the memory device. Specifically, a data state metric can reflect the state of slow charge loss, the degree of read interference, and / or other measurable features of the data state. A composite data state metric is a function of a set of component state metrics (e.g., a weighted sum). In an illustrative example, a data state metric may represent the raw bit error rate (RBER), which is the number of bit errors experienced per unit time for a given block of data.

[0019] To mitigate memory degradation, data integrity checks (also referred to herein as “scan operations”) can be performed periodically on the memory device. Data integrity checks may involve evaluating one or more data state metrics for one or more blocks of the memory device. If a data integrity check indicates that one or more data state metrics fail to meet a corresponding quality criterion (e.g., RBER exceeds a predefined threshold), then one or more media management operations can be performed on the affected blocks to mitigate the detected memory degradation. In an illustrative example, media management operations may include flush or “fold” operations, which involve relocating data stored at the affected block of the memory device to another block.

[0020] Some memory subsystems can perform periodic verbose background scans, sequentially scanning all pages (addressable by their respective word lines) across all blocks of all memory devices. For certain types of applications, a verbose scan may need to be completed over a predetermined time period (e.g., 30 days). However, as the number of word lines per block in a memory device increases, the scan frequency should also increase to meet the associated time period requirements of verbose scans. Since scan operations consume certain resources of the memory subsystem, increasing the scan frequency can cause a significant degradation in memory subsystem performance. Conversely, limiting the scan frequency to meet performance requirements may result in failure to meet scan cycle requirements. Furthermore, longer verbose scan cycles can make the level of memory degradation in some pages unacceptable, because pages addressable by some word lines may be more susceptible to various memory degradation mechanisms and therefore may require more frequent scanning than pages addressable by other word lines.

[0021] This disclosure addresses the above and other deficiencies by introducing a scan segment method based on memory degradation parameters and system requirements. In an illustrative example, a subset of “weak” word lines of the memory device is identified, making pages addressable by the identified “weak” word lines more susceptible to various memory degradation mechanisms. In all blocks of the memory device, pages addressable by the identified “weak” word lines (also referred to herein as “forced” word lines) are scanned in each scan iteration. Additionally, for each block of the memory device, each scan iteration includes pages addressable by a subset of the remaining word lines (also referred to herein as “predetermined” word lines). Therefore, a full scan will consist of a certain number of scan iterations, such that for all blocks of the memory device, each iteration scans pages addressable by all forced word lines and pages addressable by one or more predetermined word lines.

[0022] Therefore, the advantages of the systems and methods implemented according to various aspects of this disclosure include ensuring constant memory degradation characteristics throughout a given memory device by performing predetermined scan and media management operations while ensuring that a full scan of all blocks of the memory device can be performed within the time period specified by the system requirements, and that the predetermined scan and media management operations can be performed more frequently on pages addressable by “weak” word lines compared to pages addressable by remaining word lines.

[0023] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0024] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0025] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., computer contained in a vehicle, industrial equipment or networked commercially available device), or such computing device containing memory and processing power.

[0026] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical connections, optical connections, magnetic connections, etc.

[0027] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and to read data from memory subsystem 110.

[0028] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can also utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transferring control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0029] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0030] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND type flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. Crosspoint arrays of non-volatile memory cells can perform bit storage based on variations in volume resistance in conjunction with stackable cross-grid data access arrays. Furthermore, compared to many flash-based memories, crosspoint non-volatile memories can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND-type flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0031] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each memory device 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. Memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks. Some types of memory (such as 3D cross-point) may group pages across dies and channels to form management units.

[0032] While non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0033] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include digital circuitry with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0034] The memory subsystem controller 115 may include a processing means comprising one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0035] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0036] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to enable the desired access to the memory device 130. The memory subsystem controller 115 may also be responsible for other operations such as media management operations (including wear leveling and garbage collection), error detection and error correction code (ECC) operations, encryption operations, caching operations, and address translation between logical addresses (e.g., logical addresses, namespaces) and physical addresses (e.g., physical MU addresses, physical block addresses) associated with the memory device 130.

[0037] Each physical management unit (e.g., block) can be reliably programmed and erased a certain number of times. For write-intensive applications, the memory subsystem controller 115 can implement a wear leveling algorithm to monitor and extend the number of write cycles per block. The wear leveling algorithm ensures that all available write cycles for each block are used equally.

[0038] The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions for accessing the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0039] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0040] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is the original memory device 130 having on-die control logic (e.g., local controller 132) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0041] According to embodiments of this disclosure, memory subsystem 110 includes a scan management component 113 for implementing charge loss scan operation management. In some embodiments, controller 115 includes at least a portion of scan management component 113. For example, controller 115 may include processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, scan management component 113 is part of host system 120, an application, or an operating system. Scan management component 113 can manage block scan operations, as described in more detail below.

[0042] In one embodiment, scan management component 113 may implement a scan segment method based on memory degradation parameters and system requirements. In this specification, a "scan segment" refers to the set of word lines of pages that should be scanned within a block before moving to the next block of the memory device. A "full scan instance" defines a loop that scans all blocks for all scan segments.

[0043] In an illustrative example, the scan management component 113 may identify a subset of “weak” word lines of the memory device 130, making pages addressable by the identified “weak” word lines more susceptible to various memory degradation mechanisms. In one embodiment, some word lines of the memory device may be pre-characterized as “weak,” and the identifiers of those word lines may be stored in a firmware metadata structure residing in one or more reserved metadata blocks of the memory device 130. In another embodiment, “weak” word lines may be dynamically identified during the lifetime of the memory device 130, for example, by selecting a subset of word lines from all word lines of the memory device 130 that address pages that generate the largest number of error handling operations.

[0044] In some embodiments, different sets of “weak” word lines can be identified based on the bit-per-cell characteristics of the block (e.g., for single-level cell (SLC) blocks, multi-level cell (MLC) blocks, three-level cell (TLC) blocks, four-level cell (QLC) blocks, etc.).

[0045] A full scan of memory device 130 may comprise multiple scan iterations, such that each scan iteration involves scanning pages addressable by the identified “weak” word lines (referred to herein as “forced” word lines) across all blocks of the memory device. Each scan iteration further involves scanning pages addressable by a subset of the remaining word lines (referred to herein as “predetermined” word lines) for each block of the memory device. Thus, a full scan would comprise scanning all pages across all blocks of the memory device by performing a certain number of scan iterations, such that each iteration scans pages addressable by all forced word lines and pages addressable by one or more predetermined word lines for all blocks of the memory device.

[0046] Therefore, a full scan will ensure constant memory degradation characteristics throughout the memory device 130 by performing a predetermined scan and media management operation, while ensuring that a full scan of all blocks of the memory device can be performed within the time period specified by the system requirements. The predetermined scan and media management operation can be performed more frequently on pages that can be addressed by "weak" word lines compared to pages that can be addressed by remaining word lines.

[0047] Figure 2 A full scan of an example implemented by the memory subsystem controller according to various aspects of this disclosure is illustrated schematically. (As by...) Figure 2 To explain in a whimsical way, for Figure 1 For each block of the memory device 130, a full scan 200 may include performing periodic scan iterations 220A to 220N. Each scan iteration 220 includes scanning pages addressable by all forced word lines 210K and 210L. Therefore, after performing the m-th scan iteration 220M, pages addressable by all forced word lines 210K and 210L will be scanned M times.

[0048] Each scan iteration 220 further includes scanning a subset of the remaining word lines, referred to as “predetermined” word lines (e.g., scanning WL0, WL5, WL10, and WL15 during the first scan iteration, and scanning WL2, WL6, WL12, and WL16, etc., during the second scan iteration). Thus, after all scan iterations 220A to 220N have been performed, a page addressable by all word lines will be scanned at least once.

[0049] In some embodiments, a scan operation performed by the memory subsystem controller on a given page may involve reading the page and calculating the values ​​of one or more data state metrics (e.g., bit error rate). In an illustrative example, the bit error rate involves evaluating the bits read from a given page through an error-checking mechanism implemented by the memory device. The error-checking mechanism may verify and, if necessary, correct the sequence of data bits read from the memory device by means of one or more redundant metadata bits (e.g., a checksum of the hash of the data bit sequence) associated with the data bit sequence stored on the memory device.

[0050] Therefore, in response to the determination that the value of a data state metric fails to meet a predefined quality standard (e.g., the bit error rate exceeds a predefined threshold), the memory subsystem controller may perform a media management operation (e.g., a folding operation) relative to a block that includes a given page.

[0051] In certain situations, it may be necessary to modify the scan scheduling strategy described above. Specifically, after a power-on event, the memory subsystem controller may need to scan all erased pages in all open cursor blocks before writing any data to a block. "Cursor" in this document refers to the processing thread that writes multiple data blocks to a selected location on the memory device.

[0052] Therefore, the memory subsystem controller scans two erased pages in each open cursor block: the page with the last programmed word line plus one, and the page in the last word line group. If these pages do not meet predefined quality criteria, no additional data should be programmed into the block, and a new block is opened for the cursor. Once the power-on requirements are met, a full scan can continue according to its normal schedule.

[0053] Therefore, whenever a new scan segment is selected, open cursor blocks are scanned first according to the block selection order criterion. To ensure that there is sufficient tolerance in these blocks for the time they remain open, they can be rescanned at a rate faster than the frequency at which a new scan instance is started. In an illustrative example, open cursor and erase pool blocks should be scanned at a frequency equal to MS_OPEN_CURSOR_FREQ. Therefore, after determining that MS_OPEN_CURSOR_FREQ has elapsed since the block was opened / erased, the memory subsystem controller can add the open cursor / erased block back to the pool of blocks to be scanned with high priority using the currently selected scan segment (i.e., once the scan operation for the current block is completed, the memory subsystem controller scans the current scan segment word line in each of the open cursor / erased blocks). In some embodiments, for erased blocks, only forced word lines can be scanned.

[0054] Figure 3 This is a flowchart of an example method for performing a full scan of a memory device according to some embodiments of the present disclosure. Method 300 may be performed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 300 is performed by… Figure 1 The scan management component 113 executes the operation. Although shown in a specific sequence or order, the order of operations may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated operations may be performed in different orders, while some operations may be performed in parallel. In addition, in some embodiments, one or more operations may be omitted. Therefore, not all of the illustrated operations are required in each embodiment, and other processing flows are possible.

[0055] At operation 310, the processing logic may evaluate one or more full scan instance triggering conditions and initiate a full scan instance at operation 320 in response to determining that at least one full scan instance triggering condition has been met. In an illustrative example, a full scan instance may be triggered in response to the detection of a new clean power cycle (e.g., a power-on event following a normal shutdown event). In another illustrative example, a full scan instance may be triggered in response to the detection of a “dirty” power cycle (e.g., a power-on event following an asynchronous power loss event). In yet another illustrative example, a full scan instance may be triggered in response to the detection of any power state where a system timer has been lost or reset. In yet another illustrative example, a full scan instance may be triggered in response to determining that a predefined time period has elapsed since the start or completion of a previous full scan instance.

[0056] At operation 330, the processing logic may select a scan segment for performing the scan operation. The scan segment may contain one or more forced word lines and one or more predetermined word lines, as explained in more detail above. In an illustrative example, the first iteration of a full scan instance may involve selecting a random scan segment, and the scan segment identifier may be incremented at each subsequent scan iteration, wrapping back to the first segment after reaching the segment with the largest identifier among all segments. In various illustrative examples, other techniques may be used to select the scan segment (e.g., applying a predefined function transformation to the identifier of the scan segment selected for a previous iteration of the full scan instance).

[0057] At operation 340, the processing logic selects the set of blocks to scan. In an illustrative example, blocks from one or more open cursors can be selected. In another illustrative example, one or more data blocks (e.g., QLC or SLC blocks) with a predefined number of bits per unit can be randomly selected.

[0058] At operation 350, the processing logic selects a set of word lines for scanning. In some embodiments, the set of word lines may include all mandatory word lines and one or more predetermined word lines, as explained in more detail above herein. In an illustrative example, predetermined word lines may be selected based on a predefined lookup table. In another illustrative example, word lines with the minimum number of word lines may be scheduled for a first scan segment, and the number of word lines may be incremented for each subsequent scan segment. In another illustrative example, a predefined function transformation may be applied to the identifiers of the word lines selected for the previously scan segment. In response to scanning all word lines in the selected scan segment, the method loops back to operation 340 for block selection.

[0059] At operation 360, the processing logic selects the pages to scan. In an illustrative example, page selection can be performed based on a start page identifier and an end page identifier, which can be selected for a given word line using a predefined lookup table. The processing logic can randomly select a page number between 1 and (end page identifier - start page identifier + 1) / number of bits per unit. Therefore, the lower page identifier can be determined as the start page identifier plus the product of a random integer and the number of bits per unit. The upper page identifier can be equal to the lower page identifier plus one. The additional page identifier can be equal to the lower page identifier plus two. The top page identifier can be equal to the lower page identifier plus three. In response to scanning the selected set of pages, the method loops back to operation 350 to perform word line selection.

[0060] At operation 370, the selected page is processed by a logical scan, as described in more detail above. In some implementations, different scan operations may be performed for erased pages, partially written pages, and fully written pages. In an illustrative example, for erased pages, an NDEP scan may be performed, which determines whether the voltage distribution of the erased page has shifted beyond a certain point. For fully written pages, a valley health scan may be performed, which identifies and evaluates the tolerance status between threshold voltage distribution valleys. In response to scanning the selected page, the method loops back to operation 360 to select the next page for scanning. In response to determining that all scan segments have been scanned, the full scan instance is terminated.

[0061] Figure 4 This is a flowchart illustrating another example of a method for performing a full scan of a memory device according to some embodiments of the present disclosure. Method 400 may be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1 The scan management component 114 executes the operation. Although shown in a specific sequence or order, the order of operations may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated operations may be performed in different orders, while some operations may be performed in parallel. In addition, in some embodiments, one or more operations may be omitted. Therefore, not all of the illustrated operations are required in each embodiment, and other processing flows are possible.

[0062] At operation 410, the processing logic identifies one or more forced scan word lines and one or more remaining word lines of the memory device (also referred to herein as “pre-defined” word lines). In an illustrative example, the processing logic identifies a subset of the memory device’s “weak” word lines as forced word lines to be scanned at each iteration of a full scan instance. In one embodiment, some word lines of the memory device may be pre-characterized as “weak,” and the identifiers of those word lines may be stored in a firmware metadata structure residing in one or more reserved metadata blocks of the memory device. In another embodiment, “weak” word lines may be dynamically identified during the lifetime of the memory device, for example, by selecting a subset of the word lines from all word lines of the memory device that address the page that generates the maximum number of error handling operations, as described in more detail above herein.

[0063] At operation 420, the processing logic initiates a full scan instance of the memory device. A full scan instance involves performing multiple scan iterations relative to the memory device.

[0064] At operation 430, the processing logic scans a page that can be addressed by forced word lines. Scanning a page may involve evaluating a data state metric (e.g., bit error rate) relative to the page. In response to determining that the value of the data state metric fails to meet a predefined quality criterion (e.g., the bit error rate exceeds a predefined threshold), the processing logic may perform a media management operation (e.g., a folding operation) relative to the block containing the page, as explained in more detail above herein.

[0065] At operation 440, the processing logic selects one or more word lines from a plurality of predetermined word lines. In an illustrative example, the processing logic randomly selects one or more word lines for the first iteration of a full-scan example, and at each subsequent iteration increments each of the word line identifiers by a predefined increment value. In another illustrative example, the processing logic randomly selects one or more word lines for the first iteration of a full-scan example, and at each subsequent iteration applies a predefined functional transformation to each of the word line identifiers by a predefined increment value, as described in more detail above herein.

[0066] At operation 450, the processing logic scans a page addressable by a selected predetermined word line. Scanning a page may involve evaluating a data state metric (e.g., bit error rate) relative to the page. In response to determining that the value of the data state metric fails to meet a predefined quality criterion (e.g., the bit error rate exceeds a predefined threshold), the processing logic may perform a media management operation (e.g., a folding operation) relative to the block containing the page, as explained in more detail above herein.

[0067] In response to determining at operation 450 that the termination condition has been met, the method terminates; otherwise, the method loops back to operation 430. In an illustrative example, the termination condition determines whether all pages of all blocks of the memory device have been scanned by the current full scan instance. In another illustrative example, the termination condition determines whether the combination of predetermined scan word lines and forced word lines selected by multiple scan iterations contains all word lines of the memory device.

[0068] Figure 5 An example machine illustrating computer system 900 is described, within which a set of instructions is executable to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 900 may correspond to including, coupled to, or utilizing a memory subsystem (e.g., Figure 1 Or the host system of the memory subsystem 110 of 2 (e.g., Figure 1 Or the host system 120 of 2), or can be used to perform controller operations (e.g., execute the operating system to perform corresponding...). Figure 1 (or operation of scan management component 113 of 2). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0069] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, web application, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0070] The example computer system 900 includes a processing device 902 that communicates with each other via a bus 930, a main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 810 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 918.

[0071] Processing device 902 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 902 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 902 is configured to execute instructions 928 for performing the operations and steps discussed herein. Computer system 900 may further include network interface device 912 for communication on network 920.

[0072] The data storage system 918 may include a machine-readable storage medium 924 (also referred to as a computer-readable medium) on which one or more sets of instructions 928 or software embodying any one or more of the methods or functions described herein are stored. The instructions 928 may also reside wholly or at least partially within main memory 904 and / or processing device 902 during execution by computer system 900, which also constitute machine-readable storage media. The machine-readable storage medium 924, the data storage system 918, and / or main memory 904 may correspond to... Figure 1 Or the memory subsystem 110 of 2.

[0073] In one embodiment, instruction 928 includes instructions for implementing the corresponding Figure 1 Or the instructions for the function of the scan manager component 113 of 2. Although the machine-readable storage medium 924 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. It should also be considered that the term "machine-readable storage medium" includes any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0074] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, algorithms are conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0075] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0076] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specifically constructed for a desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk each coupled to a computer system bus, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions.

[0077] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as set forth in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0078] This disclosure may be provided as a computer program product or software, which may contain machine-readable media having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc. As used herein, the terms “instance” or “exemplary” mean used as an example, instance, or illustration. Any aspect or design described herein as an “instance” or “exemplary” is not necessarily to be construed as superior to or better than other aspects or designs. Indeed, the use of the terms “instance” or “exemplary” is intended to present concepts in a specific manner. As used in this application, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise stated or obvious from the context, “X contains A or B” is intended to indicate any natural inclusive permutation. That is, if X contains A; X contains B; or X contains both A and B, then "X contains either A or B" is satisfied under any of the foregoing examples. Additionally, the article "a / an" as used in this application and the appended claims can be generally interpreted as meaning "one or more," unless otherwise specified or clearly indicated from the context. Furthermore, the use of the terms "embodiment," "an embodiment," "implementation," or "one implementation" throughout this document may or may not mean the same embodiment or implementation. The one or more embodiments or implementations described herein may be combined in particular embodiments or implementations. The terms "first," "second," "third," "fourth," etc., as used herein, are intended as markers to distinguish different elements and may not necessarily have the ordinal meaning according to their numerical designations.

[0079] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A system comprising: Memory devices; and A processing device operatively coupled to the memory device to perform operations including: Identify one or more forced scan word lines and one or more remaining word lines of the memory device; Performing multiple scan iterations relative to multiple pages of the memory device, such that performing each scan iteration includes: One or more predetermined scan word lines of the memory device are identified among the remaining word lines. Scan a subset of pages of the memory device that can be addressed by the forced scan word line and the predetermined scan word line; The combination of the first plurality of pages addressable by the predetermined scan word line, which can be selected by the plurality of scan iterations, and the second plurality of pages addressable by the forced scan word line, includes the plurality of pages of the memory device.

2. The system of claim 1, wherein scanning the subset of pages of the memory device further comprises: Evaluate data state metrics relative to a specific page within the subset of pages; In response to determining that the data status metric fails to meet quality standards, a media management operation is performed relative to the block containing the specific page.

3. The system of claim 2, wherein performing the media management operation includes relocating data stored in the block that includes the specific page to another block.

4. The system of claim 2, wherein the data state metric reflects the bit error rate of the particular page.

5. The system of claim 1, wherein identifying the one or more forced scan word lines further comprises: Read the system metadata associated with the memory device.

6. The system of claim 1, wherein identifying the one or more forced scan word lines further comprises: Among the multiple word lines of the memory device, one or more word lines are identified that trigger more error handling operations than the remaining word lines of the memory device.

7. The system of claim 1, wherein identifying the one or more predetermined scan word lines further comprises: Each of the identifiers in the predetermined scan word lines processed by the previous scan iteration is incremented by a predefined value.

8. The system of claim 1, wherein identifying the one or more predetermined scan word lines further comprises: The identifier of the remaining word line of the memory device is applied by a predefined function transformation.

9. The system of claim 1, wherein identifying the one or more predetermined scan word lines further comprises: A predefined number of word lines are randomly selected from the remaining word lines of the memory device.

10. A method comprising: The processing device identifies one or more forced scan word lines of the memory device and one or more remaining word lines of the memory device; Performing multiple scan iterations relative to multiple pages of the memory device, such that performing each scan iteration includes: One or more predetermined scan word lines of the memory device are identified among the remaining word lines. Scan a subset of pages of the memory device that can be addressed by the forced scan word line and the predetermined scan word line; The combination of the first plurality of pages addressable by the predetermined scan word line, which can be selected by the plurality of scan iterations, and the second plurality of pages addressable by the forced scan word line, includes the plurality of pages of the memory device.

11. The method of claim 10, wherein scanning the subset of pages of the memory device further comprises: Evaluate data state metrics relative to a specific page within the subset of pages; In response to determining that the data status metric fails to meet quality standards, a media management operation is performed relative to the block containing the specific page.

12. The method of claim 10, wherein identifying the one or more forced scan word lines further comprises: Read the system metadata associated with the memory device.

13. The method of claim 10, wherein identifying the one or more forced scan word lines further comprises: Among the multiple word lines of the memory device, one or more word lines are identified that trigger more error handling operations than the remaining word lines of the memory device.

14. The method of claim 10, wherein identifying the one or more predetermined scan word lines further comprises: Each of the identifiers in the predetermined scan word lines processed by the previous scan iteration is incremented by a predefined value.

15. The method of claim 10, wherein identifying the one or more predetermined scan word lines further comprises: The identifier of the remaining word line of the memory device is applied by a predefined function transformation.

16. The method of claim 10, wherein identifying the one or more predetermined scan word lines further comprises: A predefined number of word lines are randomly selected from the remaining word lines of the memory device.

17. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means, cause the processing means to perform operations including: Identify one or more forced scan word lines of the memory device and one or more remaining word lines of the memory device; Performing multiple scan iterations relative to multiple pages of the memory device, such that performing each scan iteration includes: One or more predetermined scan word lines of the memory device are identified among the remaining word lines. Scan a subset of pages of the memory device that can be addressed by the forced scan word line and the predetermined scan word line; The combination of the first plurality of pages addressable by the predetermined scan word line, which can be selected by the plurality of scan iterations, and the second plurality of pages addressable by the forced scan word line, includes the plurality of pages of the memory device.

18. The non-transitory computer-readable storage medium of claim 17, wherein scanning the subset of pages of the memory device further comprises: Evaluate data state metrics relative to a specific page within the subset of pages; In response to determining that the data status metric fails to meet quality standards, a media management operation is performed relative to the block containing the specific page.

19. The non-transitory computer-readable storage medium of claim 17, wherein identifying the one or more forced scan word lines further comprises: Among the multiple word lines of the memory device, one or more word lines are identified that trigger more error handling operations than the remaining word lines of the memory device.

20. The non-transitory computer-readable storage medium of claim 17, wherein identifying the one or more predetermined scan word lines further comprises: The identifier of the remaining word line of the memory device is applied by a predefined function transformation.

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