A method, apparatus, device and medium for testing memory address retention time
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2021-06-08
- Publication Date
- 2026-05-29
AI Technical Summary
Existing technologies require the test vector to traverse all memory cells when testing the address retention time of SRAM memory, resulting in a large workload, long processing time, and inaccurate test results.
By selecting a fixed memory cell module and a reference memory cell, an address hold-time test vector is written, the test vector is run, and the data is corrected to determine the accurate address hold-time.
It reduced the testing workload, improved testing efficiency and accuracy, and achieved faster test results.
Smart Images
Figure CN115458027B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuits, and more particularly to a method, apparatus, device, and medium for testing memory address retention time. Background Technology
[0002] With the development of the information age, the application of SRAM (Static Random-Access Memory) is becoming increasingly widespread, leading to higher requirements for testing related memory parameters. Common tests for SRAM memory circuits currently include: DC (Direct Current) parameters, AC (Alternating Current) parameters, and functional tests. Among these, AC parameter testing includes many parameters, such as propagation delay, setup / hold time, operating frequency, and address access time. Furthermore, the address hold time parameter, as one of the key AC parameters of SRAM circuits, is crucial because it ensures that the address signal remains unchanged for a period of time after the write / read control signal or chip select signal terminates within the write cycle of the memory cell corresponding to the current address, preventing data from being mistakenly written to the memory cell corresponding to the next address.
[0003] During the research and development testing phase, if the address hold time parameter value is determined, the traditional method requires first writing background data into the memory cell corresponding to the full address, and then sequentially writing background inverse code data and reading memory cell data into the memory cell corresponding to each address.
[0004] However, in the process of implementing the technical solution of the embodiments of this application, the inventors of this application discovered that the above-mentioned technology has at least the following technical problems: 1. The test vector of the existing test scheme that can test the specific value of the address hold time needs to traverse the entire address memory unit. If an SRAM memory has a total of n address lines, then traversing the entire address of the memory requires... Each storage unit requires writing background data to the full-address storage unit first, and then performing write and read operations on the storage unit corresponding to each address, totaling [amount missing]. The test cycle is 1. With the increase in memory capacity and the number of address pins, this method requires a large workload for test vector development and is time-consuming, making it unsuitable for production testing. 2. The method of obtaining specific values requires reading the stored data in each memory cell for comparison and verification. Since the address has already been flipped between two memory cells, the actual measured value is not the strictly defined address hold time. Summary of the Invention
[0005] This application provides a method, apparatus, device, and medium for testing memory address retention time, which solves the technical problems of huge testing workload and inaccurate data results in the prior art, and achieves the technical effect of improving testing efficiency and accuracy.
[0006] On the one hand, this application provides the following technical solution through one embodiment:
[0007] A method for testing memory address hold time includes:
[0008] Determine the fixed memory cell module and reference memory cell;
[0009] Write address hold-time test vectors;
[0010] Run the address hold-time test vector to determine the address hold-time data;
[0011] The address retention time data is corrected.
[0012] Preferably, the determination of the fixed memory cell module and the reference memory cell includes:
[0013] The memory cell in which all address line port levels are "0" is selected as the first reference memory cell;
[0014] The memory cells with only one address line port level of "1" and the other address line ports of "0" are selected sequentially as the first memory module;
[0015] The memory cell in which all address line port levels are "1" is selected as the second reference memory cell;
[0016] The memory cells with only one address line port level of "0" and the other address line ports of "1" are selected as the second memory modules.
[0017] Preferably, the step of writing the address hold time test vector includes:
[0018] Background data is written into the first storage module and the first reference storage unit, and then the data in the first reference storage unit is read.
[0019] Perform a first preset step, which includes: writing background inverse code data to any target storage unit in the first storage module, then reading the data in the target storage unit, and finally switching back to the first reference storage unit and reading the data in the first reference storage unit;
[0020] The first preset step is executed sequentially on all storage cells in the first storage module;
[0021] Background data is written into the second storage module and the second reference storage unit, and then the data in the second reference storage unit is read.
[0022] Perform the second preset step, which includes: writing background inverse code data to the target storage unit in the second storage module, then reading the data in the target storage unit, and finally switching back to the second reference storage unit and reading the data in the second reference storage unit;
[0023] The second preset step is executed sequentially on all storage cells in the second storage module.
[0024] Preferably, determining the test address hold time data includes:
[0025] Determine the initial time interval between the address signal transition time and the transition edge of the write / read control port.
[0026] Determine whether the data read from the reference storage unit is the background inverse code data, and whether the data read from the target storage unit is the background data;
[0027] The initial time interval is gradually reduced in a stepwise manner, and the test vector is run repeatedly. When the data read from any storage unit is inconsistent with the corresponding written background data, the time interval at this point is the address hold time.
[0028] Preferably, the address retention time after the write operation is terminated includes:
[0029] When writing the background data, the levels of the write / read control port and the chip select / enable control port are both in a write-enabled state;
[0030] When writing the background inverse code data, the write-read control pin first maintains a certain pulse width of write-enabled state, and then switches to write-disable state, while other control pins are all write-enabled.
[0031] Preferably, the test allows for address retention time after termination, including:
[0032] When writing the background data, the levels of the write / read control port and the chip select / enable control port are both in a write-enabled state;
[0033] When writing the background inverse code data, the chip select / enable control pin first maintains a certain pulse width of write active, and then switches to the chip select / enable disabled state, while other control pins are all write active level.
[0034] Preferably, the step of correcting the address retention time data includes:
[0035] Measure the time interval between the address pin's transition from the first state to the second state to determine the compensation time;
[0036] Subtract the compensation time from the address hold time data to obtain the corrected address hold time data.
[0037] Secondly, through one embodiment of this application, the following technical solution is provided:
[0038] An apparatus for testing the address retention time of a memory circuit, comprising:
[0039] The selection unit is used to determine the fixed memory cell module and the reference memory cell;
[0040] Write a unit for writing address hold-time test vectors;
[0041] The processing unit is used to run the address hold-time test vector and determine the address hold-time data;
[0042] A correction unit is used to correct the address hold time data.
[0043] Preferably, the selection unit is further configured to:
[0044] The memory cell in which all address line port levels are "0" is selected as the first reference memory cell;
[0045] The memory cells with only one address line port level of "1" and the other address line ports of "0" are selected sequentially as the first memory module;
[0046] The memory cell in which all address line port levels are "1" is selected as the second reference memory cell;
[0047] The memory cells with only one address line port level of "0" and the other address line ports of "1" are selected as the second memory modules.
[0048] Preferably, the writing unit is further configured to:
[0049] Background data is written into the first storage module and the first reference storage unit, and then the data in the first reference storage unit is read.
[0050] Perform a first preset step, which includes: writing background inverse code data to any target storage unit in the first storage module, then reading the data in the target storage unit, and finally switching back to the first reference storage unit and reading the data in the first reference storage unit;
[0051] The first preset step is executed sequentially on all storage cells in the first storage module;
[0052] Background data is written into the second storage module and the second reference storage unit, and then the data in the second reference storage unit is read.
[0053] Perform the second preset step, which includes: writing background inverse code data to the target storage unit in the second storage module, then reading the data in the target storage unit, and finally switching back to the second reference storage unit and reading the data in the second reference storage unit;
[0054] The second preset step is executed sequentially on all storage cells in the second storage module.
[0055] Preferably, the processing unit is further configured to:
[0056] Determine the initial time interval between the address signal transition time and the transition edge of the write / read control port.
[0057] Determine whether the data read from the reference storage unit is the background inverse code data, and whether the data read from the target storage unit is the background data;
[0058] The initial time interval is gradually reduced in a stepwise manner, and the test vector is run repeatedly. When the data read from any storage unit is inconsistent with the corresponding written background data, the time interval at this point is the address hold time.
[0059] Preferably, the processing unit is further configured to:
[0060] When writing the background data, the levels of the write / read control port and the chip select / enable control port are both in a write-enabled state;
[0061] When writing the background inverse code data, the write-read control pin first maintains a certain pulse width of write-enabled state, and then switches to write-disable state, while other control pins are all write-enabled.
[0062] Preferably, the processing unit is further configured to:
[0063] When writing the background data, the levels of the write / read control port and the chip select / enable control port are both in a write-enabled state;
[0064] When writing the background inverse code data, the chip select / enable control pin first maintains a certain pulse width of write active, and then switches to the chip select / enable disabled state, while other control pins are all write active level.
[0065] Preferably, the correction unit is further configured to:
[0066] Measure the time interval between the address pin's transition from the first state to the second state to determine the compensation time;
[0067] Subtract the compensation time from the address hold time data to obtain the corrected address hold time data.
[0068] Thirdly, through one embodiment of this application, the following technical solution is provided:
[0069] An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that the processor executes the computer program to implement the steps described in the first aspect.
[0070] Fourthly, through one embodiment of this application, the following technical solution is provided:
[0071] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps described in the first aspect.
[0072] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:
[0073] This invention discloses a method, apparatus, device, and medium for testing memory address hold time. The method includes writing an address hold time test vector, which reduces the workload of testing. Then, by running the address hold time test vector, address hold time data can be determined. Furthermore, the address hold time data can be corrected to make the measurement results more accurate. This solves the technical problems of huge testing workload and inaccurate data in the prior art, and achieves the technical effect of improving testing efficiency and accuracy. Attached Figure Description
[0074] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0075] Figure 1 This is a flowchart illustrating a method for testing memory address retention time in an embodiment of the present invention;
[0076] Figure 2 This is a schematic diagram illustrating the transition from the AX state to the AV state of the address line in an embodiment of the present invention;
[0077] Figure 3 This is a schematic diagram illustrating the transition from the AX state to the AV state of a single address line in an embodiment of the present invention.
[0078] Figure 4This is a timing diagram of the background data writing process in an embodiment of the present invention;
[0079] Figure 5 The address retention time t after write termination in this embodiment of the invention WHAX Test timing diagram;
[0080] Figure 6 In this embodiment of the invention, the address retention time t after termination is allowed. EFAX Test timing diagram;
[0081] Figure 7 This is a schematic diagram of the AX state to AV state when the level of a single address line flips from high to low in an embodiment of the present invention;
[0082] Figure 8 This is a schematic diagram of the AX state to AV state when the level of a single address line flips from low to high in an embodiment of the present invention;
[0083] Figure 9 This is a structural diagram of a device for testing the address retention time of a memory circuit according to an embodiment of the present invention;
[0084] Figure 10 This is a structural diagram of an electronic device according to an embodiment of the present invention;
[0085] Figure 11 This is a structural diagram of a computer-readable storage medium according to an embodiment of the present invention. Detailed Implementation
[0086] This application provides a method, apparatus, device, and medium for testing memory address retention time, which solves the technical problems of huge testing workload and inaccurate data results in the prior art, and achieves the technical effect of improving testing efficiency and accuracy.
[0087] The technical solution of this application embodiment is to solve the above-mentioned technical problems, and the general idea is as follows:
[0088] A method for testing memory address hold time includes: determining a fixed memory cell module and a reference memory cell; writing an address hold time test vector; running the address hold time test vector to determine address hold time data; and correcting the address hold time data.
[0089] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.
[0090] First, it should be clarified that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.
[0091] Example 1
[0092] Specifically, such as Figure 1 As shown, this application embodiment provides a method for testing memory address retention time, including:
[0093] Step S110: Determine the fixed memory cell module and the reference memory cell.
[0094] Step S120: Compile the address hold-time test vector.
[0095] Step S130: Run the address hold-time test vector to determine the address hold-time data.
[0096] Step S140: Correct the address hold time data.
[0097] For memory circuits, such as Figure 2 As shown, during the switching process between different memory cells A1 and A2, the address lines typically experience level transitions. Any address line that toggles the fastest (e.g., ...) Figure 2 The left dashed line (address line) indicates that the address line level has changed from its original level to the middle level, signifying the transition to the AX state. The address line that toggles the slowest (e.g., the one with the lowest toggling speed) is the one with the highest toggling speed. Figure 2 The time it takes for the level of the address line (the right dashed line in the diagram) to transition to the effective level of the next memory cell is AV. At this time, the switching between memory cells A1 and A2 is completed.
[0098] Based on the working principle of each input port of Static Random Access Memory (SRAM), assuming that an SRAM has only one address line A1, the states of AX and AV during the transition of a single address line are as follows: Figure 3 As shown. When address line A1 begins to transition into the AX state, NWE remains low (write state). Even though address line A1 has already entered the AX state, it does not affect the writing of data to memory cell A1 until address line A1 transitions from the AX state to the AV state. Only then does the memory cell change to A2, and data begins to be written to cell A2. In the address hold time test, a read operation is required to verify the data stored in the memory cell in order to determine the transition point of address line A1. Therefore, the actual address hold time measured is the transition time from the AV state to the WH state, not the AX state.
[0099] This application first selects the memory cell corresponding to the fixed address of the SRAM memory and the corresponding reference memory cell as the target memory cell; then writes test vectors to perform write and read operations on the target memory cell; sets the timing according to the specific test parameters and tests the hold time test value of each address line of the memory in a step-by-step manner; finally, by correcting the test value data, the accurate address hold time is obtained.
[0100] The present invention will be further described in detail below with reference to specific embodiments and the accompanying drawings:
[0101] For example, the object under test is the CY7C109, a 128K × 8-bit SRAM product manufactured by Cypress Semiconductor. This SRAM has 17 address lines, namely A0, A2...A16, which are collectively referred to as Addr. The chip select enable pins are NCE1 and CE2, the write / read control port is NWE, and there are 8 data input / output ports, namely IO0, IO1...IO7, which are collectively referred to as IO.
[0102] First, determine the fixed memory cell module and reference memory cell, and then perform the following steps.
[0103] a1. Select the memory cell with address port 00000000000000000 as reference memory cell 0.
[0104] a2. Select memory cells sequentially where only one address line port level is "1" and the other address line port levels are "0", denoted as Addr1~Addr17, collectively referred to as memory cell module 1.
[0105] a3. Select the memory cell with address port 11111111111111111 as reference memory cell 1.
[0106] a4. Select memory cells with only one address line port level of "0" and the other address line port levels of "1" in sequence, denoted as Addr18~Addr34, collectively referred to as memory cell module 2.
[0107] Next, we will write the address hold-time test vector and execute the following steps.
[0108] Step b1. Write background data 0x55 into storage unit module 1 and reference storage unit 00000000000000000.
[0109] Step b2. Read the stored data from reference storage unit 00000000000000000.
[0110] Step b3. Starting from storage unit Addr1 in address module 1, write 0xaa, and then read the stored data in that storage unit.
[0111] Step b4. Jump back to reference memory location 00000000000000000 and read the data.
[0112] Step b5. Perform the operations from steps b3 to b4 sequentially on the storage units Addr1 to Addr17.
[0113] Step b6. Write background data 0xaa into storage unit module 2 and reference storage unit 11111111111111111.
[0114] Step b7. Read the stored data from reference storage unit 11111111111111111.
[0115] Step b8. Write 0x55 starting from memory cell Addr18 in address module 2, and then read the data in that memory cell.
[0116] Step b9. Jump back to reference memory cell 11111111111111111 and read the data.
[0117] Step b10. Perform steps b8 and b9 sequentially on memory units Addr18 to Addr34.
[0118] There are a total of 140 test vectors.
[0119] Next, the address hold-time test vector is run to determine the address hold-time data. This address hold-time data includes the address hold-time t after write termination. WHAX Data and address retention time t after termination EFAX data.
[0120] For the address retention time t after write termination WHAX The test will be conducted by following these steps.
[0121] c1. Set the timing for writing background data in steps b1 and b6 to normal write timing (NEW, NCE are low), such as... Figure 4 As shown.
[0122] c2. In the write operations of steps b3 and b8, NWE first maintains a certain pulse width for write-enabled operation, then transitions to write-disabled state, while other control pins remain at write-enabled level. Figure 5 As shown. The initial value of the time interval t between the address signal transition time and the NWE transition edge is 5ns.
[0123] c3. Run the test vector in step b, and compare whether the data read in step b3 is 0x55 and whether the data read in b8 is 0xaa.
[0124] c4. Gradually decrease the time interval t in a step-by-step manner, and repeatedly run the test vector. When the data read from any memory unit is inconsistent with the corresponding written background data, the time interval t at this point is denoted as t_t. WHA"X” .
[0125] For the allowed address retention time t after termination EFAX The test will be conducted by following these steps.
[0126] d1. Set the timing of writing background data in steps b1 and b6 to the normal writing timing.
[0127] d2. In the write operations of steps b3 and b8, the NCE pin first maintains a write-enabled state with a certain pulse width, then transitions to the enable / disable state. All other control pins remain at the write-enabled level. Figure 6 As shown, the initial value of the time interval t between the address signal transition time and the NCE transition edge is set to 5ns.
[0128] d3. Run the test vector in step b, and compare whether the data read in step b3 is 0x55 and whether the data read in b8 is 0xaa.
[0129] d4. Gradually decrease the time interval t in a stepwise manner, and repeatedly run the test vector. When the data read from any memory unit is inconsistent with the corresponding written background data, the time interval t at this point is denoted as t_t. EFA"X” .
[0130] Finally, the address retention time data is corrected.
[0131] In the specific implementation process, based on the high and low level V input of this SRAM... IH / V IL The voltage value is measured using an oscilloscope, and the time interval between the address pin's AX state and AV state is recorded as Δt. Figure 7 , Figure 8 This shows the transitions of a single address line from high to low and from low to high. The formula for the corrected address hold time is as follows:
[0132] Address retention time t after write termination WHAX =t WHA"X” -△t
[0133] Allowed address retention time t after termination EFAX = t EFA"X” -△t
[0134] Example 2
[0135] Based on the same inventive concept, such as Figure 9 As shown, this embodiment provides an apparatus 900 for testing the address retention time of a memory circuit, comprising:
[0136] Select unit 910 is used to determine the fixed memory cell module and the reference memory cell;
[0137] Write unit 920 to write address hold-time test vectors;
[0138] Processing unit 930 is used to run the address hold-time test vector to determine address hold-time data;
[0139] The correction unit 940 is used to correct the address hold time data.
[0140] Since the apparatus for testing the address retention time of a memory circuit described in this embodiment is the same apparatus used to implement the method for testing the address retention time of a memory circuit in this embodiment of the invention, those skilled in the art can understand the specific implementation and various variations of the apparatus for testing the address retention time of a memory circuit in this embodiment based on the method for testing the address retention time of a memory circuit described in this embodiment of the invention. Therefore, how the apparatus for testing the address retention time of a memory circuit implements the method in this embodiment of the invention will not be described in detail here. Any apparatus used by those skilled in the art to implement the method for testing the address retention time of a memory circuit in this embodiment of the invention falls within the scope of protection of this invention.
[0141] Example 3
[0142] Based on the same inventive concept, such as Figure 10 As shown, this embodiment provides an electronic device, including a memory 1010, a processor 1020, and a computer program 1011 stored in the memory 1010 and executable on the processor 1020. When the processor 1020 executes the computer program 1011, it performs the following steps:
[0143] The fixed memory cell module and reference memory cell are determined; an address hold-time test vector is written; the address hold-time test vector is run to determine the address hold-time data; and the address hold-time data is corrected.
[0144] Since the electronic device described in this embodiment is the electronic device used to implement the method for testing memory address retention time in the embodiments of this application, those skilled in the art can understand the specific implementation and various variations of the electronic device in this embodiment based on the method for testing memory address retention time described in the embodiments of this application. Therefore, how the electronic device implements the method in the embodiments of this application will not be described in detail here. Any electronic device used by those skilled in the art to implement the method for testing memory address retention time in the embodiments of this application falls within the scope of protection of this application.
[0145] Example 4
[0146] Based on the same inventive concept, such as Figure 11 As shown, this embodiment provides a computer-readable storage medium 1100, on which a computer program 1110 is stored. When the computer program 1110 is executed by a processor, it performs the following steps:
[0147] The fixed memory cell module and reference memory cell are determined; an address hold-time test vector is written; the address hold-time test vector is run to determine the address hold-time data; and the address hold-time data is corrected.
[0148] The technical solutions described in the embodiments of this application above have at least the following technical effects or advantages:
[0149] 1. In this embodiment, by selecting the memory cell module and the corresponding reference memory cell, the switching states of each address line from low to high and from high to low are comprehensively covered while significantly reducing the test vector, ensuring the comprehensiveness of the address hold time parameter test. If an SRAM has n address lines, this scheme only requires 4(2n+1) lines of test vectors, greatly saving vector development time in the test program and improving test efficiency.
[0150] 2. In this embodiment of the application, by correcting the address hold time data, the time interval between address lines AX and AV is compensated, and accurate address hold time parameters can be obtained through data correction.
[0151] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.
[0152] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.
Claims
1. A method for testing memory address retention time, characterized in that, include: Determine the fixed memory cell module and reference memory cell; The determination of the fixed memory cell module and the reference memory cell includes: The memory cell in which all address line port levels are "0" is selected as the first reference memory cell; The memory cells with only one address line port level of "1" and the other address line ports of "0" are selected sequentially as the first memory module; The memory cell with all address line port levels set to "1" is selected as the second reference memory cell; The memory cells with only one address line port level of "0" and the other address line ports of "1" are selected sequentially as the second memory modules; Write an address hold-time test vector; the writing of the address hold-time test vector includes: Background data is written into the first storage module and the first reference storage unit, and then the data in the first reference storage unit is read. Perform a first preset step, which includes: writing background inverse code data to any target storage unit in the first storage module, then reading the data in the target storage unit, and finally switching back to the first reference storage unit and reading the data in the first reference storage unit; The first preset step is executed sequentially on all storage cells in the first storage module; Background data is written into the second storage module and the second reference storage unit, and then the data in the second reference storage unit is read. Perform the second preset step, which includes: writing background inverse code data to the target storage unit in the second storage module, then reading the data in the target storage unit, and finally switching back to the second reference storage unit and reading the data in the second reference storage unit; The second preset step is executed sequentially on all storage cells in the second storage module; Run the address hold-time test vector to determine the address hold-time data; the determination of the address hold-time data includes: Determine the initial time interval between the address signal transition time and the transition edge of the write / read control port. Determine whether the data read from the reference storage unit is the background inverse code data, and whether the data read from the target storage unit is the background data; The initial time interval is gradually reduced in a stepwise manner, and the test vector is run repeatedly. When the data read from any storage unit is inconsistent with the corresponding written background data, the time interval at this point is the address hold time. The address retention time data is corrected.
2. The method as described in claim 1, characterized in that, Test the address retention time after write termination, including: When writing the background data, the levels of the write / read control port and the chip select / enable control port are both in a write-enabled state; When writing the background inverse code data, the write-read control pin first maintains a certain pulse width of write-enabled state, and then switches to write-disable state, while other control pins are all write-enabled.
3. The method as described in claim 1, characterized in that, The test allows for address retention time after termination, including: When writing the background data, the levels of the write / read control port and the chip select / enable control port are both in a write-enabled state; When writing the background inverse code data, the chip select / enable control pin first maintains a certain pulse width of write active, and then switches to the chip select / enable disabled state, while other control pins are all write active level.
4. The method as described in claim 1, characterized in that, The correction of the address hold time data includes: Measure the time interval between the address pin's transition from the first state to the second state to determine the compensation time; Subtract the compensation time from the address hold time data to obtain the corrected address hold time data.
5. An apparatus for testing the address retention time of a memory circuit, characterized in that, include: A selection unit is used to determine the fixed memory cell module and the reference memory cell. Specifically, the selection unit is used to select a memory cell with all address line port levels set to "0" as the first reference memory cell; sequentially select a memory cell with only one address line port level set to "1" and the other address line ports set to "0" as the first memory cell module; select a memory cell with all address line port levels set to "1" as the second reference memory cell; and sequentially select a memory cell with only one address line port level set to "0" and the other address line ports set to "1" as the second memory cell module. The writing unit is used to write the address hold time test vector. Specifically, the writing unit is used to write background data into the first storage module and the first reference storage unit, and then read the data from the first reference storage unit. The process involves executing a first preset step, which includes: writing background inverse code data to any target storage unit in the first storage module, then reading the data in the target storage unit, and finally switching back to the first reference storage unit and reading the data in the first reference storage unit; sequentially executing the first preset step on all storage units in the first storage module; writing background data to the second storage module and the second reference storage unit, and then reading the data in the second reference storage unit; and executing a second preset step, which includes: writing background inverse code data to a target storage unit in the second storage module, then reading the data in the target storage unit, and finally switching back to the second reference storage unit and reading the data in the second reference storage unit; and sequentially executing the second preset step on all storage units in the second storage module. The processing unit is used to run the address hold time test vector to determine the address hold time data. Specifically, the processing unit is used to determine the initial time interval between the address signal transition time and the transition edge of the write / read control port, determine whether the data read from the reference memory unit is the background inverse code data, and whether the data read from the target memory unit is the background data; the initial time interval is gradually reduced in a stepwise manner, and the test vector is run repeatedly. When the data read from any memory unit is inconsistent with the corresponding written background data, the time interval at this time is the address hold time. A correction unit is used to correct the address hold time data.
6. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method according to any one of claims 1-5.
7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method described in any one of claims 1-5.