In-memory computer

Abstract

A multi-processor computer system includes an in-memory computer including a compute engine and storage elements, and a processor external to the in-memory computer. The processor has a memory address space for writing data into at least some of the storage elements and for reading data from at least some of the storage elements. The compute engine is operable to process data stored in the storage elements in response to read operations or write operations by the processor to the storage elements. The compute engine can include a bit-serial multiplier, and bits of numbers can be stored in sequential addresses in the storage elements. Dot products between numbers in a vector can be computed by successively accessing, multiplying, counting, and accumulating bits in the numbers.

Description

Technical Field

[0001] This disclosure generally relates to distributed digital memory and computing element architectures, devices, and methods that facilitate matrix multiplication. Background Technology

[0002] Tensor computation is an important operation in many mathematical calculations. For example, linear algebra can use matrix multiplication to solve systems of linear equations, such as differential equations. This type of mathematical computation is applied in fields such as pattern matching, artificial intelligence, analytic geometry, engineering, physics, natural sciences, computer science, computer animation, and economics.

[0003] Matrix multiplication is typically performed in digital computers that execute stored programs. These programs describe the operations to be performed, and the hardware in the computer (e.g., digital multipliers and adders) performs these operations. The data (matrices) used in the operations is stored in digital memory, such as static random access memory (SRAM) or dynamic random access memory (DRAM) accessed via a memory and address bus. The number of bits retrieved at a time in parallel with a single access or read command is limited by the bus width and corresponds to the number of bits in memory enabled by the address provided to the memory. Therefore, access to data stored in memory is an inherent limitation of conventional digital computing systems. In some computing systems, specially designed hardware can accelerate computation.

[0004] Typically, computations requiring large matrices and high data rates can take longer to solve and consume more power than expected. Therefore, computational logic and memory architectures capable of performing matrix multiplication at higher data rates and with less power are needed. Summary of the Invention

[0005] Embodiments of this disclosure may particularly provide a memory computer having an architecture adapted to perform matrix multiplication with improved efficiency at a faster rate and with less power. The memory computer can provide massively parallel processing of large numbers of values, for example, performing multiple matrix multiplication operations simultaneously, such as dot products. According to embodiments of this disclosure, a multiprocessor computer system may include a memory computer and a processor. The memory computer may include a computing engine and storage elements for storing data. The computing engine is operable to process data stored in the storage elements of the memory computer. The processor may be external to and connected to the memory computer. The processor may have a memory address space for writing data to at least some of the storage elements and for reading data from at least some of the storage elements. In embodiments, the computing engine is operable to (i) process data stored in the storage elements in response to a processor read operation on a storage element, (ii) in response to a processor write operation on a storage element, or (iii) both (i) and (ii). The memory computer is operable to return processed data to the processor in response to a read operation or in response to a write operation. In some embodiments, storage elements (e.g., memory in a memory computer) may be divided into two or more groups, each group responding to different addresses provided simultaneously (e.g., responding to addresses provided on separate address lines), such that data from the two or more groups can be accessed simultaneously in parallel. In some embodiments, storage elements (e.g., memory in a memory computer) respond to only one address (e.g., having only one set of address lines).

[0006] In some embodiments, a read or write operation may provide a read-write address in the memory address space, a storage element may store data at the read-write address, and a computing engine is operable to process the stored data. In some embodiments, the computing engine is operable to store the processed data at the read-write address in the storage element. In some embodiments, the computing engine is operable to store the processed data at a processing address in the storage element that is different from the read-write address. In some embodiments, a read or write operation may provide a read-write address in the memory address space, a storage element may store data at an address in the memory address space that is different from the read-write address, and a computing engine is operable to process data stored at different addresses in the storage element. In some embodiments, the computing engine is operable to store the processed data at the read-write address. In some embodiments, the computing engine is operable to store the processed data at a processing address in the memory address space that is different from the read-write address. In some embodiments, the computing engine is operable to process data differently based on one of a plurality of different read-write addresses.

[0007] According to embodiments of this disclosure, a memory computer may include a memory mode controller, a processor connected to the memory mode controller via any combination of function lines, one or more address lines, and one or more data lines, and the memory mode controller may be connected to a storage element and a computing engine. In some embodiments, the memory mode controller may control the computing engine in response to an RW address to process data stored in the storage element. In some embodiments, the memory mode controller may include address analysis circuitry for analyzing the RW address and controlling the computing engine in response to address analysis. In some embodiments, the memory mode controller may control the computing engine in response to a function line to process data stored in the storage element. In some embodiments, the memory mode controller may include function analysis circuitry for analyzing function lines and controlling the computing engine in response to function line analysis. In some embodiments, the memory mode controller is operable to (i) read processed data from the storage element (22) or (ii) write processed data to the storage element, or (iii) both (i) and (ii).

[0008] According to embodiments of this disclosure, at least one storage element can be mapped to multiple addresses in the processor's memory space. In some embodiments, no storage element is mapped to multiple addresses in the processor's memory space. In some embodiments, a memory mode controller is operable to map a write address to a write storage element in response to a write operation from the processor, and to map a read address to a different read storage element in response to a read operation from the processor on the write address. In some embodiments, a memory mode controller is operable to map a write address to a write storage element in response to a write operation from the processor, and to map a read address to a different read storage element in response to a read operation and a function line. In some embodiments, RW addresses are mapped to at least three different storage elements, and the computing engine processes data differently according to the function line.

[0009] According to embodiments of this disclosure, a multiprocessor computer system may include a plurality of computing engines, wherein each computing engine is operable to simultaneously multiply the bits of each number in two one-dimensional arrays of numbers. Some embodiments may include a plurality of computing engines sufficient to simultaneously multiply the bits of each number in two two-dimensional arrays of numbers. In some embodiments, (i) at least some processing instructions are stored in storage elements within a memory computer address range, (ii) at least some data are stored in storage elements within a memory computer address range, or (iii) both (i) and (ii).

[0010] According to embodiments of this disclosure, a multiprocessor computer system may include: a memory computer including a computing engine and storage elements for storing data, the computing engine being operable to read, write, and process data stored in the storage elements of the memory computer; and a processor located external to and connected to the memory computer, the processor having a memory address space for writing data to at least some of the storage elements and for reading data from at least some of the storage elements. In some embodiments, the computing engine is operable to process data stored in the storage elements in response to read or write operations of the processor on the storage elements, and at least one of the storage elements is mapped to a plurality of addresses in the processor's memory space.

[0011] According to embodiments of this disclosure, a multiprocessor computer system may include a memory computer and a processor. The memory computer may include a memory mode controller, a computing engine, and storage elements for storing data. The computing engine is operable to read, write, and process data stored in the storage elements of the memory computer. The processor may be external to and connected to the memory computer. The processor may have a memory address space for writing data to at least some of the storage elements and for reading data from at least some of the storage elements. In some embodiments, the processor may be connected to the memory mode controller via any combination of function lines, one or more address lines, and one or more data lines. The memory mode controller may be connected to the storage elements and the computing engine.

[0012] According to embodiments of this disclosure, a dot product calculator may include: a controller operable to sequentially provide memory addresses; and a memory operable to receive memory addresses from the controller and store at least one vector X and a vector or matrix Y. Each vector may have numbers, each number may have bits, and the bits for each number of vector X and the bits for each number of vector Y may be accessed simultaneously in parallel. In some embodiments, bit multipliers, such as AND gates, may be connected to the memory such that each bit multiplier, in response to a memory address provided by the controller, simultaneously inputs bits of the numbers of vector X and vector Y and outputs the product of the input bits. A group counter operable to count the non-zero bits of the numbers output from the bit multipliers. A serial accumulator may sequentially accumulate the counts, each count and bit having a position value or position corresponding to the same address. In some embodiments, the same bits of each number of both vector X and vector Y are stored at the same address of the memory address provided by the controller. In some embodiments, the memory addresses in the sequence are digitally adjacent. In some embodiments, the group counter is analog, (ii) the serial accumulator is analog, or (iii) both (i) and (ii). In some embodiments, the group counter is digital, (ii) the serial accumulator is digital, or (iii) both (i) and (ii).

[0013] In some embodiments, the memory is operable to store multiple pairs of vectors X and Y, and the dot product calculator may include bit multipliers (e.g., AND gates) connected to each pair of the memory. Each bit multiplier (e.g., each AND gate) is operable to simultaneously input bits of multiple vectors X in a pair and bits of multiple vectors Y in the same pair, and output the product of the input bits. A group counter for each pair is operable to count the non-zero bits output from the bit multipliers (e.g., AND gates) in that pair. A serial accumulator for each group counter is operable to sequentially accumulate all or at least a portion of the counts from the group counter, each count and bit having a position value (e.g., position) corresponding to the same address. In some embodiments, multiple pairs of vectors X may form a first two-dimensional digital matrix, and multiple pairs of vectors Y may form a second two-dimensional digital matrix, and the dot product calculator is operable to compute an array of scalar values ​​corresponding to the dot product between the first two-dimensional matrix and the second two-dimensional matrix.

[0014] According to embodiments of this disclosure, a dot product calculator may include: a controller operable to sequentially provide a memory address; and a memory operable to receive the memory address from the controller and store a first two-dimensional number array (a first matrix) and a second two-dimensional number array (a second matrix). Bits of each number in the first matrix and bits of each number in the second matrix can be accessed simultaneously in parallel. A bit multiplier (e.g., an AND gate) for each number in the first or second matrix may be connected to the memory and operable to simultaneously and in parallel input bits from the numbers in the first matrix and input bits from the numbers in the second matrix, and output the product of the input bits. A group counter for each one-dimensional number array in the first or second matrix is ​​operable to count the non-zero bits output from the bit multiplier (e.g., an AND gate) receiving the one-dimensional number array. A serial accumulator for each group counter is operable to sequentially accumulate all or at least a portion of the counts of the group counter. Each count and bit may have a position value corresponding to the same address.

[0015] According to embodiments of this disclosure, a dot product calculator may include: a controller operable to sequentially provide a memory address; a memory operable to receive the memory address from the controller and store a first n-dimensional array of numbers (a first matrix) and a second m-dimensional array of numbers (a second matrix), wherein the same bits of each number in the first matrix and each number in the second matrix can be accessed simultaneously in parallel; and a calculation engine connected to the memory, operable to calculate an array of scalar numbers corresponding to the dot product between the first and second matrices. In some embodiments, n or m is 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, or 12. In some embodiments, the storage element includes bit cells, and the calculation engine includes capacitors associated with pairs of bit cells, or capacitors associated with groups of multiple bit cells. In some embodiments, the storage element includes bit cells, and the calculation engine includes binary logic associated with pairs of bit cells, or binary logic associated with groups of multiple bit cells.

[0016] According to embodiments of this disclosure, a multiprocessor computer system may include a memory computer and a processor. The memory computer may include a memory mode controller, a computing engine, and storage elements for storing data. The computing engine is operable to read, write, and process data stored in the storage elements of the memory computer. The processor may be external to and connected to the memory computer. The processor may have a memory address space for writing data to at least some of the storage elements and for reading data from at least some of the storage elements. The processor may be connected to the memory mode controller, and the memory mode controller may be connected to the storage elements and the computing engine. The memory mode controller may receive memory addresses from the processor and map memory addresses from a first memory address to a second memory address that is different from the first memory address. In some embodiments, the first memory address may be a virtual address. In some embodiments, the first memory address may be a physical memory address. In some embodiments, the second memory address may be a physical memory address.

[0017] According to embodiments of this disclosure, a multiprocessor computer system may include a memory computer, which includes a computing engine and a processor. The memory computer may include storage elements for storing multi-digit numbers. The computing engine is operable to process multi-digit numbers (e.g., data) stored in the storage elements of the memory computer. The processor may be external to and connected to the memory computer. The processor may have a memory address space for writing multi-digit numbers to at least some of the storage elements and for reading data (e.g., multi-digit numbers) from at least some of the storage elements. In some embodiments, different bits of the multi-digit number are stored at different storage element addresses in different storage elements, for example, such that a read operation on a storage element can only retrieve one bit of any one of the multi-digit numbers, for example, one bit of each of the multi-digit numbers, for example, a bit having the same location or location value. Therefore, each bit of the multi-digit number may be stored at a storage element address different from any other bit of the multi-digit number. In some embodiments, only some, but not all, bits of the multi-digit number may be stored at storage element addresses different from any other bit of the multi-digit number. For example, some bits of the multi-digit number may be stored separately in different memory groups (including storage elements) simultaneously in response to a common storage element address.

[0018] According to embodiments of this disclosure, a multiprocessor computer system may include a memory computer, which includes a computing engine, storage elements for storing data, and a processor. The computing engine is operable to process data stored in the storage elements of the memory computer. The processor may be located externally to the memory computer, connected to the memory computer, and may have a memory address space for writing data to at least some of the storage elements and for reading data from at least some of the storage elements. In some embodiments, the computing engine is operable to (i) process data stored in the storage element for the first time in response to a read or write operation by the processor at a first address on the storage element, and (ii) process data stored in the storage element for the second time in response to a read or write operation by the processor at a second address on the storage element, wherein the first address is different from the second address, and the first processing is different from the second processing.

[0019] According to embodiments of this disclosure, a method for multiplying a number A by a number B, where both A and B have bits in bit positions, may include: (i) sequentially multiplying bits of A by bits of B to provide a bit product for each combination (e.g., pair) of bits in A and B that have common bit positions, and adding the bit products; (ii) shifting the added bit product by product positions; (iii) accumulating the shifted added bit products; and (iv) repeating steps (i)-(iii) for each bit position of A and B to provide a product of A and B.

[0020] According to embodiments of this disclosure, a method for calculating the dot product between a vector X having a digit A and a vector Y having a digit B, wherein A and B have bits at bit positions, may include: (i) multiplying the bits of A by the bits of B to provide a bit product of A and B for each bit combination (e.g., a pair) of A and B having a common bit position in vectors X and Y; (ii) counting the bit products; (iii) accumulating the count; (iv) repeating steps (i)-(iii) for each bit combination having a common bit position; (v) shifting the accumulated count to that bit position; (vi) summing the shifted accumulated counts; and repeating steps (i)-(vi) for each bit position of the product of A and B to provide a dot product of A and B, which is an summed shifted accumulated count.

[0021] According to embodiments of this disclosure, a multiprocessor computer system may include a memory computer, which includes a computing engine and storage elements for storing multi-digit numbers. In some embodiments, at least some (e.g., all) of the different bits of the multi-digit number are stored at different storage element addresses in the storage elements. In some embodiments, the memory computer is operable to provide one or more storage element addresses to the storage elements and retrieve bits of different multi-digit numbers having a common bit location from the storage elements. In some embodiments, the computing engine includes a bit multiplier for multiplying the bits of different multi-digit numbers having a common bit location, providing a product for each pair of multiplied bits. In some embodiments, the computing engine includes a group counter for counting the digits of the non-zero products of the multiplied bit pairs. In some embodiments, at least some of the different bits of the multi-digit number are stored in different, simultaneously accessible storage elements in the storage elements (e.g., stored in different memory groups in response to different memory addresses). These bits can be multiplied and counted simultaneously using separate bit multipliers and group counters, thereby reducing the time, number of cycles, and energy required to compute the dot product of multi-digit numbers.

[0022] Computational memories or storage elements that can be addressed simultaneously and accessed individually can be separate memory banks. As used herein, different memory banks that respond to a common memory address can be considered to have different memory addresses because different memory banks are different memory banks that respond to different and separate enable, power, or access signals that can be considered part of a memory address.

[0023] Embodiments of this disclosure provide fast, efficient, and low-power digital computing circuits suitable for matrix multiplication, such as those commonly found in pattern matching, machine learning, and artificial intelligence applications. Attached Figure Description

[0024] The foregoing and other objects, aspects, features, and advantages of this disclosure will become more apparent and better understood from the following description taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a schematic block diagram of a memory computer system according to an illustrative embodiment of the present disclosure; Figure 2 This is a memory allocation diagram according to an illustrative embodiment of the present disclosure; Figure 3A This is a flowchart of a write operation of a memory computer system according to an illustrative embodiment of the present disclosure; Figure 3B This is a flowchart of a read operation of a memory computer system according to an illustrative embodiment of the present disclosure; Figure 4A This is a flowchart of a read operation of a memory computer system according to an illustrative embodiment of the present disclosure; Figure 4B This is a flowchart of a write operation of a memory computer system according to an illustrative embodiment of the present disclosure; Figure 5A This is a flowchart of a read operation from a second address different from the first address after a write operation to a first address for a memory computer system according to an illustrative embodiment of the present disclosure, wherein data in the first address is processed; Figure 5B This is a flowchart of a read operation from any one of a plurality of second addresses different from the first address after a write operation to a first address for a memory computer system according to an illustrative embodiment of the present disclosure, wherein data in the first address is processed according to the second address; Figure 6A , Figure 6B and Figure 7 This is a hardware block diagram of a memory computer according to an illustrative embodiment of the present disclosure; Figure 8 This is a hardware block diagram of a memory computer having a multidimensional array of computing elements according to an illustrative embodiment of the present disclosure; Figure 9 This is a schematic diagram of a memory computer system with a serial accumulator according to an illustrative embodiment of the present disclosure; Figure 10 This is a schematic diagram of a two-dimensional array of memory elements and a one-dimensional array of computing elements according to an illustrative embodiment of the present disclosure; Figure 11A and Figure 11B The rows and columns of bits in binary multiplication, which are useful in understanding embodiments of this disclosure, are shown; Figure 12A It is a pseudocode calculation with bit-serial accumulation of row-by-row dot product according to an illustrative embodiment of the present disclosure; Figure 12B This is a flowchart of column-by-column dot product calculation with bit-serial accumulation according to an illustrative embodiment of the present disclosure; Figure 13A This is a schematic block diagram of a controller, computing memory, and computing engine with digital processing according to an illustrative embodiment of the present disclosure; Figure 13B This is a schematic block diagram of a controller, computing memory, and computing engine with analog processing according to an illustrative embodiment of the present disclosure; Figure 14A This is a schematic diagram illustrating digital bit multiplication and serial accumulation according to an illustrative embodiment of the present disclosure; Figure 14B This is a schematic diagram illustrating analog bit multiplication and serial accumulation according to an illustrative embodiment of the present disclosure; Figure 15A This is a hardware block diagram of a bit multiplier computing element including transistors according to an illustrative embodiment of the present disclosure. Figure 15B This is a hardware block diagram of a bit multiplier computational element including transistor pairs according to an illustrative embodiment of the present disclosure; and Figure 16 This is a logic diagram of the first stage of a group counter according to an illustrative embodiment of the present disclosure; The features and advantages of this disclosure will become more apparent from the specific embodiments set forth below, taken in conjunction with the accompanying drawings, in which the same reference numerals consistently identify corresponding elements. In the drawings, the same reference numerals generally denote identical, functionally similar, and / or structurally similar elements. The drawings are not necessarily drawn to scale. Detailed Implementation

[0025] In some embodiments of this disclosure, the multiprocessor computer system includes a memory computer, which includes a memory mode controller, a compute memory, and a compute engine. The compute memory is operable to store data and is accessible by the memory mode controller and the compute engine. The compute engine is operable to read, write, and process data stored in the compute memory. The compute memory may include one or more memory elements. Each memory element may store one or more bits, such as a single value of any number of bits, including bits, bytes, words, long words, or bits. The compute engine may include one or more compute elements. Each compute element may include one or more processing elements, such as bit multipliers. As used herein, the term compute engine may refer to one or more compute elements or collectively to a plurality of compute elements.

[0026] Embodiments of this disclosure may include a processor located external to and connected to a memory computer, and operable to write data to and read data from at least some portions of the compute memory by sending function commands and addresses to a memory mode controller. Function commands may include read and write commands. Optionally, in some embodiments, the processor sends data to or reads data from the memory mode controller. In some embodiments, the processor sends data directly to or reads data directly from the compute memory or compute engine.

[0027] According to embodiments of this disclosure and as follows Figure 1As shown, a multiprocessor computer system 80 typically includes a memory computer 10 and a processor 70 located external to and connected to the memory computer 10. The memory computer 10 may include a memory mode controller 12 (or MMC 12), a computing engine 30, and a computing memory 20 for storing data (e.g., memory accessed via addresses). The computing engine 30 is operable to read, write, and process data stored in the computing memory 20 of the memory computer 10. The processor 70 may have a memory address space for writing data to at least some of the computing memories in the computing memory 20 and for reading data from at least some of the computing memories in the computing memory 20. The memory mode controller 12 may operate as an interface between the processor 70 and the computing memory 20, or as an interface between the processor 70 and both the computing memory 20 and the computing engine 30, such as... Figure 1 As shown. In this embodiment, the address lines and function lines (e.g., read lines or write lines) of the processor 70 are connected to the memory mode controller 12. Therefore, the memory mode controller 12 is operable to, for example, read processed data from or write processed data to the memory element 22 of the computing memory 20 in response to the processor 70, or perform both. The memory element 22 is also a bit cell 22 for storing one or more bits and a storage element 22 for storing data. Similarly, the memory mode controller 12 is operable to read processed data from or write processed data to the data storage (e.g., registers) in the computing engine 30, or perform both. Furthermore, the memory mode controller 12 is operable to transform, map, or convert addresses received from or written to the processor 70 within the memory address space of the processor 70 accessible to the memory computer 10. The conversion or transformation of memory addresses from or to the processor 70 by the memory mode controller 12 can be a memory mapping operation, and the converted or transformed address is a memory-mapped address.

[0028] Signals transmitted to and received from the processor 70 can communicate via a bus 13 (e.g., a busbar) connecting the processor 70 to the memory mode controller 12. The memory mode controller 12 is operable to intercept any combination of read signals, write signals, other functional signals (collectively referred to as functional signals 13A), address signals 13B, and data signals 13C sent from the processor 70 to the compute memory 20 or compute engine 30, and convert them into signals suitable for embodiments of this disclosure. Similarly, the memory mode controller 12 is operable to intercept any combination of read signals, write signals, other functional signals (collectively referred to as functional signals 13A), address signals 13B, and data signals 13C sent from the compute memory 20 or compute engine 30 to the processor 70, and convert them into signals suitable for embodiments of this disclosure. The bus 13 may include wires or lines (e.g., electrical conductors or optical conductors) carrying or transmitting signals, and the wires, lines, or signals herein have common labels to avoid confusion; for example, the wires or lines and the signals transmitted on the wires or lines may have the same labels and references. Therefore, the processor 70 can be connected to the memory mode controller 12 using any combination of function lines 13A (including read or write control lines), one or more address lines 13B, and one or more data lines 13C, and the memory mode controller 12 can be connected to the computing memory 20 and the computing engine 30 using any combination of the same lines or other lines necessary to control or interact with the computing memory 20 and the computing engine 30.

[0029] In some embodiments, the memory mode controller 12 (also referred to herein as MMC 12) is operable to map (e.g., modify, translate, or transform addresses provided by the processor 70 to access memory element 22 locations (addresses) to other different memory element 22 locations (addresses) in compute memory 20, such as the memory element 22 address location where compute engine 30 stores (writes) processed data. In some embodiments, compute engine 30 stores or accesses processed data in or from local memory or registers separate from compute memory 20, and MMC 12 maps read or write addresses from processor 70 to local memory or registers. Mapping addresses means translating, modifying, or transforming addresses indicating one physical memory location to another different physical memory location. By utilizing MMC 12 to map read or write addresses from processor 70 to memory element 22 (or other memory or register devices), the interface and control for storing, processing, and accessing processed data by processor 70 are greatly simplified, and a simple, well-understood, or standardized interface from processor 70 to memory computer 10 is provided, thereby reducing and simplifying the system interface complexity, hardware, and software of processor 70.

[0030] Therefore, in some embodiments of this disclosure, the multiprocessor computer system 80 may include a memory computer 10, which includes a computing engine 30 for storing data, a computing memory 20, and a processor 70 located external to and connected to the memory computer 10. The processor 70 may have a memory address space for writing data to and reading data from at least some of the computing memories in the computing memory 20. The computing engine 30 is operable to read, write, and process data stored in the computing memory 20 of the memory computer 10, and is operable to process data stored in the memory element 22, for example, in response to a read operation (e.g., a read command or read function) by the processor 70 on the memory element 22, or in response to a write operation (e.g., a write command or write function) from or by the processor on the memory element 22, or both. The processed data may be stored in the computing memory 20, in local storage in the computing engine 30, transferred to the MMC 12, or provided directly to the processor 70 in response to operations by the processor 70. Data line 13C used by processor 70 can transmit binary data stored on bit line 24 (BL 24) and is intended for writing to or reading from compute memory 20 at addresses transmitted on word line 26 (WL 26). Therefore, data line 13C may include or be bit line 24, and address line 13B may include or be word line 26. In some embodiments, a write operation causes compute memory 20 to receive data and compute engine 30 to operate on the written data to process the data and store the processed data value in compute memory 20. In some embodiments, a read operation causes compute engine 30 to access data in compute memory 20, operate on the accessed data to process the data, and return the processed data value to MMC 12 or directly to processor 70.

[0031] Processor 70 can be any computing device external to memory computer 10, such as a stored program machine or state machine (e.g., a digital or analog computer, processor, or controller). Memory computer 10 can include any of the aforementioned elements or logic circuits or other computing or data processing circuits or systems, and computing memory 20 can be any data storage structure as described above or a memory device such as a register or flip-flop or an addressable memory device such as SRAM or DRAM. Memory mode controller 12 (MMC 12) can similarly include or be circuitry, such as logic circuitry or digital, analog, or mixed-signal circuitry, for example, implemented in an integrated circuit, such as CMOS circuitry, including electronic devices such as transistors, diodes, capacitors, and resistors. MMC 12 can include one or more packaged integrated circuits, or can be incorporated into other components of memory computer 10, for example, packaged together with computing memory 20 or computing engine 30.

[0032] In some embodiments, during operation, a write request (e.g., a write control signal) from processor 70, having a data value (e.g., on data line 13C) and a write address (e.g., on address line 13B), is intercepted by MMC 12. In some embodiments, only the write address (e.g., transmitted on address line 13B) is intercepted by MMC 12, and the data value is directly transmitted on data line 13C to compute memory 20 or compute engine 30. In other embodiments, both the write address (e.g., transmitted on address line 13B) and the data value (e.g., transmitted on data line 13C) are intercepted by MMC 12. In some embodiments, MMC 12 does not modify the write address, and the data value is written to compute memory 20 at the write address. In some embodiments, the write address is modified by MMC 12 (e.g., converted, mapped, or transformed), and the data value is written to compute memory 20 or compute engine 30 at a different modified (e.g., memory-mapped) address. In some embodiments, the write operation is then completed. However, in some other embodiments, the write control signal is intercepted by MMC 12, and, for example, after or independently of writing the data value, a control signal (e.g., control signal F) for computing engine 30 is triggered to process the written data value or other stored data values ​​that are not part of the write request. The processed data may be stored in one or more computing memories 20 or in memory, registers, or flip-flops in computing engine 30 (e.g., memory element 22).

[0033] In some embodiments, during operation, a read request (e.g., a read control signal) and a read address (e.g., on address line 13B) from processor 70 are intercepted by MMC 12. In some embodiments, only the read address (e.g., transmitted on address line 13B) is intercepted by MMC 12, and any data value returned in response to the read request can be transmitted directly from compute memory 20 or compute engine 30 on data line 13C. In other embodiments, both the read address (e.g., transmitted on address line 13B) and the data value (e.g., transmitted from compute memory 20 or compute engine 30) are intercepted by MMC 12. In some embodiments, the read address is not modified by MMC 12, and the data value is read from compute memory 20 at the read address. In some embodiments, the read address is modified by MMC 12 (e.g., converted, mapped, or transformed), and the data value is read from compute memory 20 or compute engine 30 at different modified (e.g., memory mapped) addresses, for example, using a lookup table that defines memory mappings and possible functional operations. In some embodiments, the read operation is then completed. However, in some other embodiments, the read control signal is intercepted by MMC 12 and triggers control signals (e.g., control signal F) for computing engine 30 to process data values ​​stored in computing memory 20 or computing engine 30. The processed data may be stored in memory, registers, or triggers in computing engine 30, or in one or more computing memories 20. In either case, in embodiments, memory computer 10 is operable to return processed data to processor 70 in response to a read operation (or even in response to a write operation), for example, on data line 13C.

[0034] As used herein, for example, the address of a read or write operation provided by processor 70 may be referred to as an "RW address" to distinguish it from a translated (modified, transformed, or mapped) address that is different from an RW address provided by processor 70. An RW address may be an address in the memory space of processor 70. A read operation or command of processor 70 with an RW address is operable to read data, for example, processed data, from memory element 22 or other memory or register mapped to the RW address by MMC 12, and to provide the read data to processor 70, for example, on data line 13C. A write operation or command of processor 70 with an RW address is operable to write data from processor 70 (e.g., from data line 13C) to memory element 22 or other memory or register mapped to the RW address by MMC 12.

[0035] In some embodiments, the MMC 12 can map read and write addresses, such as... Figure 2As shown, however, MMC 12 is not limited to such a specific embodiment; as those skilled in computing and digital design will understand, other embodiments providing similar functionality are also possible. Figure 2 As shown, the memory space of processor 70 may include multiple portions or memory groups. Computational memory 20 may have a logical address at the starting address of any memory group, and this logical address is selected to accommodate processor 70 and any other memory associated with processor 70. The first portion of computational memory 20 (in...) Figure 2 The memory address space (marked as starting from the "memory group start address") and the address associated with the first part can be interpreted by the MMC 12 as normal SRAM access, allowing any data read or written from or written to the RW address that has a value within the memory address space as normal memory. In such an embodiment, the MMC 12 does not need to modify, convert, map, or transform the RW address, and the computation memory 20 in the memory computer 10 is programmed (e.g., using firmware or address logic) to respond to RW addresses via read or write memory operations.

[0036] In contrast, the RW address in the 20 address space of the computation memory (from) Figure 2 The address (starting from the "mapped start address") can be modified, mapped, converted, or transformed to allow access to and processing of data values ​​other than the data value stored at address RW in compute memory 20 in response to a read operation. For example, a data value can be written to address 100 of compute memory 20. 16 (All addresses are assumed to be in hexadecimal notation). Subsequent read operations at address 200 of compute memory 20 can access, process, and return the data value at address 100. MMC 12 analyzes RW address 200 and modifies it to address 100 to access data and perform operations. Alternatively, the data value can be written to address 200, and subsequent read operations to address 200 can trigger compute engine 30 to process the data value written to address 200 of compute memory 20 and return the processed value. Optionally, the processed value can be written to compute memory 20.

[0037] In some embodiments and as Figure 2 As shown, the address space of the memory computer 10 (e.g., IMC 10) can map multiple copies of data stored in the memory address space or the IMC address space. For example, the IMC address space can be subdivided, such as... Figure 2As shown by the dashed line. Therefore, data values ​​can be written to the memory address space, for example, at address 100. If processor 70 performs a subsequent read operation from address 200 (e.g., in the IMC address space), computing engine 30 can perform a first processing (e.g., function, operation, or algorithm) on the data at address 100 in response to a control signal from MMC 12. If processor 70 performs a subsequent read operation from address 300 (e.g., in the IMC address space), computing engine 30 can perform a second different processing on the data at address 100. If processor 70 performs a subsequent read operation from address 400 (e.g., in the IMC address space), computing engine 30 can perform a third different processing on the data at address 100. Therefore, depending on the address provided by the read operation, the read operation can trigger different functional operations on the data stored in computing memory 20. In some embodiments, MMC 12 can analyze the function value (e.g., provided by processor 70 on function line 13A) to determine the desired operation and control computing engine 30 to perform the indicated operation, instead of using a different read address.

[0038] Any memory, register, or flip-flop in compute memory 20 and (more generally) memory computer 10 can be logically mapped to the memory space of processor 70 using logic circuitry and stored variables, thereby simplifying the logical interface between processor 70 and memory computer 10. According to embodiments of this disclosure, processor 70 can write one or more data values ​​to memory computer 10 and then read processed data values ​​from memory computer 10 without requiring further operations by processor 70 and using, for example, conventional memory (e.g., static random access memory (SRAM) or dynamic RAM (DRAM)) read and write memory control signals, thereby simplifying the hardware, software, or logical interface between processor 70 and memory computer 10, and also improving performance by reducing the number of data write or read (access) operations in the system.

[0039] In embodiments of this disclosure, the operation of the computing engine 30 can respond to one of a plurality of different addresses (write address or read address). For example, if data is read using a first address, a first function can be performed on the data stored in the computing memory 20, and if data is read using a second address different from the first address, a second function different from the first function can be performed. The MMC 12 can control the computing engine 30 to process data differently in response to different read addresses, and also controls memory mapping such that data is returned from the same data storage location in the memory element 22 or the computing engine 30, or in other embodiments, processed data is returned from different physical memories. Similarly, if data is written using a first address, a first function can be performed on the data stored in the computing memory 20, and if data is written using a second address different from the first address, a second function different from the first function can be performed. The MMC 12 can control the computing engine 30 to process data differently in response to different write addresses, and also controls memory mapping such that data is written to the same data storage location in the memory element 22 or the computing engine 30, or in other embodiments, the written data is stored in different memories. Therefore, the computing engine 30 is operable to process data differently based on one of a plurality of different RW addresses.

[0040] The memory mode controller 12 may include analysis circuitry 19 for analyzing RW addresses and controlling the compute engine 30 in response to address analysis. Analysis circuitry 19 may include logic circuitry, which may be programmable or may include one or more state machines. In some embodiments of this disclosure, at least one memory element 22 of the compute memory 20 is mapped to multiple addresses in the memory space of the processor 70, and the memory mode controller 12 is operable to map a write address to a write memory element 22 of the compute memory 20 in response to a write operation from the processor 70, and to map a read address to a different read memory element 22 in response to a read operation from the processor 70. Therefore, in embodiments, depending on the address-associated functionality of the processor 70, the MMC 12 may map the same RW address received from the processor 70 to one or more different physical compute memories 20.

[0041] In some embodiments, different functions may be provided to the MMC 12. For example, a single bit may encode a read or write signal or operation, but multiple function lines 13A may provide additional function signals to the MMC 12. The additional function lines 13A may specify different operations performed in conjunction with read or write operations of the computing engine 30. The MMC 12 may input and analyze the function signals 13A provided by the processor 70 and control the computing engine 30 in response to the analyzed functions. The function signals 13A may also encode read or write operations. Thus, in some embodiments, the memory computer 10 includes a memory mode controller 12, the processor 70 is connected to the memory mode controller 12 via any combination of one or more function lines 13A, one or more address lines 13B, and one or more data lines 13C, the memory mode controller 12 is connected to the computing memory 20 and the computing engine 30, and the computing engine 30 is operable to process data in different ways (e.g., using different functions, algorithms, or mathematical operations) according to the function signals 13A provided from the processor 70 to the MMC 12.

[0042] In some such embodiments, the memory mode controller 12 may control the computing engine 30 in response to function line 13A to process data stored in memory element 22. In embodiments, the memory mode controller 12 is operable to map a write address to write memory element 22 in response to a write operation from processor 70, and to map a read address to a different read memory element 22 in response to a read operation and function line 13A. The memory mode controller 12 may include analysis circuitry 19 for analyzing function signal 13A and controlling the computing engine 30 in response to function line analysis. In some embodiments, RW addresses are mapped to at least two or three different computing memories 20, and the computing engine 30 processes data differently according to function signal 13A, for example, in response to control signals from MMC 12. Analysis circuitry 19 may analyze both or either function signal 13A and address signal 13B. The use of one or more function lines can increase the diversity of functions performed by the computing engine 30 and thus increase the utility of the memory computer 10.

[0043] Figures 3A to 5B The flowcharts illustrate various methods of this disclosure performed by the in-memory computer 10. In these figures, each vertical column refers to a function or operation performed by a device or circuit labeled at the top of the column. Figure 3A This illustrates a simple write operation without associated compute engine 30 operations (no data processing). For example... Figure 3AAs shown, in step 100, processor 70 issues a write command (e.g., on function line 13A and optionally with additional functions indicated on function line 13A) having an RW address (e.g., on address line 13B) and a data value (e.g., on data line 13C). MMC 12 receives the issued write command, and in step 110, analyzes the write command (e.g., in conjunction with any other function signal 13A) to determine that compute engine 30 does not perform any operation, and passes the write command to compute memory 20. In step 120, compute memory 20 stores the data value at the RW address. This process can be operationally similar to a regular write command provided by processor 70 to SRAM or DRAM or any other useful memory compatible with read or write commands provided by MMC 12, processor 70, or compute engine 30.

[0044] like Figure 3B As shown, in step 105, processor 70 issues a read command with an RW address (e.g., on address line 13B) (e.g., on function line 13A and optionally with additional functions indicated on function line 13A). MMC 12 receives the issued read command and analyzes it in step 110 (e.g., in conjunction with any other function signal 13A) to determine that compute engine 30 does not perform any operation, and then passes the read command to compute memory 20. In step 125, compute memory 20 reads the data value at the RW address. In step 150 (e.g., on data line 13C), the read data value is returned (step 150 can be functionally the same as reading step 125). This process can be operationally similar to a regular read command provided by processor 70 to SRAM or DRAM.

[0045] According to embodiments of this disclosure, it can be done as follows Figure 4AAs shown, a data read operation is performed. In step 105, processor 70 may issue a read command (e.g., on function line 13A and optionally with additional functions indicated on function line 13A) having an RW address (e.g., on address line 13B). MMC 12 receives the issued read command, analyzes the read command and RW address (e.g., in conjunction with any other function signal 13A, if present) in step 115 to determine that computing engine 30 will perform an operation on data stored in computing memory 20 (stored at the RW address or the address of the translation (memory mapping)), and passes the read command to computing memory 20 and computing engine 30. Computing memory 20 reads the data value at the address determined by MMC 12 in step 115 and provides the data value to computing engine 30 in step 125. Computing engine 30 processes the data value in step 130 and returns the processed data to processor 70 in step 150. Optionally, in step 140, the processed data is stored in computing memory 20. Therefore, in step 150, the simple read operation of processor 70 (step 105) returns the processed data without any further operation by processor 70, thereby providing a simple interface to processor 70.

[0046] According to embodiments of this disclosure, a data write operation can be performed in step 100, such as... Figure 4B As shown. Then, as referenced Figure 4A The process proceeds to steps 115, 125, and 130. In step 150, the processed data can be returned to processor 70. Optionally, in step 140, the processed data is stored in computing memory 20. This allows the data to be stored in computing memory 20 for further operations in subsequent processing steps.

[0047] Figure 5A The method of this disclosure is illustrated, wherein the processed data is stored in computing memory 20 at a physical location different from the original data, source data, or input data. For example... Figure 5AAs shown, data is first written to RW address A by processor 70 in step 100. In response to the write command, the RW address is analyzed by MMC 12 in step 110, and the data is stored in compute memory 20 in step 120. Subsequently, in step 125, processor 70 reads back the written data using the same RW address A. MMC 12 receives the RW address and read command, analyzes the RW address in step 115, and controls compute memory 20 in step 130 to access the stored data and compute engine 30 to process the stored data. In this method, the processed data is stored at address B, which is different from RW address A, in step 140, and returned to processor 70 in step 150. Therefore, in effect, the processor 70's read operation on RW address A returns the processed data stored at address B. The processing and storage location details in memory computer 10 are invisible to processor 70, thereby simplifying the interface between processor 70 and memory computer 10, reducing the number of operations of processor 70, and improving performance.

[0048] Figure 5B The method of this disclosure is illustrated, wherein a read operation on an address can specify an operation on data stored at that address or another address. For example... Figure 5B As shown, data is first written to RW address A by processor 70 in step 100. In response to the write command, the RW address is analyzed by MMC 12 in step 110, and the data is stored in compute memory 20 in step 120. Subsequently, in step 125, processor 70 reads back the written data using an RW address different from A. MMC 12 receives the RW address and read command, analyzes the RW address in step 115, and, based on the address selection operation provided by MMC 12, controls compute memory 20 in step 430 to access the stored data and compute engine 30 to process the stored data. For example, if the RW address is B, operation X is performed; if the RW address is C, operation Y is performed; and if the RW address is D, operation Z is performed. The processed data can be stored in any suitable storage location (e.g., physical locations A, B, C, or D), and in step 150, it is returned to processor 70. In some embodiments, processed data can be directly returned to processor 70, and MMC 12 does not need to actually perform operations, especially if data line 13C does not pass through MMC 12. Therefore, processor 70 effectively performs the selected operation on the data using a read operation at the selected address. The processing and storage location details in memory computer 10 are invisible to processor 70, thereby simplifying the interface between processor 70 and memory computer 10, reducing the number of operations performed by processor 70, and improving performance.

[0049] Typically, the MMC 12 can control the computing engine 30 to perform one or more operations based on signals provided on function line 13A. The processor 70 can provide the MMC 12 with address A on address line 13B, data D on data line 13C, and function F on function line 13A. In some embodiments, function F is a read (R) or write (W) command; in other embodiments, function F can be encoded as a processing operation. The MMC 12 receives A, optionally D, and F, and analyzes at least address A and function F. If a write operation F is indicated (e.g., F=W), data D is written to the computing memory 20. If a read operation F is indicated (e.g., F=R), data D is read from the computing memory 20. If the function operation is indicated by function line 13A or by an address specification, the computing engine 30 accesses the stored data and, in response to the specification, processes the data according to control signals (instructions) provided by the MMC 12. The control signals provided by the MMC 12 can depend on function F, address A, or a combination of both. After the computing engine 30 has finished processing the data, the data may be stored in the computing memory 20 and returned to the processor 70, or, for example, returned directly to the processor 70 on the data line 13C.

[0050] In some embodiments of this disclosure, default operations are performed by computing engine 30 in response to read or write requests from processor 70, and no additional functional information is required or provided (e.g., on function line 13A).

[0051] In some embodiments, a single read (or write) operation can perform an entire vector or matrix operation. For example, processor 70 can write multiple data vectors into the memory address space. MMC 12 can detect a single read operation from one address (or another address location) in the memory address space where the data vectors are stored, and computation engine 30 can perform an entire vector operation (e.g., dot product) on the multiple data vectors to produce a single value returned to processor 70. The operation performed can depend on the address of the read operation, such as the IMC address space or the vector space.

[0052] Figure 2The output space indicated in the configuration may provide additional storage accessible to the processor 70 within the compute memory 20, or provide readable storage for processed data (e.g., an extension of the memory address space). Configuration and operation values ​​specifying functional operations and data types (e.g., data formats and vector specifications) may be stored in the configuration (configuration) and state spaces. Read or write operations on data stored in the compute trigger space may also trigger data processing functions of the compute engine 30. These locations may also specify the interaction between the compute engine 30 and the processor 70 in handling data access, for example, specifying data polling, blocking or non-blocking reads or interrupts. These functions may be specified by the format of a bus that transmits data, addresses, and functions (e.g., an APB, AHB, or AXI bus or any other suitable bus) (e.g., bus 13).

[0053] By providing a compiler for the programming language that automatically controls the operation of the processor 70 and the memory computer 10, the processor 70 and the memory computer 10 can operate together without the user's visibility. The operation of the MMC 12, the compute memory 20, and the compute engine 30 can be controlled by compiled object or machine code. Such a compiler can manage access to the memory bank of the compute memory 20 and the functional operation of the compute engine 30 of the processor 70, so that the processor 70 program substantially controls the memory computer 10. In some embodiments, a compiler is not required, and processor 70 hardware signals (e.g., read, write, or function signal 13) can be interpreted by the memory computer 10 (e.g., by the MMC 12) to perform the desired operation.

[0054] In some embodiments of this disclosure, the computing engine 30 processes data very quickly, and the processor 70 experiences no more latency when receiving processed data than in the case of SRAM. In other embodiments, the processor 70 may experience some latency. In such embodiments, the multiprocessor computer system 80 may include a read or write handshake (e.g., interactive control signals specified by bus 13 format and control signals) to indicate to the processor 70 that the processed data is ready and a read operation can be performed.

[0055] According to embodiments of this disclosure, the memory computer 10 can be designed to share the same functionality and physical interface as conventional SRAM. This compatibility allows the memory computer 10 to be seamlessly integrated into existing computer platforms (e.g., processor 70) without requiring any major architectural changes. For applications with greater hardware engineering flexibility, the memory computer 10 can be instantiated with optional interface signals to control computation and optimize system integration.

[0056] Figure 6A , Figure 6B and Figure 7This is a hardware block diagram illustrating an embodiment of the present disclosure, wherein different components (blocks) of the memory computer 10 are shown with different shades. Figure 6A , Figure 6B and Figure 7 As shown, portions of the memory computer 10, which may be the memory mode controller 12 (MMC 12), are shown in the lightest shade, medium shades represent bit cells 22 of the compute memory 20, and the darkest shades represent elements of the compute engine 30. Some blocks are arbitrarily allocated; for example, a compute engine 30 buffer can be considered part of compute memory 20, compute engine 30, or MMC 12. Similarly, the configuration and state spaces can be considered part of compute memory 20 or MMC 12. Data stored in compute memory 20 can be accessed (e.g., read or write) via bit lines 24 (data lines that transmit data values) and word lines 26 that transmit addresses, such as... Figure 1 As shown.

[0057] Computational memory 20 may include multiple independently addressable memories, for example, enabling simultaneous access to two different sets of numbers stored in different memories. Therefore, computational memory 20 may include multiple independently addressable memories, or memory computer 10 may include multiple computational memories 20.

[0058] As shown in the figure Figure 6A , Figure 6B and Figure 7As shown, the memory computer 10, including a memory mode controller 12, computation memory 20, and computation engine 30, may be, include, or be configured as a dot product calculator. The dot product calculator may include a controller (e.g., processor 70 or MMC 12), computation memory 20 (e.g., including bit cells 22), computation engine 30 including an AND gate 14 (e.g., bit multiplier 14) having two unit inputs and providing a unit output equal to the product of the input bits, a group counter 34 (e.g., including bit counter 34), and a serial accumulator 38 (e.g., including analog or digital shift and accumulate circuitry 38 or SAC 38). Computation memory 20 may include multiple independently addressable memories or groups of memories, such as computation memory 20A and computation memory 20B. In some embodiments, the bit product may be stored as a digital value (e.g., in a flip-flop, register, or other one-bit memory) or an analog value (e.g., as charge in a capacitor), and the serial accumulator 38 may be a digital accumulator including one or more digital adders or an analog accumulator using capacitors. A controller (e.g., MMC 12) is operable to sequentially provide memory addresses to compute memory 20. In an embodiment, MMC 12 simultaneously provides at least two separate addresses to independently addressable compute memories 20A and 20B to read two different datasets stored at the two separate addresses, for example, corresponding to two different numbers. Compute memory 20 is operable to receive (input) memory addresses from the controller and store at least two vectors (tuples) X and Y. Each vector X and Y may have N numbers (elements in the tuple), and each number in the vector may be represented here by a subscript n (e.g., X...). n and n Each binary number n can have at least B bits, and each bit in binary number n is individually referenced here as b, with an index corresponding to that bit (e.g., with an index corresponding to the value of the element in a tuple). n Or Y n (The subscript of the position in the middle).

[0059] MMC 12 can organize vector values ​​in various different ways within computational memory 20. For example... Figure 6AAs shown, the same bits (e.g., having the same position value) of each of the N numbers in vector X can be accessed simultaneously in parallel, for example, at a common address stored in bit units 22 at least N bits wide (e.g., for each individual address applied to computation memory 20, N bit units 22 return N bits), where each number in vector X has b bits. The numbers in vector Y can similarly be stored at different addresses in computation memory 20, where the same bits (e.g., having the same position value) of each number in vector Y are accessible in parallel, where each number in vector Y has c bits. Computation memory 20 can be at least deep enough to store the bits of each number in vectors X and Y (e.g., 2B bit deep if the same number has bits and therefore computation memory 20 for at least 2B different addresses). In the example, the numbers in both vectors X and Y have eight bits, for example, for at least one value X. n The eight bits and the value Y for at least one value n The eight bits, for a total of sixteen bits, require sixteen different memory addresses. MMC 12 can control computation memory 20 to simultaneously access bits that share a common positional value for all N values ​​in vector X and bits that share the same positional value for all values ​​in vector Y. (In contrast, a regular read provides all bits of a stored number.) The corresponding bits (e.g., those with the same positional value b) are then applied to an array of bit multipliers (AND gates) 14. The bit product is counted by a group counter 34, shifted according to bit position b (e.g., bit position b), and accumulated by a serial accumulator 38. This process is repeated for each bit b from zero to B (here, B is the largest number of bits in the numbers of vector X or vector Y) to provide the dot product of vectors X and Y.

[0060] Figure 6B An embodiment is shown having two or more computational memories 20 (e.g., 20A, 20B, 20C...) that can be accessed simultaneously by different memory addresses. In some such embodiments, multiple arrays of bit multipliers 14 (AND gates 14) can be provided for bits with different bit positions in the numbers of vectors X and Y. By storing bits with different bit positions in different computational memories 20 in response to different memory addresses (e.g., in different memory groups) and applying these bits to different arrays of bit multipliers 14, different bits with different bit positions can be computed and counted simultaneously. Each array of bit multipliers 14 provides a product that is counted simultaneously by different group counters 34. Figure 6B A separate computation memory 20 is shown for the numbers in vector Y only, but a separate computation memory 20 could be provided for the numbers in each vector whose dot product is computed (e.g., also for the numbers in vector X). Figure 6BThe connections of bits from the additional bit multiplier 14 to the numbers in the X vector are not fully shown, but are indicated and labeled "X". Once bits from each individual compute memory 20 are multiplied, these bits are counted (e.g., using a separate group counter 34), each count is shifted to fit the bit position of the product, and the counts are accumulated. If different compute memories 20 and group counters 34 are provided for each bit position, all counts can be accumulated in parallel at once. If only some bits are multiplied and counted at a time, the remaining bits can be accumulated sequentially. For example, if a number has eight bits stored in two different, simultaneously accessible compute memories 20 (e.g., with two different memory groups), two bits of each number in the vector can be multiplied and counted at once. Multiple bits require four (eight divided by two) cycles, and the serial accumulator 38 accumulates serially four times. Typically, multiple different bits can be stored using separately accessible compute memories 20 for different numbers, and bits in different compute memories 20 can be multiplied, counted, and accumulated simultaneously. The number of accumulation cycles depends on the number of bits and the number of different compute memories 20 that can be accessed individually and simultaneously. Using multiple compute memories 20 (multiple memory groups) can increase throughput because fewer accumulation cycles are required and the power used can be reduced.

[0061] The embodiments disclosed herein are not subject to Figure 6A and Figure 6B The limitation of storing two vectors in a diagram. More generally, as Figure 7 As shown, MMC 12 can store vectors in any desired format and access the corresponding bits of the numbers in each of vectors X and Y with the same position values ​​in any desired order, to sequentially provide, count, and serially accumulate the bits of each number in vectors X and Y as multipliers and multipliers. Figure 6A , Figure 6B and Figure 7 An embodiment of the computation engine 30 including a one-dimensional array of numbers with bit multipliers 14 (equivalent to AND gates 14) is shown. In other embodiments of this disclosure and as... Figure 8 As shown, computation memory 20 can receive and store multiple vector pairs, for example, one or more pairs of two-dimensional digital matrices. MMC 12 can control computation memory 20 to sequentially apply multiple vectors stored in computation memory 20, thereby sequentially computing multiple vector operations and providing matrix or tensor operations. As used herein, computation engine 30 can refer to a single bit multiplier 14, a one-dimensional array of bit multipliers 14, or a two-dimensional array of bit multipliers 14, such as... Figure 8 As shown, it may include one or more group counters 34 and one or more serial accumulators 38, for example, one for each vector operation.

[0062] In some embodiments and as Figure 8 As shown, the memory computer 10 includes multiple one-dimensional or two-dimensional arrays of computing engines 30. The multiple arrays of computing engines 30 can, for example, under the control of MMC 12, perform bitwise multiplication of multiple vector pairs, with the products of the multiple vector pairs being accumulated to provide multiple dot products. In some embodiments, the bits of the multiple vector pairs are corresponding bits of a single number (e.g., having a common positional value). In some embodiments, the bits of the multiple vector pairs are corresponding bits of different numbers in a common vector pair (as described above). In some embodiments, the bits of the multiple vector pairs are corresponding bits of numbers in different vector pairs. Therefore, some embodiments of this disclosure include multiple computing engines 30. Each computing engine 30 (a one-dimensional array of bit multipliers 14) is operable to simultaneously multiply the bits of each number in two one-dimensional arrays of numbers. In embodiments, the memory computer 10 includes multiple computing engines 30 sufficient to simultaneously multiply the bits of each number in two two-dimensional arrays of numbers (two matrices).

[0063] In some embodiments, the computation engine 30 includes multiple dot product calculators, such as a two-dimensional array of dot product calculators (e.g., a logically connected two-dimensional array). The multiple dot product calculators can compute multiple vector dot products simultaneously. In some embodiments, the vector pairs in the multiple dot products are in a common matrix. In some embodiments, the vector pairs in the multiple dot products are in different matrices. Similarly, the computer memory 20 may include multiple pairs of independently addressable memories, each of which can provide bits for a pair of numbers used for dot product computation.

[0064] Figure 8 A logic block diagram illustrating an embodiment including a computing engine 30 and multiple arrays is provided. Figure 8 As shown, computation memory 20 can store multiple two-dimensional value arrays of simultaneously accessible values ​​in pairs in computation memories 20A, 20B, for example, multiple two-dimensional matrices, under the guidance of MMC 12. MMC 12 can then access computation memory 20 and provide the two-dimensional matrix (or submatrix) of values ​​to the two-dimensional array of bit multiplier 14 (forming at least a portion of computation engine 30). Each one-dimensional array of computation engine 30 (e.g., the array of bit multiplier 14 together with computation memories 20A, 20B and the corresponding arrays of group counter 34 and serial accumulator 38) then computes a dot product, as described above, thereby producing the entire matrix of scalar results in a single operation.

[0065] According to embodiments of this disclosure, the example of a 1024-element dot product of octet values ​​in two vectors can be extended to provide multiple arrays of computation engine 30 (or computation engine 30 including multiple arrays of bit multipliers 14, for example, such as...) Figure 8(As shown). For example, in embodiments of this disclosure, in response to a read or write command from external processor 70, a dot product between two matrices, each having a 1024 x 1024 octet value, can be performed in a single operation. In this example, computation engine 30 may include a bit multiplier of 1024 x 1024 (equal to 2...). 20 Array 14. Computational memory 20 can be organized to provide 1024 × 1024 bits of values ​​in parallel for each matrix in response to a read command from MMC 12 to computational engine 30, one bit at a time. These bits are multiplied (via bit multiplier 14), counted (via group counter 34), and serially accumulated (via SAC 38) to produce a 1024 × 1024 array of scalar results. Considering the high density of small transistors in a large semiconductor substrate, 2 20 Bit multiplier 14 (e.g., such as Figure 6B and Figures 9 to 1 (As shown in Figure 2) This is easily implemented in the array of the computing engine 30. In fact, the element numbers in each vector and the number of bits in each number in the example are merely illustrative. The memory computer 10 has computing engines 30 with more or fewer numbers, for example, 2. 16 2 18 2 20 2 22 2 24 or 2 26 14-bit multipliers with bit lengths of 4, 8, 12, 16, 20, 24, 28, 32, or 64.

[0066] The dot product calculator may have at least N logical AND gates 14 connected to computation memory 20, such that each AND gate 14, in response to a memory address provided to computation memory 20 by a controller (e.g., MMC 12), simultaneously receives bits b of a number n from vector X and bits b of a number n from vector Y, thereby performing bit multiplication on bit pairs of corresponding numbers (elements) from vectors X and Y that have the same position (same bit b). If the corresponding numbers having a common ordered position in vectors X and Y are referenced by subscript n, and each number X... n and Y n If the bits in the array are referenced by the index b for the bit in B, then for a given b, AND gate 14 can, for all n from zero to (N-1), simultaneously set X... nb Multiply by T nb Then, in response to the sequential memory address provided by the controller, the multiplication is repeated for all b from 0 to B-1, and the products are counted and accumulated.

[0067] For each memory address (each bit b) provided by the controller to the computational memory 20, the group counter 34 is operable to count the non-zero bits from N AND gates 14. The group counter 34 can be or includes one or more digital counters 34 or analog adders 34, and can have a separate input connected to each output of the AND gates 14. For example, the group counter 34 can include a series of counters first used to combine pairs of AND gate outputs (e.g., a one-bit counter providing a two-bit sum with values ​​from 0 to 2 or a triplet with values ​​from 0 to 3), then used to combine two-bit sums (e.g., a two-bit adder providing a three-bit sum with values ​​from 0 to 4), and so on, to produce a final count of all non-zero bits. Skilled digital designers will understand that different logic designs can implement the group counter 34.

[0068] For example and reference Figure 6A and Figure 9 For the bits in vectors X and Y, where N=2 and B=2 in the first loop, it is called X. nb and Y nb (where n is a number in the corresponding vector and b is the bit at the corresponding position of that number), and in response to the first address (e.g., any address 0), AND gate 14 will X 00 Multiply by Y 00 and X 10 Multiply by Y 10 The two products are then presented to the group counter 34, which, if not zero, is counted, and the count is provided to the serial accumulator 38 (thus initializing SAC 38 with the count value). In the second loop and in response to the second address (e.g., address 1), AND gate 14 can convert X... 00 Multiply by Y 01 and X 10 Multiply by Y 11 The two products are then presented to a group counter 34, which counts them, shifts them according to their relative positions, and provides the shifted count to a serial accumulator 38, which effectively multiplies the new count value by a factor of 2 (e.g., by shifting the binary count by one bit, since its position value is twice the existing count value), and adds the second-shifted count value to the existing value. This process is repeated for the second bits of X0 and Y0 and X1 and Y1 to provide the dot product of vectors X and Y.

[0069] More typically, embodiments of this disclosure include computing the dot product of a vector X with M values ​​of B bits and a vector Y with N values ​​of C bits. N and M can be the same or different, and B and C can be the same or different. X is computed at time zero (e.g., using memory address 0). 00 and Y 00 X 10 and Y10 X 20 and Y 20 And so on up to X （N-1）0 and Y （N-1）0 The non-zero bits are counted and stored in the serial accumulator 38. At a subsequent time (e.g., using memory address 1), X is calculated. 01 and Y 00 X 11 and Y 10 X 21 and Y 20 And so on up to X （N-1）1 and Y （N-1）0 The non-zero bits are counted, and this count is serially accumulated by serial accumulator 38 (where the count is shifted by 1). This process is repeated for each combination of bits B in X and bits C in Y, with a shift corresponding to the bit position, for example, to multiply the count by 2. b The shift count is serially accumulated by serial accumulator 38. The final continuous accumulated value is then the scalar result of the dot product.

[0070] In some embodiments, the numbers in each of X and Y have the same number of bits B. In some embodiments, the numbers in X have bits B that are different from the numbers in Y. Furthermore, in some embodiments, vectors X and Y are one-dimensional vectors. In some embodiments, one or both of vectors X and Y are two-dimensional vectors (e.g., two-dimensional matrices). More generally, operands X and Y can be tensors of any dimension having numbers (elements), and the MMC 12 and computation engine 30 can organize the operand elements in computation memory 20, control which elements in the computation operands, and perform the computation. In some embodiments, computation engine 30 can include other computational elements (e.g., in addition to or with bit multiplier 14 (AND gate 14), group counter 34, and serial accumulator 38) to perform other computations (e.g., other vector, matrix, or tensor operations).

[0071] like Figure 9 As shown, the output of the group counter 34 (the sum of the non-zero bits) is provided as a shift count to the serial accumulator 38 (e.g., an analog or digital shift and accumulate circuit 38). The time serial accumulator 38 (SAC 38) is operable to sequentially accumulate the counts of consecutive shifts (from the outputs of N AND gates 14 for each bit b). Each count has a position value corresponding to the bit b for which the count is performed, and is obtained by shifting the count to the position of the visited bit (starting from zero and effectively multiplying by 2). bThe cumulative sum of the counts is adjusted for the position of the counted bit b. The cumulative sum after multiplying, shifting, and serially accumulating all B bits is the dot product (also the inner product or scalar product) of vectors X and Y. This process can be controlled using, for example, a state machine that can be part of the computation engine 30.

[0072] like Figure 10 As shown, bits at the same position in the numbers of vector X are stored at a common address, for example, in computational memory 20, such that these bits can be accessed simultaneously and in parallel in response to each memory address provided by the controller. The numbers in vector Y are similarly stored at different addresses in computational memory 20. The controller can simultaneously provide independent addresses to access bits at the same position in the numbers of vector X and vector Y. Figure 10 Only one set of bit cells 22 is shown. In some embodiments, numerically consecutive addresses can access bits with consecutive positions in each number of vectors X, Y, or both X and Y. Bits with consecutive position values ​​do not necessarily need to be stored at consecutive addresses in computation memory 20 and accessed consecutively, because SAC 38 can shift each count by the amount corresponding to the position of the bit being multiplied, regardless of the bit order in computation memory 20. However, as a logic designer should understand, such digital consecutive memory access of the controller, digital consecutive bit storage in the addresses of computation memory 20, and digital consecutive bit position shifting of SAC 38 can simplify the design of this disclosure. A skilled designer should also understand that the numbers in vectors X and Y can be stored in computation memory 20 before calculating the dot product of vectors X and Y, and the result of the calculation can be stored in memory or a register (e.g., an accumulation register), or otherwise provided to processor 70 using logic circuit design. Furthermore, MMC 12 can organize vectors X and Y in any desired arrangement and access the numbers in the vectors in any order to present the bits for multiplication sequentially using any necessary intermediate storage. In response to a single read or write operation by the processor 70 to any desired location (address) in the compute memory 20, the MMC 12 can provide multiple compute memory 20 accesses (e.g., different accesses simultaneously) and corresponding compute engine 30 operations. Any desired location includes any compute memory 20 location storing vectors X and Y, any compute memory 20 location storing the result of a compute engine 30 operation, or any other desired compute memory 20 location, such as memory mapped by the MMC 12.

[0073] Figure 10An embodiment of computational memory 20 (including bit cells 22) and address lines (e.g., word lines 26) and data lines (bit lines 24) is shown. When accessed, the computational memory and address and data lines provide stored data sensed by sense amplifiers (amps) and provide the sensed stored data to AND gate 14 (bit multiplier 14) for processing in computational engine 30. Figure 10 An array of bit cells 22 for a vector X is shown. Another vector Y may be provided by another portion of computation memory 20, registers or memory in computation engine 30, or received from processor 70 via MMC 12 as a write operation to perform or trigger (initiate) a dot product calculation. In some embodiments, a read operation on the output buffer may trigger a dot product operation in computation engine 30.

[0074] In some embodiments, the computing memory 20 may include a plurality of bit units 22 or groups of bit units 22 (e.g., ...) that store a plurality of multi-digit values ​​accessed and processed by a single computing engine 30. Figure 10 (As shown). The bit cells 22 of the computation memory 20 can be connected to a common bit line 24 and different word lines 26 to enable bit writing into each bit cell 22. In some embodiments, the outputs of each bit cell 22 storing a number (e.g., in a column) can be concatenated together such that only one bit q of that number is connected to the computation engine 30 at a time using different addresses on the bit line 26. Therefore, a single bit q in the bit cell 22 connected to the bit line 24 can be selected by the corresponding word line 26 and operated on by the computation engine 30 at a time. Figure 10 In this context, each column unit can store the number X. n Different bits b, and different columns store different numbers X. n .

[0075] like Figure 11A and Figure 11B As shown in the 4-bit example, each row 21R of the product is a product of one bit of value B multiplied by one bit of value A. (A and B can be numbers in vectors X and Y, respectively, and can have different numbers of bits, although in this illustrative example, each number is shown as four bits.) Figure 11A and Figure 11B In this model, rows are spatially shifted relative to each other to represent the relative size (position) of the product in each row of 21R, much like writing multiplication by hand on paper. Figure 11A As shown. Figure 11BAs shown, the bit products (the values ​​being multiplied) in each bit column 21C of the product (having the same size or position) can be summed. Each column sum has a relative magnitude of 2 (or half) relative to the adjacent bit column 21C. Because each bit column 21C of the product has a different position value (relative size), the values ​​in each column 21 of the product must be scaled to multiply them by their position values ​​before adding them together, for example, shifted by 1 to 6 bits to multiply them by 2, 4, 8, 16, 32, or 64. Scaled and summed column sums provide the product of two multi-bit binary values ​​A and B.

[0076] In embodiments of this disclosure, Figure 12A and Figure 12B The process is illustrated in which, for each value in vectors X and Y, a first value A with C bits and a second value B with D bits are multiplied using a bit-sequential accumulation of the product from bit multiplier 14, wherein the same bits of each value A in vector X are stored at a common address location, and the same bits of each value B in vector Y are stored at a different common address location than value A. Figure 12A and Figure 12B Alternative processes and flowcharts using pseudo-software are shown, illustrating the steps in vector multiplication; those working with logic design and software will find them easy to understand. Figure 12A and Figure 12B The steps shown can be implemented in a state machine or using software applied to the CPU in the MMC 12, and such embodiments are included in this disclosure.

[0077] Figure 12A It shows the method for accumulation Figure 11A The pseudocode implementation of the dot product calculation for each sequential row 21R. For example... Figure 12A As shown, the two index variables A_idx and B_idx indicate the corresponding bit of each of the values ​​A and B in vectors X and Y, and are constrained by the number of bits in each value A_bit_prec and B_bit_prec, respectively. The sum of each bit combination in each value A and B is multiplied (using AND operation), counted, shifted, and accumulated within two nested loops to provide the dot product value of A and B in Acc.

[0078] Figure 12B It shows the method for accumulation Figure 11B The state diagram version calculated using the same dot product of sequence column 21C. For example... Figure 12B As shown, in step 200, the three counter variables i, j, k, and DotProduct are initialized to zero. In the bit-sequence multiplication, i sets the range of bit A of the value A (e.g., bit A...). a ), j sets the range of bit b of value B (e.g., bit B) b ), k is Figure 11BThe relative position or position (shift or multiple of 2) in column 21C. The largest number of digits in A is C, and the largest number of digits in B is D (C and D can be the same, e.g., ...). Figure 11A and Figure 11B (As shown, or different). In step 205, the serial accumulator value is also set to zero. In step 210, bit b is set to j, and in step 215, bit a is set to i, which is the maximum range of bits accumulated in a given column 21C. In step 220, using the array of bit multipliers 14, for each value A in vector X and value B in vector Y, A a Multiply by B b Each bit multiplier returns a single bit that has the same position for each number A and B in vectors X and Y, respectively. These bits are counted by the group counter 34 in step 225 and accumulated in the serial accumulator 38 in step 230 to be located at the common bit position (e.g., in common column 21C, such as...). Figure 11B The total number of bits equal to 1 in (as shown) is added together. (The multiple rectangles in step 220 show the same operation performed on the same bit positions of different numbers in vectors X and Y.) If b is not equal to i (tested in step 235), then all bits in bit position column 21C have not yet been multiplied and accumulated, b is incremented in step 240, a is decremented in step 245, and this process is repeated in steps 220, 225, and 230 until all bits in bit position column 21C are multiplied and accumulated. Figure 11B As shown in column 21C, the bits (indices) of B are incremented from zero to the maximum value i, while the bits (indices) of A are decremented from the maximum value i to zero. Once all bits in a position (column 21C) have been counted and summed (b=i), the sum of column 21C is shifted in step 250 as indicated by counter k (initially zero, equal to i+j), and added to the DotProduct value in step 255, and the next column 21C of the number multiplication can continue. If the maximum number of bits in column 21C has not yet been reached (e.g., bit multiplication still starts with B0), as tested in step 260, i and k are incremented in steps 265 and 270 (where k=i+j), and the serial accumulation process for the next column 21C is performed by first clearing the serial accumulator in step 205. If the maximum number of bits in column 21C has been reached (e.g., C bits in column 21C have been multiplied - Figure 11B The central column 21C in the multiplication) but not all columns 21C have been calculated (tested in step 275), in step 280, i is set to the maximum bit (bit C-1 of value A) so that a can be decremented from its maximum bit position, in step 285, j is incremented to start b at the appropriate bit position, and in step 270, k is incremented to indicate the next bit position (e.g., as Figure 11BAs shown, the next column 21C in the product). If all columns 21C have been calculated (step 275), the process is complete, and the summed value in step 255 is the dot product of vectors X and Y. Figure 12B All operations can be performed by the computing engine 30 using bits A and B accessed from computing memory 20A and 20B via MMC 12.

[0079] The calculation of the dot product can be accomplished by sequentially calculating subsets of numbers A and B in vectors X and Y. Since addition is an cumulative operation, the bits being multiplied can be counted and added in any order (appropriately shifted according to their bit positions). Therefore, if the number of the bit multiplier 14 is less than the number of values ​​in the vector (the length of the vector), then according to embodiments of this disclosure, subsets of the numbers in the vector can be multiplied bitwise and their cumulative sums combined to provide the complete bit product. Thus, the in-memory computer 10 can be applied to vectors, matrices, or tensors of various lengths and is not limited by the physical implementation of the bit multiplier 14 for a specific number in the computing engine 30. Similarly, the in-memory computer 10 is not limited by the number of bits in the multiplied numbers because, according to embodiments of this disclosure, bit multiplication is iterative and accumulates sequentially over time. Larger numbers with more bits can be multiplied using more iterations and time compared to smaller numbers with fewer bits. Therefore, in the computing engine 30 of embodiments of this disclosure, there are no computational limitations on vector length and the number of bits.

[0080] According to embodiments of this disclosure, and as Figure 13A and Figure 13B As shown, each computing memory 20A, 20B (collectively referred to as computing memory 20) can be connected to a common computing engine 30. Specifically, computing memory 20 can store multiple bits of one or more multi-digit values ​​that can be accessed and processed by computing engine 30. Computing memories 20A and 20B can be accessed independently via separate word lines 26A, 26B. In some embodiments, and as... Figure 13A and Figure 13B As shown, bit unit 22 is directly connected to computing engine 30 and can be accessed in parallel in a single time. Figure 13A As shown, access bits from each of the compute memories 20A and 20B can be multiplied together using bit multiplier 14 and accumulated using digital logic with SAC 38. In some embodiments, the bit product and its accumulation can be analog, or as... Figure 13B As shown, SAC 38 can be digital and can accumulate and shift digital data values ​​converted by analog-to-digital converter 36.

[0081] Figure 14A This is a schematic diagram illustrating digital storage and accumulation. Figure 14B This is a schematic diagram illustrating simulated storage and accumulation. Figure 14A In this configuration, each product storage circuit 16 stores a digital (1-bit) value corresponding to a bit of a different digital pair A, B of vectors X and Y in a register, flip-flop, or latch. The product storage circuit 16 can be accessed in parallel with the group counter 34, and the count bits from the group counter 34 are digitally shifted and accumulated in the SAC 38. Figure 14B An example of using simulated values ​​to perform the processing is shown. Figure 14B In this configuration, when switch S (switch 18, e.g., transistor 50) is in multiplication mode (e.g., on), each capacitor 16 receives a bit product. When switch S is in accumulation mode (e.g., off), each capacitor 16 is connected together. The capacitor values ​​are averaged and stored in accumulation capacitor 17, and the average value can be converted into a digital value using analog-to-digital converter (ADC) 36 and summed using SAC 38 to provide a product of two multi-bit values. Whenever the product value in capacitor 16 is averaged with the charge on accumulation capacitor 17, the product charge is effectively divided by 2, thus providing scaling for each subsequent bit product. Figure 15A and Figure 15B Only one bit of storage for each value A and b in vectors X and Y is shown, but in reality, multiple bits b are provided sequentially, such as... Figure 10 As shown.

[0082] According to embodiments of this disclosure, the computing engine 30 may include a multi-bit multiplier 14 that multiplies individual bits of each of two numbers at a time. Different numbers can be multiplied by providing the individual bits of the two numbers to different bit multipliers 14. In some embodiments, the bits of each of the two numbers are multiplied sequentially and accumulated, for example, using a multiplication table such as... Figure 9 The shifter shown. Figure 15A A simple bit multiplier 14 (AND gate 14) is shown. For example... Figure 15A As shown, computing element 14 is operable to receive data from bit cells 22A and 22B. Computing element 14 may include a one-bit multiplier 14 (e.g., switch 50 or transistor 50) that receives input from bit cell 22. One input (e.g., bit cell 22B) is connected to the gate, and the other input (e.g., bit cell 22A) is connected to the source. When the data in both bit cells 22A and 22B (collectively referred to as bit cell 22) has a high voltage (e.g., logic 1), the high voltage is transferred to the drain of transistor 50 and then to product storage circuitry 16 (e.g., digital flip-flop or latch or analog storage circuitry, e.g., capacitor 16) as a product of the bit data stored in bit cells 22A and 22B.

[0083] Figure 15BA more complex, electrically efficient, and space-efficient bit multiplication circuit 14 is shown. In some such embodiments, a pair of MOS (metal-oxide-semiconductor) transistors 15 includes two transistors 50 driven by complementary outputs from bit cell 22. If the output of bit cell 22 is high (e.g., storing 1 or a positive charge), a VREFP signal (positive voltage reference) is transmitted through the MOS transistor pair 15. Each of the two MOS transistor pairs 15 connected in series is connected to bit cell 22A and bit cell 22B, respectively. If both outputs are positive, a positive value (e.g., 1 or a positive charge or voltage) is transmitted as the product of the bit data stored in bit cells 22A and 22B to the product storage circuit 16. If the output of either bit cell 22A or 22B is low, a low or zero charge or voltage value is stored in the product storage circuit 16.

[0084] Figure 15B The bit multiplier 14 shown comprises two pairs of simple MOS (metal-oxide-semiconductor) transistors connected in series, with separate differential inputs and a common output. One of the pair of 15 simple MOS transistors is controlled by a positive control signal, and the other simple MOS transistor is controlled by an inverted (negative) version of the same control signal, such as the positive and negative outputs of any single bit cell 22 (e.g., a D flip-flop, latch, or inverter pair). This series of MOS transistor pairs 15 can reduce the need for fewer, simpler transistors to operate at much lower voltages (e.g., one percent or less, such as 0.624%, or 10mV instead of 1.65V), and therefore require much less power.

[0085] A conventional AND gate-based bit multiplier might require, for example, six relatively large transistors operating at relatively high voltages to implement the bit multiplication circuitry. In contrast, and according to embodiments of this disclosure, the bit multiplier 14 may include a series-connected pair of differential MOS transistors 15 that can operate at relatively low voltages (e.g., no greater than 1V and as low as 10mV) and low power, for example, with only four relatively small transistors. In embodiments, the MOS transistor pair 15 operates in an analog relatively low-power state with an analog voltage, which is less than a digital relatively high-power state with a digital voltage. In some embodiments, the analog voltage is no greater than one-half, one-quarter, one-fifth, one-tenth, one-twentieth, one-fiftieth, or one-hundredth of the digital voltage (e.g., 50%, 25%, 20%, 10%, 5%, 2%, or 1%).

[0086] Figure 16The first stage of a group counter 34 is shown. Given three-bit products P0, P1, P2 having the same position in three distinct numbers, a two-bit sum has: a higher bit D1, which is 1 if at least two of the bit products are 1; and a lower bit D0, which is 1 if all three bit products are 1, or if only one bit product is 1. The two-bit sum (with values ​​of zero, one, two, or three) can then be added to another two-bit sum with a three-bit adder, and so on, to ultimately sum all the bit products using multiple stages of adders for incrementing bits. In some embodiments, the first stage can use four-bit products to provide three-bit sums (values ​​0 to 4). Those skilled in the art will understand that various methods and logic circuits can be used to implement the group counter 34.

[0087] In some embodiments, the memory computer 10 provides an array of dot product functions, which may be matrix-vector products (e.g., where the matrix dimension is 1). Each row (or column) of the bit cells 22 in the memory computer 10 can perform a dot product. Therefore, in some embodiments, the computation engine 30 includes a multiplier responsive to the bit cells 22 storing two elements A and B, each element comprising bits of an arbitrary number. The computation engine 30 is connected to the storage element 22 via data lines (bit lines 24) and writes to and reads from the storage element 22 using control signals. In operation, data is written to the storage element 22 using bit lines and word lines 24, 26. The computation engine 30 can read data from the bit cells 22 and operate (process) on the read data. The storage element 22 of the memory computer 10 may be memory-mapped to a processor (controller) 70. The controller 70 may write data to the storage element 22 in such a manner that the computation engine 30 computes appropriate portions of multi-bit multiplications. Multiple bit product values ​​are serially accumulated in accumulator storage circuit 17. When accumulator switch 18 is turned on, the product is stored in capacitor 16. Whenever accumulator switch 18 (e.g., MOS transistor pair 15 in switch 18) is turned off, the value stored in accumulator storage circuit 17 is averaged with the bit product in capacitor 16.

[0088] Therefore, embodiments of this disclosure may include a dot product calculator, wherein computation memory 20 is operable to store multiple pairs of vectors X and Y (e.g., two matrices, each comprising multiple vectors). N AND gates 14 (bit multipliers 14) for each vector pair (e.g., from different matrices) may be connected to computation memory 20 such that each AND gate 14, in response to a memory address provided by a controller, simultaneously inputs bits of the numbers of vector X in a pair and corresponding bits of the numbers of vector Y in the same pair (e.g., having the same position value), and outputs the product of the input bits. A group counter 34 for each vector pair is operable to count the non-zero bits output from the N AND gates 14 in that pair. A serial accumulator 38 for each group counter 34 is operable to sequentially accumulate counts from the group counter 34, each count and bit having a position value corresponding to the same address. Multiple pairs of vectors X may form a first two-dimensional digital matrix, and multiple pairs of vectors Y may form a second two-dimensional digital matrix, and the dot product calculator is operable to compute an array of scalar values ​​corresponding to the dot product between the first and second two-dimensional digital matrices.

[0089] According to embodiments of this disclosure, the dot product calculator may include a controller (e.g., MMC 12 or external processor 70) operable to sequentially provide memory addresses to computational memory 20. Computational memory 20 is operable to receive memory addresses from the controller and store a first two-dimensional number array (first matrix) and a second two-dimensional number array (second matrix), wherein, in response to each memory address, the same bit of each number in the first matrix and each number in the second matrix can be accessed simultaneously in parallel. An AND gate 14 for each number in the first or second matrix may be connected to computational memory 20, operable to simultaneously input bits from the numbers in the first matrix and bits from the numbers in the second matrix in response to the memory address provided by the controller and output the product of the input bits. A group counter 34 for each one-dimensional number array in the first or second matrix is ​​operable to count the non-zero bits output from the AND gate 14 receiving the one-dimensional number array, and a serial accumulator 38 for each group counter 34 is operable to sequentially accumulate the counts of the group counter 34, each count and bit having a position value corresponding to the same address.

[0090] More typically, the dot product calculator may include a controller (e.g., MMC 12 or external processor 70) operable to sequentially provide memory addresses, and computation memory 20 operable to receive memory addresses from the controller and store a first n-dimensional array of numbers (a first matrix) and a second n-dimensional array of numbers (a second matrix). In response to each memory address provided to computation memory 20 by the controller, the same bits of each number in the first matrix and each number in the second matrix can be accessed simultaneously in parallel. A computation engine 30 is connected to computation memory 20 and operable to compute an array of scalar numbers corresponding to the dot product between the first and second matrices. In embodiments, n may be 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, or other positive integers. Therefore, embodiments of this disclosure can provide matrix and tensor operations. The dot product calculator may be included in a multiprocessor computer system 80 or an in-memory computer 10, and the controller may be an MMC 12 or an external processor 70.

[0091] The embodiments disclosed herein have been designed and modeled. The in-memory computer 10 can add linear algebra capabilities to standard memory structures, delivering performance improvements of 50x to 130x in latency and energy efficiency compared to conventional solutions, particularly in applications heavily reliant on computationally intensive linear algebra operations (e.g., neural networks or digital signal processing). The in-memory computer 10 can be integrated with various processing architectures, including but not limited to x86, ARM, RISC-V, GPUs, NPUs, or general-purpose ASICs. By integrating the in-memory computer 10 with the processor 70, the processor 70 can offload computationally expensive workloads, such as dot product primitives. This allows the processor 70 to avoid the energy and time costs required to execute these primitives while retaining all necessary control to efficiently and quickly execute high-order linear algebra routines, such as matrix-vector products, convolution operations, etc. The in-memory computer 10 ensures seamless backward compatibility with existing linear algebra-intensive libraries and algorithms and significantly improves performance.

[0092] The memory computer 10 was modeled and compared with three ARM Cortex-Mo processor configurations: an ARM Cortex-Mo processor with a serial multiplier (A), an ARM Cortex-Mo processor with a single-loop multiplier (B), and an ARM Cortex-Mo processor with the memory computer 10 (C). All configurations were set to operate at a frequency of 250 MHz. The operation was a 1024-element dot product, where 8-bit values ​​were calculated with absolute integer precision (no floating-point operations) and rounded to 8 bits. Latency is the number of clock cycles required for the Mo core to complete the operation, in microseconds. Power is the average power consumed by the system during operation. Energy is the total energy consumed by the system to complete the operation, including leakage. For configuration A, the latency was 40,710 cycles within 162,840 microseconds, the power used was 0.82 mW, and the energy used was 134,570 pJ. For configuration B, the delay is 8,966 cycles over 35,864 microseconds, the power used is 1.45 mW, and the energy used is 51,987 pJ. For configuration C, the delay is 337 cycles over 1,348 microseconds, the power used is 0.72 mW, and the energy used is 1,022 pJ.

[0093] The embodiments disclosed herein are not limited to the specific examples shown in the accompanying drawings and described herein. Those skilled in the art will readily understand that various implementations of analog and digital circuits can be used to implement the described operations, and such implementations are included in the embodiments of this disclosure.

[0094] Embodiments of this disclosure can be used in neural networks, pattern matching computers, or machine learning computers, providing efficient and timely processing with reduced power and hardware requirements. Such embodiments may include computational accelerators designed for static or dynamic processing workloads, such as neural network accelerators, pattern matching accelerators, machine learning accelerators, or artificial intelligence computational accelerators.

[0095] Some implementations of the embodiments have been described, and it will now be apparent to those skilled in the art that other implementations incorporating the concepts of this disclosure may be used. Therefore, this disclosure should not be limited to certain implementations, but should be limited only by the spirit and scope of the appended claims.

[0096] Throughout the description, where devices and systems are described as having, including, or containing specific elements, or where processes and methods are described as having, including, or containing specific steps, it is also conceivable that there are apparatuses and systems that are substantially composed of or comprised of the disclosed technology, and that there are processes and methods that are substantially composed of or comprised of the processing steps, according to the disclosed technology.

[0097] It should be understood that the order of steps or the sequence of actions is irrelevant as long as the disclosed technology remains operable. Furthermore, in some cases, two or more steps or actions can be performed simultaneously. This disclosure has been described in detail with particular reference to certain embodiments thereof; however, it should be understood that variations and modifications may be made within the spirit and scope of the appended claims. Parts list

[0098] F Control line / control wire / control signal; 10 Memory computer architecture / memory computer; 12 Memory mode controller; 13 Bus / signal; 13A Function line / function wire / function signal; 13B Address line / address wire / address signal; 13C Data line / data wire / data signal; 14 Bit multiplier / bit multiplication circuit / AND gate / computing element; 15 MOS transistor pairs; 16 Accumulation memory circuit / flip-flop / latch / capacitor; 17 Accumulation capacitor / accumulation memory circuit; 18 Switch / / S; 19 Analysis circuit; 20, 20A, 20B Computation memory; 21C Bit column; 21R Bit row; 22, 22A, 22B Memory element / bit cell / memory element; 24 Bit line / data line; 26, 26A, 26B Word line / address line; 30 Computation engine (CE); 34 Group counter / bit counter; 36 Analog-to-digital converter (ADC); 38 Digital shift accumulator (SAC) circuit / serial accumulator; 50 Switch / transistor; 70 Controller / external processor / processor; 80 Multiprocessor computer system; 100 Processor write step; 105 Processor read step; 110 MMC analysis address step; 115 MMC analysis address and operation steps; 120 Memory write step; 125 Memory read step; 130 Computation engine process steps; 140 Computation engine write to memory step; 150 Return processed data step; 200 Set counter i=0, j=0, k=0 step; 205 Set accumulation = 0 step; 210 Set b=j step; 215 Set a=i step; 220 A a x B b Multiplication step; 225 Counting group step; 230 Serial accumulation step; 235 b=i? step; 240 Increment b step; 245 Decrement a step; 250 Shift j step; 255 Addition step; 260 i=N-1? step; 265 Increment i step; 270 Increment k step; 275 j=M-1? step; 280 Set i=N-1 step; 285 Increment j step; 290 Complete step

Claims

1. A multiprocessor computer system (80), comprising: The memory computer (10) includes a computing engine (30) and a storage element (22) for storing data, the computing engine (30) being operable to process data stored in the storage element (22) of the memory computer (10); as well as A processor (70), located externally to and connected to the memory computer (10), having a memory address space for writing data to at least some of the storage elements (22) and reading data from at least some of the storage elements (22), and The computing engine (10) is operable to process data stored in the storage element (22) in response to (i) a read operation of the processor (70) on the storage element (22), (ii) a write operation of the processor (70) on the storage element (22), or (iii) both (i) and (ii).

2. The multiprocessor computer system according to claim 1, wherein, The memory computer (10) is operable to return the processed data to the processor (70) in response to the read operation or the write operation.

3. The multiprocessor computer system according to any one of claims 1 to 2, wherein, The read or write operation provides an RW address in the memory address space, the storage element (22) stores the data at the RW address, and the computing engine (30) is operable to process the stored data.

4. The multiprocessor computer system according to any one of claims 1 to 3, wherein, The computing engine (30) is operable to store the processed data at the RW address in the storage element (22).

5. The multiprocessor computer system according to any one of claims 1 to 3, wherein, The computing engine (30) is operable to store the processed data in the storage element (22) at a processing address different from the RW address.

6. The multiprocessor computer system according to any one of claims 1 to 2, wherein, The read or write operation provides an RW address in the memory address space, the storage element (22) stores data at an address in the memory address space that is different from the RW address, and the computing engine (30) is operable to process the data stored at the different address in the storage element (22).

7. The multiprocessor computer system according to any one of claims 1 to 6, wherein, The computing engine (30) is operable to store the processed data at the RW address.

8. The multiprocessor computer system according to any one of claims 1 to 6, wherein, The computing engine (30) is operable to store the processed data at a processing address in the memory address space that is different from the RW address.

9. The multiprocessor computer system according to any one of claims 6 to 8, wherein, The computing engine (30) is operable to process data differently based on one of a plurality of different RW addresses.

10. The multiprocessor computer system according to any one of claims 1 to 9, wherein, The memory computer (10) includes a memory mode controller (12), the processor (70) is connected to the memory mode controller (12) via any combination of function lines (13A), one or more address lines and one or more data lines, and the memory mode controller (12) is connected to the storage element (22) and the computing engine (30).

11. The multiprocessor computer system according to claim 10, wherein, The memory mode controller (12) responds to the RW address to control the computing engine (30) to process the data stored in the storage element (22).

12. The multiprocessor computer system according to any one of claims 1 to 10, wherein, The memory mode controller (12) includes an address analysis circuit for analyzing the RW address and controlling the computing engine (30) in response to the address analysis.

13. The multiprocessor computer system according to any one of claims 10 to 12, wherein, The memory mode controller (12) responds to the function line (13A) to control the computing engine (30) to process the data stored in the storage element (22).

14. The multiprocessor computer system according to any one of claims 10 to 13, wherein, The memory mode controller (12) includes a function analysis circuit for analyzing the function line (13A) and controlling the computing engine (30) in response to the function line analysis.

15. The multiprocessor computer system according to claim 10, wherein, The memory mode controller (12) is operable to (i) read processed data from the storage element (22) or (ii) write processed data to the storage element (22), or (iii) both (i) and (ii).

16. The multiprocessor computer system according to any one of claims 1 to 15, wherein, At least one of the storage elements (22) is mapped to multiple addresses in the memory space of the processor (70).

17. The multiprocessor computer system according to claim 16, wherein, The memory mode controller (12) is operable to map a write address to a write storage element (22) in response to a write operation from the processor (70), and to map a read address to a read storage element (22) different from the write storage element (22) in response to a read operation from the processor (70) on the write address.

18. The multiprocessor computer system according to any one of claims 16 and 17, wherein, The memory mode controller (12) is operable to map a write address to a write storage element (22) in response to a write operation from the processor (70), and to map a read address to a read storage element (22) different from the write storage element (22) in response to a read operation and the function line (13A).

19. The multiprocessor computer system according to claim 9, wherein, The RW address is mapped to at least three different storage elements (22), and the computing engine (30) processes data differently according to the function line (13A).

20. The multiprocessor computer system according to claim 1, comprising a plurality of computing engines, wherein, Each computing engine is operable to simultaneously multiply the bits of each number in two one-dimensional arrays of numbers.

21. The multiprocessor computer system of claim 20, comprising a plurality of computing engines, the plurality of computing engines being capable of simultaneously multiplying the bits of each number in two two-dimensional arrays of numbers.

22. The multiprocessor computer system according to claim 1, wherein, (i) at least some processing instructions are stored in storage elements within the memory computer address range, (ii) at least some data are stored in storage elements within the memory computer address range, or (iii) both (i) and (ii).

23. A multiprocessor computer system (80), comprising: The memory computer (10) includes a computing engine (30) and a storage element (22) for storing data. The computing engine (30) is operable to read, write and process data stored in the storage element (22) of the memory computer (10). as well as A processor (70), located external to and connected to the memory computer (10), having a memory address space for writing data to at least some of the storage elements (22) and reading data from at least some of the storage elements (22), and characterized in that... The computing engine (10) is operable to process data stored in the storage element (22) in response to read or write operations of the processor (70) on the storage element (22), and At least one of the storage elements (22) is mapped to multiple addresses in the memory space of the processor (70).

24. A multiprocessor computer system (80), comprising: The memory computer (10) includes a memory mode controller (12), a computing engine (30), and storage elements (22) for storing data. The computing engine (30) is operable to read, write, and process data stored in the storage elements (22) of the memory computer (10). as well as A processor (70), located external to and connected to the memory computer (10), having a memory address space for writing data to at least some of the storage elements (22) and reading data from at least some of the storage elements (22), and characterized in that... The processor (70) is connected to the memory mode controller (12) via any combination of function lines (13A), one or more address lines (13B) and one or more data lines (13C), and the memory mode controller (12) is connected to the storage element (22) and the computing engine (30).

25. A dot product calculator, comprising: A controller (12, 70) is operable to sequentially provide memory addresses; as well as Memory (22), operable to receive a memory address from the controller and store at least one vector X and a vector or matrix Y, each vector having a number, each number having bits, wherein bits for each number of vector X and bits for each number of vector Y can be accessed simultaneously in parallel, characterized in that... Bit multipliers (14), the bit multipliers being connected to the memory, such that each bit multiplier, in response to the memory address provided by the controller, simultaneously inputs bits of the numbers in vector X and bits of the numbers in vector Y, and outputs the product of the input bits; A group counter (34) is operable to count the non-zero bits of the output from the bit multiplier; as well as A serial accumulator (38) is used to accumulate the counts sequentially, with each count and bit having a position value corresponding to the same address.

26. The dot product calculator according to claim 25, wherein, The same bits of each number in both vectors X and Y are stored at the same address in the memory address provided by the controller.

27. The dot product calculator according to any one of claims 25 and 26, wherein, The memory addresses in the sequence are numerically adjacent.

28. The dot product calculator according to any one of claims 25 to 27, wherein, (i) the group counter is analog, (ii) the serial accumulator is analog, or (iii) both (i) and (ii).

29. The dot product calculator according to any one of claims 25 to 28, wherein, (i) the group counter is digital, (ii) the serial accumulator is digital, or (iii) both (i) and (ii).

30. The dot product calculator according to any one of claims 25 to 29, wherein, The memory (22) is operable to store multiple pairs of vectors X and Y, and includes: Bit multipliers (14) for each pair connected to memory (22), each bit multiplier (14) is operable to simultaneously input bits of multiple vectors X in a pair and bits of multiple vectors Y in the same pair, and output the product of the input bits; A group counter (34) for each pair, the group counter being operable to count the non-zero bits of the digits output from the bit multiplier in the pair; and A serial accumulator (38) for each group counter, the serial accumulator being operable to sequentially accumulate all or at least a portion of the counts from the group counter, each count and bit having a position value corresponding to the same address.

31. The dot product calculator according to claim 30, wherein, The plurality of pairs of vectors X form a first two-dimensional digital matrix, and the plurality of pairs of vectors Y form a second two-dimensional digital matrix, and the dot product calculator is operable to calculate an array of scalar values ​​corresponding to the dot product between the first two-dimensional matrix and the second two-dimensional matrix.

32. A dot product calculator, comprising: Controller (12, 70), operable to sequentially provide memory addresses, Its features are, The memory (22) is operable to receive the memory address from the controller and store a first two-dimensional number array (first matrix) and a second two-dimensional number array (second matrix), wherein the bits of each number in the first matrix and the bits of each number in the second matrix can be accessed simultaneously in parallel. Bit multipliers (14) for each number in the first matrix or the second matrix, the bit multipliers being connected to the memory, the memory being operable to simultaneously and in parallel input bits from the numbers in the first matrix and bits from the numbers in the second matrix, and output the product of the input bits; A group counter (34) for each one-dimensional number array in the first or second matrix, the group counter being operable to count the non-zero bits of the digits output from the bit multiplier receiving the one-dimensional number array; and A serial accumulator (38) for each group counter, the serial accumulator being operable to sequentially accumulate the counts of the group counters, each count and bit having a position value corresponding to the same address.

33. A dot product calculator, comprising: A controller (12, 70) is operable to sequentially provide memory addresses; as well as Memory (22), operable to receive a memory address from the controller and store a first n-dimensional number array (first matrix) and a second m-dimensional number array (second matrix), wherein the same bits of each number in the first matrix and each number in the second matrix can be accessed simultaneously in parallel, characterized in that... A computing engine connected to the memory, operable to compute an array of scalar numbers corresponding to the dot product between the first matrix and the second matrix.

34. The multiprocessor computer system according to claim 1, wherein, The storage element includes bit cells, and the computing engine includes capacitors associated with pairs of bit cells, or capacitors associated with groups of multiple bit cells.

35. The multiprocessor computer system according to claim 1, wherein, The storage element includes bit cells, and the computing engine includes binary logic associated with pairs of bit cells, or binary logic associated with groups of multiple bit cells.

36. A multiprocessor computer system (80), comprising: The memory computer (10) includes a memory mode controller (12), a computing engine (30), and storage elements (22) for storing data. The computing engine (30) is operable to read, write, and process data stored in the storage elements (22) of the memory computer (10). as well as A processor (70), located external to and connected to the memory computer (10), having a memory address space for writing data to at least some of the storage elements (22) and reading data from at least some of the storage elements (22), and characterized in that... The processor (70) is connected to the memory mode controller (12), which is connected to the storage element (22) and the computing engine (30). The memory mode controller (12) receives a memory address from the processor (70) and maps the memory address from a first memory address to a second memory address that is different from the first memory address.

37. A multiprocessor computer system (80), comprising: A memory computer (10) includes a computing engine (30) and a storage element (22) for storing multi-digit numbers, the computing engine (30) being operable to process multi-digit numbers stored in the storage element (22) of the memory computer (10); as well as A processor (70), located external to and connected to the memory computer (10), has a memory address space for writing the multi-digit number to at least some of the storage elements (22) and reading the multi-digit number from at least some of the storage elements (22). The feature is that at least some of the different bits of the multi-digit number are stored at different storage element addresses in the storage element (22), or in different memory groups in response to the same storage element address.

38. The multiprocessor computer system (80) according to claim 37, wherein, Each bit of the multi-bit data is stored at a different memory element address in the memory element or in a different memory group than any other bit of the multi-bit data.

39. A multiprocessor computer system (80), comprising: The memory computer (10) includes a computing engine (30) and a storage element (22) for storing data, the computing engine (30) being operable to process data stored in the storage element (22) of the memory computer (10); as well as A processor (70), located externally to and connected to the memory computer (10), having a memory address space for writing data to at least some of the storage elements (22) and reading data from at least some of the storage elements (22), and The computing engine (10) is characterized in that it is operable to (i) process data stored in the storage element (22) for the first time in response to a read or write operation by the processor (70) at a first address on the storage element (22), and (ii) process data stored in the storage element (22) for the second time in response to a read or write operation by the processor (70) at a second address on the storage element (22), wherein the first address is different from the second address, and the first processing is different from the second processing.

40. A method for multiplying a number A by a number B, where both A and B have bits in a bit position, comprising: (i) Multiply the bits of A by the bits of B in sequence to provide a bit product for each combination of bits in A and B that have a common bit position, and add the bit products together; (ii) Shift the bitwise product of the addition to the product position; (iii) The bit product of cumulative shifts; and (iv) Repeat steps (i)-(iii) for each bit position of A and B to provide the product of A and B.

41. A method for calculating the dot product between a vector X having a digit A and a vector Y having a digit B, wherein A and B have bits at bit positions, comprising: (i) Multiply the bits of A by the bits of B to provide a bitwise product of a pair of bits in A and B that have a common bit position for each A and B in vectors X and Y; (ii) Count the bit products; (iii) Accumulate the count; (iv) Repeat steps (i)-(iii) for each bit combination with a common bit position; (v) Shift the accumulated count to the bit position; (vi) Add up the cumulative counts of the shifts; as well as Repeat steps (i)-(vi) for each bit position of the product of A and B to provide a dot product of A and B, which is an accumulated count of the added shifts.

42. A multiprocessor computer system (80), comprising: A memory computer (10), the memory computer including a computing engine (30) and storage elements (22) for storing multi-digit numbers, and The feature is that at least some of the different bits of the multi-digit number are stored at different storage element addresses in the storage element (22), or in different memory groups in response to the same storage element address.

43. The multiprocessor computer system (80) according to claim 42, wherein, The memory computer (10) is operable to provide one or more storage element addresses to the storage element (22) and retrieve bits of different multi-digit numbers having common bit positions from the storage element (22).

44. The multiprocessor computer system (80) according to claim 43, wherein, The computing engine (30) includes a bit multiplier (14) for multiplying bits of different multi-digit numbers that have a common bit position, providing a product for each pair of bits being multiplied.

45. The multiprocessor computer system (80) according to claim 44, wherein, The computing engine (30) includes a group counter (34) for counting the digits of the non-zero product of the multiplied bit pairs.

46. ​​The multiprocessor computer system (80) according to claim 42, wherein, All the different bits of the multi-digit number are stored at different memory element addresses or in different memory groups in the memory element (22).

47. The multiprocessor computer system (80) according to claim 42, wherein, At least some of the different bits of the multi-digit number are stored in different, simultaneously accessible storage elements in the storage element (22).

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