An apparatus and method for temporarily bonding wafers, and a manufacturing process of semiconductor devices

Through the temporary bonding method of spraying sealant combined with vacuum technology, the complex and rigorous wafer bonding problems in the prior art are solved, and an efficient and low-cost wafer bonding process is achieved, which is suitable for batch processing of single-chip and multiple wafers.

CN115458464BActive Publication Date: 2025-08-05杨士琦
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Patent Information

Application Number
CN202211058034.7
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-08-30
Publication Date
2025-08-05
Estimated Expiration
2042-08-30

AI Technical Summary

Technical Problem

The existing temporary bonding process is too complex and the conditions are harsh, and there are problems such as adhesive heating requirements, strict strength requirements for the top chuck and bottom chuck, and long-term vacuum removal of solvents, resulting in low throughput and high process costs.

Method used

The nozzle spray sealant combined with vacuum technology is used to achieve close bonding of the wafer and remove the vacuum after edge sealing, without the need for a long time to remove the solvent, simplifying the process flow.

Benefits of technology

It improves bonding efficiency, reduces process costs, avoids chemical and thermal stability problems of adhesives, simplifies operating conditions, and is suitable for batch processing of single and multi-wafers.

✦ Generated by Eureka AI based on patent content.

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Abstract

The present invention relates to an apparatus and method for temporarily bonding wafers, and a manufacturing process of semiconductor devices. An apparatus for temporarily bonding wafers includes: a chamber, in which a top chuck and a bottom chuck are respectively provided at the top and bottom inside the chamber; and a nozzle is also provided inside the chamber; a vacuum pump communicating with the inside of the chamber. The upper wafer to be bonded and the lower carrier are clamped face to face by using the top chuck and the bottom chuck and placed in the chamber; then the chamber is evacuated, and a sealant is sprayed on the edge area where the upper wafer and the lower carrier are in contact by using the nozzle; after that, the vacuum in the chamber is released, and the subsequent process is continued. The present invention solves the problems that the existing temporary bonding process is too complex and the conditions are too harsh, and at the same time improves the bonding efficiency.
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Description

Technical Field

[0001] The present invention relates to the field of transistors, and in particular to a device and method for temporarily bonding wafers, and a process for preparing semiconductor devices. Background Art

[0002] In some semiconductor device manufacturing processes, two semiconductor wafers need to be temporarily bonded together before active structures (such as capacitors, gates, PIN structures, etc.) can be made. The existing technology usually uses adhesive to coat the surfaces of the two wafers to be bonded, and then uses a top chuck and a bottom chuck to tightly clamp the two wafers together, while heating them at the same time. This process has the following problems: the adhesive used needs to be heated to ensure the flexibility and viscosity of the adhesive; at the same time, the top chuck and the bottom chuck need to exert a large force to press the upper and lower wafers tightly together; the top chuck and the bottom chuck are also required to be strictly parallel to reduce the total thickness deviation (TTV) of the wafers; after bonding, a long vacuum is required to remove the solvent in the adhesive; the processing time is long and the throughput is low; in subsequent processes, the temporary adhesive is usually susceptible to chemical and thermal corrosion, which may lead to unexpected early debonding; and an expensive and time-consuming glue removal process is performed during the later debonding process.

[0003] It can be seen that the existing temporary bonding process is too complicated and the conditions are harsh.

[0004] To this end, the present invention is proposed. Summary of the Invention

[0005] The main purpose of the present invention is to provide an apparatus and method for temporarily bonding wafers, as well as a process for preparing semiconductor devices, which solves the problem that the existing temporary bonding process is too complicated and has harsh conditions, while improving the bonding efficiency.

[0006] In order to achieve the above objectives, the present invention provides the following technical solutions.

[0007] A first aspect of the present invention provides an apparatus for temporarily bonding wafers, comprising:

[0008] A chamber, wherein a top chuck and a bottom chuck are respectively provided on the top and bottom of the chamber;

[0009] and a nozzle is also provided in the chamber;

[0010] A vacuum pump is in communication with the interior of the chamber.

[0011] Compared with existing equipment, this device has an additional nozzle, which is mainly used to spray sealant, which is mainly used for edge sealing. In actual application, the nozzle can also be connected to a liquid storage tank, which stores sealant.

[0012] The above-mentioned equipment achieves the goal of tightly bonding wafers under vacuum. A sealant is sprayed on the edges of the bonding process to seal the edges, further enhancing the tightness of the temporary bonding. Furthermore, the vacuum in the chamber can be released after sealing, eliminating the need for prolonged vacuum removal of solvents. The detailed method for bonding wafers is described below.

[0013] A second aspect of the present invention provides a method for temporarily bonding wafers, which is performed in the apparatus for temporarily bonding wafers described above and comprises the following steps:

[0014] Using the top chuck and the bottom chuck, the upper wafer to be bonded and the lower carrier are clamped face to face and placed in the chamber;

[0015] The chamber is then vacuumed, and a sealant is sprayed onto the edge area where the upper wafer and the lower carrier are bonded using the nozzle;

[0016] The vacuum in the chamber is then released and subsequent processes are continued.

[0017] From the steps of the above method, it can be seen that the present invention has the following advantages:

[0018] (1) No glue is required, and the bonding is maintained by vacuum rather than bonding;

[0019] (2) No long vacuum duration;

[0020] (3) Achieving a high vacuum level in a chamber without any solvent is always much faster than using a solvent;

[0021] (4) No need to worry about the chemical and thermal stability of the temporary bonding material in subsequent processes;

[0022] (5) The process cost is much lower due to the shortened cutting material and processing time;

[0023] (6) There is no strict parallelism and bonding force between the top chuck and the bottom chuck;

[0024] (7) Heating is optional.

[0025] In addition, the steps of the above bonding method can be further adjusted to optimize the overall effect of the method, as listed below.

[0026] In some embodiments, the sealant may be made of a material that takes into account the chemical resistance, high temperature resistance, mechanical strength, etc. required for subsequent product processes, and the present invention is not limited to this.

[0027] In some embodiments, the vacuum process is performed to a level higher than the vacuum required for subsequent processes, so as to avoid a negative pressure state between the bonding interface and the outside world during the process.

[0028] In some embodiments, each of the lower carrier and the upper wafer is a single piece.

[0029] This embodiment refers to single-piece processing.

[0030] In some embodiments, the lower carrier is a single piece, and the upper wafers are multiple pieces; and when bonding, all the upper wafers are spaced and bonded to the surface of the lower carrier.

[0031] This embodiment refers to batch processing of multiple pieces, which greatly improves the processing efficiency.

[0032] In some embodiments, a sealant is sprayed on the edge area where each upper wafer is bonded to the lower carrier.

[0033] The sealant is sprayed on all the edge areas to improve the sealing performance.

[0034] In some embodiments, before the bonding, a release layer is further provided on the surface of the lower carrier, and then the release layer is bonded to the upper wafer. [[ID=�]]

[0035] On the one hand, the release layer can avoid damage to the wafer surface and improve the device processing quality.

[0036] The third aspect of the present invention provides a preparation process of a semiconductor device, including:

[0037] First, temporarily bond the upper wafer to the lower carrier by the method described above;

[0038] Then, fabricate a circuit structure on the upper wafer;

[0039] After that, remove the redundant layer to release the upper wafer with the circuit structure.

[0040] The lower carrier provides support and provides a stable structural support for the circuit fabrication of the upper wafer.

[0041] In some embodiments, when the upper wafers are multiple pieces, after removing the redundant layer, it further includes: dividing into multiple independent upper wafers.

[0042] In some embodiments, after the temporary bonding and before fabricating the circuit structure, it further includes: <�

[0043] Filling the blank areas between adjacent upper wafers with an insulating material.

[0044] In some embodiments, when the upper wafer is a single piece or a single slice, removing the redundant layer may include: first slicing to remove the sealant, and then removing the lower carrier (or the lower carrier and the release layer).

[0045] In summary, compared with the prior art, the present invention achieves the following technical effects:

[0046] No glue is required, and the bonding is maintained by vacuum instead of adhesion; there is no long vacuum duration; achieving a high vacuum level in the chamber without any solvent is always much faster than using a solvent; there is no need to worry about the chemical and thermal stability of the temporary bonding material in subsequent processes; the process cost is much lower; there is no strict parallelism and bonding force between the top chuck and the bottom chuck. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention.

[0048] Figure 1 It is a schematic structural diagram of the temporary bonding device provided by the present invention;

[0049] Figures 2 to 5 It is a schematic structural diagram obtained by each step of the bonding method provided in Embodiment 1 of the present invention;

[0050] Figures 6 to 10 It is a schematic structural diagram obtained by each step of the bonding method provided in Embodiment 2 of the present invention;

[0051] Figures 11 to 15 It is a schematic structural diagram obtained by each step of the bonding method provided in Embodiment 3 of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0052] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. However, it should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present disclosure.

[0053] Schematic structural diagrams according to embodiments of the present disclosure are shown in the drawings. These figures are not drawn to scale, where certain details are enlarged for the purpose of clear expression and certain details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are only exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0054] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, it can be directly on the other layer / element or an intervening layer / element may be present therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed.

[0055] As described in the background, existing temporary bonding techniques have numerous steps and demanding operating conditions. To address this, the present invention combines a sealant with a vacuum seal to achieve a temporary bonding process with mild operating conditions and a simplified process. This bonding technology can be used for temporary bonding of a single wafer or for batch bonding of multiple wafers. A release layer can also be added between the carrier and the wafer to reduce damage to the wafer, as shown in the examples listed below.

[0056] In addition, the bonding process of the following embodiments is as follows Figure 1 The device shown comprises:

[0057] A chamber 11, wherein a top chuck 12 and a bottom chuck 13 are provided at the top and bottom of the chamber 11 respectively;

[0058] And there is a nozzle 14 in the chamber 11;

[0059] A vacuum pump (not shown) is connected to the interior of the chamber 11 .

[0060] Example 1

[0061] Combine Figures 2 to 5 Explains temporary bonding and device processing of a single wafer

[0062] In the first step, the upper wafer 101 and the lower carrier 102 to be bonded are clamped face to face in a chamber using a top chuck and a bottom chuck.

[0063] The second step is vacuuming.

[0064] In the third step, a nozzle is used to spray a sealant 103 on the edge area where the upper wafer 101 and the lower carrier 102 are attached to seal the edge. Figure 2 shown.

[0065] The fourth step is to release the vacuum in the chamber and prepare to make the circuit structure on the upper wafer.

[0066] Step 5: Make circuit structure 101a on the upper wafer, such as Figure 3 shown.

[0067] Step 6: Remove the edge sealant 103, such as Figure 4 shown.

[0068] Step 7: Break the static vacuum and release the lower carrier 102, as Figure 5 shown.

[0069] Example 2

[0070] Combined with Figures 6 to 10 illustrate the temporary bonding and device processing of a single wafer

[0071] Step 1: Add a release layer 204 to the surface of the lower carrier 202.

[0072] Step 2: Use the top chuck and bottom chuck to clamp the upper wafer 201 to be bonded and the lower carrier 202 face-to-face and place them in the chamber. The release layer 204 is in contact with the upper wafer 201.

[0073] Step 3: Evacuate the chamber.

[0074] Step 4: Spray a sealant 203 on the edge area where the upper wafer 201 and the lower carrier 202 are in contact to seal the edge, as Figure 6 shown.

[0075] Step 5: Release the vacuum in the chamber and prepare to fabricate a circuit structure on the upper wafer.

[0076] Step 6: Fabricate a circuit structure 201a on the upper wafer, as Figure 7 shown.

[0077] Step 7: Release and remove the lower carrier, as Figure 8 shown.

[0078] Step 8: Remove the release layer, as Figure 9 shown.

[0079] Step 9: Remove the edge-sealing sealant, as Figure 10 shown.

[0080] Example 3

[0081] Combined with Figures 11 to 15 illustrate the temporary bonding and device processing of multiple wafers

[0082] Step 1: Add a release layer 304 to the surface of the lower carrier 302.

[0083] Step 2: Use the top chuck and bottom chuck to clamp all the upper wafers 301 to be bonded and the lower carrier face-to-face and place them in the chamber. The release layer 304 is in contact with the upper wafers 301 and the multiple upper wafers are arranged at intervals.

[0084] Step 3: Evacuate the chamber.

[0085] In the fourth step, spray sealant on the edge area where the upper wafer 301 and the lower carrier 302 are in contact to seal the edge, as Figure 11 shown.

[0086] In the fifth step, release the vacuum in the chamber and fill the blank area between adjacent upper wafers with the insulating material 305, as Figure 12 shown.

[0087] In the sixth step, fabricate the circuit structure 301a on the upper wafer, as Figure 13 shown.

[0088] In the seventh step, release and remove the lower carrier 302, as Figure 4 shown.

[0089] In the eighth step, remove the release layer 304, as Figure 15 shown.

[0090] The embodiments of the present disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should fall within the scope of the present disclosure.

Claims

1. A method for temporarily bonding wafers, characterized in that: The process is carried out in a device for temporarily bonding wafers, wherein the device for temporarily bonding wafers comprises: A chamber, wherein a top chuck and a bottom chuck are respectively provided on the top and bottom of the chamber; The chamber further includes a nozzle, the nozzle being tilted toward the upper surface of the bottom chuck and biased toward the middle of the bottom chuck; a vacuum pump in communication with the interior of the chamber; The method for temporarily bonding wafers comprises the following steps: Adding a release layer on the surface of the lower carrier; The upper wafer and the lower carrier to be bonded are clamped face-to-face in the chamber using the top chuck and the bottom chuck, the release layer is bonded to the upper wafer, the size of the lower carrier is larger than the size of the upper wafer, and the edge of the upper wafer is within the contour of the lower carrier; the lower carrier is a single piece, and the upper wafers are multiple pieces; and during bonding, all the upper wafers are bonded to the surface of the release layer at intervals; The chamber is then vacuumed, and a sealant is sprayed onto the edge area where each upper wafer and the lower carrier are bonded using the nozzle; The vacuum in the chamber is then released and subsequent processes are continued.

2. A process for preparing a semiconductor device, characterized in that: include: First, temporarily bond the upper wafer to the lower carrier using the method of claim 1; Then, a circuit structure is fabricated on the upper wafer; The excess layers are then removed, releasing the upper wafer with the circuit structure.

3. The preparation process according to claim 2, characterized in that When there are multiple upper wafers, after removing the redundant layers, the method further includes: dividing the upper wafers into multiple independent upper wafers.

4. The preparation process according to claim 3, characterized in that After the temporary bonding and before the circuit structure fabrication, the following steps are further included: Fill the empty space between adjacent upper wafers with insulating material.

Citation Information

Patent Citations

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