Display module, display device

Abstract

The present disclosure provides a display module and a display device, belonging to the field of display technology. The display module includes a display panel and a circuit board connected to the display panel, wherein the display panel includes: a base substrate having a display area and a peripheral area located outside the display area; a driving circuit layer provided on one side of the base substrate, the driving circuit layer including a signal line, the orthographic projection of the signal line on the base substrate being located in the display area; a conductive member provided on a side of the base substrate away from the driving circuit layer, the conductive member being connected to the circuit board; wherein the display panel is further provided with a first conductive through hole, the orthographic projection of the first conductive through hole on the base substrate being located in the display area, the signal line being connected to the conductive member through the first conductive through hole. The present disclosure helps to achieve a narrower bezel design for the display panel.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display module and a display device. Background Art

[0002] With the continuous development of display technology, people's requirements for display technology are gradually increasing.

[0003] The screen bezel refers to the distance from the active area (AA) to the screen edge. Consumers are increasingly demanding screen bezels, hoping for narrower bezels. However, existing screen bezels are still relatively wide, failing to meet consumer demands.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art. Summary of the Invention

[0005] The present disclosure aims to provide a display module and a display panel to achieve a narrower frame design of the display panel.

[0006] To achieve the above-mentioned purpose, the present invention adopts the following technical solutions:

[0007] According to a first aspect of the present disclosure, a display module is provided, comprising a display panel and a circuit board connected to the display panel, wherein the display panel comprises:

[0008] A base substrate having a display area and a peripheral area located outside the display area;

[0009] A driving circuit layer is provided on one side of the base substrate, the driving circuit layer includes a signal line, and an orthographic projection of the signal line on the base substrate is located in the display area;

[0010] A conductive member is provided on a side of the base substrate away from the driving circuit layer, and the conductive member is connected to the circuit board;

[0011] The display panel is further provided with a first conductive through hole, the orthographic projection of the first conductive through hole on the base substrate is located in the display area, and the signal line is connected to the conductive member through the first conductive through hole.

[0012] In an exemplary embodiment of the present disclosure, the display area includes:

[0013] a first display area;

[0014] a second display area, located outside the first display area, wherein the pixel density of the first display area is greater than the pixel density of the second display area;

[0015] The orthographic projection of the first conductive through hole on the base substrate is located in the second display area.

[0016] In an exemplary embodiment of the present disclosure, the signal line includes:

[0017] a first signal line, whose orthographic projection on the base substrate is located in the first display area;

[0018] a second signal line connected to the first signal line, and having an orthographic projection on the base substrate located in the second display area;

[0019] Wherein, the second signal line is connected to the conductive member through the first conductive through hole;

[0020] The line width of the second signal line is greater than the line width of the first signal line.

[0021] In an exemplary embodiment of the present disclosure, the driving circuit layer includes multiple conductive layers;

[0022] The signal line includes:

[0023] a first signal line, whose orthographic projection on the base substrate is located in the first display area;

[0024] a second signal line connected to the first signal line, and having an orthographic projection on the base substrate located in the second display area;

[0025] Wherein, the second signal line is connected to the conductive member through the first conductive through hole;

[0026] The second signal lines are distributed in at least two of the conductive layers, and the second signal lines distributed in different conductive layers are connected by vias.

[0027] In an exemplary embodiment of the present disclosure, the signal line includes:

[0028] a first signal line, whose orthographic projection on the base substrate is located in the first display area;

[0029] a second signal line connected to the first signal line, and having an orthographic projection on the base substrate located in the second display area;

[0030] Wherein, the second signal line is connected to the conductive member through the first conductive through hole;

[0031] The second signal line includes multiple main signal lines and multiple connecting lines. The multiple main signal lines extend along the first direction and are arranged at intervals along the second direction. The connecting lines extend along the second direction. Two adjacent main signal lines are connected through the connecting lines and / or the first conductive through-holes.

[0032] In an exemplary embodiment of the present disclosure, the orthographic projection of the second signal line on the base substrate is in a grid shape.

[0033] In an exemplary embodiment of the present disclosure, there are a plurality of first conductive through holes, and the orthographic projections of the plurality of first conductive through holes on the base substrate are dispersed in the second display area;

[0034] The sum of the orthographic projection areas of the plurality of first conductive vias on the base substrate accounts for 5%-50% of the area of ​​the second display region.

[0035] In an exemplary embodiment of the present disclosure, the signal line is a power supply voltage line.

[0036] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0037] a light-emitting layer, provided on a side of the driving circuit layer away from the base substrate, the light-emitting layer comprising a pixel definition layer and a plurality of light-emitting devices separated by the pixel definition layer;

[0038] an encapsulation layer, provided on a side of the light-emitting layer away from the base substrate;

[0039] The display panel further includes a first through hole and a conductive material filled in the first through hole, the first through hole penetrates the encapsulation layer, the drive circuit layer and the base substrate, the first conductive through hole includes the first through hole and the conductive material filled in the first through hole, and the conductive material is connected to the conductive member;

[0040] The first through hole exposes at least a portion of the signal line.

[0041] In an exemplary embodiment of the present disclosure, the driving circuit layer includes:

[0042] An active layer is provided on one side of the base substrate;

[0043] a first gate insulating layer, provided on a side of the active layer away from the base substrate, the first gate insulating layer covering the active layer;

[0044] a first gate metal layer, provided on a side of the first gate insulating layer away from the substrate, the first gate metal layer including a gate of a transistor and a first plate of a capacitor;

[0045] a second gate insulating layer, provided on a side of the first gate metal layer away from the base substrate;

[0046] a second gate metal layer, provided on a side of the second gate insulating layer away from the base substrate, the second gate metal layer comprising a second plate of the capacitor;

[0047] an interlayer dielectric layer, provided on a side of the second gate metal layer away from the base substrate;

[0048] A first source-drain layer is provided on a side of the interlayer dielectric layer away from the base substrate, the first source-drain layer including a source and a drain of the transistor;

[0049] Wherein, the signal line is at least partially distributed in the first gate metal layer and / or the second gate metal layer;

[0050] The second gate insulating layer or the interlayer dielectric layer covers at least a portion of the surface of the signal line away from the substrate, and the second gate insulating layer and the interlayer dielectric layer are inorganic material layers;

[0051] The first through hole exposes a sidewall of the signal line and at least a portion of a surface of the signal line away from the base substrate.

[0052] In an exemplary embodiment of the present disclosure, the driving circuit layer further includes:

[0053] A first planarization layer is provided on a side of the first source / drain layer away from the base substrate;

[0054] a second source-drain layer, disposed on a side of the first planarization layer away from the first planarization layer, wherein at least a portion of the second source-drain layer is connected to the first source-drain layer;

[0055] a second planarization layer, provided on a side of the second source / drain layer away from the base substrate, wherein a groove is provided in the second planarization layer;

[0056] Wherein, the encapsulation layer fills the groove;

[0057] The orthographic projection of the pixel definition layer on the base substrate is located within the orthographic projection of the second planarization layer on the base substrate;

[0058] The orthographic projection of the groove on the base substrate is located on a side of the orthographic projection of the pixel definition layer on the base substrate close to the orthographic projection of the first conductive through hole on the base substrate.

[0059] In an exemplary embodiment of the present disclosure, the surface of the base substrate away from the driving circuit layer has a binding area, and the binding area is provided with a pad;

[0060] The conductive member is connected to the pad via a conductive metal wire, and the circuit board is bent to a side of the base substrate away from the driving circuit layer and connected to the pad.

[0061] In an exemplary embodiment of the present disclosure, the circuit board has a first surface and a second surface that are opposite to each other, and the first surface of the circuit board is provided with connecting pins;

[0062] The display panel further includes a conductive metal line, the conductive metal line being connected to the conductive member and extending to the second surface of the circuit board;

[0063] A second conductive through-hole is provided on the circuit board, and the conductive metal wire is connected to the connecting pin through the second conductive through-hole.

[0064] According to a second aspect of the present disclosure, a display device is provided, comprising the display module as described in the first aspect.

[0065] The display module provided herein includes a display panel and a circuit board connected to the display panel. The display panel includes a base substrate, a drive circuit layer disposed on one side of the base substrate, and a conductive member disposed on a side of the base substrate away from the drive circuit layer. The drive circuit layer includes a signal line, which is connected to the conductive member and, in turn, to the circuit board via a first conductive via disposed on the display panel. Both the signal line and the first conductive via are located in the display area, thereby reducing the width of the border area and facilitating a narrower border design for the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] The above and other features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the accompanying drawings.

[0067] Figure 1 is a schematic diagram of a substrate structure in an exemplary embodiment of the present disclosure;

[0068] Figure 2 is a schematic diagram of a signal line distribution structure in an exemplary embodiment of the present disclosure;

[0069] Figure 3 is a schematic diagram of a signal line distribution structure in another exemplary embodiment of the present disclosure;

[0070] Figure 4 is a cross-sectional view of a display panel in an exemplary embodiment of the present disclosure;

[0071] Figure 5 yes Figure 2 or Figure 3 A-A' direction cross section;

[0072] Figure 61 is a schematic diagram of a protective film structure formed on a display panel in an exemplary embodiment of the present disclosure;

[0073] Figure 7 is a schematic diagram of pixel arrangement in the first display area in an exemplary embodiment of the present disclosure;

[0074] Figure 8 is a schematic diagram of the pixel arrangement and the first conductive through hole in the second display area in an exemplary embodiment of the present disclosure;

[0075] Figure 9 is a schematic diagram of a pixel arrangement in a second display area and a first conductive through hole in another exemplary embodiment of the present disclosure;

[0076] Figure 10 is a schematic diagram of a pixel arrangement in the second display area and a first conductive through hole in another exemplary embodiment of the present disclosure;

[0077] Figure 11 is a schematic diagram of a pixel arrangement in the second display area and a first conductive through hole in another exemplary embodiment of the present disclosure;

[0078] Figure 12 is a schematic diagram of the second surface structure of the substrate in an exemplary embodiment of the present disclosure;

[0079] Figure 13 is a schematic diagram of the display module structure in an exemplary embodiment of the present disclosure;

[0080] Figure 14 is a schematic diagram of a display module structure in another exemplary embodiment of the present disclosure;

[0081] Figure 15 It is a schematic diagram of the display module structure in another exemplary embodiment of the present disclosure.

[0082] The main components in the figure are described as follows:

[0083] 01-display panel; 1-substrate; 11-display area; 111-first display area; 112-second display area; 12-peripheral area; 2-driving circuit layer; 21-light shielding layer; 221-active layer; 222-first gate insulating layer; 223-first gate metal layer; 224-second gate insulating layer; 225-second gate metal layer; 226-interlayer dielectric layer; 227-first source / drain layer; 23-first planarization layer; 24-second source / drain layer; 25-second planarization layer; 251-groove; 26-insulating layer; 3-light-emitting layer; 31-first electrode layer; 32-pixel definition layer; 321-opening; 33-light-emitting functional layer; 34-second electrode layer; 4-encapsulation layer; 41-first inorganic layer; 4 2-organic layer; 43-second inorganic layer; 5-signal line; 51-first signal line; 52-second signal line; 521-first sub-signal line; 522-second sub-signal line; 523-connecting line; 524-main signal line; 6-first conductive through-hole; 61-first through-hole; 62-conductive material; 7-protective film; 71-second through-hole; 8-conductive member; 9-conductive metal wire; 91-branch line; 92-bus; 93-pad; 94-binding area; 10-pixel unit; 101-first sub-pixel; 102-second sub-pixel; 103-third sub-pixel; 02-driver chip; 03-circuit board; 031-connecting pin; 032-second conductive through-hole; 04-control terminal; 05-chip-on-film. DETAILED DESCRIPTION

[0084] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of the embodiments of the present disclosure.

[0085] In the drawings, the thickness of regions and layers may be exaggerated for clarity. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.

[0086] The described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure can be practiced without one or more of the specific details, or other methods, components, materials, etc. can be adopted. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid obscuring the main technical ideas of the present disclosure.

[0087] When a structure is “on” another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is “directly” disposed on the other structure, or that the structure is “indirectly” disposed on the other structure via another structure.

[0088] The terms "a," "an," and "the" are used to indicate the presence of one or more elements / components; the terms "including" and "having" are used to indicate an open-ended inclusiveness and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc. The terms "first," "second," etc. are used merely as labels and do not limit the quantity of the items to which they refer.

[0089] In related art, signal lines such as the power supply voltage line of a display panel are typically extended from the two side frames of the display area to the fan-shaped area and the binding area for connection to the circuit board. This approach hinders further reduction of the frame and fails to meet consumer demand. In addition, the presence of these signal lines in the frame area makes it impossible to create stretchable structures such as openings in the frame area, resulting in the frame area's inability to deform, thus limiting the application of display panels in non-flat display devices.

[0090] like Figure 1 、 Figure 5 and Figure 13 As shown, the present disclosure provides a display module, including a display panel 01 and a circuit board 03 connected to the display panel 01. The display panel 01 includes a base substrate 1, a drive circuit layer 2, and a conductive member 8. The base substrate 1 has a display area 11 and a peripheral area 12 located outside the display area 11. The drive circuit layer 2 is provided on one side of the base substrate 1 and includes a signal line 5. The orthographic projection of the signal line 5 on the base substrate 1 is located in the display area 11. The conductive member 8 is provided on a side of the base substrate 1 away from the drive circuit layer 2 and is connected to the circuit board 03. The display panel 01 is provided with a first conductive via 6. The orthographic projection of the first conductive via 6 on the base substrate 1 is located in the display area 11. The signal line 5 is connected to the conductive member 8 through the first conductive via 6.

[0091] The display module provided by the present disclosure includes a display panel 01 and a circuit board 03 connected to the display panel 01. The display panel 01 includes a base substrate 1, a drive circuit layer 2 provided on one side of the base substrate 1, and a conductive member 8 provided on a side of the base substrate 1 away from the drive circuit layer 2. The drive circuit layer 2 includes a signal line 5, which is connected to the conductive member 8 and further connected to the circuit board 03 via a first conductive via 6 provided on the display panel 01. The signal line 5 and the first conductive via 6 are both located in the display area 11, thereby reducing the width of the border area and helping to achieve a narrower border design for the display panel 01.

[0092] The components of the display module provided by the present disclosure will be described in detail below with reference to specific embodiments and drawings.

[0093] like Figure 1 、 Figure 5 and Figure 13 As shown, the display module provided by the present disclosure includes a display panel 01 and a circuit board 03 connected to the display panel 01. The display panel 01 can be an OLED (Organic Light-Emitting Diode) display panel. The circuit board 03 can be an FPC or a PCB.

[0094] like Figure 5 As shown, the display panel 01 includes a base substrate 1, a drive circuit layer 2, and a conductive member 8. The drive circuit layer 2 is provided on one side of the base substrate 1, and the conductive member 8 is provided on a side of the base substrate 1 away from the drive circuit layer 2. That is, the base substrate 1 has a first surface and a second surface disposed opposite each other, the drive circuit layer 2 is provided on the first surface of the base substrate 1, and the conductive member 8 is provided on the second surface of the base substrate 1.

[0095] The substrate 1 may be a substrate 1 of an inorganic material or a substrate 1 of an organic material. For example, in one embodiment of the present disclosure, the material of the substrate 1 may be a glass material such as soda-lime glass, quartz glass, sapphire glass, or a metal material such as stainless steel, aluminum, nickel, etc. The substrate 1 may also be a flexible substrate 1. For example, in one embodiment of the present disclosure, the material of the substrate 1 may be polyimide (PI). The substrate 1 may also be a composite of multiple layers of material. For example, in one embodiment of the present disclosure, the substrate 1 may include a bottom film layer, a pressure-sensitive adhesive layer, a first polyimide layer, and a second polyimide layer stacked in sequence.

[0096] like Figure 1 As shown, the substrate 1 may include a display area 11 and a peripheral area 12 located outside the display area 11. The display area 11 may be provided with pixel circuits, light-emitting devices, and other structures to display images. The peripheral area 12 may be provided with peripheral circuits and other structures to drive the pixel circuits located in the display area 11.

[0097] In some embodiments of the present disclosure, the display area 11 includes a first display area 111 and a second display area 112, wherein the second display area 112 is located on the periphery of the first display area 111. The second display area 112 may be located on one side, both sides, or all four sides of the first display area 111, and the present disclosure does not specifically limit this. In one embodiment, the second display area 112 is located on both sides of the first display area 111 in a first direction X, and the first direction X may be a row direction, a column direction, or other direction, and the specific details may not be limited. The pixel density of the second display area 112 is less than the pixel density of the first display area 111. The specific difference in pixel density between the second display area 112 and the first display area 111 can be set according to actual conditions, and the present disclosure does not specifically limit this.

[0098] The driving circuit layer 2 is provided on one side of the base substrate 1. The driving circuit layer 2 includes a driving circuit for driving each light-emitting device to emit light. The driving circuit may include a pixel circuit and a peripheral circuit. The pixel circuit is provided in the display area 11. It can be a 7T1C, 7T2C, 6T1C or 6T2C pixel circuit. As long as it can drive the light-emitting device to emit light, its structure is not particularly limited here. The number of pixel circuits is the same as the number of light-emitting devices, and they are connected to each light-emitting device in a one-to-one correspondence so as to control the light emission of each light-emitting device separately. Among them, nTmC means that a pixel circuit includes n transistors (represented by the letter "T") and m capacitors (represented by the letter "C").

[0099] The peripheral circuit is located in the peripheral region 12 and is connected to the pixel circuit for inputting a drive signal to the pixel circuit to control the light-emitting device to emit light. The peripheral circuit may include a gate drive circuit and a light-emitting control circuit, and of course, may also include other circuits. The specific structure of the peripheral circuit is not particularly limited herein.

[0100] The drive circuit layer 2 includes signal lines 5, which can be used to provide various signals to the pixel circuits or light-emitting devices, such as scan signals and power supply voltage signals. In some embodiments, the signal lines 5 are power supply voltage lines that can provide power supply voltage signals, such as Vdd signals or Vss signals, to the pixel circuits and light-emitting devices. The orthographic projection of the signal lines 5 on the base substrate 1 is located in the display area 11. This approach reduces the space occupied by the signal lines 5 in the peripheral area 12, i.e., the border area, and helps achieve a narrower border design for the display panel 01.

[0101] Display panel 01 also includes a first conductive via 6 , through which signal line 5 can be connected to conductive member 8 and, in turn, to circuit board 03 . The orthographic projection of first conductive via 6 on base substrate 1 is located in display area 11 . Thus, neither signal line 5 nor first conductive via 6 occupies space in peripheral area 12 . This solution effectively reduces the bezel width of display panel 01 while enabling connection between signal line 5 and circuit board 03 , achieving a narrower bezel design.

[0102] In some embodiments of the present disclosure, the orthographic projection of the first conductive via 6 on the base substrate 1 is located in the second display area 112. In this way, the normal display of the first display area 111 can be ensured, thereby reducing the overall impact of the first conductive via 6 on the display screen of the display panel 01.

[0103] like Figure 5 As shown, in some embodiments of the present disclosure, the signal line 5 includes a first signal line 51 and a second signal line 52, wherein the second signal line 52 is connected to the first signal line 51. The orthographic projection of the first signal line 51 on the base substrate 1 is located in the first display area 111, and the orthographic projection of the second signal line 52 on the base substrate 1 is located in the second display area 112. The second signal line 52 can be connected to the conductive member 8 through the first first conductive via 6 located in the second display area 112.

[0104] The present disclosure can reduce the resistance of the second signal line 52 in a variety of ways, thereby reducing power loss. For example, in some embodiments, the driving circuit layer 2 is a multi-layer film layer stacked structure, the driving circuit layer 2 may include multiple conductive layers, and the signal line 5 may be distributed in at least one conductive layer. Specifically, the signal lines 5 in different areas may be distributed in different conductive layers. For example, the second signal line 52 may be distributed in at least two conductive layers, and the signal lines 5 distributed in different conductive layers may be connected through vias. In this way, it helps to reduce the resistance of the second signal line 52. At the same time, since the second signal line 52 is connected to the first signal line 51, it further helps to reduce the resistance of the first signal line 51. In the present disclosure, the signal lines 5 distributed in different conductive layers are connected in parallel, and the first signal line 51 and the second signal line 52 are connected in series.

[0105] In other embodiments, the line width of the second signal line 52 is greater than the line width of the first signal line 51. In this embodiment, the second signal line 52 can be distributed in a single conductive layer or in at least two conductive layers, as long as the line width of the second signal line 52 is greater than the line width of the first signal line 51.

[0106] like Figure 2As shown, in some other embodiments, the second signal line 52 includes multiple main signal lines 524 and multiple connecting lines 523. The multiple main signal lines 524 extend along the first direction X and are arranged at intervals along the second direction Y. The connecting lines 523 extend along the second direction Y. Two adjacent main signal lines 524 are connected via the connecting line 523 and / or the first conductive via 6. In this embodiment, the first direction X can be a row direction or a column direction, and the second direction Y can be a direction having a certain angle with the first direction X. The angle can be greater than 0° and less than or equal to 90°.

[0107] Two adjacent main signal lines 524 can be connected via a connecting line 523, a first conductive via 6, or a combination of the two. For example, when a first conductive via 6 is provided between two adjacent main signal lines 524, the two main signal lines 524 can be connected via the connecting line 523 and the first conductive via 6. Specifically, there can be two connecting lines 523, with one end of each connecting line 523 connected to the first conductive via 6 and the other end of each connecting line 523 connected to a different main signal line 524. In this manner, two adjacent signal lines 5 can be connected. When no first conductive via 6 is provided between two adjacent signal lines 5, the two signal lines 5 can be connected via the connecting line 523. In this embodiment, multiple main signal lines 524 extending along the first direction X are connected in the second direction Y via the connecting lines 523 and / or the first conductive via 6. This allows the second signal lines 52 to have a generally mesh-like structure, thereby reducing the resistance of the second signal lines 52.

[0108] like Figure 3 As shown, in some other embodiments of the present disclosure, the orthographic projection of the second signal line 52 on the substrate 1 is a mesh structure. Specifically, the second signal line 52 includes a plurality of first sub-signal lines 521 and a plurality of second sub-signal lines 522. The plurality of first sub-signal lines 521 extend along the first direction X and are arranged at intervals along the second direction Y. The plurality of second sub-signal lines 522 extend along the second direction Y and are arranged at intervals along the first direction X. The first sub-signal lines 521 and the second sub-signal lines 522 are connected to form a mesh structure. The first first conductive via 6 can be located within the mesh defined by the first sub-signal lines 521 and the second sub-signal lines 522. The second signal line 52 also includes a connecting line 523, and the first sub-signal line 521 and the second sub-signal line 522 are connected to the first first conductive via 6 via the connecting line 523. The number of first first conductive vias 6 can be multiple, and the plurality of first first conductive vias 6 can be dispersed within different meshes.

[0109] In the present disclosure, there are multiple first-first conductive vias 6, and the orthographic projections of the multiple first-first conductive vias 6 on the base substrate 1 are dispersed throughout the second display area 112. In this way, the size of each first-first conductive via 6 is not excessively large, and does not affect the display effect of the display panel 01. The sum of the areas of the orthographic projections of the multiple first-first conductive vias 6 on the base substrate 1 accounts for 5%-50% of the area of ​​the second display area 112, and specifically may be 9%, 9.22%, 19%-40%, 19.2%, 41.05%, 45%, 45.8%, 50%, etc., but is not limited thereto.

[0110] In some embodiments of the present disclosure, the pixel density of the second display area 112 can be reduced to provide space for the first conductive via 6. For example, Figure 7 As shown, the first display area 111 of the base substrate 1 may correspond to a plurality of pixel units 10, each pixel unit 10 including a first sub-pixel 101, a second sub-pixel 102 and two third sub-pixels 103. In the pixel unit 10, the first sub-pixel 101 and the second sub-pixel 102 are arranged along the first direction X, and the two third sub-pixels 103 are arranged along the second direction Y to form a third sub-pixel group. The first direction X and the second direction Y form an angle, and the angle range is 80-100°. Preferably, the first direction X and the second direction Y are approximately perpendicular. It should be noted that in the present disclosure, the first direction X and the second direction Y being approximately perpendicular is a relative concept, not an absolute perpendicularity. The third sub-pixel group is arranged on one side of the second sub-pixel 102 along the first direction X. A plurality of pixel units 10 are arranged along the first direction X to form rows and along the second direction Y to form columns, and the pixel units 10 in two adjacent rows are staggered.

[0111] Furthermore, the first sub-pixel 101 may be a red sub-pixel, the second sub-pixel 102 may be a blue sub-pixel, and the third sub-pixel 103 may be a green sub-pixel. The projected area of ​​the red sub-pixel on the substrate 1 is larger than the projected area of ​​the blue sub-pixel on the substrate 1, and the projected area of ​​the green sub-pixel on the substrate 1 is larger than the projected area of ​​the blue sub-pixel on the substrate 1.

[0112] The pixel arrangement of the second display area 112 can refer to the first display area 111, and based on the pixel arrangement of the first display area 111, some sub-pixels are removed, and the first conductive vias 6 are provided in the area where the sub-pixels are removed. For example, in some embodiments, compared with the first display area 111, a third sub-pixel 103 of some pixel units 10 is removed in the second display area 112. Figure 8As shown, a third sub-pixel 103 is removed from every other row of pixel units 10, and in the pixel units 10 in the same row where the third sub-pixel 103 unit 10 needs to be removed, a third sub-pixel 103 is removed every other pixel unit 10. A first conductive through hole 6 is formed in the area where the third sub-pixel 103 is removed. Figure 9 As shown in FIG. 1 , in another embodiment, each pixel unit 10 removes a third sub-pixel 103. Figure 10 As shown, in some other embodiments, the entire pixel unit 10 is removed in alternate rows, and the first conductive vias 6 are formed in the removed area. Of course, part of the first sub-pixel 101 or part of the first sub-pixel 101 can also be removed, which will not be described in detail here.

[0113] In addition, there are also many ways to arrange the sub-pixels in the display area 11. Figure 11 As shown, in other embodiments, the first display area 111 of the substrate 1 may include a plurality of pixel units 10, each pixel unit 10 including a first sub-pixel 101, a second sub-pixel 102, and two third sub-pixels 103. The first sub-pixel 101 and the second sub-pixel 102 are arranged along a first direction X, and the two third sub-pixels 103 are arranged on opposite sides of the first sub-pixel 101 and the second sub-pixel 102 along a second direction Y. That is, one of the two third sub-pixels 103 is arranged on one side of the first sub-pixel 101 and the second sub-pixel 102 in the second direction Y, and the other third sub-pixel 103 is arranged on the other side of the second sub-pixel 102 and the second sub-pixel 102 in the second direction Y. The plurality of pixel units 10 are arranged sequentially along the first direction X to form rows, and the pixel units 10 in two adjacent rows are staggered.

[0114] As above, the first sub-pixel 101 may be a red sub-pixel, the second sub-pixel 102 may be a blue sub-pixel, and the third sub-pixel 103 may be a green sub-pixel.

[0115] In this type of embodiment, space for the first conductive via 6 can also be provided by removing certain sub-pixels. For example, a third sub-pixel 103 can be removed from every other row of pixel units 10. Furthermore, in the same row of pixel units 10 where the third sub-pixel 103 is to be removed, a third sub-pixel 103 is removed from every other pixel unit 10. The first conductive via 6 is formed in the area where the third sub-pixel 103 is removed.

[0116] In summary, there are many ways to form the first conductive vias 6 in the second display area 112 , which are not particularly limited in the present disclosure.

[0117] In the present disclosure, the structural design of the first signal line 51 located in the first display area 111 may refer to the structural design of the second signal line 52 described above, or may be conventionally designed, which is not specifically limited in the present disclosure.

[0118] like Figure 6 As shown, the film structure of the driving circuit layer 2 can be various. Taking the transistor in the driving circuit as a top-gate thin-film transistor as an example, the driving circuit layer 2 can include an active layer 221, a first gate insulating layer 222, a first gate metal layer 223, a second gate insulating layer 224, a second gate metal layer 225, an interlayer dielectric layer 226, and a first source and drain layer 227. The active layer 221 is disposed on one side of the base substrate 1. The material of the active layer 221 can be polycrystalline silicon or IGZO (indium gallium zinc oxide), and its conductive properties at different locations can be modified through processes such as doping. The active layer 221 may include the active regions of each transistor in the driving circuit. The first gate insulating layer 222 is disposed on the side of the active layer 221 away from the base substrate 1 and covers the active layer 221. The first gate insulating layer 222 can be a single layer of silicon nitride, silicon oxide, aluminum oxide, or a combination of these layers. The first gate insulating layer 222 can be formed by a deposition method. For example, a silicon oxide layer can be formed as a gate insulating material layer by vapor phase chemical deposition. After the gate insulating material layer is patterned, the first gate insulating layer 222 can be formed. The first gate metal layer 223 is arranged on the side of the first gate insulating layer 222 away from the base substrate 1. The first gate metal layer 223 may include the gate of each transistor in the pixel circuit and the first plate of the capacitor. The first gate metal layer 223 may include a metal material or an alloy material to ensure its good conductivity. Of course, the first gate metal layer 223 may also be made of a transparent conductive material 62, such as ITO (indium tin oxide) or IZO (indium zinc oxide). The second gate insulating layer 224 is arranged on the side of the first gate metal layer 223 away from the base substrate 1. The second gate insulating layer 224 covers the first gate metal layer 223. The second gate metal layer 225 is arranged on the side of the second gate insulating layer 224 away from the base substrate 1. The second gate metal layer 225 may include the second plate of the capacitor. The interlayer dielectric layer 226 is provided on the side of the second gate metal layer 225 away from the base substrate 1, and the interlayer dielectric layer 226 covers the second gate metal layer 225. The first source and drain layer 227 is provided on the side of the interlayer dielectric layer 226 away from the base substrate 1. The first source and drain layer 227 may include the source and drain of each transistor, and the source and drain of each transistor are connected to their respective active areas. The first source and drain layer 227 may include a metal material or an alloy material to ensure its good electrical conductivity. Of course, the first source and drain layer 227 may also use a transparent conductive material 62, such as ITO (indium tin oxide), IZO (indium zinc oxide), etc.

[0119] In some embodiments, the driving circuit layer 2 further includes a first planarization layer 23, a second source / drain layer 24, and a second planarization layer 25. The first planarization layer 23 is disposed on a side of the first source / drain layer 227 away from the base substrate 1, and the first planarization layer 23 covers the first source / drain layer 227. The second source / drain layer 24 is disposed on a side of the first planarization layer 23 away from the base substrate 1, and the second source / drain layer 24 may include a patch cord. The second planarization layer 25 is disposed on a side of the second source / drain layer 24 away from the base substrate 1, and the second planarization layer 25 covers the second source / drain layer 24.

[0120] Furthermore, the driving circuit layer 2 further includes an insulating layer 26 , which is disposed on a side of the second planarization layer 25 away from the base substrate 1 .

[0121] In some embodiments, the driving circuit layer 2 further includes a light shielding layer 21 disposed between the base substrate 1 and the active layer 221 . The light shielding layer 21 is used to shield the active layer 221 from light. The material of the light shielding layer 21 can be an opaque metal material or a metal alloy material.

[0122] The multi-layer conductive layer included in the driving circuit layer 2 can be any film layer with conductive properties in the driving circuit layer 2, such as the multi-layer conductive layer can include a first gate metal layer 223, a second gate metal layer 225, a first source and drain layer 227, and a second source and drain layer 24. The signal line 5 can be distributed in any of these film layers. For example, in one embodiment, the second signal line 52 is distributed in the first gate metal layer 223 and the second gate metal layer 225, and the second signal line 52 distributed in these two conductive layers is connected by a via hole. For another example, the second signal line 52 is distributed in the first source and drain layer 227 and the second source and drain layer 24, and the second signal line 52 distributed in these two conductive layers is connected by a via hole. The above is only an example to illustrate the distribution method of the signal line 5 in the driving circuit layer 2, but is not limited to this.

[0123] In some embodiments of the present disclosure, the display panel 01 further includes a light-emitting layer 3 and an encapsulation layer 4. The light-emitting layer 3 is disposed on the side of the driving circuit layer 2 away from the base substrate 1. The light-emitting layer 3 includes a first electrode layer 31, a pixel definition layer 32, a light-emitting functional layer 33, and a second electrode layer 34. The first electrode layer 31, the light-emitting functional layer 33, and the second electrode layer 34 can form multiple light-emitting devices, with the pixel definition layer 32 used to separate the multiple light-emitting devices. That is, the light-emitting layer 3 may include the pixel definition layer 32 and the multiple light-emitting devices separated by the pixel definition layer 32. The first electrode layer 31 is disposed on the side of the driving circuit layer 2 away from the base substrate 1 and includes multiple first electrodes arranged in an interval. The first electrodes can be connected to the source or drain of the transistor in the first source / drain layer 227 via the second source / drain layer 24. The material of the first electrode layer 31 can be a metal or alloy material to ensure good electrical conductivity. Of course, transparent conductive materials 62 such as ITO (indium tin oxide) and IZO (indium zinc oxide) can also be used. The first electrode layer 31 can be a single-layer film structure or a multi-layer film stack structure. For example, the first electrode layer 31 can be a multi-layer stack structure formed of ITO / Ag / ITO or Ti / Al / Ti. The pixel definition layer 32 is disposed on the side of the first electrode layer 31 away from the substrate 1, such as on the side of the insulating layer 26 away from the substrate 1. The pixel definition layer 32 is provided with multiple openings 321, each of which exposes each first electrode. The light-emitting functional layer 33 is disposed on the side of the first electrode layer 31 away from the substrate 1. The light-emitting functional layer 33 may include a hole injection layer, a hole transport layer, a light-emitting material layer, an electron transport layer, and an electron injection layer stacked in sequence in a direction away from the drive backplane. Visible light is generated by allowing holes and electrons to recombine into excitons in the light-emitting material layer, and the excitons radiate photons. The specific light-emitting principle is not described in detail here. The second electrode layer 34 is disposed on the side of the light-emitting functional layer 33 away from the substrate 1. The second electrode layer 34 can serve as the cathode of the light-emitting device.

[0124] The encapsulation layer 4 is disposed on the side of the light emitting layer 3 away from the base substrate 1. The encapsulation layer 4 covers the surface of the light emitting layer 3 away from the base substrate 11, and can be used to protect the light emitting layer 3 and prevent external water and oxygen from corroding the light emitting device.

[0125] In some embodiments of the present disclosure, encapsulation can be achieved by thin-film encapsulation (TFE). Specifically, the encapsulation layer 4 may include a first inorganic layer 41, an organic layer 42, and a second inorganic layer 43, wherein the first inorganic layer 41 covers the surface of the light-emitting layer 3 away from the base substrate 1, the organic layer 42 may be arranged on the surface of the first inorganic layer 41 away from the base substrate 1, and the boundary of the organic layer 42 is limited to the inner side of the boundary of the first inorganic layer 41, the second inorganic layer 43 covers the organic layer 42 and the first inorganic layer 41 not covered by the organic layer 42, and the second inorganic layer 43 can block the intrusion of water and oxygen, and the flexible organic layer 42 can achieve flattening.

[0126] like Figure 4 and Figure 5 As shown, the display panel 01 also includes a first through-hole 61 and a conductive material 62 filled in the first through-hole 61. The first through-hole 61 penetrates the encapsulation layer 4, the drive circuit layer 2, and the base substrate 1. The first conductive through-hole 6 includes the first through-hole 61 and the conductive material 62 filled in the first through-hole 61. The conductive material 62 is connected to the conductive member 8. The first through-hole 61 exposes at least a portion of the signal line 5. When the conductive material 62 is filled in the first through-hole 61, the signal line 5 can be electrically connected to the conductive member 8 through the conductive material 62. Furthermore, the first through-hole 61 exposes the sidewall of the signal line 5 and at least a portion of the surface on the side away from the base substrate 1.

[0127] like Figure 6 As shown, in the present disclosure, before filling the first through-hole 61 with the conductive material 62, a protective film 7 can be formed on the side of the encapsulation layer 4 away from the base substrate 1, covering the encapsulation layer 4. Subsequently, a second through-hole 71 is formed in the encapsulation layer 4, communicating with the first through-hole 61. The conductive material 62 is filled into the first through-hole 61 through the second through-hole 71 to form the first conductive through-hole 6. Preferably, after the conductive material 62 is filled, the protective film 7 can be removed.

[0128] Preferably, the signal line 5 is at least partially distributed in the first gate metal layer 223 and / or the second gate metal layer 225, and the second gate insulating layer 224 or the interlayer dielectric layer 226 covers at least a portion of the surface of the signal line 5 away from the substrate 1. The second gate insulating layer 224 and the interlayer dielectric layer 226 are inorganic material layers with good water-blocking properties, which help prevent the signal line 5 from being corroded by external water and oxygen. For example, in one embodiment, the signal line 5 is at least partially disposed in the first source and drain layer 227, and at least a portion of the signal line 5 is disposed in the first gate metal layer 223 and / or the second gate metal layer 225, and this portion is connected to the first source and drain layer 227 through a via. However, this is not limited to this, and the signal line 5 can also be disposed in other film layers, such as the second source and drain layer 24.

[0129] Furthermore, the second inorganic layer 43 in the encapsulation layer 4 wraps around the sidewalls of the film layers in the display panel 01 located between the conductive layer where the signal line 5 is located and the second inorganic layer 43. For example, if at least a portion of the signal line 5 is located in the second gate metal layer 225, the second inorganic layer 43 wraps around the sidewalls of the organic layer 42, the first inorganic layer 41, the light-emitting layer 3, the insulating layer 26, the second planarization layer 25, the first planarization layer 23, and the interlayer dielectric layer 226 to prevent external water and oxygen from corroding the film layers of the display panel 01.

[0130] In some embodiments of the present disclosure, a groove 251 is defined in the second planarization layer 25; the encapsulation layer 4 fills the groove 251. The orthographic projection of the pixel definition layer 32 on the base substrate 1 is located within the orthographic projection of the second planarization layer 25 on the base substrate 1; the orthographic projection of the groove 251 on the base substrate 1 is located on the side of the orthographic projection of the pixel definition layer 32 on the base substrate 1 that is closer to the orthographic projection of the first conductive via 6 on the base substrate 1. This prevents corrosion of the light-emitting device by external water and oxygen. Furthermore, the first inorganic layer 41 and the organic layer 42 may also be filled in the groove 251 to form a water-blocking structure.

[0131] like Figures 12 to 15 As shown, in the present disclosure, there are various ways to connect conductive member 8 to circuit board 03. For example, circuit board 03 has a first surface and a second surface disposed opposite each other. The first surface of circuit board 03 and the first surface of substrate 1 are oriented in the same direction, and the second surface of circuit board 03 and the second surface of substrate 1 are oriented in the same direction. Connecting pins 031 for connecting to conductive member 8 are provided on circuit board 03. Connecting pins 031 can be located on either the first or second surface of circuit board 03.

[0132] like Figure 12 、 Figure 13 and Figure 14 As shown, Figure 12 This is a second surface view of the substrate 1. Figure 13 and Figure 14This is a view of the first surface of the base substrate 1 and circuit board 03. In one embodiment, connecting pins 031 are provided on the second surface of circuit board 03. The surface of the base substrate 1 facing away from the drive circuit layer 2 has a bonding area 94, which is provided with a soldering pad 93. Conductive members 8 are connected to soldering pads 93. Circuit board 03 is bent to the side of the base substrate 1 facing away from the drive circuit layer 2 and connected to soldering pads 93. Specifically, bonding area 94 is located on the side of the base substrate 1 facing away from the drive circuit layer 2, where they are connected. There are multiple conductive members 8, spaced apart on the side of the base substrate 1 facing away from the drive circuit layer 2. Each conductive member 8 is connected by a conductive metal wire 9, which extends to the bonding area 94 and connects to soldering pads 93. Circuit board 03 is bent to the side of the base substrate 1 facing away from the drive circuit layer 2, where connecting pins 031 on the second surface of circuit board 03 are connected to soldering pads 93. When the signal line 5 is a power voltage line, the signal line 5 transmitting the VDD signal and the signal line 5 transmitting the VSS signal can be connected to the pads 93 transmitting the corresponding signals through different first conductive vias 6 . Figure 13 and Figure 14 In the figure, the pad 93 and the like are indicated by dotted lines, indicating that the structure is provided on the back side.

[0133] like Figure 15 As shown, in other embodiments, the connecting pin 031 is provided on the first surface of the circuit board. The display panel 01 also includes a conductive metal wire 9, which is connected to the conductive member 8 and extends to the second surface of the circuit board 03. The circuit board 03 is provided with a second conductive through-hole 032, through which the conductive metal wire 9 is connected to the connecting pin 031. Specifically, there are multiple conductive members 8, and the multiple conductive members 8 are spaced apart and distributed on the side surface of the base substrate 1 away from the driving circuit layer 2. The conductive members 8 are connected to each other by a conductive metal wire 9, which extends to the second surface of the circuit board 03 and is connected to the connecting pin 031 through the second conductive through-hole 032.

[0134] like Figure 12 As shown, further, in some embodiments, the conductive metal line 9 may include a bus 92 and multiple branches 91 connected to the bus 92, the multiple branches 91 are used to connect the various conductive parts 8, and the bus 92 is used to connect to the pad 93 or the second conductive through hole 032.

[0135] In some embodiments of the present disclosure, the display module further includes a driver chip (IC) 02, which can be connected to the chip-on-film 05 ( Figure 13 ) is connected between the display panel 01 and the circuit board 03, and can also be set on the base substrate 1 ( Figure 14 and Figure 15The signal in the signal line 5 can be controlled by the driver chip 02 or directly by the control terminal 04 connected to the circuit board 03.

[0136] The present disclosure also provides a display device including a display module. The display module may be any of the above-described embodiments. The specific structure and beneficial effects thereof may be referenced above with respect to the display panel embodiments, and are not further described here. The display device of the present disclosure may be a mobile phone, tablet computer, television, or other electronic device, which are not listed here.

[0137] It should be understood that the present disclosure is not limited in its application to the detailed structure and arrangement of the components set forth in this specification. The present disclosure is capable of other embodiments and can be implemented and executed in a variety of ways. The aforementioned variations and modifications fall within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or evident in the text and / or the drawings. All of these different combinations constitute multiple alternative aspects of the present disclosure. The embodiments of this specification illustrate the best mode known for implementing the present disclosure and will enable those skilled in the art to utilize the present disclosure.

Claims

1. A display module, characterized in that: The device comprises a display panel and a circuit board connected to the display panel, wherein the display panel comprises: A base substrate having a display area and a peripheral area located outside the display area; A driving circuit layer is provided on one side of the base substrate, the driving circuit layer includes a signal line, and an orthographic projection of the signal line on the base substrate is located in the display area; A conductive member is provided on a side of the base substrate away from the driving circuit layer, and the conductive member is connected to the circuit board; The display panel is further provided with a first conductive through hole, the orthographic projection of the first conductive through hole on the base substrate is located in the display area, the signal line is connected to the conductive member through the first conductive through hole, and the display panel also includes a light-emitting device arranged in the display area.

2. The display module according to claim 1, wherein: The display area includes: a first display area; a second display area, located outside the first display area, wherein the pixel density of the first display area is greater than the pixel density of the second display area; The orthographic projection of the first conductive through hole on the base substrate is located in the second display area.

3. The display module according to claim 2, wherein: The signal line includes: a first signal line, whose orthographic projection on the base substrate is located in the first display area; a second signal line connected to the first signal line, and having an orthographic projection on the base substrate located in the second display area; Wherein, the second signal line is connected to the conductive member through the first conductive through hole; The line width of the second signal line is greater than the line width of the first signal line.

4. The display module according to claim 2, wherein: The driving circuit layer includes multiple conductive layers; The signal line includes: a first signal line, whose orthographic projection on the base substrate is located in the first display area; a second signal line connected to the first signal line, and having an orthographic projection on the base substrate located in the second display area; Wherein, the second signal line is connected to the conductive member through the first conductive through hole; The second signal lines are distributed in at least two of the conductive layers, and the second signal lines distributed in different conductive layers are connected by vias.

5. The display module according to claim 2, wherein: The signal line includes: a first signal line, whose orthographic projection on the base substrate is located in the first display area; a second signal line connected to the first signal line, and having an orthographic projection on the base substrate located in the second display area; Wherein, the second signal line is connected to the conductive member through the first conductive through hole; The second signal line includes multiple main signal lines and multiple connecting lines. The multiple main signal lines extend along the first direction and are arranged at intervals along the second direction. The connecting lines extend along the second direction. Two adjacent main signal lines are connected through the connecting lines and / or the first conductive through-holes.

6. The display module according to claim 3 or 4, characterized in that: The orthographic projection of the second signal line on the base substrate is in a grid shape.

7. The display module according to claim 2, wherein: There are multiple first conductive through holes, and the orthographic projections of the multiple first conductive through holes on the base substrate are dispersed in the second display area; The sum of the orthographic projection areas of the plurality of first conductive vias on the base substrate accounts for 5%-50% of the area of ​​the second display region.

8. The display module according to claim 1, wherein: The signal line is a power supply voltage line.

9. The display module according to claim 1, wherein: The display panel further includes: a light-emitting layer, provided on a side of the driving circuit layer away from the base substrate, the light-emitting layer comprising a pixel definition layer and a plurality of light-emitting devices separated by the pixel definition layer; an encapsulation layer, provided on a side of the light-emitting layer away from the base substrate; The display panel further includes a first through hole and a conductive material filled in the first through hole, the first through hole penetrates the encapsulation layer, the drive circuit layer and the base substrate, the first conductive through hole includes the first through hole and the conductive material filled in the first through hole, and the conductive material is connected to the conductive member; The first through hole exposes at least a portion of the signal line.

10. The display module according to claim 9, wherein: The driving circuit layer includes: An active layer is provided on one side of the base substrate; a first gate insulating layer, provided on a side of the active layer away from the base substrate, the first gate insulating layer covering the active layer; a first gate metal layer, provided on a side of the first gate insulating layer away from the substrate, the first gate metal layer including a gate of a transistor and a first plate of a capacitor; a second gate insulating layer, provided on a side of the first gate metal layer away from the base substrate; a second gate metal layer, provided on a side of the second gate insulating layer away from the base substrate, the second gate metal layer comprising a second plate of the capacitor; an interlayer dielectric layer, provided on a side of the second gate metal layer away from the base substrate; A first source-drain layer is provided on a side of the interlayer dielectric layer away from the base substrate, the first source-drain layer including a source and a drain of the transistor; Wherein, the signal line is at least partially distributed in the first gate metal layer and / or the second gate metal layer; The second gate insulating layer or the interlayer dielectric layer covers at least a portion of the surface of the signal line away from the substrate, and the second gate insulating layer and the interlayer dielectric layer are inorganic material layers; The first through hole exposes a sidewall of the signal line and at least a portion of a surface of the signal line away from the base substrate.

11. The display module according to claim 10, wherein: The driving circuit layer further includes: A first planarization layer is provided on a side of the first source / drain layer away from the base substrate; a second source-drain layer, disposed on a side of the first planarization layer away from the first planarization layer, wherein at least a portion of the second source-drain layer is connected to the first source-drain layer; a second planarization layer, provided on a side of the second source / drain layer away from the base substrate, wherein a groove is provided in the second planarization layer; Wherein, the encapsulation layer fills the groove; The orthographic projection of the pixel definition layer on the base substrate is located within the orthographic projection of the second planarization layer on the base substrate; The orthographic projection of the groove on the base substrate is located on a side of the orthographic projection of the pixel definition layer on the base substrate close to the orthographic projection of the first conductive through hole on the base substrate.

12. The display module according to claim 1, wherein: The surface of the base substrate away from the driving circuit layer has a binding area, and the binding area is provided with a pad; The conductive member is connected to the pad via a conductive metal wire, and the circuit board is bent to a side of the base substrate away from the driving circuit layer and connected to the pad.

13. The display module according to claim 1, wherein: The circuit board has a first surface and a second surface that are arranged opposite to each other, and the first surface of the circuit board is provided with connecting pins; The display panel further includes a conductive metal line, the conductive metal line being connected to the conductive member and extending to the second surface of the circuit board; A second conductive through-hole is provided on the circuit board, and the conductive metal wire is connected to the connecting pin through the second conductive through-hole.

14. A display device, characterized in that: Comprising the display module according to any one of claims 1-13.

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