Display device and electronic device

Abstract

A display device capable of performing appropriate display without converting an image signal is provided. In a case where display is performed at a high resolution, individual data is supplied to each pixel through a first signal line and a first transistor included in each pixel. In a case where display is performed at a low resolution, the same data is supplied to a plurality of pixels through a second signal line and a second transistor electrically connected to the plurality of pixels. In a case where there are a plurality of display target image data and resolutions corresponding thereto are different, display can be performed without up-conversion or down-conversion by switching the supply path of the image data as described above.

Description

[0001] This invention application is a divisional application of the invention patent application entitled "Display Device and Electronic Device" with international application number PCT / IB2018 / 058354, international application date of October 26, 2018, and Chinese national phase application number 201880068248.8. Technical Field

[0002] One aspect of the present invention relates to a display device.

[0003] Note that one aspect of the present invention is not limited to the aforementioned technical fields. The technical field of one aspect of the invention disclosed in this specification relates to an object, method, or manufacturing method. Furthermore, one aspect of the present invention relates to a process, machine, manufacture, or composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, energy storage devices, memory devices, imaging devices, methods for driving these devices, or methods for manufacturing these devices.

[0004] Note that in this specification, etc., a semiconductor device refers to any device capable of operating by utilizing the characteristics of semiconductors. Transistors and semiconductor circuits are one type of semiconductor device. Additionally, storage devices, display devices, imaging devices, and electronic devices sometimes include semiconductor devices. Background Technology

[0005] The technique of using metal oxides formed on a substrate to construct transistors has attracted attention. For example, Patent Documents 1 and 2 have disclosed techniques for using transistors using zinc oxide or In-Ga-Zn type oxides as switching elements for pixels in display devices.

[0006] In addition, Patent Document 3 discloses a storage device having a structure that uses transistors with extremely low off-state current in storage cells.

[0007] [Preliminary Technology Documents]

[0008] [Patent Literature]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 2007-123861

[0010] [Patent Document 2] Japanese Patent Application Publication No. 2007-96055

[0011] [Patent Document 3] Japanese Patent Application Publication No. 2011-119674 Summary of the Invention

[0012] The technical problem that the invention aims to solve

[0013] With the continuous improvement of display device resolution, hardware capable of displaying images at 8K or 4K resolution (7680×4320 pixels) or higher has been developed. On the other hand, because high-resolution images require massive amounts of data, peripheral technologies such as camera devices, storage devices, and communication devices need to be adjusted in order to make high-resolution display devices more widespread.

[0014] Furthermore, for a display device to display an image properly, the image data must correspond to the display device's resolution. For example, if the display device has a resolution of 8K4K, and the image data is for 4K2K (3840×2160 pixels), full-screen display is not possible unless the data size is multiplied by four. Conversely, if the display device has a resolution of 4K2K, and the image data is for 8K4K, the data size needs to be multiplied by one-quarter.

[0015] This results in the problem that such data conversion requires dedicated circuitry, leading to increased power consumption. It is preferable to input the image data directly into the pixels of the display device without conversion.

[0016] In addition, upconversion is a technique used to generate high-resolution image data. By performing upconversion, low-resolution images can be converted into pseudo-high-resolution images.

[0017] Note that the upconversion device needs to analyze a large amount of image data to generate new image data, which increases the circuit size and power consumption. Additionally, sometimes the processing volume is too large to handle in real time, resulting in display latency.

[0018] Although upconversion has the aforementioned problems, it is possible to mitigate issues such as power consumption and latency by distributing upconversion-related functions across multiple devices, for example.

[0019] Therefore, one objective of this invention is to provide a display device capable of performing appropriate display without converting image data. Another objective of this invention is to provide a display device capable of image processing. Another objective of this invention is to provide a display device capable of performing upconversion operations. Finally, one objective of this invention is to provide a display device capable of displaying two images overlapping.

[0020] Furthermore, one objective of this invention is to provide a low-power display device. Additionally, one objective of this invention is to provide a highly reliable display device. Furthermore, one objective of this invention is to provide a novel display device, etc. Furthermore, one objective of this invention is to provide a driving method for the aforementioned display device. Furthermore, one objective of this invention is to provide a novel semiconductor device, etc.

[0021] Note that the description of these objectives does not preclude the existence of other objectives. One aspect of the invention does not require achieving all of the above objectives. Furthermore, objectives other than those described above are obvious from the description, drawings, and claims, and can be extracted from the description, drawings, and claims.

[0022] The technical problem that the invention aims to solve

[0023] One aspect of the present invention relates to a display device capable of performing appropriate display without converting image data. Another aspect of the present invention relates to a display device capable of performing image processing.

[0024] One aspect of the present invention is a display device including a first transistor and a first circuit to a fourth circuit, wherein each of the first circuits to the fourth circuit includes a second transistor, a first capacitor and a circuit block, one of the source and drain of the second transistor is electrically connected to one electrode of the first capacitor, one electrode of the first capacitor is electrically connected to the circuit block, and the other electrode of the first capacitor is electrically connected to one of the source and drain of the first transistor.

[0025] The second transistor preferably has a metal oxide in the channel formation region, and the metal oxide preferably has In, Zn and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf).

[0026] The gate of the second transistor included in the first circuit can be electrically connected to the gate of the second transistor included in the second circuit, and the gate of the second transistor included in the third circuit can be electrically connected to the gate of the second transistor included in the fourth circuit.

[0027] Furthermore, one of the source and drain of the second transistor included in the first circuit can be electrically connected to the other of the source and drain of the second transistor included in the third circuit, and the other of the source and drain of the second transistor included in the second circuit can be electrically connected to the other of the source and drain of the second transistor included in the fourth circuit.

[0028] The first to fourth circuits can all be configured as a matrix of pixels. The first circuit can be configured in the nth row and ith column (n and i are natural numbers), the second circuit can be configured in the nth row and (i+x)th column (x is a natural number), the third circuit can be configured in the (n+1)th row and ith column, and the fourth circuit can be configured in the (n+1)th row and (i+x)th column.

[0029] It can have the following structure: the circuit block includes a third transistor, a fourth transistor, a second capacitor, and an organic EL element. One electrode of the organic EL element is electrically connected to one of the source and drain of the fourth transistor. The other of the source and drain of the fourth transistor is electrically connected to one electrode of the second capacitor. One electrode of the second capacitor is electrically connected to one of the source and drain of the third transistor. The gate of the third transistor is electrically connected to the other electrode of the second capacitor. The other electrode of the second capacitor is electrically connected to one electrode of the first capacitor.

[0030] The above structure may also include a fifth transistor and a fifth circuit. One of the source and drain of the fifth transistor may be electrically connected to the other of the source and drain of the fourth transistor, and the other of the source and drain of the fifth transistor may be electrically connected to the fifth circuit.

[0031] The fifth circuit can also supply a fixed potential. Additionally, the fifth circuit can also read current values ​​and generate correction data.

[0032] In addition, it can have the following structure: the circuit block includes a sixth transistor, a third capacitor and a liquid crystal element, one electrode of the liquid crystal element is electrically connected to one electrode of the capacitor, one electrode of the capacitor is electrically connected to one of the source and drain of the sixth transistor, and the other of the source and drain of the sixth transistor is electrically connected to one electrode of the first capacitor.

[0033] The sixth transistor preferably has a metal oxide in the channel formation region, and the metal oxide preferably has In, Zn and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf).

[0034] Furthermore, another aspect of the present invention is a display device comprising a first transistor, a first circuit, a second circuit, a third circuit, a first wiring, a second wiring, and a third wiring, wherein each of the first to third circuits includes a second transistor, a first capacitor, and a display element; one of the source and drain of the second transistor is electrically connected to one electrode of the first capacitor; one electrode of the first capacitor is electrically connected to the display element; the first to third circuits are arranged adjacent to each other in one direction; a first wiring is provided between the first circuit and the second circuit; a second wiring and a third wiring are provided between the second circuit and the third circuit; the first wiring is electrically connected to the other of the source and drain of the second transistor included in the second circuit; the second wiring is electrically connected to the other of the source and drain of the second transistor included in the third circuit; the third wiring is electrically connected to one of the source and drain of the first transistor; and the other of the source and drain of the first transistor is electrically connected to the other electrode of the first capacitor included in any of the first to third circuits.

[0035] Furthermore, another aspect of the present invention is a display device comprising a first transistor, a first circuit, a second circuit, a third circuit, a first wiring, a second wiring, a third wiring, and a fourth wiring, wherein each of the first to third circuits includes a second transistor, a first capacitor, a second capacitor, and a display element; one of the source and drain of the second transistor is electrically connected to an electrode of the first capacitor; one electrode of the first capacitor is electrically connected to an electrode of the second capacitor; one electrode of the second capacitor is electrically connected to the display element; the first to third circuits are arranged adjacent to each other in one direction; a first wiring and a second wiring are provided between the first circuit and the second circuit; a third wiring and a fourth wiring are provided between the second circuit and the third circuit; the first wiring is electrically connected to the other of the source and drain of the second transistor included in the second circuit; the second wiring is electrically connected to the other of the second capacitor included in the first circuit; the second wiring is electrically connected to the other of the second capacitor included in the second circuit; the third wiring is electrically connected to the other of the source and drain of the second transistor included in the third circuit; the fourth wiring is electrically connected to one of the source and drain of the first transistor; and the other of the source and drain of the first transistor is electrically connected to the other electrode of the first capacitor included in any of the first to third circuits.

[0036] Invention Effects

[0037] By using one aspect of the present invention, a display device capable of appropriate display without converting image data can be provided. By using one aspect of the present invention, a display device capable of image processing can be provided. By using one aspect of the present invention, a display device capable of upconversion can be provided. By using one aspect of the present invention, a display device capable of displaying two images overlapping can be provided.

[0038] Furthermore, a low-power display device can be provided. Additionally, a highly reliable display device can be provided. Furthermore, a novel display device can be provided, etc. Furthermore, a driving method for the above-mentioned display device can be provided. Furthermore, a novel semiconductor device can be provided, etc. Brief description of the attached figures

[0039] [ Figure 1 [Diagram illustrating pixel circuitry]

[0040] [Figure 2] is a timing diagram illustrating the operation of the pixel circuit.

[0041] [Figure 3] A diagram illustrating the upconversion.

[0042] [Figure 4] A diagram illustrating the circuit blocks.

[0043] [Figure 5] A diagram illustrating the circuit blocks.

[0044] [Figure 6] is a diagram illustrating the pixel circuit.

[0045] [ Figure 7 [A block diagram illustrating the display device.]

[0046] [Figure 8] is a diagram illustrating an example of a neural network structure.

[0047] [ Figure 9 [A block diagram illustrating the display device.]

[0048] [ Figure 10 A diagram illustrating the structure of the pixels used for simulation.

[0049] [Figure 11] A graph illustrating the simulation results.

[0050] [Figure 12] A graph illustrating the simulation results.

[0051] [Figure 13] A graph illustrating the simulation results.

[0052] [ Figure 14 A diagram illustrating the structure of a pixel.

[0053] [ Figure 15 A diagram illustrating the structure of a pixel.

[0054] [Figure 16] A diagram illustrating the display device.

[0055] [Figure 17] A diagram illustrating the touch panel.

[0056] [Figure 18] A diagram illustrating the display device.

[0057] [Figure 19] A diagram illustrating a transistor.

[0058] [Figure 20] A diagram illustrating a transistor.

[0059] [Figure 21] A diagram illustrating a transistor.

[0060] [Figure 22] A diagram illustrating a transistor.

[0061] [Figure 23] A diagram illustrating an electronic device.

[0062] Methods of implementing the invention

[0063] The embodiments will be described in detail with reference to the accompanying drawings. Note that the invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as limited only to the embodiments described below. Note that in the structure of the invention described below, the same reference numerals are used in different drawings to denote the same parts or parts having the same function, and repeated descriptions are omitted. Note that sometimes the shading of the same constituent elements is appropriately omitted or changed in different drawings.

[0064] (Implementation Method 1)

[0065] In this embodiment, a display device according to one aspect of the present invention will be described with reference to the accompanying drawings.

[0066] One aspect of the present invention is a display device capable of appropriately displaying two image data sets, one for high resolution and one for low resolution, without up-converting or down-converting them. In high-resolution display, different data is supplied to each pixel via a first data line and a first transistor included in each pixel. In low-resolution display, the same data is supplied to the multiple pixels via a second data line and a second transistor electrically connected to the multiple pixels.

[0067] When there is image data for multiple display objects and their corresponding resolutions are different, the image data supply path can be switched as described above to display the image without up-conversion or down-conversion.

[0068] Here, high-resolution image data is, for example, equivalent to data corresponding to 8K4K (7680×4320 pixels). Furthermore, low-resolution image data is, for example, equivalent to data with the amount of data corresponding to 4K2K (3840×2160 pixels). That is, it is assumed that the effective ratio of the amount of high-resolution image data to low-resolution image data (corresponding to the effective number of pixels) is 4:1.

[0069] Furthermore, as long as the ratio of data quantity (pixel count) is 4:1, it is not limited to the above examples. High-resolution image data can also correspond to 4K2K data, and low-resolution image data can also correspond to FullHD (pixel count: 1920×1080) data. Alternatively, high-resolution image data can also correspond to 16K8K (pixel count: 15360×8640) data, and low-resolution image data can also correspond to 8K4K data.

[0070] Each pixel has a storage node, which can hold first data. The first data can be generated by an external device and written into each pixel. The first data can be capacitively coupled to second data and supplied to the display element. Alternatively, the first data can be capacitively coupled after the second data has been written to the storage node.

[0071] Therefore, the display element can display the corrected image. Through this correction, even in the case of displaying at low resolution as described above, image upconversion can be performed at the pixel level. Alternatively, a portion or the entire image in the display area can be corrected for wide dynamic range display. Alternatively, by using different image data as first and second data, arbitrary images can be displayed in an overlapping manner.

[0072] Figure 1 This diagram illustrates a portion (four pixels) of a pixel matrix arranged in a matrix-like configuration in a display device according to one aspect of the present invention. Each pixel 10 is provided with a transistor 102, a capacitor 103, and a circuit block 110. The circuit block 110 may include transistors, capacitors, and display elements, etc. Details will be described later. Note that n and m within parentheses indicate specific rows, and i and j indicate specific columns.

[0073] Each pixel 10 is configured in a matrix structure, meaning it can be placed in the nth row, i-th column (n and i are natural numbers greater than or equal to 1), the nth row, (i+x)-th column (x is a natural number greater than or equal to 1), the (n+1)th row, i-th column, and the (n+1)th row, (i+x)-th column. Furthermore, Figure 1 The layout is shown when x=1.

[0074] Furthermore, the pixel array includes transistors 101 electrically connected to the four pixels 10. The transistors 101 are positioned differently from the pixels 10, specifically in the m-th row and j-th column (where m and j are natural numbers greater than or equal to 1). Preferably, the m-th row is located between the n-th and (n+1)-th rows. Furthermore, the j-th column is preferably located between the i-th and (i+x)-th columns. Moreover, the transistors 101 are integral components of each pixel 10; in other words, each pixel shares the transistors 101.

[0075] One of the source and drain terminals of transistor 102 is electrically connected to one electrode of capacitor 103. One electrode of capacitor 103 is electrically connected to circuit block 110. The other electrode of capacitor 103 is electrically connected to one of the source and drain terminals of transistor 101.

[0076] Here, the wiring connecting one of the source and drain terminals of transistor 102, one electrode of capacitor 103, and the circuit block is designated as node NM. Furthermore, the constituent elements of the circuit block 110 connected to node NM can allow node NM to be in a floating state.

[0077] The gate of transistor 102 is electrically connected to wiring 121. The gate of transistor 101 is electrically connected to wiring 122. The other of the source and drain of transistor 102 is electrically connected to wiring 124. The other of the source and drain of transistor 101 is electrically connected to wiring 125.

[0078] Wiring 121 and 122 can function as signal lines for controlling the operation of transistors. Wiring 124 and 125 can function as signal lines for supplying image data or correction data. Furthermore, wiring 124 can also be considered a signal line for writing data to node NM.

[0079] Node NM is a storage node. By turning on transistor 102, data supplied to wiring 124 can be written to node NM. By using a transistor with extremely low off-state current as transistor 102, the potential of node NM can be maintained for a long time. As this transistor, for example, a transistor with metal oxide used for the channel formation region (hereinafter, OS transistor) can be used.

[0080] OS transistors can be used not only in transistor 102 but also in other transistors constituting the pixel. Transistor 102 can also be a transistor containing Si in the channel forming region (hereinafter referred to as a Si transistor), or a combination of OS transistors and Si transistors. Examples of Si transistors include transistors containing amorphous silicon and transistors containing crystalline silicon (typically low-temperature polycrystalline silicon or monocrystalline silicon).

[0081] As semiconductor materials for OS transistors, metal oxides with a bandgap of 2 eV or higher, preferably 2.5 eV or higher, and more preferably 3 eV or higher, can be used. Typical examples include indium-containing oxide semiconductors, such as CAAC-OS or CAC-OS mentioned later. In CAAC-OS, the atoms constituting the crystal are stable, making it suitable for transistors where reliability is critical. CAC-OS exhibits high mobility, making it suitable for transistors used in high-speed driving.

[0082] OS transistors exhibit extremely low off-state current characteristics due to their large bandgap. Unlike Si transistors, OS transistors do not experience impact ionization, avalanche breakdown, or short-channel effects, thus enabling the formation of highly reliable circuits.

[0083] As the semiconductor layer in the OS transistor, a film labeled "In-M-Zn oxide" can be used, for example, containing indium, zinc, and M (metals such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium).

[0084] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn type oxide, it is preferable that the atomic ratio of the metal elements in the sputtering target used to form the In-M-Zn oxide film satisfies In≥M and Zn≥M. Preferred atomic ratios of the metal elements in this sputtering target include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, and In:M:Zn = 5:1:8. Note that the atomic ratio of the formed semiconductor layer may vary within ±40% of the atomic ratio of the metal elements in the sputtering target described above.

[0085] As a semiconductor layer, an oxide semiconductor with a low carrier density can be used. For example, a semiconductor layer with a carrier density of 1 × 10⁻⁶ can be used. 17 / cm 3 The following is preferred: 1×10 15 / cm 3 Hereinafter, 1×10 is more preferred. 13 / cm 3 Hereinafter, 1×10 is further preferred. 11 / cm 3 The following is a further preferred option: less than 1×10 10 / cm 3 1×10 -9 / cm 3The above refers to oxide semiconductors. Such oxide semiconductors are called high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. These oxide semiconductors have low defect level densities and are therefore considered to have stable properties.

[0086] Note that the present invention is not limited to the above description, and materials with appropriate compositions can be used according to the desired semiconductor and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. Furthermore, it is preferable to appropriately set the carrier density, impurity concentration, defect density, ratio of metal elements to oxygen atoms, interatomic distance, density, etc., of the semiconductor layer to obtain the desired semiconductor characteristics of the transistor.

[0087] When the oxide semiconductor constituting the semiconductor layer contains silicon or carbon, one of Group 14 elements, the increase in oxygen vacancies causes the semiconductor layer to become n-type. Therefore, the concentration of silicon or carbon in the semiconductor layer (measured by secondary ion mass spectrometry) is set to 2 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 17 atoms / cm 3 the following.

[0088] Furthermore, sometimes when alkali metals and alkaline earth metals bond with oxide semiconductors, charge carriers are generated, increasing the off-state current of the transistor. Therefore, the concentration of the alkali metal or alkaline earth metal in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3 the following.

[0089] Furthermore, when the oxide semiconductor constituting the semiconductor layer contains nitrogen, electrons are generated as charge carriers, increasing the charge carrier density and making it easier to achieve n-type characteristics. As a result, transistors using nitrogen-containing oxide semiconductors tend to become normally-on. Therefore, the nitrogen concentration in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is preferably 5 × 10⁻⁶. 18 atoms / cm 3 the following.

[0090] Alternatively, the semiconductor layer may also have a non-single-crystal structure. Non-single-crystal structures include, for example, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) with c-axis orientation, polycrystalline structures, microcrystalline structures, or amorphous structures. Among non-single-crystal structures, amorphous structures have the highest defect state density, while CAAC-OS has the lowest.

[0091] Amorphous oxide semiconductor films, for example, have a disordered atomic arrangement and lack crystalline components. Alternatively, amorphous oxide films may be completely amorphous and lack crystalline regions.

[0092] Furthermore, the semiconductor layer can also be a mixture of two or more regions having an amorphous structure, a microcrystalline structure, a polycrystalline structure, a CAAC-OS region, and a single-crystal structure. The mixture sometimes has, for example, a single-layer structure or a stacked structure including two or more of the aforementioned regions.

[0093] The following describes the configuration of a non-single-crystal semiconductor layer, specifically a CAC (Cloud-Aligned Composite)-OS.

[0094] CAC-OS, for example, refers to a configuration in which elements are non-uniformly distributed within an oxide semiconductor, wherein the size of the material containing the non-uniformly distributed elements is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or approximately. Note that, below, the state in which one or more metal elements are non-uniformly distributed within an oxide semiconductor and the regions containing those metal elements are mixed with a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or approximately, is referred to as mosaic or patch-like.

[0095] The oxide semiconductor preferably contains at least indium. In particular, it preferably contains both indium and zinc. In addition, it may also contain one or more of the following: aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.

[0096] For example, CAC-OS in In-Ga-Zn oxides (in particular, In-Ga-Zn oxides can be referred to as CAC-IGZO) refers to materials that are indium oxides (hereinafter referred to as InO). X1 (X1 is a real number greater than 0) or indium zinc oxide (hereinafter referred to as In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) and gallium oxide (hereinafter referred to as GaO) X3 (X3 is a real number greater than 0) or gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0) etc., thus forming a mosaic pattern, and the mosaic-shaped InO X1 or In X2 Zn Y2 OZ2 The composition (hereinafter also referred to as cloud-like) is uniformly distributed in the membrane.

[0097] In other words, CAC-OS is a system with GaO X3 The region with In as the main component and X2 Zn Y2 O Z2 or InO X1 A composite oxide semiconductor is formed by mixing regions that are the main components together. In this specification, for example, when the ratio of the number of In atoms to the number of elements M in the first region is greater than that in the second region, the In concentration in the first region is higher than that in the second region.

[0098] Note that IGZO is a general term, sometimes referring to compounds containing In, Ga, Zn, and O. A typical example is InGaO3 (ZnO). m1 (m1 is a natural number) or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1≤x0≤1, m0 is any number) represents a crystalline compound.

[0099] The aforementioned crystalline compounds have single-crystal, polycrystalline, or CAAC structures. The CAAC structure is a crystalline structure in which multiple IGZO nanocrystals have c-axis orientation and are connected in a non-oriented manner on the ab plane.

[0100] On the other hand, CAC-OS is related to the material composition of oxide semiconductors. CAC-OS refers to a material composition containing In, Ga, Zn, and O, in which nanoparticle-like regions dominated by Ga and nanoparticle-like regions dominated by In are observed to be randomly dispersed in a mosaic pattern in one part and in another part, respectively. Therefore, in CAC-OS, the crystal structure is a secondary factor.

[0101] CAC-OS does not contain stacked structures consisting of two or more different membranes. For example, it does not contain a structure consisting of two layers: one with In as the main component and the other with Ga as the main component.

[0102] Note that sometimes GaO cannot be observed. X3 Regions with In as the main component X2 Zn Y2 O Z2 or InO X1 Clear boundaries between regions that are the main components.

[0103] In the case where CAC-OS contains one or more of aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium to replace gallium, CAC-OS refers to a composition in which nanoparticle-like regions with the metal element as the main component are observed in one part, and nanoparticle-like regions with In as the main component are observed to be randomly dispersed in a mosaic pattern in another part.

[0104] CAC-OS can be formed, for example, by sputtering without intentionally heating the substrate. When forming CAC-OS by sputtering, one or more gases selected from inert gases (typically argon), oxygen gases, and nitrogen gases can be used as the film-forming gas. Furthermore, the lower the proportion of oxygen gas in the total flow rate of the film-forming gas during film formation, the better; for example, the oxygen gas flow rate ratio is set to 0% or more and less than 30%, preferably 0% or more and less than 10%.

[0105] CAC-OS has the following characteristics: when measured using the out-of-plane method (XRD), one of the methods for X-ray diffraction, with θ / 2θ scanning, no clear peak is observed. In other words, based on X-ray diffraction, it can be determined that there is no orientation in the ab plane direction or the c-axis direction within the measurement region.

[0106] Furthermore, in the electron diffraction pattern of CAC-OS obtained by irradiating it with an electron beam with a diameter of 1 nm (also known as a nanobeam), a ring-shaped region of high brightness and multiple bright spots within this ring-shaped region were observed. Therefore, based on the electron diffraction pattern, it can be concluded that the crystal structure of CAC-OS has an nc (nano-crystal) structure that is unoriented in both the planar and cross-sectional directions.

[0107] Furthermore, for example, in CAC-OS of In-Ga-Zn oxides, based on EDX surface analysis images (EDX mapping) obtained by energy dispersive X-ray spectroscopy (EDX), it can be confirmed that: [the structure exhibits characteristics of GaO]. X3 Regions with In as the main component and X2 Zn Y2 O Z2 or InO X1 A mixture of components whose main components are unevenly distributed in different regions.

[0108] CAC-OS differs in structure from IGZO compounds, which have a uniform distribution of metallic elements, and thus exhibits different properties. In other words, CAC-OS possesses properties centered around GaO. X3Regions with In as the main component and In X2 Zn Y2 O Z2 or InO X1 The regions that are the main components are separated from each other, and the regions that are the main components of each element are mosaic-like.

[0109] Here, in In X2 Zn Y2 O Z2 or InO X1 The conductivity of regions with GaO as the main component is higher than that of regions with GaO as the main component. X3 The region is dominated by components such as In. In other words, when charge carriers flow through a region dominated by In X2 Zn Y2 O Z2 or InO X1 When In is the dominant component, it exhibits the conductivity of an oxide semiconductor. Therefore, when In... X2 Zn Y2 O Z2 or InO X1 When the region that is the main component is distributed in a cloud-like manner in an oxide semiconductor, a high field-effect mobility (μ) can be achieved.

[0110] On the other hand, with GaO X3 The insulation of regions with In as the main component is higher than that of regions with In as the main component. X2 Zn Y2 O Z2 or InO X1 The region where GaO is the main component. In other words, when GaO is used... X3 When regions with these as the main components are distributed in an oxide semiconductor, leakage current can be suppressed, thus achieving good switching operation.

[0111] Therefore, when CAC-OS is used in semiconductor devices, it is due to GaO X3 The insulation properties of In and other materials and their causes X2 Zn Y2 O Z2 or InO X1 The complementary effect of conductivity can achieve high on-state current (I) on ) and high field-effect mobility (μ).

[0112] Furthermore, semiconductor components using CAC-OS exhibit high reliability. Therefore, CAC-OS is suitable as a constituent material for a wide variety of semiconductor devices.

[0113] First, refer to Figure 2A1 , Figure 2A2The timing diagram shown illustrates an example of writing different data to each of pixel 10. This operation is equivalent, for example, to inputting high-resolution image data (8K4K data) in a display device with a pixel count corresponding to 8K4K. Furthermore, although this is described with respect to one pixel 10, the same operation can be performed on the other pixels 10.

[0114] In the following description, a high potential is represented by "H", a low potential by "L", and a specific potential between a high and a low potential by "M". Note that "M" can be a reference potential such as 0V or GND, or other potentials. Furthermore, high-resolution image data is designated as "VsH", and high-resolution correction data is designated as "Vp1". Additionally, "VsH" can also be referred to as any first data, and "Vp1" can be referred to as any second data.

[0115] First, refer to Figure 2A1 This section describes the process of writing image data (VsH) to node NM. Note that detailed variations in potential distribution, coupling, or losses due to circuit structure, operating conditions, etc., are not considered here. Potential changes caused by capacitive coupling depend on the capacitance ratio of the supply side to the supplied side, but for ease of explanation, it is assumed that the capacitance of node NM is sufficiently small.

[0116] At time T1, the potential of wiring 121 is set to "H", the potential of wiring 122 is set to "H", the potential of wiring 124 is set to "VsH", and the potential of wiring 125 is set to "M". This turns on transistor 101, and the potential of the other electrode of capacitor 103 becomes "M". This operation is used to reset the circuit for subsequent calibration (capacitive coupling).

[0117] In addition, transistor 102 is turned on, and the potential of wiring 124 (image data "VsH") is written to node NM.

[0118] At time T2, the potential of wiring 121 is set to "L", the potential of wiring 122 is set to "L", the potential of wiring 124 is set to "M", and the potential of wiring 125 is set to "M". As a result, transistors 101 and 102 are de-conducted, and node NM retains the image data "VsH".

[0119] This step involves writing the image data "VsH". Next, refer to... Figure 2A2 This describes the correction of the image data "VsH" and the display operation of the display elements included in circuit block 110.

[0120] Figure 2A1 , Figure 2A2 The work can be carried out continuously within a horizontal period. Alternatively, it can also... Figure 2A1The work is performed in the kth frame (k is a natural number), and Figure 2A2 The operation is performed in frame k+1.

[0121] At time T11, the potential of wiring 121 is set to "L", the potential of wiring 122 to "H", the potential of wiring 124 to "M", and the potential of wiring 125 to "Vp1". This turns on transistor 101, and the potential of node NM is added to the potential of wiring 125 by the capacitive coupling of capacitor 103. Here, "Vp1" is the correction data, and node NM becomes the potential "VsH+Vp1" formed by adding the correction data "Vp1" to the image data "VsH".

[0122] At time T12, the potential of wiring 121 is set to "L", the potential of wiring 122 is set to "L", the potential of wiring 124 is set to "M", and the potential of wiring 125 is set to "M". As a result, transistor 101 is not turned on, and the potential of node NM is maintained at "VsH+Vp1".

[0123] Then, the display element included in circuit block 110 displays the potential corresponding to node NM. Additionally, depending on the structure of the circuit block, the display may sometimes be performed from time T1 or time T11.

[0124] In this way, images with a wide dynamic range can be displayed by selecting pixels for correction. Furthermore, although the correction data "Vp1" value is the same for all four pixels, it is sufficient to achieve the desired visual effect of brightness and darkness. Alternatively, without correction, the potential of wiring 125 can be maintained at "M" at time T11. Or, the potential of wiring 122 can be set to "L" to prevent transistor 101 from conducting.

[0125] Next, refer to Figure 2B1 , Figure 2B2 The timing diagram shown illustrates the operation of writing the same data to four pixels 10. This operation is equivalent, for example, to inputting low-resolution image data (4K2K data) into a display device with a pixel count corresponding to 8K4K.

[0126] First, refer to Figure 2B1 This section explains how the correction data (Vp2) is written to node NM. Below, the low-resolution image data is referred to as "VsL," and the low-resolution correction data is referred to as "Vp2." Note that "VsL" can also be referred to as any first data, and "Vp2" can also be referred to as any second data.

[0127] At time T1, the potential of wiring 121 is set to "H", the potential of wiring 122 is set to "H", the potential of wiring 124 is set to "Vp2", and the potential of wiring 125 is set to "M". This turns on transistor 101, and the potential of the other electrode of capacitor 103 becomes "M". This operation is used to reset the circuit for subsequent calibration (capacitive coupling).

[0128] In addition, transistor 102 is turned on, and the potential of wiring 124 (correction data "Vp2") is written to node NM.

[0129] At time T2, the potential of wiring 121 is set to "L", the potential of wiring 122 is set to "L", the potential of wiring 124 is set to "M", and the potential of wiring 125 is set to "M". As a result, transistors 101 and 102 are de-conducted, and node NM holds the image data "Vp2".

[0130] This step involves writing the correction data "Vp2". Next, refer to... Figure 2B2 This describes the correction of the image data "VsL" and the display operation of the display elements included in circuit block 110.

[0131] Figure 2B1 , Figure 2B2 The work can be carried out continuously within a horizontal period. Alternatively, it can also... Figure 2B1 The work is performed in the kth frame, and Figure 2B2 The operation is performed in frame k+1.

[0132] At time T11, the potential of wiring 121 is set to "L", the potential of wiring 122 to "H", the potential of wiring 124 to "M", and the potential of wiring 125 to "VsL". This turns on transistor 101, and the potential of node NM is added to the potential of wiring 125 "VsL" via capacitive coupling from capacitor 103. Here, "VsL" represents image data, and node NM is the potential "Vp2+VsL" formed by adding image data "VsL" to correction data "Vp2".

[0133] At time T12, the potential of wiring 121 is set to "L", the potential of wiring 122 is set to "L", the potential of wiring 124 is set to "M", and the potential of wiring 125 is set to "M". As a result, transistor 101 is not turned on, and the potential of node NM is maintained at "Vp2+VsL".

[0134] Then, the display element included in circuit block 110 performs the display operation corresponding to the potential of node NM. In addition, depending on the structure of the circuit block, the display operation is sometimes performed from time T11.

[0135] Because the correction data "Vp2" can input different values ​​for each pixel 10, even if the image data "VsL" is the same, each pixel 10 can display a different image. In other words, upconversion is possible. Note that without correction, at time T1, the potential of wiring 124 is maintained at "M". Alternatively, at time T11, the potential of wiring 125 is maintained at "M". Or, the potential of wiring 122 is set to "L" to prevent transistor 101 from conducting. Without correction, all four pixels can display the same image.

[0136] By operating as described above, raw image data can be input to the display device without up- or down-conversion, thus enabling proper display. Furthermore, appropriate corrections can be made to the image display.

[0137] Here, refer to Figure 3A , Figure 3B This describes the upconversion process when inputting low-resolution image data.

[0138] For example, an 8K4K display has four times the number of pixels of a 4K2K display. That is, when image data that would be displayed by one pixel on a 4K2K display is displayed on an 8K4K display, all four pixels on the 8K4K display will display the same image data.

[0139] Figure 3A This is a diagram illustrating whether or not upconversion is performed. When viewed sequentially from left to right, Figure 3A The diagram shows the state of the original image (image data S1) displayed on one pixel of a 4K2K display device, the state of the image data S1 without upconversion displayed on four pixels of an 8K4K display device, and the state of the upconverted image data S0 to S2 displayed on four pixels of an 8K4K display device.

[0140] like Figure 3A As shown, before upconversion, all four pixels display image data S1, and after upconversion, each pixel displays image data S0 to S2, which helps to improve resolution.

[0141] Figure 3B The upconversion process in pixel 10 is explained. In pixel 10, as previously described, arbitrary correction data can be appended to the image data. Therefore, the original image data S1 is provided to each pixel as is.

[0142] In addition, correction data W1 to W3 are supplied to each pixel. There are no particular restrictions on the method for generating W1 to W3. The correction data can be generated in real time using an external device, or it can be generated by reading the correction data stored in the recording medium and synchronizing it with the image data S1.

[0143] By performing the previously described operation on pixel 10, the image data S1 supplied to each pixel is appended with correction data (W1, W2, or W3), thereby generating new image data S0 to S2. Thus, an image of the original image data S1 that has been upconverted can be displayed.

[0144] Existing upconversion methods utilizing external correction generate new image data, thus placing a significant burden on external devices. However, in one aspect of the present invention described above, new image data is generated within the pixels supplied with correction data, rather than altering the supplied image data, thereby reducing the burden on external devices. Furthermore, new image data can be generated within pixels in fewer steps, even in display devices with a high pixel count and short horizontal time intervals.

[0145] Note that although the above conversion is used as an example, this method can be used for all tasks that combine two image data for display. For example, it can be used to overlay an image and a text image. Furthermore, it can be used to overlap different images.

[0146] Figures 4A to 4C This is an example of a structure that can be used in circuit block 110 and includes EL elements as display elements.

[0147] Figure 4A The structure shown includes a transistor 111, a capacitor 113, and an EL element 114. One of the source and drain terminals of transistor 111 is electrically connected to one electrode of EL element 114. One electrode of EL element 114 is electrically connected to one electrode of capacitor 113. The other electrode of capacitor 113 is electrically connected to the gate of transistor 111. The gate of transistor 111 is electrically connected to node NM.

[0148] Another of the source and drain terminals of transistor 111 is electrically connected to wiring 128. The other electrode of EL element 114 is electrically connected to wiring 129. Wiring 128 and 129 have the function of supplying power. For example, wiring 128 can supply a high-potential power supply. Furthermore, wiring 129 can supply a low-potential power supply.

[0149] In this structure, current flows through EL element 114 when the potential at node NM is above the threshold voltage of transistor 111. Therefore, sometimes in Figure 2A1 , Figure 2B1The EL element 114 begins to emit light at time T1 in the timing diagram shown, therefore this structure is preferably used for operation without correction.

[0150] Figure 4B Yes Figure 4A The structure of the additional transistor 112 is described. One of the source and drain of transistor 112 is electrically connected to one of the source and drain of transistor 111. The other of the source and drain of transistor 112 is electrically connected to EL element 114. The gate of transistor 112 is electrically connected to wiring 126. Wiring 126 may function as a signal line to control the conduction of transistor 112.

[0151] In this structure, regardless of the potential of node NM, current flows through EL element 114 when transistor 112 is turned on. Therefore, it is possible to... Figure 2A2 , Figure 2B2 The EL element 114 begins emitting light after time T12 in the timing diagram shown, thus the structure is suitable for operation with accompanying correction.

[0152] Figure 4C Yes Figure 4B The structure of the additional transistor 115 is described. One of the source and drain of transistor 115 is electrically connected to one of the source and drain of transistor 111. The other of the source and drain of transistor 115 is electrically connected to wiring 130. The gate of transistor 115 is electrically connected to wiring 131. Wiring 131 can function as a signal line to control the conduction of transistor 115. Alternatively, the gate of transistor 115 can also be electrically connected to wiring 122.

[0153] Wiring 130 can be connected to circuit 120 and used as a monitoring line to obtain the electrical characteristics of transistor 111. In addition, the writing of image data can also be stabilized by supplying a specific potential from wiring 130 through transistor 115 to one of the source and drain of transistor 111.

[0154] When wiring 130 is used as a monitoring line, circuit 120 generates the potential of the threshold voltage of correction transistor 111 as the aforementioned correction data (Vp2).

[0155] Figures 5A to 5C This is an example of a structure that can be used in circuit block 110 and include a liquid crystal element as a display element.

[0156] Figure 5A The structure shown includes a capacitor 116 and a liquid crystal element 117. One electrode of the liquid crystal element 117 is electrically connected to one electrode of the capacitor 116. One electrode of the capacitor 116 is electrically connected to node NM.

[0157] The other electrode of capacitor 116 is electrically connected to wiring 132. The other electrode of liquid crystal element 117 is electrically connected to wiring 133. Wiring 132 and 133 have the function of supplying power. For example, wiring 132 and 133 can supply reference potentials such as GND and 0V or any potential.

[0158] In this structure, the liquid crystal element 117 begins operation when the potential at node NM exceeds the operating threshold of the liquid crystal element 117. Therefore, sometimes... Figure 2A1 , Figure 2B1 The timing diagram shown begins displaying at time T1, therefore this structure is preferably used for operation without correction. Note that in the case of a transmissive liquid crystal display device, the transmissive liquid crystal display also employs... Figure 2A1 , Figure 2B2 The backlight is turned off by the time T12 shown, which prevents unwanted display operations from being seen.

[0159] Figure 5B Yes Figure 5A The structure of the additional transistor 118 is described. One of the source and drain of transistor 118 is electrically connected to one electrode of capacitor 116. The other of the source and drain of transistor 118 is electrically connected to node NM. The gate of transistor 118 is electrically connected to wiring 126. Wiring 126 may function as a signal line to control the conduction of transistor 118.

[0160] In this structure, while transistor 118 is turned on, the potential of node NM is applied to liquid crystal element 117. Therefore, it is possible to... Figure 2A2 , Figure 2B2 The liquid crystal element begins operation after time T12 in the timing diagram shown, thus this structure is suitable for operation accompanied by calibration.

[0161] Furthermore, since the potential supplied to capacitor 116 and liquid crystal element 117 remains constant while transistor 118 is in a non-conducting state, it is preferable to reset the potential supplied to capacitor 116 and liquid crystal element 117 before rewriting the image data. This reset can be achieved, for example, by supplying a reset potential to wiring 124 and simultaneously turning on transistors 102 and 118.

[0162] Figure 5C Yes Figure 5B The structure of the additional transistor 119 is described. One of the source and drain of transistor 119 is electrically connected to one electrode of liquid crystal element 117. The other of the source and drain of transistor 119 is electrically connected to wiring 130. The gate of transistor 119 is electrically connected to wiring 131. Wiring 131 can function as a signal line to control the conduction of transistor 119. Alternatively, the gate of transistor 119 can also be electrically connected to wiring 122.

[0163] The circuit 120 electrically connected to wiring 130 is as described above. Figure 4C Similarly, as described above, it can also have the function of resetting the potential of the supply capacitor 116 and the liquid crystal element 117.

[0164] In addition, such as Figure 6A , Figure 6B As shown, transistors 101 and 102 can also be configured with a back gate. Figure 6A The diagram shows a structure in which the back gate and front gate are electrically connected, which has the effect of improving the turn-on current. Figure 6B The diagram shows a structure where the back gate is electrically connected to wiring 134, which can supply a constant potential and control the threshold voltage of the transistor. Alternatively, it can also be... Figures 4A to 4C and Figures 5A to 5C The transistors included in the circuit block 110 shown have back gates.

[0165] Figure 7 This is an example of a block diagram of a display device according to one aspect of the present invention. The display device includes a pixel array 11 in which pixels 10 are arranged in a matrix, row drivers 12 and 13, column drivers 14 and 15, circuitry 16, and selection circuitry 17 and 18.

[0166] Row drivers 12 and 13, and column drivers 14 and 15, can be, for example, shift register circuits or decoder circuits. Circuit 16 has the function of generating correction data. Note that circuit 16 can also be described as an external device used to generate correction data.

[0167] Row driver 12 is electrically connected to wiring 121 and can control the conduction of transistor 102. Row driver 13 is electrically connected to wiring 122 and can control the conduction of transistor 101. In addition, column driver 14 can be electrically connected to wiring 124, and column driver 15 is electrically connected to wiring 125.

[0168] High-resolution image data "VsH" (e.g., 8K4K data) or low-resolution image data "VsL" (e.g., 4K2K data) is input to circuit 16. When inputting image data "VsH", correction data "Vp1" is generated and output to column driver 15 via selection circuit 18. When inputting image data "VsL", correction data "Vp2" is generated and output to column driver 14 via selection circuit 17.

[0169] Additionally, image data "VsH" can be input to column driver 14 via selection circuit 17. Image data "VsL" can be input to column driver 15 via selection circuit 18. Furthermore, when externally inputting correction data Vp1 and correction data Vp2, these correction data Vp1 and correction data Vp2 can be input to column driver 14 or column driver 15 via selection circuit 17 or selection circuit 18.

[0170] Circuit 16 can have a neural network. For example, a deep neural network that has been trained on a large number of images as supervised data can be used to generate high-precision correction data.

[0171] like Figure 8A As shown, a neural network (NN) can consist of an input layer (IL), an output layer (OL), and intermediate layers (hidden layers) (HL). Each of the input layer (IL), output layer (OL), and intermediate layers (HL) includes one or more neurons (units). Note that the intermediate layers (HL) can be one or more. A neural network containing two or more intermediate layers (HL) can be called a deep neural network (DNN), and learning using deep neural networks can be called deep learning.

[0172] In the input layer (IL), each neuron receives input data; in the intermediate layer (HL), each neuron receives the output signals from neurons in the preceding or following layer; and in the output layer (OL), each neuron receives the output signals from neurons in the preceding layer. Note that each neuron can be fully connected to all neurons in the preceding and following layers, or it can be connected to only some neurons.

[0173] Figure 8B An example of computation using neurons is shown. Here, neuron N and two neurons in the previous layer that output signals to neuron N are shown. Neuron N is input with the outputs x1 and x2 of the neurons in the previous layer. In neuron N, the sum x1w1 + x2w2, which is the product of output x1 and weight w1 (x1w1) and output x2 and weight w2 (x2w2), is calculated. Then, a bias voltage b is applied as needed to obtain the value a = x1w1 + x2w2 + b. The value a is transformed by the activation function h, and the output signal y = h(a) is output from neuron N.

[0174] Thus, the computation of neurons involves adding the product of the output and weights of the neurons in the previous layer, i.e., a product summation operation (x1w1 + x2w2 above). This product summation operation can be performed in software or in hardware. When performing the product summation operation in hardware, a product summation circuit can be used. This product summation circuit can be either a digital circuit or an analog circuit.

[0175] The product summation circuit can be constructed using either Si transistors or OS transistors. In particular, OS transistors are preferred for use as transistors in analog memory to construct the product summation circuit because they have extremely low off-state current. Note that the product summation circuit can also be constructed using both Si transistors and OS transistors.

[0176] In addition, such as Figure 9 As shown, the function of row driver 13 can also be integrated into row driver 12. Alternatively, the functions of column driver 15 and column driver 14 can also be integrated. In this case, correction data, image data, and output data from circuit 16 are input to selection circuit 19, and any one of these data is output to column driver 14 in an appropriate timing sequence.

[0177] The row driver 12 can, for example, be structured as a combination of shift register 20 and buffer circuit 21. By controlling the conduction of buffer circuit 21, data can be selectively output to wiring 121 or wiring 122. Similarly, the column driver 14 can, for example, be structured as a combination of shift register 22 and selection circuit 23. Data can be selectively output to wiring 124 or wiring 125 by selection circuit 23.

[0178] exist Figure 7 In the structure shown, different drivers are used depending on the resolution of the image data. Therefore, for example, when performing low-resolution and uncorrected display operations, row driver 13 and column driver 15 can operate, and the operation of row driver 12 and column driver 14 can be stopped. Furthermore, the number of used wirings 122 and 125 is half the number of unused wirings 121 and 124, thus reducing the power required for data charging and discharging. Additionally, in the structure shown in FIG8, power consumption can be reduced by halving the number of driver output stages when performing the same display operation.

[0179] Next, the explanation will be Figure 4A The circuit block shown is applied to Figure 1 The structure of the pixel array shown (refer to) Figure 10 The simulation results are as follows. The parameters are as follows: Transistor size is L / W = 6μm / 6μm (transistor 102), L / W = 4μm / 4μm (other transistors); capacitor 103 has a capacitance of 150fF; capacitor 113 has a capacitance of 50fF; EL element 114 is an FN diode model; wiring 128 is set to +10V anode potential; wiring 129 is set to -5V cathode potential. Note that SPICE was used as the circuit simulation software.

[0180] Figures 11A to 11C It is a simulation result that verifies a high-resolution display (without correction). Figure 11A This is a timing diagram used for verification. In Figure 11A During time T1 to T2, image data (V) is written from wiring 124 by turning on transistor 102. DATA ).

[0181] Figure 11B It is the current (I) flowing through EL element 114 LED ) relative to image data (V DATA The simulation results. Although Figure 11B It is a simulation result in one pixel, but it is confirmed that any pixel (pix1 to pix4) can be displayed in grayscale.

[0182] also, Figure 11C It is the potential (V) of node NM NM ) relative to image data (V DATA The simulation results show the change in the potential (V) of node NM in any pixel. NM ) and image data "V DATA "Proportional to each other."

[0183] In other words, it was confirmed that high-resolution image data (V) supplied from wiring 124 can be displayed. DATA ).

[0184] Figures 12A to 12C It is a simulation result to verify a low-resolution display (without correction). Figure 12A , Figure 12B This is a timing diagram used for verification. First, in Figure 12A During time intervals T1 to T2, the potential of node NM is reset. Then, in Figure 12B During the time intervals T3 to T4, image data (V) is written from wiring 125 by turning on transistor 101. DATA ).

[0185] Figure 12C It is the current (I) flowing through EL element 114 LED ) relative to image data (V DATA The simulation results. Although Figure 12B It is a simulation result in one pixel, but it is confirmed that any pixel (pix1 to pix4) can be displayed in grayscale.

[0186] also, Figure 12D It is the potential (V) of node NM NM ) relative to image data (V DATA The simulation results show the change in the potential (V) of node NM in any pixel. NM ) and image data (V DATA It is directly proportional to.

[0187] In other words, it was confirmed that low-resolution image data (V) supplied from wiring 125 can be displayed. DATA ).

[0188] Figures 13A to 13C These are simulation results validating a low-resolution display (after calibration). Figure 13A , Figure 13B This is a timing diagram used for verification. First, in Figure 13A During time T1 to T2, correction data (Vp) is written from the 124-pair node NM of the wiring. Then, in Figure 13B During the time intervals T3 to T4, image data (V) is written from wiring 125 by turning on transistor 101. DATA ).

[0189] Figure 13C It is the current (I) flowing through EL element 114 in each calibration data. LED The simulation results were compared to the image data. It was confirmed that writing 1V to 8V as correction data (Vp) and comparing it with the image data (V...)... DATA Grayscale display is possible in any combination of these.

[0190] also, Figure 13D It is the potential (V) of node NM in each correction data (Vp). NM ) relative to image data (V DATA The simulation results of the change were confirmed. It was found that writing 1V to 8V as correction data (Vp) and mixing it with the image data (V) DATA In any case of combination, the potential (V) of node NM is... NM ) and image data (V DATA It is proportional to the correction data (Vp).

[0191] In other words, it was confirmed that the correction data (Vp) supplied from wiring 124 and the low-resolution image data (Vp) supplied from wiring 125 can be combined. DATA (This will be used to display the content.)

[0192] Figure 14 This is an example of using pixels according to one aspect of the present invention in an EL display device capable of color display. Generally speaking, pixels in a display device capable of color display have a combination of sub-pixels emitting R (red), G (green), and B (blue) colors. Figure 14 In this context, three sub-pixels arranged horizontally—sub-pixels 10R, 10G, and 10B—constitute one pixel, representing four pixels in both the horizontal and vertical directions. Additionally, in... Figure 14 The wiring, such as power cords, is omitted.

[0193] As described above, in one aspect of the present invention, correction data Vp1 or image data VsL can be input to four pixels configured in a matrix (here, equivalent to four sub-pixels emitting the same color) via transistor 101. Here, each column is provided with wiring 124 electrically connected to each sub-pixel, and each pair of sub-pixels in the horizontal direction is provided with wiring 125 electrically connected to transistor 101.

[0194] In this structure, for example in Figure 14 In the top-left pixel (PIX1), there is a wiring 124[i+1] between sub-pixels 10R and 10G, and two wirings, wiring 124[i+2] and wiring 125[j+1], between sub-pixels 10G and 10B. Therefore, when the constituent elements are arranged as densely as possible, it is difficult to keep the spacing between sub-pixels (the spacing between constituent elements with the same function) constant.

[0195] Therefore, when the pixel electrodes connected to sub-pixel 10R, sub-pixel 10G, and sub-pixel 10B are respectively electrodes 25R, 25G, and 25B, as follows: Figure 14 As shown, a structure in which electrodes 25R, 25G, and 25B are arranged at equal intervals is preferred. Note that although pixel electrodes can also be considered constituent elements of each sub-pixel, for clarity, they are represented here as distinct constituent elements. This structure is effective for top-emitting EL displays or reflective liquid crystal displays.

[0196] Figure 15 This is an example of using pixels according to one aspect of the present invention in a liquid crystal display device capable of color display. To ensure a constant spacing between sub-pixels in the liquid crystal display device, for example... Figure 15 In the top-left pixel (PIX2), wiring 132[j], which is electrically connected to the other electrode of capacitor 116, is placed between sub-pixels 10R and 10G. Wiring 132 is electrically connected to the capacitors 116 included in sub-pixels 10R and 10G. Additionally, the capacitor 116 included in sub-pixel 10B is electrically connected to wiring 132[j+1], which is placed between sub-pixels 10R of the pixel adjacent to sub-pixel 10B.

[0197] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc.

[0198] (Implementation Method 2)

[0199] This embodiment describes structural examples of a display element using a liquid crystal element and a display device using an EL element. Note that the components, operation, and functions of the display device described in Embodiment 1 are omitted in this embodiment.

[0200] Figures 16A to 16C The structure of a display device in which one aspect of the present invention can be used is shown.

[0201] exist Figure 16A In this process, a sealant 4005 is provided around a display portion 215 disposed on a first substrate 4001, and the display portion 215 is sealed by the first substrate 4001, the sealant 4005, and the second substrate 4006.

[0202] The display unit 215 is provided with embodiment 1. Figure 7 or Figure 9 The pixel array 11 is shown. Note that the scan line drive circuit described below is equivalent to a row driver, while the signal line drive circuit is equivalent to a column driver.

[0203] exist Figure 16A In this circuit, the scan line driving circuit 221a, signal line driving circuit 231a, signal line driving circuit 232a, and common line driving circuit 241a all include multiple integrated circuits 4042 disposed on the printed circuit board 4041. The integrated circuits 4042 are formed of single-crystal semiconductors or polycrystalline semiconductors. Signal line driving circuits 231a and 232a function as column drivers as shown in Embodiment 1. Scan line driving circuit 221a functions as a row driver as shown in Embodiment 1. Common line driving circuit 241a functions as a wiring supplying power and a wiring supplying Vref, as shown in Embodiment 1, supplying a predetermined potential.

[0204] Various signals and potentials are supplied to the scan line drive circuit 221a, common line drive circuit 241a, signal line drive circuit 231a and signal line drive circuit 232a through the FPC (Flexible printed circuit) 4018.

[0205] The integrated circuit 4042, included in the scan line driving circuit 221a and the common line driving circuit 241a, has the function of supplying selection signals to the display unit 215. The integrated circuit 4042, included in the signal line driving circuit 231a and the signal line driving circuit 232a, has the function of supplying image data to the display unit 215. The integrated circuit 4042 is mounted in a region different from the region surrounded by the sealant 4005 on the first substrate 4001.

[0206] Note that there are no particular restrictions on the connection method of the integrated circuit 4042. The wire bonding method, COG (Chip On Glass) method, TCP (Tape Carrier Package) method, and COF (Chip On Film) method can be used.

[0207] Figure 16B An example is shown of an integrated circuit 4042 included in signal line drive circuits 231a and 232a, which is mounted using the COG method. Furthermore, a system-on-panel can be formed by forming a portion or all of the drive circuit on a first substrate 4001 on which the display section 215 is formed.

[0208] Figure 16B An example is shown in which the scan line driving circuit 221a and the common line driving circuit 241a are formed on a substrate on which the display section 215 is formed. By simultaneously forming the driving circuit and the pixel circuit within the display section 215, the number of components can be reduced. As a result, productivity can be improved.

[0209] In addition, Figure 16B In this process, a sealant 4005 is provided around the display portion 215, the scan line drive circuit 221a, and the common line drive circuit 241a disposed on the first substrate 4001. A second substrate 4006 is disposed on the display portion 215, the scan line drive circuit 221a, and the common line drive circuit 241a. Thus, the display portion 215, the scan line drive circuit 221a, and the common line drive circuit 241a are sealed together with the display element by the first substrate 4001, the sealant 4005, and the second substrate 4006.

[0210] Although Figure 16B The illustration shows an example of separately forming signal line driving circuits 231a and 232a and mounting them to the first substrate 4001. However, one aspect of the invention is not limited to this structure; a scan line driving circuit may also be separately formed and mounted, or a part of the signal line driving circuit or a part of the scan line driving circuit may be separately formed and mounted. Additionally, as... Figure 16C The signal line driving circuit 231a and signal line driving circuit 232a can also be formed on the substrate on which the display section 215 is formed.

[0211] In addition, display devices sometimes include a panel in which the display element is sealed and a module, including an IC and a controller, which is installed in the panel.

[0212] The display section and scan line driving circuit disposed on the first substrate include a plurality of transistors. The transistors shown in the above embodiment can be used as such transistors.

[0213] The transistors included in the peripheral driving circuit and the transistors included in the pixel circuit of the display unit can have the same structure or different structures. The transistors included in the peripheral driving circuit can all have the same structure or combine two or more structures. Similarly, the transistors included in the pixel circuit can all have the same structure or combine two or more structures.

[0214] Alternatively, an input device 4200 can be provided on the second substrate 4006. The structure shown in FIG16, which provides an input device 4200 for a display device, can be used as a touch panel.

[0215] There are no particular limitations on the sensing elements (also referred to as sensor elements) included in the touch panel of one embodiment of the present invention. In addition, various sensors capable of detecting the proximity or contact of a detection object such as a finger or stylus can also be used as sensing elements.

[0216] For example, various methods can be used as sensors, such as electrostatic capacitive, resistive film, surface acoustic wave, infrared, optical, and pressure-sensitive types.

[0217] In this embodiment, a touch panel including an electrostatic capacitive sensing element will be used as an example for explanation.

[0218] As electrostatic capacitive sensors, there are surface-type electrostatic capacitive sensors and projection-type electrostatic capacitive sensors. Furthermore, projection-type electrostatic capacitive sensors include self-capacitance type and mutual-capacitance type. Mutual-capacitance type is preferred because it allows for simultaneous multi-point sensing.

[0219] The touch panel of one aspect of the present invention can adopt various structures such as a structure in which a display device and a sensing element are bonded together separately, or a structure in which electrodes constituting the sensing element are provided on one or both of the substrate supporting the display element and the opposing substrate.

[0220] Figure 17A and Figure 17B An example of a touch panel is shown. Figure 17A This is a 3D view of the touch panel 4210. Figure 17B This is a three-dimensional schematic diagram of the input device 4200. Note that, for clarity, only typical components are shown.

[0221] The touch panel 4210 has a structure that integrates separately manufactured display devices and sensing elements.

[0222] The touch panel 4210 includes an input device 4200 and a display device arranged in an overlapping manner.

[0223] Input device 4200 includes substrate 4263, electrode 4227, electrode 4228, multiple wirings 4237, multiple wirings 4238, and multiple wirings 4239. For example, electrode 4227 may be electrically connected to wiring 4237 or wiring 4239. Additionally, electrode 4228 may be electrically connected to wiring 4239. FPC 4272b may be electrically connected to the multiple wirings 4237 and multiple wirings 4238. FPC 4272b may be equipped with IC 4273b.

[0224] A touch sensor may be disposed between the first substrate 4001 and the second substrate 4006 of the display device. When a touch sensor is disposed between the first substrate 4001 and the second substrate 4006, an optical touch sensor utilizing a photoelectric conversion element may be used in addition to an electrostatic capacitive touch sensor.

[0225] Figure 18A and Figure 18B It is along Figure 16B The cross-sectional view of the dotted lines N1-N2 in the diagram. Figure 18A and Figure 18B The display device shown includes an electrode 4015, which is electrically connected to the terminals of the FPC 4018 via an anisotropic conductive layer 4019. Additionally, in Figure 18A and Figure 18B In this process, electrode 4015 is electrically connected to wiring 4014 in the openings formed in insulating layer 4112, insulating layer 4111 and insulating layer 4110.

[0226] Electrode 4015 and first electrode layer 4030 are formed using the same conductive layer, and wiring 4014 and source and drain electrodes of transistors 4010 and 4011 are formed using the same conductive layer.

[0227] Additionally, the display section 215 and the scan line driving circuit 221a disposed on the first substrate 4001 include a plurality of transistors. Figure 18A and Figure 18B The image shows transistor 4010 in display unit 215 and transistor 4011 in scan line drive circuit 221a. Although Figure 18A and Figure 18B The transistors 4010 and 4011 are shown as bottom-gate transistors, but top-gate transistors can also be used.

[0228] exist Figure 18A and Figure 18B In this configuration, an insulating layer 4112 is provided on transistors 4010 and 4011. Additionally, in... Figure 18B In the middle, a partition wall 4510 is formed on the insulating layer 4112.

[0229] Additionally, transistors 4010 and 4011 are disposed on insulating layer 4102. Furthermore, transistors 4010 and 4011 include an electrode 4017 formed on insulating layer 4111. Electrode 4017 can be used as a back gate electrode.

[0230] in addition, Figure 18A and Figure 18B The display device shown includes a capacitor 4020. The capacitor 4020 includes an electrode 4021 formed in the same process as the gate electrode of the transistor 4010, and an electrode formed in the same process as the source and drain electrodes. Each electrode overlaps with the others separated by an insulating layer 4103.

[0231] Generally, the capacitance of the capacitor installed in the pixel section of the display device is set considering factors such as the leakage current of the transistors arranged in the pixel section, so that it can maintain its charge for a specified period. The capacitance can be set considering factors such as the off-state current of the transistors.

[0232] The transistor 4010 disposed in the display unit 215 is electrically connected to the display element. Figure 18A This is an example of a liquid crystal display device that uses liquid crystal elements as display components. Figure 18A In this design, the liquid crystal element 4013, serving as a display element, includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. Note that insulating layers 4032 and 4033, used as alignment films, are disposed to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is disposed on one side of the second substrate 4006, and the first electrode layer 4030 and the second electrode layer 4031 overlap with the liquid crystal layer 4008.

[0233] The spacer 4035 is a columnar spacer obtained by selectively etching the insulating layer, and it is provided to control the spacing (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. Note that spherical spacers can also be used.

[0234] Furthermore, optical components (optical substrates) such as a black matrix (light-shielding layer), a color layer (color filter), polarizing components, phase difference components, and anti-reflection components can be appropriately provided as needed. For example, circular polarization utilizing polarizing substrates and phase difference substrates can also be used. Additionally, backlighting or sidelighting can be used as the light source. Micro-LEDs can also be used as the aforementioned backlighting or sidelighting.

[0235] exist Figure 18A In the display device shown, a light-shielding layer 4132, a coloring layer 4131 and an insulating layer 4133 are disposed between the second substrate 4006 and the second electrode layer 4031.

[0236] Examples of materials suitable for use in the light-shielding layer include carbon black, titanium black, metals, metal oxides, or composite oxides comprising solid solutions of multiple metal oxides. The light-shielding layer can also be a film containing a resin material or a thin film containing inorganic materials such as metals. Alternatively, a laminated film containing a material with a coloring layer can be used for the light-shielding layer. For example, a laminated structure can be used consisting of a film containing a material with a coloring layer for transmitting a certain color of light and a film containing a material with a coloring layer for transmitting other colors of light. By using the same material for the coloring layer and the light-shielding layer, the process can be simplified, allowing the use of the same equipment, which is therefore preferable.

[0237] Examples of materials that can be used for the coloring layer include metallic materials, resin materials, and resin materials containing pigments or dyes. The methods for forming the light-shielding layer and the coloring layer are the same as those for forming the aforementioned layers. For example, inkjet printing can also be used.

[0238] in addition, Figure 18A and Figure 18B The display device shown includes an insulating layer 4111 and an insulating layer 4104. The insulating layers 4111 and 4104 are designed to prevent impurities from permeating. By sandwiching the semiconductor layer of the transistor between the insulating layers 4111 and 4104, the ingress of external impurities can be prevented.

[0239] Furthermore, as a display element included in a display device, a light-emitting element (also known as an EL element) utilizing electroluminescence can be applied. An EL element has a layer containing a light-emitting compound (also known as an "EL layer") between a pair of electrodes. When a potential difference higher than the threshold voltage of the EL element is created between the pair of electrodes, holes are injected into the EL layer from the anode side, while electrons are injected into the EL layer from the cathode side. The injected electrons and holes recombine in the EL layer, thereby causing the light-emitting material contained in the EL layer to emit light.

[0240] EL elements are distinguished based on whether the light-emitting material is an organic compound or an inorganic compound. The former is usually called an organic EL element, while the latter is called an inorganic EL element.

[0241] In organic light-emitting diode (EL) devices, electrons are injected into the EL layer from one electrode by applying a voltage, while holes are injected into the EL layer from the other electrode. Through the recombination of these charge carriers (electrons and holes), the luminescent organic compound forms an excited state, and emits light when it returns to the ground state from this excited state. Due to this mechanism, such light-emitting devices are called current-excited light-emitting devices (LEDs).

[0242] In addition to light-emitting compounds, the EL layer can also include materials with high hole injection capacity, materials with high hole transport capacity, hole blocking materials, materials with high electron transport capacity, materials with high electron injection capacity, or bipolar materials (materials with high electron and hole transport capacity), etc.

[0243] EL layers can be formed by methods such as vapor deposition (including vacuum vapor deposition), transfer printing, printing, inkjet printing, and coating.

[0244] Inorganic EL devices are classified into dispersed inorganic EL devices and thin-film inorganic EL devices based on their device structure. Dispersed inorganic EL devices include a light-emitting layer in which luminescent material particles are dispersed in a binder, and their light emission mechanism utilizes donor-acceptor recombination luminescence. Thin-film inorganic EL devices have a structure in which the light-emitting layer is sandwiched between dielectric layers, and these dielectric layers are sandwiched between electrodes; their light emission mechanism utilizes localized luminescence from the inner-shell electron transitions of metal ions. Note that organic EL devices are used here as the light-emitting element for explanation.

[0245] To extract light, at least one of the pair of electrodes of the light-emitting element is made transparent. A transistor and a light-emitting element are formed on a substrate. The light-emitting element can be a top-emitting structure that extracts light from a surface opposite to the substrate; a bottom-emitting structure that extracts light from a surface on one side of the substrate; or a double-sided emitting structure that extracts light from both surfaces.

[0246] Figure 18B This is an example of a light-emitting display device (also called an "EL display device") that uses a light-emitting element as a display element. The light-emitting element 4513, which is used as a display element, is electrically connected to a transistor 4010 disposed in the display section 215. Although the light-emitting element 4513 has a stacked structure of a first electrode layer 4030, a light-emitting layer 4511, and a second electrode layer 4031, it is not limited to this structure. The structure of the light-emitting element 4513 can be appropriately modified according to the direction of light extracted from the light-emitting element 4513, etc.

[0247] The partition wall 4510 is formed using organic or inorganic insulating materials. It is particularly preferred to use a photosensitive resin material to form an opening in the first electrode layer 4030, and the side of the opening is formed as an inclined surface with a continuous curvature.

[0248] The light-emitting layer 4511 can be composed of a single layer or a stack of multiple layers.

[0249] The light-emitting element 4513 can emit light in colors such as white, red, green, blue, cyan, magenta, or yellow, depending on the material constituting the light-emitting layer 4511.

[0250] Methods for achieving color display include: a method of combining a white-emitting element 4513 and a coloring layer; and a method of setting a different emitting element 4513 for each pixel. The former method has higher productivity than the latter. On the other hand, in the latter method, an emitting layer 4511 needs to be formed for each pixel, so its productivity is lower than that of the former method. However, the latter method can obtain emitting colors with higher color purity than the former method. By giving the emitting element 4513 a microcavity structure in the latter method, color purity can be further improved.

[0251] The luminescent layer 4511 may also contain inorganic compounds such as quantum dots. For example, by using quantum dots in the luminescent layer, they can also be used as luminescent materials.

[0252] To prevent oxygen, hydrogen, moisture, carbon dioxide, etc., from entering the light-emitting element 4513, a protective layer can be formed on the second electrode layer 4031 and the partition wall 4510. Silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum oxynitride, DLC (diamond-like carbon), etc., can be formed as the protective layer. Furthermore, a filler 4514 is provided and sealed within the space sealed by the first substrate 4001, the second substrate 4006, and the sealant 4005. Thus, to prevent exposure to external gases, it is preferable to use a protective film (adhesive film, UV-curable resin film, etc.) with high hermeticity and low degassing for encapsulation (sealing).

[0253] As filler 4514, in addition to inert gases such as nitrogen or argon, ultraviolet-curing resins or thermosetting resins can also be used, such as PVC (polyvinyl chloride), acrylic resins, polyimide, epoxy resins, silicone resins, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate). Filler 4514 may also contain a desiccant.

[0254] As a sealant 4005, glass materials such as glass powder or two-component mixed resins that cure at room temperature, such as light-curing resins or thermosetting resins, can be used. Sealant 4005 may also contain a desiccant.

[0255] Additionally, depending on the requirements, optical thin films such as polarizers or circular polarizers (including elliptical polarizers), phase retardation plates (λ / 4 plates, λ / 2 plates), and color filters can be appropriately placed on the light-emitting surface of the light-emitting element. Furthermore, anti-reflective films can be placed on the polarizers or circular polarizers. For example, anti-glare treatment can be performed, which reduces reflected glare by utilizing the surface's unevenness to diffuse reflected light.

[0256] By incorporating a microcavity structure into the light-emitting element, it is possible to extract light with high color purity. Furthermore, by combining the microcavity structure with color filters, reflected glare can be prevented, thereby improving image visibility.

[0257] Regarding the first electrode layer and the second electrode layer (also known as the pixel electrode layer, common electrode layer, counter electrode layer, etc.) that apply voltage to the display element, their light transmittance and reflectivity can be selected according to the direction of light extraction, the location of the electrode layer, and the pattern structure of the electrode layer.

[0258] As the first electrode layer 4030 and the second electrode layer 4031, transparent conductive materials such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon oxide can be used.

[0259] Furthermore, the first electrode layer 4030 and the second electrode layer 4031 may be formed from one or more of the following metals: tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), or their alloys or nitrides.

[0260] Furthermore, the first electrode layer 4030 and the second electrode layer 4031 can be formed using a conductive composition containing a conductive polymer (also known as a conductive polymer). As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. Examples include polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers or derivatives thereof composed of two or more of aniline, pyrrole, and thiophene.

[0261] Furthermore, since transistors are easily damaged by static electricity, etc., it is preferable to provide a protection circuit to protect the drive circuit. The protection circuit is preferably constructed using non-linear components.

[0262] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc.

[0263] (Implementation Method 3)

[0264] In this embodiment, an example of a transistor that can be used instead of the transistors shown in the above embodiments will be described with reference to the accompanying drawings.

[0265] One embodiment of the display device of the present invention can be manufactured using transistors of various types, such as bottom-gate transistors or top-gate transistors. Therefore, the semiconductor layer material or transistor structure used can be easily changed to accommodate existing production lines.

[0266] Bottom-gate transistor

[0267] Figure 19A1 A cross-sectional view along the channel length of a channel-protected transistor 810, one of the bottom-gate transistors, is shown. Figure 19A1 In this embodiment, transistor 810 is formed on substrate 771. Furthermore, transistor 810 includes an electrode 746 on substrate 771, separated by an insulating layer 772. Additionally, a semiconductor layer 742 is included on electrode 746, separated by an insulating layer 726. Electrode 746 can be used as a gate electrode. Insulating layer 726 can be used as a gate insulating layer.

[0268] Additionally, an insulating layer 741 is included in the channel formation region of the semiconductor layer 742. Furthermore, electrodes 744a and 744b are included on the insulating layer 726 in contact with a portion of the semiconductor layer 742. Electrode 744a can be used as one of the source electrode and the drain electrode. Electrode 744b can be used as the other of the source electrode and the drain electrode. A portion of electrode 744a and a portion of electrode 744b are formed on the insulating layer 741.

[0269] The insulating layer 741 can be used as a channel protection layer. By providing the insulating layer 741 on the channel formation region, the semiconductor layer 742 can be prevented from being exposed during the formation of electrodes 744a and 744b. This prevents the channel formation region of the semiconductor layer 742 from being etched during the formation of electrodes 744a and 744b. According to one aspect of the present invention, a transistor with excellent electrical characteristics can be realized.

[0270] Additionally, transistor 810 includes an insulating layer 728 on electrodes 744a, 744b and insulating layer 741, and an insulating layer 729 on insulating layer 728.

[0271] When an oxide semiconductor is used in semiconductor layer 742, it is preferable to use a material capable of abstracting oxygen from a portion of semiconductor layer 742 to generate oxygen vacancies in at least the portions of electrodes 744a and 744b that are in contact with semiconductor layer 742. The carrier concentration in the region of semiconductor layer 742 where oxygen vacancies are generated increases, and this region becomes n-type, forming an n-type region (n... + (Layer). Therefore, this region can be used as a source region or a drain region. When an oxide semiconductor is used for the semiconductor layer 742, tungsten, titanium, etc. can be cited as examples of materials that can abstract oxygen from the semiconductor layer 742 to generate oxygen vacancies.

[0272] By forming source and drain regions in semiconductor layer 742, the contact resistance between electrodes 744a and 744b and semiconductor layer 742 can be reduced. Therefore, the electrical characteristics of the transistor, such as field-effect mobility and threshold voltage, can be optimized.

[0273] When a semiconductor such as silicon is used for semiconductor layer 742, it is preferable to provide layers that are used as n-type or p-type semiconductors between semiconductor layer 742 and electrode 744a and between semiconductor layer 742 and electrode 744b. The layers used as n-type or p-type semiconductors can be used as the source region or drain region of a transistor.

[0274] The insulating layer 729 is preferably formed of a material that prevents impurities from diffusing into the transistor from the outside or reduces the diffusion of impurities. Alternatively, the insulating layer 729 may be omitted if necessary.

[0275] Figure 19A2 The transistor 811 shown differs from transistor 810 in that it includes an electrode 723 on the insulating layer 729, which can be used as a back gate electrode. The electrode 723 can be formed using the same material and method as the electrode 746.

[0276] Generally, the back gate electrode is formed using a conductive layer and is positioned such that a channel region of the semiconductor layer is sandwiched between the gate electrode and the back gate electrode. Therefore, the back gate electrode can have the same function as the gate electrode. The potential of the back gate electrode can be the same as the gate electrode, or it can be ground potential (GND potential) or any other potential. Furthermore, the threshold voltage of the transistor can be changed by independently altering the potential of the back gate electrode without being linked to the gate electrode.

[0277] Both electrode 746 and electrode 723 can be used as gate electrodes. Therefore, insulating layers 726, 728, and 729 can all be used as gate insulating layers. Alternatively, electrode 723 can be disposed between insulating layers 728 and 729.

[0278] Note that when one of electrodes 746 and 723 is referred to as the "gate electrode," the other is referred to as the "back gate electrode." For example, in transistor 811, when electrode 723 is referred to as the "gate electrode," electrode 746 is referred to as the "back gate electrode." Additionally, when electrode 723 is used as the "gate electrode," transistor 811 is a type of top-gate transistor. Furthermore, sometimes one of electrodes 746 and 723 is referred to as the "first gate electrode," and sometimes the other is referred to as the "second gate electrode."

[0279] By setting electrodes 746 and 723 with the semiconductor layer 742 in between and setting their potentials to be the same, the area through which charge carriers flow in the semiconductor layer 742 is expanded in the film thickness direction, thus increasing the amount of charge carrier movement. As a result, the on-state current of transistor 811 increases, and the field-effect mobility also increases.

[0280] Therefore, transistor 811 is a transistor with a large on-state current relative to its occupied area. That is, the occupied area of ​​transistor 811 can be reduced relative to the required on-state current. According to one aspect of the invention, the occupied area of ​​the transistor can be reduced. Therefore, according to one aspect of the invention, a highly integrated semiconductor device can be realized.

[0281] Furthermore, since the gate electrode and back gate electrode are formed using conductive layers, they have the function of preventing electric fields generated outside the transistor from affecting the semiconductor layer forming the channel (especially the electric field shielding function against static electricity, etc.). In addition, when the back gate electrode is formed to be larger than the semiconductor layer so as to cover the semiconductor layer with the back gate electrode, the electric field shielding function can be improved.

[0282] Furthermore, by using a conductive film with light-shielding properties to form the back gate electrode, light can be prevented from entering the semiconductor layer from the back gate electrode side. This prevents light degradation of the semiconductor layer and degradation of electrical characteristics such as threshold voltage drift in the transistor.

[0283] According to one aspect of the present invention, a transistor with high reliability can be realized. Furthermore, a semiconductor device with high reliability can be realized.

[0284] Figure 19B1 Showing with Figure 19A1 A cross-sectional view along the channel length of a channel-protected transistor 820 with a different structure. Transistor 820 has a structure substantially the same as transistor 810, except that insulating layer 741 covers the end of semiconductor layer 742. In an opening formed by selectively removing portions of insulating layer 741 overlapping semiconductor layer 742, semiconductor layer 742 is electrically connected to electrode 744a. Additionally, in other openings formed by selectively removing portions of insulating layer 741 overlapping semiconductor layer 742, semiconductor layer 742 is electrically connected to electrode 744b. The region of insulating layer 741 overlapping the channel formation region can be used as a channel protection layer.

[0285] Figure 19B2 The transistor 821 shown differs from the transistor 820 in that it includes an electrode 723 on the insulating layer 729, which can be used as a back gate electrode.

[0286] By providing the insulating layer 741, the exposure of the semiconductor layer 742 generated during the formation of electrodes 744a and 744b can be prevented. Therefore, the thinning of the semiconductor layer 742 during the formation of electrodes 744a and 744b can be prevented.

[0287] Furthermore, compared to transistors 810 and 811, the distances between electrodes 744a and 746, and between electrodes 744b and 746, are longer in transistors 820 and 821. Therefore, the parasitic capacitance generated between electrodes 744a and 746 can be reduced. Additionally, the parasitic capacitance generated between electrodes 744b and 746 can also be reduced. According to one aspect of the present invention, a transistor with excellent electrical characteristics can be provided.

[0288] Figure 19C1 A cross-sectional view along the channel length of a channel-etched transistor 825, one type of bottom-gate transistor, is shown. In transistor 825, electrodes 744a and 744b are formed without an insulating layer 741. Therefore, a portion of the semiconductor layer 742 exposed during the formation of electrodes 744a and 744b is sometimes etched. On the other hand, since the insulating layer 729 is not provided, the transistor's productivity can be improved.

[0289] Figure 19C2 The difference between transistor 826 and transistor 825 is that transistor 826 has an electrode 723 on insulating layer 729 that can be used as a back gate electrode.

[0290] Figures 20A1 to 20C2 Cross-sectional views of transistors 810, 811, 820, 821, 825, and 826 in the channel width direction are shown.

[0291] exist Figure 20B2 and Figure 20C2 In the structure shown, the gate electrode and the back gate electrode are connected to each other, so that the gate electrode and the back gate electrode have the same potential. In addition, the semiconductor layer 742 is sandwiched between the gate electrode and the back gate electrode.

[0292] In the channel width direction, the lengths of the gate electrode and the back gate electrode are greater than those of the semiconductor layer 742, and the semiconductor layer 742 is sandwiched between insulating layers 726, 741, 728, and 729 and covered by the gate electrode or the back gate electrode.

[0293] By employing this structure, the semiconductor layer 742 included in the transistor can be surrounded by the electric fields of the gate electrode and the back gate electrode.

[0294] The device structure of a transistor, such as transistor 821 or transistor 826, which uses the electric fields of the gate electrode and the back gate electrode to surround the semiconductor layer 742 forming the channel region, can be called a Surrounded channel (S-channel) structure.

[0295] By employing an S-channel structure, an electric field for inducing channel formation can be effectively applied to the semiconductor layer 742 using one or both of the gate and back gate electrodes. This improves the transistor's current drive capability, resulting in higher on-state current characteristics. Furthermore, the increased on-state current allows for transistor miniaturization. Additionally, the S-channel structure enhances the transistor's mechanical strength.

[0296] Top-gate transistor

[0297] Figure 21A1 The illustrated transistor 842 is one of the top-gate transistors. Electrodes 744a and 744b are electrically connected to the semiconductor layer 742 through openings formed in insulating layers 728 and 729.

[0298] Additionally, a portion of the insulating layer 726 that does not overlap with electrode 746 is removed, and impurities 755 are introduced into semiconductor layer 742 using electrode 746 and the remaining insulating layer 726 as a mask. This allows impurity regions to be formed in semiconductor layer 742 in a self-aligned manner. Transistor 842 includes a region where the insulating layer 726 extends beyond the end of electrode 746. The impurity concentration in the region of semiconductor layer 742 where impurities 755 are introduced through insulating layer 726 is lower than in the region where impurities 755 are introduced without insulating layer 726. Lightly doped drain (LDD) regions are formed in the region of semiconductor layer 742 that does not overlap with electrode 746.

[0299] Figure 21A2 The transistor 843 shown differs from transistor 842 in that it includes an electrode 723. Transistor 843 includes an electrode 723 formed on a substrate 771. The electrode 723 is separated from the region where the insulating layer 772 overlaps with the semiconductor layer 742. The electrode 723 can be used as a back gate electrode.

[0300] In addition, such as Figure 21B1 The transistor 844 shown Figure 21B2 As shown in transistor 845, the insulating layer 726 in the area not overlapping with electrode 746 can also be completely removed. Additionally, as... Figure 21C1 The transistor 846 shown and Figure 21C2 As with the transistor 847 shown, the insulating layer 726 can also be left unremoved.

[0301] In transistors 842 to 847, impurities 755 can be introduced into the semiconductor layer 742 after the electrode 746 is formed, using the electrode 746 as a mask, thereby forming impurity regions in the semiconductor layer 742 in a self-aligned manner. According to one aspect of the invention, transistors with excellent electrical characteristics can be realized. Furthermore, according to one aspect of the invention, semiconductor devices with high integration density can be realized.

[0302] Figures 22A1 to 22C2 Cross-sectional views of transistors 842, 843, 844, 845, 846, and 847 in the channel width direction are shown.

[0303] Transistors 843, 845, and 847 have the aforementioned S-channel structure. However, they are not limited to this; transistors 843, 845, and 847 may also not have an S-channel structure.

[0304] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc.

[0305] (Implementation Method 4)

[0306] Examples of electronic devices that can utilize a display device according to one aspect of the present invention include display devices, personal computers, image storage devices and image reproduction devices with recording media, mobile phones, game consoles including portable game consoles, portable data terminals, e-book readers, shooting devices such as video cameras or digital cameras, head-mounted displays, navigation systems, audio reproduction devices (car audio systems, digital audio players, etc.), photocopiers, fax machines, printers, multifunction printers, automatic teller machines (ATMs), and vending machines. Figure 23 shows specific examples of these electronic devices.

[0307] Figure 23A It is a digital camera, which includes a frame 961, a shutter button 962, a microphone 963, a speaker 967, a display unit 965, operation keys 966, a zoom button 968, a lens 969, etc. By using the display device of one aspect of the present invention in the display unit 965, various images can be displayed.

[0308] Figure 23B It is a digital signage, which includes a large display unit 922. For example, it can be installed on the side of a pillar 921. By using a display device according to one aspect of the present invention in the display unit 922, a display of high quality can be achieved.

[0309] Figure 23CThis is a mobile phone, which includes a frame 951, a display unit 952, operation buttons 953, an external connection port 954, a speaker 955, a microphone 956, a camera 957, etc. The mobile phone includes a touch sensor in the display unit 952. All operations, such as making calls or inputting text, can be performed by touching the display unit 952 with a finger or stylus. Furthermore, the frame 901 and the display unit 952 are flexible and can be bent as shown in the figure. By using a display device according to one aspect of the present invention in the display unit 952, various images can be displayed.

[0310] Figure 23D This is a portable data terminal, which includes a housing 911, a display unit 912, a speaker 913, a camera 919, etc. Data can be input or output using the touch panel function of the display unit 912. By using a display device according to one aspect of the present invention in the display unit 912, various images can be displayed.

[0311] Figure 23E It is a television set, which includes a frame 971, a display unit 973, operation keys 974, a speaker 975, a communication connection terminal 976, and a photoelectric sensor 977, etc. The display unit 973 is equipped with a touch sensor, which allows for input operations. By using a display device according to one aspect of the present invention in the display unit 973, various images can be displayed.

[0312] Figure 23F This is an information processing terminal, which includes a frame 901, a display unit 902, a display unit 903, and a sensor 904. Display units 902 and 903 are composed of a single display panel and are flexible. Furthermore, the frame 901 is also flexible, allowing the information processing terminal to be folded for use as shown in the attached figures, and enabling it to be used in a flat, tablet-like form. The sensor 904 can detect the shape of the frame 901; for example, when the frame is bent, the display of display units 902 and 903 can be switched. By using a display device according to one aspect of the present invention for display units 902 and 903, various images can be displayed.

[0313] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc.

[0314] [Symbol Explanation]

[0315] 10: Pixel, 10B: Subpixel, 10G: Subpixel, 10R: Subpixel, 11: Pixel matrix, 12: Row driver, 13: Row driver, 14: Column driver, 15: Column driver, 16: Circuit, 17: Select circuit, 18: Select circuit, 19: Select circuit, 20: Shift register, 21: Buffer circuit, 22: Shift register, 23: Select circuit, 25B: Electrode, 25G: Electrode, 25R: Electrode, 101: Transistor, 102: Transistor, 103: Capacitor, 110: Circuit block, 111: Transistor, 112: Transistor, 113: Capacitor, 114: EL element, 115: Transistor, 116: Capacitor, 117: Liquid crystal element, 1 18: Transistor, 119: Transistor, 120: Circuit, 121: Wiring, 122: Wiring, 124: Wiring, 125: Wiring, 126: Wiring, 128: Wiring, 129: Wiring, 130: Wiring, 131: Wiring, 132: Wiring, 133: Wiring, 134: Wiring, 215: Display section, 221a: Scan line drive circuit, 231a: Signal line drive circuit, 232a: Signal line drive circuit, 241a: Common line drive circuit, 723: Electrode, 726: Insulating layer, 728: Insulating layer, 729: Insulating layer, 741: Insulating layer, 742: Semiconductor layer, 744a: Electrode, 744b: Electrode, 746: Electrode, 755: Impurity, 771: Substrate Bottom, 772: Insulating layer, 810: Transistor, 811: Transistor, 820: Transistor, 821: Transistor, 825: Transistor, 826: Transistor, 830: Transistor, 840: Transistor, 842: Transistor, 843: Transistor, 844: Transistor, 845: Transistor, 846: Transistor, 847: Transistor, 901: Frame, 902: Display unit, 903: Display unit, 904: Sensor, 911: Frame, 912: Display unit, 913: Speaker, 919: Camera, 921: Column, 922: Display unit, 951: Frame, 952: Display unit, 953: Operation button, 954: External connection port, 955: Speaker, 956: Microphone 957: Camera; 961: Frame; 962: Shutter button; 963: Microphone; 965: Display; 966: Operation keys; 967: Speaker; 968: Zoom button; 969: Lens; 971: Frame; 973: Display; 974: Operation keys; 975: Speaker; 976: Communication connection terminal; 977: Light sensor; 4001: Substrate; 4005: Sealant; 4006: Substrate; 4008: Liquid crystal layer; 4010: Transistor; 4011: Transistor; 4013: Liquid crystal element; 4014: Wiring; 4015: Electrode; 4017: Electrode; 4018: FPC; 4019: Anisotropic conductive layer; 4020: Capacitor; 4021: Electrode.4030: Electrode layer, 4031: Electrode layer, 4032: Insulating layer, 4033: Insulating layer, 4035: Spacer, 4041: Printed circuit board, 4042: Integrated circuit, 4102: Insulating layer, 4103: Insulating layer, 4104: Insulating layer, 4110: Insulating layer, 4111: Insulating layer, 4112: Insulating layer, 4131: Coloring layer, 4132: Light-shielding layer, 4133: Insulating layer, 4200: Input device, 4210: Touch panel, 4227: Electrode, 4228: Electrode, 4237: Wiring, 4238: Wiring, 4239: Wiring, 4263: Substrate, 4272b: FPC, 4273b: IC, 4510: Spacer, 4511: Light-emitting layer, 4513: Light-emitting element, 4514: Filler material.

Claims

1. A display device comprising: a first transistor; a first circuit, a second circuit, and a third circuit; and a first wiring, a second wiring, and a third wiring, wherein each of the first circuit, the second circuit, and the third circuit includes a second transistor, a capacitor, and a display element, one of a source and a drain of the second transistor is electrically connected to one electrode of the capacitor, the one electrode of the capacitor is electrically connected to the display element, the first wiring is electrically connected to the other of the source and the drain of the second transistor in the second circuit, the second wiring is electrically connected to the other of the source and the drain of the second transistor in the third circuit, the third wiring is electrically connected to one of a source and a drain of the first transistor, correction data is configured to be supplied to the third wiring, and the other of the source and the drain of the first transistor is electrically connected to the other electrode of the capacitor in any of the first circuit, the second circuit, and the third circuit.

2. A display device comprising: a first transistor; a first circuit, a second circuit, and a third circuit; and a first wiring, a second wiring, and a third wiring, wherein each of the first circuit, the second circuit, and the third circuit includes a second transistor, a capacitor, and a display element, one of a source and a drain of the second transistor is electrically connected to one electrode of the capacitor, the one electrode of the capacitor is electrically connected to the display element, the first circuit, the second circuit, and the third circuit are adjacently arranged in one direction, the first wiring is electrically connected to the other of the source and the drain of the second transistor in the second circuit, the second wiring is electrically connected to the other of the source and the drain of the second transistor in the third circuit, the third wiring is electrically connected to one of a source and a drain of the first transistor, correction data is configured to be supplied to the third wiring, and the other of the source and the drain of the first transistor is electrically connected to the other electrode of the capacitor in any of the first circuit, the second circuit, and the third circuit.

3. The display device according to claim 1 or 2, wherein the first circuit, the second circuit, and the third circuit have a function of emitting light of different colors from each other.

4. An electronic device comprising the display device according to claim 1 or 2 and a camera.

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