A 2-bit adc circuit based on pulse neuron circuit

Abstract

The application claims a kind of 2-bit ADC circuit based on pulse neuron circuit, belongs to the field of integrated circuit design.The circuit uses the proposed pulse neuron circuit to design a simple digital pulse neural network circuit, for realizing 2-bit ADC circuit.When input voltage signal is 0-0.3V, 0.3-0.6V, 0.6-0.9V, 0.9-1.2V respectively, it corresponds to four neuron output pulse signal, then according to the pulse signal of output neuron output coding.Due to the different pulse frequency of neuron circuit produced by different input voltage signal, so the circuit only uses neuron circuit, and does not need synapse circuit.Each neuron circuit in the pulse neural network has a fixed threshold, compared with traditional Flash ADC circuit, it does not need multiple reference voltage, avoids the precision deviation problem caused by multiple reference voltage of comparator, and the implementation of 2-bit ADC circuit also lays the foundation for realizing high-precision ADC circuit by using neural network.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, and in particular relates to a method for implementing a 2-bit ADC circuit based on a spiking neuron circuit. Background Technology

[0002] An ADC, or Analog-to-Digital Converter, is used to convert analog signals into digital signals. The conversion from analog to digital signals generally involves four steps: sampling, holding, quantization, and encoding. Sampling and holding are implemented using a sample-and-hold circuit, while quantization and encoding are implemented using the ADC circuit. Therefore, an ADC is a converter that converts an analog quantity, after comparison with a standard quantity, into a discrete signal represented in binary. Traditional Flash ADC circuits typically use multiple comparators to compare the input voltage with a reference voltage. If the input voltage is less than the reference voltage, the comparator outputs logic "0"; if the input voltage is greater than the reference voltage, the comparator outputs logic "1". The logic outputs of the comparators are then encoded. In a Flash ADC, each comparator needs to obtain a reference voltage from a resistor string. Each reference voltage must be 1 LSB greater than the next reference voltage in the string. Therefore, for multiple reference voltages, the accuracy of the comparators is particularly important, requiring additional circuitry to improve comparator accuracy.

[0003] This invention provides a method for implementing a 2-bit ADC circuit based on a spiking neuron circuit, aiming to achieve a 2-bit ADC circuit using a novel approach. The invention utilizes a neuron circuit to design a simple digital spiking neural network circuit, which can classify input signals. When the input voltage signals are 0-0.3V, 0.3-0.6V, 0.6-0.9V, and 0.9-1.2V respectively, due to the parallel processing relationship between the input neurons, the neurons quickly determine the category of the input voltage and output pulse signals corresponding to the four neurons. The output neurons then encode the signals based on their pulse signals. Since the pulse frequencies generated by the neuron circuits differ depending on the input voltage signal, this circuit only uses neuron circuits and does not require synaptic circuits. The threshold of each neuron circuit is fixed, eliminating the need for multiple reference voltages compared to traditional Flash ADC circuits, thus avoiding the accuracy deviation problem caused by comparators using multiple reference voltages. Furthermore, the implementation of the 2-bit ADC circuit lays the foundation for using neural networks to achieve high-precision ADC circuits. Summary of the Invention

[0004] This invention aims to solve the problems of the prior art mentioned above. It proposes a 2-bit ADC circuit based on a spiking neuron circuit. The technical solution of this invention is as follows:

[0005] A 2-bit ADC circuit based on spiking neuron circuits includes: a group of spiking neurons, a group of monostable multivibrators (MSFs), and combinational logic circuits. The spiking neuron group converts the input voltage into a corresponding pulse sequence and classifies it; the MSFs convert the pulse sequences classified by the spiking neuron group into logic signals; and the combinational logic circuits encode the logic signals output by the MSFs to obtain the final classification result. The spiking neuron group includes four spiking neuron circuits, whose input terminals are connected to a common input voltage V. IN The monostable multivibrator group includes four repeatable trigger monostable multivibrators. The clock terminals of the four repeatable trigger monostable multivibrators are connected to the output terminals of each spiking neuron circuit, and the input signal terminals D of the four repeatable trigger monostable multivibrators are all connected to logic "1". The combinational logic circuit performs binary encoding on the signal output by the repeatable trigger monostable multivibrator group, outputting a 2-bit binary signal AB, where A is the high bit and B is the low bit.

[0006] Furthermore, the spiking neuron circuit in the spiking neuron group includes five modules: an input module, a leakage module, a state judgment module, a reset module, and a refractory period module. The input module is used to receive signals; the leakage module is used to accumulate the membrane potential according to the signal type received by the input module and to slowly leak the membrane potential in accordance with the characteristics of biological neurons; the state judgment circuit is used to compare the membrane potential in the leakage module with a fixed threshold voltage, and outputs a pulse signal once it determines that the membrane potential exceeds the threshold voltage; when the state judgment module outputs a pulse signal, the refractory period module also receives the pulse signal and generates a reset signal for a period of time, which activates the reset module; after the reset module is activated, it acts on the leakage module, causing the membrane potential to reset and cutting off the connection between the leakage module and the input module. The reset module is only disabled when the reset signal ends, and the leakage module and the input module are reconnected to enter the next processing of the input signal.

[0007] Furthermore, the input module in the spiking neuron circuit includes an excitatory input circuit and an inhibitory input circuit. The excitatory input circuit consists of an NMOS transistor M1 and a current mirror composed of PMOS transistors M2 and M3. The inhibitory input circuit consists of a PMOS transistor M4 and a current mirror composed of NMOS transistors M5 and M6. The NMOS transistor M1 receives excitatory signals from multiple other neurons, and the PMOS transistor M4 receives inhibitory signals from multiple other neurons. The input signals are then converted into current signals by the current mirror and transmitted to the leakage circuit, thereby causing a change in the membrane voltage.

[0008] The leakage module circuit uses an NMOS transistor M9 and a capacitor C. memIn parallel connection, NMOS transistor M9 simulates the leakage conductance in biological neurons, used to represent the leakage current in the LIF model; capacitor C mem This is used to represent the change in the voltage difference across the cell membrane, indicating the membrane capacitance in the LIF model. The leakage module receives the current signal from the input module. If the signal received by the input module is an excitatory signal, then the membrane capacitance C... mem The membrane potential V represented by the two ends mem Increase; if the signal received by the input module is an inhibitory signal, then the membrane capacitance C mem The membrane potential V represented by the two ends mem This will reduce; in addition, the leakage module circuit has two functions—when there is a signal input, capacitor C mem Membrane potential V at both ends mem It stores the input signal, and the value increases or decreases with the input signal; when there is no signal input, the stored membrane voltage V... mem The signal will slowly leak through NMOS transistor M9, until the resting potential or the arrival of the next signal. This leakage can be controlled by adjusting the gate bias voltage V of NMOS transistor M9. leak The membrane potential V can be adjusted. mem The leakage rate;

[0009] The state determination module consists of a comparator and an output buffer, used to compare the membrane voltage V. mem and threshold voltage, once the membrane voltage V mem Exceeding the threshold voltage V th The comparator then outputs a high-level signal to the output buffer, due to the random membrane potential V. mem The comparator is quickly reset, so it immediately outputs a low-level signal. The output buffer shapes the signal output by the comparator into a standard pulse signal and transmits it to the synaptic circuit. That is, the neuron circuit generates an action potential, outputs it to the synapse, and transmits it to the next neuron through the synaptic circuit.

[0010] The refractory period module consists of inverters INV1 and INV3 and an NMOS transistor M10. When the comparator outputs a high-level signal to inverter INV1, i.e., the membrane voltage V of the neuron circuit... mem When the threshold voltage is reached and a pulse signal is generated, inverter INV3 receives the signal and outputs a high level. This high level signal is then slowly attenuated by NMOS transistor M10, and this signal serves as the reset signal V. rst The output is given to the reset circuit to realize the reset and refractory period characteristics of the neuron circuit. The reset signal V rst The duration of the high-level signal can be controlled by the gate bias voltage of transistor M10;

[0011] The reset module consists of transistors M7 and M8. When the reset signal is low, PMOS transistor M7 is turned on and NMOS transistor M8 is turned off, allowing the leakage module circuit to receive current signals from the input module circuit, meaning the neuron circuit can receive external signals. When the reset signal is high, PMOS transistor M7 is turned off and NMOS transistor M8 is turned on, preventing the leakage circuit from receiving current signals from the input circuit, and its accumulated membrane voltage signal V... mem It will be reset to the resting potential via NMOS transistor M8. While the reset signal is maintained at a high level, the membrane voltage V mem It will remain at the resting potential. During this period, the neuronal circuit does not receive any input. This is called the refractory period of the neuronal circuit.

[0012] Furthermore, the retrievable monostable multivibrator in the monostable multivibrator group includes: a sustain-block D flip-flop, a resistor R, a capacitor C, an NMOS transistor M1, and an inverter. The output Q of the sustain-block D flip-flop is connected to one end of the resistor R, and the other end of the resistor R is connected to one end of the capacitor C, the input of the inverter, and the drain of the NMOS transistor M1. The capacitor C is connected in parallel with the NMOS transistor M1, and the other end of the capacitor C is connected to the gate of the NMOS transistor M1 and grounded. The gate of the NMOS transistor M1 is connected to the clock input CLK of the sustain-block D flip-flop. The output of the inverter is connected to the direct asynchronous reset input of the sustain-block D flip-flop. Connected. Maintain-block D flip-flop's direct asynchronous set input. Connect to logic "1".

[0013] Furthermore, the outputs of the four retrieval-triggered monostable multivibrators are Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q18, Q19, Q19, Q19, Q10 ...0, Q2 Q3 Q4 The combinational logic circuit performs binary encoding on the signal output by the repeatable triggerable monostable multivibrator group, and represents the classification result of the spiking neuron group as four cases in binary encoding, corresponding to four voltage segments respectively.

[0014] Furthermore, by setting the inhibitory input signal of the neuron circuit, the lower limit of the input voltage value that each neuron can accept can be set. That is, neuron 1 responds to an input voltage of 0-1.2V, neuron 2 only responds to an input voltage of 0.3-1.2V, neuron 3 only responds to an input voltage of 0.6-1.2V, and neuron 4 only responds to an input voltage of 0.9-1.2V. In other words, when the input voltage is in the range of 0-0.3V, only neuron 1 outputs a pulse sequence; when the input voltage is in the range of 0.3-0.6V, only neuron 1 and neuron 2 output pulse sequences; when the input voltage is in the range of 0.6-0.9V, neuron 1, neuron 2, and neuron 3 output pulse sequences; and when the input voltage is in the range of 0.9-1.2V, all four neurons output pulse sequences.

[0015] Furthermore, the repeatable triggerable monostable multivibrator converts the pulse sequence output by the neuron into a digital level signal. That is, the pulse sequence within a certain interval is converted into a high level "1", and when there is no pulse output, it is converted into a low level "0". When there is no input signal to trigger, the circuit is in a steady state; when triggered by a pulse signal, the circuit state is converted into a metastable state. During the metastable state timing time, if a new trigger pulse is input, the circuit will be re-triggered by the new input pulse. After the neuron outputs a pulse sequence, the repeatable triggerable monostable multivibrator converts the pulse sequence into a logic signal for further encoding.

[0016] Furthermore, when the input voltage is in the range of 0-0.3V, the output Q4Q3Q2Q1 = 0001 can be repeatedly triggered; when the input voltage is in the range of 0.3-0.6V, the output Q4Q3Q2Q1 = 0011 can be repeatedly triggered; when the input voltage is in the range of 0.6-0.9V, the output Q4Q3Q2Q1 = 0111 can be repeatedly triggered; when the input voltage is in the range of 0.9-1.2V, the output Q4Q3Q2Q1 = 1111 can be repeatedly triggered; and when there is no signal input, the output Q4Q3Q2Q1 = 0000 can be repeatedly triggered.

[0017] Furthermore, the sustain-block D flip-flop inside the retrievable monostable multivibrator circuit utilizes the DC feedback principle to achieve edge triggering. Sustaining means that when the input changes during the CLK period, the gate that should be opened remains open, thereby completing the predetermined operation. Blocking means that when the input changes during the CLK period, the gate that should not be opened remains closed, thereby preventing the occurrence of an undesirable operation. Due to the sustain-blocking effect, the D flip-flop only undergoes a state transition at the rising edge of the CLK signal from 0 to 1, while the flip-flop state remains unchanged at other times. That is, the sustain-block D flip-flop is triggered by the rising edge of the clock CLK, has the function of an edge-triggered flip-flop, and effectively prevents a rollover.

[0018] Furthermore, the combinational logic circuit encodes the outputs Q4Q3Q2Q1 of the retrieval-triggered monostable multivibrator group, outputting a two-bit binary encoded signal AB, where A is the high-order bit and B is the low-order bit, which can be represented as follows: When the input voltage is in the range of 0-0.3V, the combinational logic output AB = 00; when the input voltage is in the range of 0.3-0.6V, the combinational logic output AB = 01; when the input voltage is in the range of 0.6-0.9V, the combinational logic output AB = 10; when the input voltage is in the range of 0.9-1.2V, the combinational logic output AB = 11; when there is no signal input, the combinational logic output AB = 00.

[0019] The advantages and beneficial effects of this invention are as follows:

[0020] This invention provides a 2-bit ADC circuit based on a spiking neuron circuit. A simple digital spiking neural network circuit is designed using this spiking neuron circuit. Since the output signal of the spiking neuron circuit is a pulse sequence, and the frequency of the output pulse sequence changes according to the input voltage, the spiking neuron circuit can be used to classify the input voltage, and its output pulse sequence can be used for encoding. Therefore, the designed spiking neural network can classify input signals. When the input voltage signals are 0-0.3V, 0.3-0.6V, 0.6-0.9V, and 0.9-1.2V respectively, due to the parallel processing relationship between the input neurons, the neurons will quickly determine the category to which the input voltage belongs, corresponding to four neurons outputting pulse signals. The threshold of each neuron circuit is fixed. Compared with traditional Flash ADC circuits, multiple reference voltages are not required, avoiding the accuracy deviation problem caused by comparators using multiple reference voltages. Since the neuron circuit continuously outputs a pulse sequence when activated, it needs to be converted into a digital level signal to facilitate encoding of the pulse sequence output by the neuron circuit. Therefore, this invention designs a repeatable triggerable monostable multivibrator connected to the output of each neuron circuit. The pulse sequence output by the neuron serves as the clock input to the trigger, converting pulse sequences within a certain interval into a high level "1" and a low level "0" when no pulse is output. In other words, after the neuron outputs a pulse sequence, the repeatable triggerable monostable multivibrator converts the pulse sequence into a logic signal for further encoding. The repeatable triggerable monostable multivibrator does not use a retriggered integrated monostable multivibrator, but instead utilizes a hold-block D flip-flop, resistors, capacitors, transistors, and inverters to design a simple repeatable triggerable monostable multivibrator. Combinational logic circuits are used to encode the output Q4Q3Q2Q1 of the repeatable triggerable monostable multivibrator, resulting in a two-bit binary encoded signal AB, where A is the high-order bit and B is the low-order bit, corresponding to the four categories of input voltage. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a 2-bit ADC circuit based on a spiking neuron circuit, according to a preferred embodiment of the present invention.

[0022] Figure 2 A schematic diagram of the spiking neuron circuit in a 2-bit ADC circuit that provides a preferred embodiment of the present invention;

[0023] Figure 3 A schematic diagram of a repeatable monostable multivibrator circuit in a 2-bit ADC circuit that provides a preferred embodiment of the present invention;

[0024] Figure 4A circuit diagram of the sustain-block D flip-flop inside the retrievable monostable multivibrator in a 2-bit ADC circuit that provides a preferred embodiment of the present invention;

[0025] Figure 5 A schematic diagram of the test circuit for a preferred embodiment of the 2-bit ADC circuit of the present invention;

[0026] Figure 6 A schematic diagram of the simulation results of the test circuit of the 2-bit ADC circuit that provides a preferred embodiment of the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and thoroughly described below with reference to the accompanying drawings. The described embodiments are merely some embodiments of the present invention.

[0028] The technical solution of the present invention to solve the above-mentioned technical problems is:

[0029] This application presents a novel method for implementing a 2-bit ADC circuit based on a spiking neuron circuit. A simple digital spiking neural network (DSP) circuit is designed using neuron circuits to classify input signals. When the input voltage signals are 0-0.3V, 0.3-0.6V, 0.6-0.9V, and 0.9-1.2V respectively, due to the parallel processing of signals between the input neurons, the neurons quickly determine the category of the input voltage and output pulse signals corresponding to the four neurons. The output neurons then encode the signals based on their pulse signals. Since the pulse frequencies generated by the neuron circuits differ depending on the input voltage signal, this circuit only uses neuron circuits and does not require synaptic circuits. Each neuron circuit has a fixed threshold, eliminating the need for multiple reference voltages compared to traditional Flash ADC circuits. This avoids the accuracy deviation problem caused by comparators using multiple reference voltages, and the implementation of the 2-bit ADC circuit lays the foundation for implementing high-precision ADC circuits using neural networks.

[0030] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0031] Example

[0032] like Figure 1As shown, a 2-bit ADC circuit based on spiking neuron circuits includes: a group of spiking neurons, a group of monostable multivibrators, and a combinational logic circuit. The spiking neuron group is used to convert the input voltage into a corresponding pulse sequence and classify it; the monostable multivibrator group is used to convert the pulse sequence classified by the spiking neuron group into a logic signal; the combinational logic circuit is used to encode the logic signal output by the monostable multivibrator group to obtain the final classification result. The spiking neuron group includes four spiking neuron circuits, and the input terminals of the four neuron circuits are connected to a common input V. IN The monostable multivibrator (MFL) group comprises four retrieval-triggered MFLs. The clock terminals of the four MFLs are connected to the output terminals of each spiking neuron circuit, and the input signal terminals D of the four MFLs are all connected to logic "1". The combinational logic circuit performs binary encoding on the signal output by the MFL group, outputting a 2-bit binary signal AB, where A is the high-order bit and B is the low-order bit.

[0033] Preferably, the combinational logic circuit encodes the outputs Q4Q3Q2Q1 of the repeatable triggerable monostable multivibrator group, outputting a two-bit binary encoded signal AB, where A is the high-order bit and B is the low-order bit, which can be represented as follows: When the input voltage is in the range of 0-0.3V, the combinational logic output AB = 00; when the input voltage is in the range of 0.3-0.6V, the combinational logic output AB = 01; when the input voltage is in the range of 0.6-0.9V, the combinational logic output AB = 10; when the input voltage is in the range of 0.9-1.2V, the combinational logic output AB = 11; when there is no signal input, the combinational logic output AB = 00.

[0034] Figure 2 The diagram shows a spiking neuron circuit used in a 2-bit ADC circuit, comprising five modules: an input module, a leakage module, a state judgment module, a reset module, and a refractory period module. The input module receives signals; the leakage module accumulates the membrane potential based on the signal type received by the input module and slowly leaks the membrane potential, simulating the characteristics of a biological neuron; the state judgment circuit continuously compares the membrane potential in the leakage module with a fixed threshold voltage, and outputs a pulse signal once the membrane potential exceeds the threshold voltage; when the state judgment module outputs a pulse signal, the refractory period module also receives the pulse signal and generates a reset signal for a period of time, which activates the reset module; after activation, the reset module acts on the leakage module, resetting the membrane potential and disconnecting the connection between the leakage module and the input module until the reset signal ends, at which point the reset module becomes ineffective, the leakage module and input module reconnect, and the next input signal processing begins.

[0035] Preferably, the input module in the spiking neuron circuit includes an excitatory input circuit and an inhibitory input circuit. The excitatory input circuit consists of an NMOS transistor M1 and a current mirror composed of PMOS transistors M2 and M3. The inhibitory input circuit consists of a PMOS transistor M4 and a current mirror composed of NMOS transistors M5 and M6. The NMOS transistor M1 receives excitatory signals from multiple other neurons, and the PMOS transistor M4 receives inhibitory signals from multiple other neurons. The input signals are then converted into current signals by the current mirror and transmitted to the leakage circuit, thereby causing a change in the membrane voltage.

[0036] Preferably, the leakage module circuit uses an NMOS transistor M9 and a capacitor C. mem Parallel connection. NMOS transistor M9 simulates the leakage conductance in a biological neuron, used to represent the leakage current in the LIF model; capacitor C... mem This is used to represent the change in the voltage difference across the cell membrane, and represents the membrane capacitance in the LIF model. The leakage module receives the current signal from the input module. If the signal received by the input module is an excitatory signal, then the membrane capacitance C... mem The membrane potential V represented by the two ends mem Increase; if the signal received by the input module is an inhibitory signal, then the membrane capacitance C mem The membrane potential V represented by the two ends mem This will decrease. In addition, the leakage module circuit has two functions—when a signal is input, capacitor C... mem Membrane potential V at both ends mem It stores the input signal, and the value increases or decreases with the input signal; when there is no signal input, the stored membrane voltage V... mem The signal will slowly leak through NMOS transistor M9, until the resting potential or the arrival of the next signal. This leakage can be controlled by adjusting the gate bias voltage V of NMOS transistor M9. leak The membrane potential V can be adjusted. mem The leakage rate.

[0037] Preferably, the state determination module consists of a comparator and an output buffer, used to compare the membrane voltage V. mem and threshold voltage, once the membrane voltage V mem Exceeding the threshold voltage V th The comparator then outputs a high-level signal to the output buffer, due to the random membrane potential V. mem The signal is quickly reset, so the comparator immediately outputs a low-level signal. The output buffer shapes the signal output by the comparator into a standard pulse signal and transmits it to the synaptic circuit. That is, the neuron circuit generates an action potential, outputs it to the synapse, and transmits it to the next neuron through the synaptic circuit.

[0038] Preferably, the refractory period module is composed of inverters INV1 and INV3 and an NMOS transistor M10. When the comparator outputs a high-level signal to inverter INV1, i.e., the membrane voltage V of the neuron circuit... mem When the threshold voltage is reached and a pulse signal is generated, inverter INV3 receives the signal and outputs a high level. This high level signal is then slowly attenuated by NMOS transistor M10, and this signal serves as the reset signal V. rst The output is given to the reset circuit to realize the reset and refractory period characteristics of the neuron circuit. The reset signal V rst The duration of the high-level signal can be controlled by the gate bias voltage of transistor M10.

[0039] Preferably, the reset module is composed of transistors M7 and M8. When the reset signal is a low-level signal, PMOS transistor M7 is turned on and NMOS transistor M8 is turned off, allowing the leakage module circuit to receive current signals from the input module circuit, i.e., the neuron circuit can receive external signals. When the reset signal is a high-level signal, PMOS transistor M7 is turned off and NMOS transistor M8 is turned on, preventing the leakage circuit from receiving current signals from the input circuit, and its accumulated membrane voltage signal V... mem It will be reset to the resting potential via NMOS transistor M8. While the reset signal is maintained at a high level, the membrane voltage V mem It will remain at the resting potential. During this period, the neuronal circuit does not receive any input, which is called the refractory period of the neuronal circuit.

[0040] Preferably, by setting the inhibitory input signal of the neuron circuit, the lower limit of the input voltage value that each neuron can accept can be set. That is, neuron 1 responds to an input voltage of 0-1.2V, neuron 2 responds only to an input voltage of 0.3-1.2V, neuron 3 responds only to an input voltage of 0.6-1.2V, and neuron 4 responds only to an input voltage of 0.9-1.2V. In other words, when the input voltage is in the range of 0-0.3V, only neuron 1 outputs a pulse sequence; when the input voltage is in the range of 0.3-0.6V, only neuron 1 and neuron 2 output pulse sequences; when the input voltage is in the range of 0.6-0.9V, neuron 1, neuron 2, and neuron 3 output pulse sequences; and when the input voltage is in the range of 0.9-1.2V, all four neurons output pulse sequences.

[0041] Figure 3The diagram shows a retrieval-triggered monostable multivibrator (RTM) circuit used in a 2-bit ADC. The RTM in the RTM group includes a sustain-block D flip-flop, a resistor R, a capacitor C, an NMOS transistor M1, and an inverter. The output Q of the sustain-block D flip-flop is connected to one end of the resistor R. The other end of the resistor R is connected to one end of the capacitor C, the input of the inverter, and the drain of the NMOS transistor M1. The capacitor C is connected in parallel with the NMOS transistor M1, and its other end is connected to the gate of the NMOS transistor M1 and grounded. The gate of the NMOS transistor M1 is connected to the clock input CLK of the sustain-block D flip-flop. The output of the inverter is connected to the direct asynchronous reset input of the sustain-block D flip-flop. Connected. Maintain-block D flip-flop's direct asynchronous set input. Connect to logic "1".

[0042] Preferably, the repeatable triggerable monostable multivibrator converts the pulse sequence output by the neuron into a digital level signal, that is, converting the pulse sequence within a certain interval range into a high level "1", and converting it into a low level "0" when there is no pulse output. When there is no input signal to trigger, the circuit is in a steady state; when triggered by a pulse signal, the circuit state changes to a metastable state. During the metastable state timing period, if a new trigger pulse is input, the circuit will be re-triggered by the new input pulse. Therefore, after the neuron outputs a pulse sequence, the repeatable triggerable monostable multivibrator converts the pulse sequence into a logic signal for further encoding. When the input voltage is in the range of 0-0.3V, the output Q4Q3Q2Q1 = 0001 can be repeatedly triggered; when the input voltage is in the range of 0.3-0.6V, the output Q4Q3Q2Q1 = 0011 can be repeatedly triggered; when the input voltage is in the range of 0.6-0.9V, the output Q4Q3Q2Q1 = 0111 can be repeatedly triggered; when the input voltage is in the range of 0.9-1.2V, the output Q4Q3Q2Q1 = 1111 can be repeatedly triggered; when there is no signal input, the output Q4Q3Q2Q1 = 0000 can be repeatedly triggered.

[0043] Figure 4The diagram shows a sustain-block D flip-flop used internally in a retriggerable monostable multivibrator (MSV) circuit of a 2-bit ADC. This sustain-block D flip-flop utilizes DC feedback to achieve edge triggering. "Sustain" means that when the input changes during the CLK period, the gates that should be opened remain open, thus completing the intended operation; "block" means that when the input changes during the CLK period, the gates that should not be opened remain closed, thus preventing unintended operations. Due to the sustain-block function, this D flip-flop only transitions to its state at the rising edge of the CLK signal from 0 to 1, and its state remains unchanged at other times. In other words, this sustain-block D flip-flop is triggered by the rising edge of the clock CLK, possessing the function of an edge-triggered flip-flop while effectively preventing rollover.

[0044] Figure 5 The diagram shows the test circuit for a 2-bit ADC circuit. To further verify the circuit, a simple sample-and-hold circuit, which is a simple switched-capacitor circuit, was added to the input of the 2-bit ADC circuit. A decoding circuit and a simple DAC circuit were added to the output of the 2-bit ADC circuit to reconstruct the signal.

[0045] Figure 6 The image shows the simulation results of a test circuit for a 2-bit ADC. The horizontal axis of the simulation results represents time, and the vertical axis, from top to bottom, represents the input signal, the sampling voltage of the sample-and-hold circuit, and the restored signal V. DAC The circuit consists of a sampling clock for the sample-and-hold circuit, the high-order output signal A of the 2-bit ADC circuit, and the low-order output signal B of the 2-bit ADC circuit. The test circuit was simulated with a sinusoidal AC signal as input, the signal amplitude varying between 200mV and 1.2V, and the clock sampling frequency being 16 times the input signal frequency. As shown in the figure, when the input voltage signal is 0-0.3V, 0.3-0.6V, 0.6-0.9V, and 0.9-1.2V, the output digital signals A and B are 00, 01, 10, and 11, respectively. Circuit performance testing revealed a 1.9-bit bit depth and a SNDR of 13.36dB.

[0046] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0047] The above embodiments should be understood as illustrative only and not as limiting the scope of protection of the present invention. After reading the description of the present invention, those skilled in the art can make various alterations or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A 2-bit ADC circuit based on a spiking neuron circuit, characterized in that, include: The system comprises a spiking neuron group, a monostable multivibrator group, and a combinational logic circuit. The spiking neuron group converts the input voltage into a corresponding pulse sequence and classifies it. The monostable multivibrator group converts the pulse sequence classified by the spiking neuron group into a logic signal. The combinational logic circuit encodes the logic signal output by the monostable multivibrator group to obtain the final classification result. The spiking neuron group includes four spiking neuron circuits, whose input terminals are connected to a common input V. IN The monostable multivibrator group includes four retrieval-triggered monostable multivibrators. The clock terminals of the four retrieval-triggered monostable multivibrators are connected to the output terminals of each spiking neuron circuit, and the input signal terminals D of the four retrieval-triggered monostable multivibrators are all connected to logic "1". The combinational logic circuit performs binary encoding on the signal output by the retrieval-triggered monostable multivibrator group, outputting a 2-bit binary signal AB, where A is the high-order bit and B is the low-order bit. The outputs of the four retrieval monostable multivibrators are Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q1 ...1, Q1, Q1, Q2, Q3, Q4, Q5, Q Q2 Q3 Q4 The combinational logic circuit performs binary encoding on the signal output by the repeatable triggerable monostable multivibrator group, and represents the classification result of the spiking neuron group as four cases in binary encoding, corresponding to four voltage segments respectively. The combinational logic circuit encodes the outputs Q4Q3Q2Q1 of the retrieval-triggered monostable multivibrator group into a two-bit binary encoded signal AB, where A is the high-order bit and B is the low-order bit, which can be represented as follows: When the input voltage is in the range of 0-0.3V, the combinational logic output AB = 00; when the input voltage is in the range of 0.3-0.6V, the combinational logic output AB = 01; when the input voltage is in the range of 0.6-0.9V, the combinational logic output AB = 10; when the input voltage is in the range of 0.9-1.2V, the combinational logic output AB = 11; when there is no signal input, the combinational logic output AB = 00.

2. The 2-bit ADC circuit based on a spiking neuron circuit according to claim 1, characterized in that, The spiking neuron circuit in the spiking neuron group includes five modules: an input module, a leakage module, a state judgment module, a reset module, and a refractory period module. The input module is used to receive signals; the leakage module is used to accumulate the membrane potential according to the type of signal received by the input module and to slowly leak the membrane potential in a manner that simulates the characteristics of biological neurons; the state judgment circuit is used to compare the membrane potential in the leakage module with a fixed threshold voltage, and outputs a pulse signal once it determines that the membrane potential exceeds the threshold voltage. When the state judgment module outputs a pulse signal, the refractory period module also receives the pulse signal and generates a reset signal for a period of time. The reset signal will activate the reset module. After the reset module is activated, it will act on the leakage module, so that the membrane potential is reset and the connection between the leakage module and the input module is cut off. The reset module will not be effective until the reset signal ends. The leakage module and the input module will then be reconnected and enter the next processing of the input signal.

3. A 2-bit ADC circuit based on a spiking neuron circuit according to claim 2, characterized in that, The input module of the spiking neuron circuit includes an excitatory input circuit and an inhibitory input circuit. The excitatory input circuit consists of an NMOS transistor M1 and a current mirror composed of PMOS transistors M2 and M3. The inhibitory input circuit consists of a PMOS transistor M4 and a current mirror composed of NMOS transistors M5 and M6. NMOS transistor M1 receives excitatory signals from multiple other neurons, and PMOS transistor M4 receives inhibitory signals from multiple other neurons. The input signals are then converted into current signals by the current mirror and transmitted to the leakage circuit, thereby causing a change in the membrane voltage. The leakage module circuit uses an NMOS transistor M9 and a capacitor C. mem In parallel connection, NMOS transistor M9 simulates the leakage conductance in a biological neuron, used to represent the leakage current in the LIF model; capacitor C mem This is used to represent the change in the voltage difference across the cell membrane, indicating the membrane capacitance in the LIF model; the leakage module receives the current signal from the input module. If the signal received by the input module is an excitatory signal, then the membrane capacitance C... mem The membrane potential V represented by the two ends mem Increase; if the signal received by the input module is an inhibitory signal, then the membrane capacitance C mem The membrane potential V represented by the two ends mem This will reduce; in addition, the leakage module circuit has two functions—when there is a signal input, capacitor C mem Membrane potential V at both ends mem It stores the input signal, and the value increases or decreases with the input signal; when there is no signal input, the stored membrane voltage V... mem The signal will slowly leak through NMOS transistor M9, until the resting potential or the arrival of the next signal. This leakage can be controlled by adjusting the gate bias voltage V of NMOS transistor M9. leak The membrane potential V can be adjusted. mem The leakage rate; The state determination module consists of a comparator and an output buffer, used to compare the membrane voltage V. mem and threshold voltage, once the membrane voltage V mem Exceeding the threshold voltage V th The comparator then outputs a high-level signal to the output buffer, due to the random membrane potential V. mem The comparator is quickly reset, so it immediately outputs a low-level signal. The output buffer shapes the signal output by the comparator into a standard pulse signal and transmits it to the synaptic circuit. That is, the neuron circuit generates an action potential, outputs it to the synapse, and transmits it to the next neuron through the synaptic circuit. The refractory period module consists of inverters INV1 and INV3 and an NMOS transistor M10. When the comparator outputs a high-level signal to inverter INV1, i.e., the membrane voltage V of the neuron circuit... mem When the threshold voltage is reached and a pulse signal is generated, inverter INV3 receives the signal and outputs a high level. This high level signal is then slowly attenuated by NMOS transistor M10, and this signal serves as the reset signal V. rst The output is given to the reset circuit to realize the reset and refractory period characteristics of the neuron circuit. The reset signal V rst The duration of the high-level signal can be controlled by the gate bias voltage of transistor M10; The reset module consists of transistors M7 and M8. When the reset signal is low, PMOS transistor M7 is turned on and NMOS transistor M8 is turned off, allowing the leakage module circuit to receive current signals from the input module circuit, meaning the neuron circuit can receive external signals. When the reset signal is high, PMOS transistor M7 is turned off and NMOS transistor M8 is turned on, preventing the leakage circuit from receiving current signals from the input circuit, and its accumulated membrane voltage signal V... mem It will be reset to the resting potential via NMOS transistor M8. During the period when the reset signal is maintained at a high level, the membrane voltage V mem It will remain at the resting potential. During this period, the neuronal circuit does not receive any input, which is called the refractory period of the neuronal circuit.

4. A 2-bit ADC circuit based on a spiking neuron circuit according to claim 1, characterized in that, The retrievable monostable multivibrator in the monostable multivibrator group includes: a sustain-block D flip-flop, a resistor R, a capacitor C, an NMOS transistor M1, and an inverter. The output Q of the sustain-block D flip-flop is connected to one end of the resistor R. The other end of the resistor R is connected to one end of the capacitor C, the input of the inverter, and the drain of the NMOS transistor M1. The capacitor C is connected in parallel with the NMOS transistor M1, and the other end of the capacitor C is connected to the gate of the NMOS transistor M1 and grounded. The gate of the NMOS transistor M1 is connected to the clock input CLK of the sustain-block D flip-flop. The output of the inverter is connected to the direct asynchronous reset input of the sustain-block D flip-flop. Connected; the direct asynchronous set input of a hold-block D flip-flop. Connect to logic "1".

5. A 2-bit ADC circuit based on a spiking neuron circuit according to claim 3, characterized in that, By setting the inhibitory input signal of the neuron circuit, the lower limit of the input voltage value that each neuron can accept can be set. That is, neuron 1 responds to an input voltage of 0-1.2V, neuron 2 responds only to an input voltage of 0.3-1.2V, neuron 3 responds only to an input voltage of 0.6-1.2V, and neuron 4 responds only to an input voltage of 0.9-1.2V. In other words, when the input voltage is in the range of 0-0.3V, only neuron 1 outputs a pulse sequence; when the input voltage is in the range of 0.3-0.6V, only neuron 1 and neuron 2 output pulse sequences; when the input voltage is in the range of 0.6-0.9V, neuron 1, neuron 2, and neuron 3 output pulse sequences; and when the input voltage is in the range of 0.9-1.2V, all four neurons output pulse sequences.

6. A 2-bit ADC circuit based on a spiking neuron circuit according to claim 4, characterized in that, A repeatable triggerable monostable multivibrator (RTM) converts the pulse sequence output by a neuron into a digital level signal. Specifically, it converts a pulse sequence within a certain interval range into a high level "1" and a low level "0" when there is no pulse output. When there is no input signal to trigger, the circuit is in a steady state. When triggered by a pulse signal, the circuit state changes to a metastable state. During the metastable state timing period, if a new trigger pulse is input, the circuit will be re-triggered by the new input pulse. After the neuron outputs a pulse sequence, the RTM converts the pulse sequence into a logic signal for further encoding.

7. A 2-bit ADC circuit based on a spiking neuron circuit according to claim 6, characterized in that, When the input voltage is in the range of 0-0.3V, the output Q4Q3Q2Q1 = 0001 can be repeatedly triggered; when the input voltage is in the range of 0.3-0.6V, the output Q4Q3Q2Q1 = 0011 can be repeatedly triggered; when the input voltage is in the range of 0.6-0.9V, the output Q4Q3Q2Q1 = 0111 can be repeatedly triggered; when the input voltage is in the range of 0.9-1.2V, the output Q4Q3Q2Q1 = 1111 can be repeatedly triggered; when there is no signal input, the output Q4Q3Q2Q1 = 0000 can be repeatedly triggered.

8. A 2-bit ADC circuit based on a spiking neuron circuit according to claim 4, characterized in that, The sustain-block D flip-flop inside the retrievable monostable multivibrator circuit uses the DC feedback principle to achieve edge triggering. Sustain means that when the input changes during CLK, the gate that should be opened remains open, thereby completing the predetermined operation; block means that when the input changes during CLK, the gate that should not be opened remains closed, thereby preventing the occurrence of an undesirable operation. Due to the hold-block action, this D flip-flop only undergoes a state transition at the rising edge of the CLK signal when it changes from 0 to 1, while the flip-flop state remains unchanged at other times. That is, this hold-block D flip-flop is triggered by the rising edge of the clock CLK, has the function of an edge-triggered flip-flop, and effectively prevents a rollover.

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