LCD motherboard

Abstract

The present application discloses a liquid crystal display motherboard, which includes two or more sub-display panels. By connecting the data lines and DBS common electrode lines of two adjacent sub-display panels within a plane to achieve signal connection, that is, the data lines and DBS common electrode lines are both connected to the first signal transmission part, the laser routing on the liquid crystal display motherboard can be provided with only one inflection point, thereby greatly saving the tact time of the laser machine and the layout space of the liquid crystal display motherboard.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a liquid crystal display motherboard. Background Art

[0002] Liquid crystal displays (LCDs) have the advantages of being energy-efficient, lightweight, and offering exquisite visuals, and have been widely used in the display technology field. The LCD panel is the core component of LCDs. Currently, LCD panels on the market can be divided into three types: twisted nematic (TN) or super twisted nematic (STN), in-plane switching (IPS), and vertical alignment (VA). The high vertical alignment (HVA) mode is an important offshoot of the VA mode. When operating, HVA-mode LCD panels use a vertical electric field formed by the pixel electrodes on the array substrate and the CFcom to control the rotation of the liquid crystal molecules in the liquid crystal layer.

[0003] like Figure 1 As shown, the structure of the existing liquid crystal display panel is generally composed of an array substrate 11, a color filter substrate 12 (ColorFilter, abbreviated as CF) and a liquid crystal layer (Liquid Crystal Layer, abbreviated as LCL) arranged between the array substrate 11 and the color filter substrate 12. The array substrate has a signal transmission part (curing pad), an array layer, a DBS electrode, a pixel electrode and an array substrate side common electrode (Acom); CFcom and Acom are generally transparent conductive films. The color filter substrate has a CF substrate side common electrode (CFcom) and a color filter (CF). In the periphery of the display area, a seal layer 15 (seal) with conductive gold balls (Au Balls) is generally applied at the signal transmission part (curing pad) to connect CFcom and Acom together. Acom is connected to CFcom through the signal transmission part and the conductive gold balls to transmit the HVA curing signal from the color filter substrate 12 side to the array substrate 11 side through the conductive gold balls.

[0004] like Figure 2As shown, the power supply method using LOC curing requires the use of lasers to partition and insulate the display panel's Acom, DBS electrodes, pixel electrodes, array layer data lines and scan lines, CFcom and other signals, that is, to use laser routing to divide these signals into high-voltage and low-voltage areas. However, in the process of division, since different display panels will have multiple inflection points Q when powering, in fact, too many inflection points of the laser routing will not only increase the machine's cycle time (Tact time), but also increase costs. In addition, the current design of LCD motherboards tends to be extremely precise. Considering the need to reserve a no-go zone for lasers, too many inflection points of the laser routing will affect the layout design of the LCD motherboard. Summary of the Invention

[0005] The object of the present invention is to provide a liquid crystal display motherboard to solve the technical problem that the laser wiring of the liquid crystal display motherboard at the current stage has too many inflection points, which affects its ultimate layout design.

[0006] To achieve the above-mentioned objectives, the present invention provides a liquid crystal display motherboard, which includes more than two sub-display panels, each sub-display panel includes a first signal transmission part and a second signal transmission part, and the first signal transmission part and the second signal transmission part are located in the non-display area of each sub-display panel; each sub-display panel also includes: a first substrate, the first substrate includes a data line and a DBS common electrode line located on the data line, and the data line and the DBS common electrode line are both connected to the first signal transmission part; a second substrate, which is arranged in a box with the first substrate, the second substrate includes a CF common electrode line, and the CF common electrode line is connected to the second signal transmission part; and a conductive component, which is arranged between the first substrate and the second substrate and is located in the non-display area of each sub-display panel, for conducting the first signal transmission part and the second signal transmission part; wherein any two adjacent sub-display panels are defined as a first sub-display panel and a second sub-display panel, and the first signal transmission part of the first sub-display panel is connected to the first signal transmission part of the second sub-display panel through a switching line.

[0007] Furthermore, each sub-display panel includes a first voltage signal area and a second voltage signal area, the first signal transmission portion is disposed in the first voltage signal area, and the second signal transmission portion is disposed in the second voltage signal area.

[0008] Furthermore, the second voltage signal area is manufactured using LOC technology.

[0009] Furthermore, the first substrate includes: a first substrate; a first metal layer, which is arranged on the first substrate, the first metal layer includes a gate and two or more scan lines; a first insulating layer, which covers the first metal layer and extends to the surface of the first substrate; a semiconductor layer, which is arranged on the first insulating layer, and the projection of the semiconductor layer on the first substrate falls within the projection range of the gate on the first substrate; a second metal layer, which is arranged on the semiconductor layer and extends from the semiconductor layer to the surface of the first insulating layer, the second metal layer includes a source, a drain and two or more data lines; a second insulating layer, which is arranged on the second metal layer, and the second insulating layer is provided with a first through hole and a second through hole, the first through hole is used to expose the source, and the second through hole is used to expose the data line; and the adapter line includes a first connecting line, the first connecting line is arranged on the second insulating layer; wherein one end of the first connecting line is connected to the source of the first sub-display panel through the first through hole, and the other end of the first connecting line is connected to the data line of the second sub-display panel through the second through hole.

[0010] Furthermore, the first substrate also includes: a third insulating layer, which is arranged on the first connecting line and extends to the surface of the second insulating layer; a third metal layer, which is arranged on the third insulating layer, the third metal layer includes the DBS common electrode line, and the DBS common electrode line is opposite to the data line; a fourth insulating layer, which is arranged on the third metal layer, and the fourth insulating layer is provided with a third through hole, and the third through hole is used to expose the DBS common electrode line; and the adapter line also includes a second connecting line, and the second connecting line is arranged on the fourth insulating layer; wherein, one end of the second connecting line is connected to the DBS common electrode line of the first sub-display panel through the third through hole, and the other end of the second connecting line is connected to the DBS common electrode line of the second sub-display panel through the third through hole.

[0011] Furthermore, the third metal layer further includes pixel electrode lines, and the pixel electrode lines are provided in the same layer as the DBS common electrode lines.

[0012] Furthermore, a voltage of the first signal transmission part is different from a voltage of the second signal transmission part.

[0013] Furthermore, the liquid crystal display motherboard further includes: a sealant layer disposed between the first substrate and the second substrate, the sealant layer being disposed in a non-display area of each sub-display panel; and the conductive component being disposed in the sealant layer.

[0014] Furthermore, the first substrate is an array substrate, the second substrate is a color filter substrate, and a liquid crystal layer is provided between the array substrate and the color filter substrate.

[0015] Furthermore, the conductive material of the conductive component is a field effect transistor material or a semiconductor material.

[0016] The technical effect of the present invention is to provide a liquid crystal display motherboard, including two or more sub-display panels, by connecting the data lines and DBS common electrode lines of two adjacent sub-display panels within the plane to achieve signal connection, that is, the data lines and DBS common electrode lines are both connected to the first signal transmission part, so that the laser routing on the liquid crystal display motherboard has only one inflection point, thereby greatly saving the tact time of the laser machine and the arrangement space of the liquid crystal display motherboard. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0018] Figure 1 Schematic diagram of the film layer structure of an existing liquid crystal display panel.

[0019] Figure 2 Schematic diagram of using LOC technology to partition and insulate the LCD motherboard.

[0020] Figure 3 A schematic diagram of partitioning and insulating a liquid crystal display motherboard using LOC technology provided in an embodiment of the present application.

[0021] Figure 4 Schematic diagram of the film layer structure of the sub-display panel provided in an embodiment of the present application.

[0022] Figure 5 A schematic diagram of the film layer structure of the array substrate provided in an embodiment of the present application.

[0023] The components of the accompanying drawings are identified as follows:

[0024] 100, LCD motherboard; 101a, first sub-display panel; 101b, second sub-display panel; AA, display area; NA, non-display area; 1, first signal transmission unit; 2, second signal transmission unit; 3, adapter cable; 10, first voltage signal area; 20, second voltage signal area; 30, laser trace; Q, inflection point; 11, first substrate; 12, second substrate; 13, liquid crystal layer; 14, conductive component; 15, sealant layer; 111, first substrate; 112, first metal layer; 113, first insulating layer; 114, semiconductor Conductor layer; 115, second metal layer; 116, second insulating layer; 117, first connecting line; 118, third insulating layer; 119, third metal layer; 120, fourth insulating layer; 121, second connecting line; 112a, gate; 112b, scan line; 115a, source; 115b, drain; 115c, data line; 119a, DBS common electrode line; 119b, pixel electrode line; T1, first through hole; T2, second through hole; T3, third through hole; 121, second substrate; 122, CF common electrode line. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0026] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the described features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0027] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or mutual communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0028] like Figure 3-Figure 5As shown, this embodiment provides a liquid crystal display motherboard 100, which includes two or more sub-display panels, each of which includes a display area AA and a non-display area NA surrounding the display area AA.

[0029] Each sub-display panel includes a first signal transmitting portion 1 and a second signal transmitting portion 2 , and the first signal transmitting portion 1 and the second signal transmitting portion 2 are located in a non-display area NA of each sub-display panel.

[0030] Each sub-display panel further includes a first substrate 11, a second substrate 12, a liquid crystal layer 13, and a conductive component 14. The first substrate 11 is an array substrate, the second substrate 12 is a color filter substrate, and the liquid crystal layer 13 and the conductive component 14 are disposed between the array substrate and the color filter substrate. The liquid crystal layer 13 is located in the display area AA of each sub-display panel, and the conductive component 14 is located in the non-display area NA of each sub-display panel.

[0031] The first substrate 11 includes a data line 115c and a DBS common electrode line 119a located on the data line 115c. Both the data line 115c and the DBS common electrode line 119a are connected to the first signal transmission unit 1. This allows the data line 115c and the DBS common electrode line 119a to achieve signal connection between two adjacent sub-display panels through an in-plane design. Therefore, when LOC technology is used to partition and insulate the LCD motherboard 100, the laser trace 30 on the LCD motherboard 100 can be provided with only one inflection point Q, significantly reducing the tact time of the laser machine and the layout space of the LCD motherboard 100.

[0032] Specifically, the first substrate 11 includes a first substrate 111, a first metal layer 112, a first insulating layer 113, a semiconductor layer 114, a second metal layer 115, a second insulating layer 116, a first connecting line 117, a third insulating layer 118, a third metal layer 119, a fourth insulating layer 120 and a second connecting line 121.

[0033] The first substrate 111 may be a flexible substrate or a rigid substrate, which is not particularly limited herein.

[0034] The first metal layer 112 is disposed on the first substrate 111 . The first metal layer 112 includes a gate 112 a and two or more scan lines 112 b . The two or more scan lines 112 b extend in a lateral direction.

[0035] The first insulating layer 113 covers the first metal layer 112 and extends to the surface of the first substrate 111. The first insulating layer 113 is an insulating layer for the gate 112a and is made of inorganic materials such as silicon nitride and silicon oxide.

[0036] The semiconductor layer 114 is disposed on the first insulating layer 113 , and a projection of the semiconductor layer 114 on the first substrate 111 falls within a projection range of the gate 112 a on the first substrate 111 .

[0037] The second metal layer 115 is disposed on the semiconductor layer 114 and extends from the semiconductor layer 114 to the surface of the first insulating layer 113. The second metal layer 115 includes a source electrode 115a, a drain electrode 115b, and two or more data lines 115c. The two or more data lines 115c extend in a longitudinal direction.

[0038] A second insulating layer 116 is disposed on the second metal layer 115 and defines a first through hole T1 and a second through hole T2. The first through hole T1 is used to expose the source electrode 115a, and the second through hole T2 is used to expose the data line 115c. The second insulating layer 116 may be a passivation layer made of an inorganic material such as silicon nitride or silicon oxide.

[0039] A first connection line 117 is disposed on the second insulating layer 116. One end of the first connection line 117 is connected to the source electrode 115a of the first sub-display panel 101a via the first through-hole T1, and the other end of the first connection line 117 is connected to the data line 115c of the second sub-display panel 101b via the second through-hole T2. The connection point between the first connection line 117 and the source electrode 115a of the first sub-display panel 101a and the connection point between the first connection line 117 and the data line 115c of the second sub-display panel 101b constitutes the first signal transmission portion 1.

[0040] The third insulating layer 118 is disposed on the first connecting line 117 and extends to the surface of the second insulating layer 116. The third insulating layer 118 is made of inorganic materials such as silicon nitride and silicon oxide.

[0041] The third metal layer 119 is disposed on the third insulating layer 118 . The third metal layer 119 includes a pixel electrode line 119 b and a DBS common electrode disposed in the same layer. The DBS common electrode line 119 a is directly opposite to the data line 115 c .

[0042] The fourth insulating layer 120 is disposed on the third metal layer 119 and has a third through hole T3 formed therein. The third through hole T3 is used to expose the DBS common electrode line 119a. The fourth insulating layer 120 is made of inorganic materials such as silicon nitride and silicon oxide.

[0043] A second connection line 121 is disposed on the fourth insulating layer 120. One end of the second connection line 121 is connected to the DBS common electrode line 119a of the first sub-display panel 101a via the third through-hole T3, and the other end of the second connection line 121 is connected to the DBS common electrode line 119a of the second sub-display panel 101b via the third through-hole T3. This allows the data lines 115c of two adjacent sub-display panels to be connected within a plane. Therefore, when LOC technology is used to partition and insulate the liquid crystal display motherboard 100, the laser traces 30 on the liquid crystal display motherboard 100 can be provided with only one inflection point Q, thereby significantly reducing the tact time of the laser machine and the layout space of the liquid crystal display motherboard 100.

[0044] The connection point where the second connection line 121 is connected to the DBS common electrode line 119a of the first sub-display panel 101a and the connection point where the second connection line 121 is connected to the DBS common electrode line 119a of the second sub-display panel 101b are the first signal transmission part 1 .

[0045] It should be noted that, in this embodiment, the voltage of the first signal transmission part 1 connected to the source 115a and the data line 115c is V1, and the voltage of the first signal transmission part 1 connected to the DBS common electrode line 119a is V2, wherein the voltage of V1 may be the same as or different from the voltage of V2, and there is no special limitation here.

[0046] In this embodiment, the adapter line 3 includes the first connecting line 117 and the second connecting line 121. Figure 3 In the embodiment, the orthographic projection of the first connecting line 117 on the first substrate 111 and the orthographic projection of the second connecting line 121 on the first substrate 111 coincide with each other.

[0047] The second substrate 12 is aligned with the first substrate 11 , and the second substrate 12 includes a second underlay 121 and CF common electrode lines 122 .

[0048] The second substrate 121 is a color filter. The CF common electrode line 122 is disposed on the lower surface of the second substrate 121 , and the CF common electrode line 122 is connected to the second signal transmission unit 2 .

[0049] The conductive component 14 is disposed between the first substrate 11 and the second substrate 12 and located in the non-display area NA of each sub-display panel, and is used to conduct electricity between the first signal transmission unit 1 and the second signal transmission unit 2. In this embodiment, the conductive material of the conductive component 14 is a field effect transistor material or a semiconductor material.

[0050] The liquid crystal display motherboard 100 provided in this embodiment further includes a sealant layer 15 , which is disposed between the first substrate 11 and the second substrate 12 . The sealant layer 15 is disposed in the non-display area NA of each sub-display panel; the conductive component 14 is disposed in the sealant layer 15 .

[0051] In this embodiment, when each sub-display panel is in operation, a vertical electric field is formed by the pixel electrode line 119b on the array substrate side and the CF common electrode line 122 on the color filter substrate side to control the rotation of the liquid crystal molecules in the liquid crystal layer 13, and the HVA curing signal is introduced from the color filter substrate side to the array substrate side through the conductive component 14, thereby realizing the display of each sub-display panel.

[0052] Combine Figure 3 As shown, any two adjacent sub-display panels are defined as a first sub-display panel 101a and a second sub-display panel 101b. The first signal transmission unit 1 of the first sub-display panel 101a is connected to the first signal transmission unit 1 of the second sub-display panel 101b via a patch cord 3.

[0053] In this embodiment, the voltage of the first signal transmission unit 1 is different from the voltage of the second signal transmission unit 2. Each sub-display panel includes a first voltage signal area 10 and a second voltage signal area 20. The first signal transmission unit 1 is disposed in the first voltage signal area 10, and the second signal transmission unit 2 is disposed in the second voltage signal area 20. The second voltage signal area 20 is manufactured using LOC technology.

[0054] Further, combined with Figure 3-Figure 5As shown, the first signal transmission part 1 located in the first voltage signal area 10 is a low voltage signal L, and the second signal transmission part 2 located in the second voltage signal area 20 is a high voltage signal H. In this embodiment, signal lines such as the CF common electrode line 122, the pixel electrode line 119b, the data line 115c, the DBS common electrode line 119a, and the scan line 112b are divided into signal zones, wherein the signals connected to the data line 115c and the DBS common electrode line 119a are low voltage signals L, and the signals connected to the other signal lines are high voltage signals H. With such a configuration, when LOC technology is used to partition and insulate the liquid crystal display motherboard 100, it is possible to avoid the inflection points Q of the laser trace 30 being too dense and increasing the cycle time of the laser machine, and it is also possible to avoid problems such as the laser needle being unable to flexibly change direction. This embodiment includes more than two sub-display panels. By connecting the data lines 115c and the DBS common electrode lines 119a of the two adjacent sub-display panels within the plane to achieve signal connection, that is, the data lines 115c and the DBS common electrode lines 119a are both connected to the first signal transmission part 1, the laser trace 30 on the liquid crystal display motherboard 100 can have only one inflection point Q, thereby greatly saving the cycle time (Tact time) of the laser machine and the arrangement space of the liquid crystal display motherboard 100.

[0055] The above is a detailed introduction to a liquid crystal display motherboard provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A liquid crystal display motherboard, characterized in that: It includes two or more sub-display panels, each sub-display panel includes a first signal transmission part and a second signal transmission part, and the first signal transmission part and the second signal transmission part are located in a non-display area of each sub-display panel; Each sub-display panel also includes: a first substrate, the first substrate comprising a data line and a DBS common electrode line located on the data line, wherein the data line and the DBS common electrode line are both connected to the first signal transmission part; a second substrate, which is arranged in a cell-aligned relationship with the first substrate, wherein the second substrate includes a CF common electrode line, and the CF common electrode line is connected to the second signal transmission portion; and a conducting component, disposed between the first substrate and the second substrate and located in a non-display area of each sub-display panel, for conducting between the first signal transmission portion and the second signal transmission portion; Wherein, any two adjacent sub-display panels are defined as a first sub-display panel and a second sub-display panel, and the first signal transmission portion of the first sub-display panel is connected to the first signal transmission portion of the second sub-display panel via a transfer line; Each sub-display panel includes a first voltage signal area and a second voltage signal area. The first signal transmission portion is disposed in the first voltage signal area, and the second signal transmission portion is disposed in the second voltage signal area.

2. The liquid crystal display motherboard according to claim 1, characterized in that: The second voltage signal area is manufactured using LOC technology.

3. The liquid crystal display motherboard according to claim 1, wherein: The first substrate includes: a first substrate; a first metal layer disposed on the first substrate, the first metal layer comprising a gate and two or more scan lines; a first insulating layer covering the first metal layer and extending to the surface of the first substrate; a semiconductor layer, which is disposed on the first insulating layer, and a projection of the semiconductor layer on the first substrate falls within a projection range of the gate on the first substrate; a second metal layer disposed on the semiconductor layer and extending from the semiconductor layer to a surface of the first insulating layer, the second metal layer comprising a source electrode, a drain electrode, and two or more data lines; a second insulating layer disposed on the second metal layer, wherein the second insulating layer is provided with a first through hole and a second through hole, wherein the first through hole is used to expose the source electrode, and the second through hole is used to expose the data line; and The adapter line includes a first connecting line, and the first connecting line is arranged on the second insulating layer; One end of the first connection line is connected to the source electrode of the first sub-display panel through the first through hole, and the other end of the first connection line is connected to the data line of the second sub-display panel through the second through hole.

4. The liquid crystal display motherboard according to claim 3, characterized in that: The first substrate further includes: a third insulating layer, disposed on the first connecting line and extending to a surface of the second insulating layer; a third metal layer disposed on the third insulating layer, wherein the third metal layer includes the DBS common electrode line, and the DBS common electrode line is opposite to the data line; a fourth insulating layer, which is disposed on the third metal layer, and the fourth insulating layer is provided with a third through hole, wherein the third through hole is used to expose the DBS common electrode line; and The adapter line further includes a second connecting line, and the second connecting line is arranged on the fourth insulating layer; One end of the second connection line is connected to the DBS common electrode line of the first sub-display panel through the third through hole, and the other end of the second connection line is connected to the DBS common electrode line of the second sub-display panel through the third through hole.

5. The liquid crystal display motherboard according to claim 4, characterized in that: The third metal layer further includes pixel electrode lines, which are arranged in the same layer as the DBS common electrode lines.

6. The liquid crystal display motherboard according to claim 1, characterized in that: A voltage of the first signal transmission part is different from a voltage of the second signal transmission part.

7. The liquid crystal display motherboard according to claim 1, characterized in that: Also includes: a sealant layer disposed between the first substrate and the second substrate, wherein the sealant layer is disposed in a non-display area of each sub-display panel; The conductive component is arranged in the sealant layer.

8. The liquid crystal display motherboard according to claim 1, wherein: The first substrate is an array substrate, the second substrate is a color filter substrate, and a liquid crystal layer is provided between the array substrate and the color filter substrate.

9. The liquid crystal display motherboard according to claim 1, wherein: The conductive material of the conductive component is a field effect transistor material or a semiconductor material.

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