Low-power control system, controller and linear drive device based on bus communication

Abstract

The present invention provides a low-power control system, controller, and linear drive device based on bus communication, which relates to the field of low-power design technology. The control system includes: a power supply module, which is provided with a low-power voltage output port and an operating voltage output port; the power supply module supplies power to a low-power control module via the low-power voltage output port, and the low-power control module is connected to an external instruction receiving device and at least one instruction execution device by bus communication; when the low-power control module receives a control instruction output by the instruction receiving device, it controls the operating voltage output port to supply power to the instruction receiving device and each instruction execution device; and when no control instruction is received within a preset time period, it controls the low-power voltage output port to supply power to the instruction receiving device and each instruction execution device. The beneficial effect is that by providing two voltage outputs, the instruction execution device can operate normally, and at the same time, the power consumption in the sleep state meets the requirements of the standby power consumption certification standard.

Description

Technical Field

[0001] The present invention relates to the technical field of low-power design, and in particular to a low-power control system, a controller and a linear drive device based on bus communication. Background Art

[0002] With the continuous development of electronic technology, low-power circuits are increasingly being used in circuits. This is because low-power circuits can reduce circuit energy consumption, save resources, and reduce the heat generated by the circuit, which is of great significance for maintaining stable circuit operation.

[0003] Existing low-power circuits have low operating energy consumption because they operate in specific environments and cannot provide high currents, making them unsuitable for loads requiring high-current, high-voltage outputs. Even low-power circuits suitable for loads requiring high-current, high-voltage outputs typically consume over 1W in low-power mode, failing to meet standby power certification standards. Summary of the Invention

[0004] In view of the problems existing in the prior art, the present invention provides a low-power consumption control system based on bus communication, comprising:

[0005] A power supply module, the power supply module providing a low-power voltage output port and a working voltage output port;

[0006] A low-power control module, wherein the power supply module supplies power to the low-power control module via the low-power voltage output port, and the low-power control module establishes a communication connection with an external instruction receiving device and at least one instruction execution device using bus communication;

[0007] The low-power control module is used to control the power supply module to supply power to the instruction receiving device and each instruction execution device through the working voltage output port when receiving a control instruction output by the instruction receiving device, so that each instruction execution device is in an awake state and executes the control instruction.

[0008] And when the control instruction is not received within a preset time period, the power supply module is controlled to power the instruction receiving device and each instruction execution device through the low-power voltage output port, so that each instruction execution device switches from the awake state to the sleep state.

[0009] Preferably, the low-power control module includes a main control circuit, a bus communication circuit connected to the main control circuit, and a control output interface circuit; the power supply module supplies power to the main control circuit and the bus communication circuit through the low-power voltage output port; and the main control circuit is communicatively connected to the instruction receiving device and each of the instruction execution devices through the bus communication circuit;

[0010] The main control circuit is configured to, upon receiving the control instruction output by the instruction receiving device through the bus communication circuit, drive the control output interface circuit to control the power supply module to supply power to the instruction receiving device and each of the instruction execution devices through the working voltage output port, so that each of the instruction execution devices is in an awake state and executes the control instruction;

[0011] The main control circuit is also used to drive the control output interface circuit to control the power supply module to power the instruction receiving device and each instruction execution device through the low-power voltage output port when the control instruction is not received within the preset time period, so that each instruction execution device switches from the awake state to the sleep state.

[0012] Preferably, the main control circuit includes a main control chip, the first pin of the main control chip is connected to a power enable pin of the power supply module, the second pin, the third pin and the fifth pin of the main control chip are connected to the bus communication circuit, the fourth pin of the main control chip is grounded through a first capacitor, the sixth pin of the main control chip is connected to the control output interface circuit, the seventh pin of the main control chip is grounded, the eighth pin of the main control chip is grounded through a second capacitor, and the ninth pin of the main control chip is connected to the low-power voltage output port.

[0013] Preferably, the bus communication circuit includes:

[0014] a first resistor, one end of the first resistor being connected to the third pin of the main control chip, and the other end being respectively connected to the first pin of a communication chip and one end of a second resistor, and the other end of the second resistor being connected to the low-power voltage output port;

[0015] a third resistor, one end of the third resistor being connected to the fifth pin of the main control chip, and the other end being respectively connected to the second pin, the third pin and one end of a fourth resistor of the communication chip, and the other end of the fourth resistor being grounded;

[0016] a fifth resistor, one end of the fifth resistor being connected to the second pin of the main control chip, and the other end being respectively connected to the fourth pin of the communication chip and one end of a sixth resistor, and the other end of the sixth resistor being connected to the low-power voltage output port;

[0017] a seventh resistor, one end of the seventh resistor being connected to the fifth pin of the communication chip, and the other end of the seventh resistor being connected to the seventh pin of the communication chip and one end of a first bidirectional diode, wherein the fifth pin of the communication chip and the other end of the first bidirectional diode are both grounded;

[0018] an eighth resistor, one end of the eighth resistor being connected to one end of the first bidirectional diode, and the other end of the eighth resistor being connected to the control output interface circuit;

[0019] a ninth resistor, one end of the ninth resistor being respectively connected to one end of a tenth resistor, one end of a second bidirectional diode, and the sixth pin of the communication chip, the other end of the ninth resistor being connected to the control output interface circuit, the other end of the tenth resistor being connected to one end of the eighth resistor, and the other end of the second bidirectional diode being grounded;

[0020] an eleventh resistor, one end of the eleventh resistor being connected to one end of the second bidirectional diode, and the other end of the eleventh resistor being connected to the eighth pin of the communication chip and the low-power voltage output port respectively;

[0021] A third capacitor, one end of the third capacitor is connected to the low-power voltage output port, and the other end of the third capacitor is grounded.

[0022] Preferably, the control output interface circuit includes:

[0023] a relay, wherein a normally closed contact of the relay is connected to the low-power voltage output port, a normally open contact of the relay is connected to the working voltage output port, a first coil pin of the relay corresponding to the normally closed contact is connected to the anode of a diode, and a second coil pin of the relay corresponding to the normally open contact is respectively connected to the cathode of the diode and the low-power voltage output port;

[0024] a transistor, wherein the collector of the transistor is respectively connected to the first coil pin and the anode of the diode, the emitter of the transistor is grounded, the base of the transistor is respectively connected to one end of a twelfth resistor and one end of a thirteenth resistor, the other end of the twelfth resistor is connected to the sixth pin of the main control chip, and the other end of the thirteenth resistor is grounded;

[0025] The common end of the relay is connected to a plurality of bus communication interfaces respectively, and each of the bus communication interfaces is connected to the bus communication circuit respectively.

[0026] Preferably, the bus communication interface is a 4-pin interface, comprising:

[0027] A first pin interface, connected to the bus communication circuit;

[0028] A second pin interface, connected to the bus communication circuit;

[0029] The third pin interface is connected to the common terminal of the relay and one end of a fourth capacitor respectively;

[0030] The fourth pin interface is connected to the other end of the fourth capacitor and is grounded.

[0031] Preferably, there are at least two bus communication interfaces, which are respectively connected to the instruction receiving device and the instruction executing device.

[0032] The present invention also provides a controller, including the above-mentioned low-power control system, the controller including a housing, the power supply module and the low-power control module integrated in the housing, and a power connection line socket for mains power access and a plurality of bus communication interfaces for access to the instruction receiving device and each of the instruction execution devices on the side of the housing;

[0033] The power supply module is connected to the mains power through the power connection line socket, and performs AC / DC conversion and then outputs the AC / DC to the low power consumption voltage output port and the working voltage output port.

[0034] The present invention also provides a linear drive device, comprising the above-mentioned controller.

[0035] The above technical solution has the following advantages or beneficial effects:

[0036] 1) By providing two voltage outputs, the system is powered by the working voltage output port in the awake state, so that the instruction execution device that requires high current and high voltage power supply can work normally. In the sleep state, the system is powered by the low-power voltage output port, achieving a power consumption of less than 0.5W in the sleep state, meeting the requirements of the standby power consumption certification standard;

[0037] 2) By providing the same multiple bus communication interfaces, the instruction receiving device and the instruction executing device can be plugged into any bus communication interface, which is convenient for installation and use. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a schematic structural diagram of a low-power control system based on bus communication in a preferred embodiment of the present invention;

[0039] Figure 2 A circuit diagram of a main control circuit in a preferred embodiment of the present invention;

[0040] Figure 3 A circuit diagram of a bus communication circuit in a preferred embodiment of the present invention;

[0041] Figure 4This is a circuit diagram of a control output interface circuit in a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0042] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments. The present invention is not limited to this embodiment, and other embodiments may also fall within the scope of the present invention as long as they conform to the gist of the present invention.

[0043] In a preferred embodiment of the present invention, based on the above problems existing in the prior art, a low-power consumption control system based on bus communication is provided. Figure 1 Shown, including:

[0044] Power supply module 1, power supply module 1 provides a low power consumption voltage output port VCC1 and an operating voltage output port VCC2;

[0045] The low-power control module 2 and the power supply module 1 supply power to the low-power control module 2 via the low-power voltage output port VCC1. The low-power control module 2 establishes a communication connection with an external instruction receiving device 3 and at least one instruction execution device 4 in a bus communication manner.

[0046] The low-power control module 2 is used to control the power supply module 1 to supply power to the instruction receiving device 3 and each instruction execution device 4 through the working voltage output port VCC2 when receiving a control instruction output by the instruction receiving device 3, so that each instruction execution device 4 is in an awake state and executes the control instruction.

[0047] When no control instruction is received within a preset time period, the control power supply module 1 supplies power to the instruction receiving device 3 and each instruction execution device 4 through the low power voltage output port VCC1, so that each instruction execution device 4 switches from the awake state to the sleep state.

[0048] Specifically, in this embodiment, the power supply module 1 may be an ACDC power supply. The low-power voltage output port VCC1 preferably outputs low current, low power, and low voltage. This low current, low power, and low voltage allows the low-power control module to enter standby mode, but the instruction execution device 4 cannot operate, i.e., it enters a dormant state. The working voltage output port VCC2 preferably outputs high current and high voltage. Under these conditions, the instruction execution device 4 can operate normally, i.e., it enters an awake state. In the awake state, if no control instructions are received from the instruction receiving device 3 for a long period of time, the power supply automatically switches to the low-power voltage output port VCC1, transitioning to a dormant state. The long period of time is preferably represented by a preset time period, the specific value of which can be configured as needed. In the dormant state, once a control instruction is received from the instruction receiving device 3, the power supply automatically switches to the working voltage output port 4, allowing the instruction execution device 4 to operate normally and execute the control instruction. Based on this, the present technical solution can achieve low power consumption while ensuring high current and high voltage output, and meet the requirements of the standby power consumption certification standard.

[0049] In one preferred embodiment, the instruction receiving device 3 may be configured with a plurality of control buttons, and pressing any control button can trigger the generation of a corresponding control instruction to switch from the sleep state to the wake-up state.

[0050] In another preferred embodiment, in addition to the control button, the above-mentioned instruction receiving device 3 can also independently set a wake-up button. Only when the wake-up button is pressed will it trigger the generation of a control instruction that can switch from the sleep state to the wake-up state, thereby preventing false wake-up and further reducing power consumption.

[0051] In another preferred embodiment, the instruction receiving device 3 may be configured with a human-computer interaction interface, and corresponding control buttons may be provided on the human-computer interaction interface for the user to trigger in order to wake up and control the action of the instruction executing device 4 .

[0052] In a preferred embodiment of the present invention, the low-power control module 2 includes a main control circuit 21, a bus communication circuit 22 connected to the main control circuit 21, and a control output interface circuit 23. The power supply module 1 supplies power to the main control circuit 21 and the bus communication circuit 22 via the low-power voltage output port VCC1. The main control circuit 21 is communicatively connected to the instruction receiving device 3 and each instruction execution device 4 via the bus communication circuit 22.

[0053] The main control circuit 21 is used to drive the control output interface circuit 23 to control the power supply module 1 to supply power to the instruction receiving device 3 and each instruction execution device 4 through the working voltage output port VCC2 when receiving the control instruction output by the instruction receiving device 3 through the bus communication circuit 22, so that each instruction execution device 4 is in an awake state and executes the control instruction;

[0054] The main control circuit 21 is also used to drive the control output interface circuit 23 to control the power supply module 1 to power the instruction receiving device 3 and each instruction execution device 4 through the low-power voltage output port VCC1 when no control instruction is received within a preset time period, so that each instruction execution device 4 switches from the awake state to the sleep state.

[0055] In a preferred embodiment of the present invention, Figure 2 As shown, the main control circuit 21 includes a main control chip U1, a first pin of the main control chip U1 is connected to a power enable pin EN of the power supply module 1, a second pin, a third pin and a fifth pin of the main control chip U1 are connected to the bus communication circuit 22, a fourth pin of the main control chip U1 is grounded through a first capacitor C1, a sixth pin of the main control chip U1 is connected to the control output interface circuit 23, a seventh pin of the main control chip U1 is grounded, an eighth pin of the main control chip U1 is grounded through a second capacitor C2, and a ninth pin of the main chip U1 is connected to the low-power voltage output port VCC1.

[0056] In a preferred embodiment of the present invention, Figure 3 As shown, the bus communication circuit 22 includes:

[0057] A first resistor R1, one end of the first resistor R1 is connected to the third pin of the main control chip U1, and the other end is respectively connected to the first pin of a communication chip U2 and one end of a second resistor R2, and the other end of the second resistor R2 is connected to the low-power voltage output port VCC1;

[0058] A third resistor R3, one end of the third resistor R3 is connected to the fifth pin of the main control chip U1, and the other end is respectively connected to the second pin, the third pin of the communication chip U2 and one end of a fourth resistor R4, and the other end of the fourth resistor R4 is grounded;

[0059] a fifth resistor R5, one end of the fifth resistor R5 being connected to the second pin of the main control chip U1, and the other end being connected to the fourth pin of the communication chip U2 and one end of a sixth resistor R6, the other end of the sixth resistor R6 being connected to the low-power voltage output port VCC1;

[0060] a seventh resistor R7, one end of the seventh resistor R7 being connected to the fifth pin of the communication chip U2, and the other end being connected to the seventh pin of the communication chip U2 and one end of a first bidirectional diode D1, respectively. The fifth pin of the communication chip U2 and the other end of the first bidirectional diode D1 are both grounded;

[0061] an eighth resistor R8 , one end of the eighth resistor R8 being connected to one end of the first bidirectional diode D1 , and the other end of the eighth resistor R8 being connected to the control output interface circuit 23 ;

[0062] a ninth resistor R9, one end of which is respectively connected to one end of a tenth resistor R10, one end of a second bidirectional diode D2, and the sixth pin of the communication chip U2; the other end of the ninth resistor R9 is connected to the control output interface circuit 23; the other end of the tenth resistor R10 is connected to one end of the eighth resistor R8; and the other end of the second bidirectional diode D2 is grounded;

[0063] an eleventh resistor R11, one end of the eleventh resistor R11 is connected to one end of the second bidirectional diode D2, and the other end of the eleventh resistor R11 is connected to the eighth pin of the communication chip U2 and the low power voltage output port VCC1 respectively;

[0064] The third capacitor C3 has one end connected to the low power consumption voltage output port VCC1 and the other end connected to the ground.

[0065] Specifically, the bus communication methods that can be used by the above-mentioned bus communication circuit include but are not limited to R485 communication, LIN communication, CAN communication and RS422 communication. In this embodiment, the bus communication circuit corresponding to RS485 communication is shown, but it is not limited to this and can be adaptively adjusted according to different communication methods.

[0066] In a preferred embodiment of the present invention, Figure 4 As shown, the control output interface circuit 23 includes:

[0067] Relay K, with its normally closed contact NC connected to the low-power voltage output port VCC1, its normally open contact NO connected to the working voltage output port VCC2, a first coil pin CL1 of relay K corresponding to the normally closed contact NC connected to the anode of a diode D3, and a second coil pin CL2 of relay K corresponding to the normally open contact NO connected to the cathode of the diode D3 and the low-power voltage output port VCC1, respectively;

[0068] A transistor Q, wherein the collector of the transistor Q is connected to the first coil pin CL1 and the anode of the diode D3 respectively, the emitter of the transistor Q is grounded, the base of the transistor Q is connected to one end of a twelfth resistor R12 and one end of a thirteenth resistor R13 respectively, the other end of the twelfth resistor R12 is connected to the sixth pin of the main control chip U1, and the other end of the thirteenth resistor R13 is grounded;

[0069] The common terminal COM of the relay K is connected to a plurality of bus communication interfaces CN respectively, and each bus communication interface CN is connected to the bus communication circuit 22 respectively.

[0070] Specifically, in this embodiment, the relay can be replaced by a MOS tube, which can realize the switching of the normal working voltage output port. The transistor can also be replaced by a driver chip.

[0071] In a preferred embodiment of the present invention, the bus communication interface CN is a 4-pin interface, including:

[0072] The first pin interface is connected to the bus communication circuit;

[0073] The second pin interface is connected to the bus communication circuit;

[0074] The third pin interface is connected to the common terminal COM of the relay K and one end of a fourth capacitor C4 respectively;

[0075] The fourth pin interface is connected to the other end of the fourth capacitor C4 and is grounded.

[0076] In a preferred embodiment of the present invention, there are at least two bus communication interfaces CN, corresponding to the plug-in instruction receiving device 3 and the instruction executing device 4 respectively.

[0077] Specifically, in this embodiment, by providing the same bus communication interface, the instruction receiving device and the instruction executing device can be plugged into any bus communication interface, which is convenient for installation and use.

[0078] Based on Figures 2 to 4 The circuit design of this technical solution is as follows:

[0079] When the button in the instruction receiving device 3 is pressed, the control instruction is triggered and transmitted to the bus communication circuit 22 through the first pin interface RS487-B and the second pin interface RS487-A of the plugged-in bus communication interface CN, and transmitted to the third pin of the main control chip U1 through the first pin of the communication chip U2 in the bus communication circuit 22. The main control chip U1 generates a high-level signal based on the control instruction and outputs it to the control output interface circuit 23 through the sixth pin OUT-EN. At this time, the transistor Q is turned on and the normally open contact of the relay K is energized, so that the working voltage output port VCC2 is used for power supply, and the instruction execution device 4 plugged into the bus communication interface 22 can work normally. Subsequently, when the main control chip U1 does not receive a control instruction within a preset time period, it triggers the generation of a low-level signal and outputs it to the control output interface circuit 23 through the sixth pin OUT-EN. At this time, the transistor Q is cut off, and the relay K returns to the normally closed contact energized, realizing power supply from the low-power voltage output port VCC1. The instruction execution device 4 plugged into the bus communication interface 22 cannot work normally and enters sleep until a button is pressed again in the instruction receiving device 3.

[0080] The present invention also provides a controller, including the above-mentioned low-power control system, the controller including a housing, in which a power supply module and a low-power control module are integrated, and a side of the housing is provided with a power connection line socket for mains power access and multiple bus communication interfaces for accessing an instruction receiving device and each instruction execution device;

[0081] The power supply module is connected to the mains power through the power connection line socket, and performs AC / DC conversion and outputs them to the low power consumption voltage output port and the working voltage output port respectively.

[0082] The present invention also provides a linear drive device, comprising the above-mentioned controller.

[0083] Specifically, in this embodiment, this technical solution can be applied to a lifting table, where the above-mentioned controller is a lifting controller, the corresponding instruction receiving device is a hand controller, and the corresponding instruction execution device is a motor controller. In the awakened state, the linear drive system can be realized. The motor controller can also be other external devices operating under high current and high voltage.

[0084] The above description is only a preferred embodiment of the present invention and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included in the protection scope of the present invention.

Claims

1. A low-power control system based on bus communication, characterized in that: include: A power supply module, the power supply module providing a low-power voltage output port and a working voltage output port; A low-power control module, wherein the power supply module supplies power to the low-power control module via the low-power voltage output port, and the low-power control module establishes a communication connection with an external instruction receiving device and at least one instruction execution device using bus communication; The low-power control module is used to control the power supply module to supply power to the instruction receiving device and each instruction execution device through the working voltage output port when receiving a control instruction output by the instruction receiving device, so that each instruction execution device is in an awake state and executes the control instruction. and when the control instruction is not received within a preset time period, controlling the power supply module to supply power to the instruction receiving device and each of the instruction execution devices through the low-power voltage output port, so that each of the instruction execution devices switches from the awake state to the sleep state; The low-power control module includes a main control circuit, a bus communication circuit connected to the main control circuit, and a control output interface circuit. The power supply module supplies power to the main control circuit and the bus communication circuit via the low-power voltage output port. The main control circuit is communicatively connected to the instruction receiving device and each of the instruction execution devices via the bus communication circuit. The main control circuit is configured to, upon receiving the control instruction output by the instruction receiving device through the bus communication circuit, drive the control output interface circuit to control the power supply module to supply power to the instruction receiving device and each of the instruction execution devices through the working voltage output port, so that each of the instruction execution devices is in an awake state and executes the control instruction; The main control circuit is further configured to, when the control instruction is not received within the preset time period, drive the control output interface circuit to control the power supply module to supply power to the instruction receiving device and each of the instruction execution devices through the low-power voltage output port, so that each of the instruction execution devices switches from the awake state to the sleep state; The main control circuit includes a main control chip, a first pin of the main control chip is connected to a power enable pin of the power supply module, a second pin, a third pin and a fifth pin of the main control chip are connected to the bus communication circuit, a fourth pin of the main control chip is grounded via a first capacitor, a sixth pin of the main control chip is connected to the control output interface circuit, a seventh pin of the main control chip is grounded, an eighth pin of the main control chip is grounded via a second capacitor, and a ninth pin of the main control chip is connected to the low-power voltage output port; The bus communication circuit comprises: a first resistor, one end of the first resistor being connected to the third pin of the main control chip, and the other end being respectively connected to the first pin of a communication chip and one end of a second resistor, and the other end of the second resistor being connected to the low-power voltage output port; a third resistor, one end of the third resistor being connected to the fifth pin of the main control chip, and the other end being respectively connected to the second pin, the third pin and one end of a fourth resistor of the communication chip, and the other end of the fourth resistor being grounded; a fifth resistor, one end of the fifth resistor being connected to the second pin of the main control chip, and the other end being respectively connected to the fourth pin of the communication chip and one end of a sixth resistor, and the other end of the sixth resistor being connected to the low-power voltage output port; a seventh resistor, one end of the seventh resistor being connected to the fifth pin of the communication chip, and the other end of the seventh resistor being connected to the seventh pin of the communication chip and one end of a first bidirectional diode, wherein the fifth pin of the communication chip and the other end of the first bidirectional diode are both grounded; an eighth resistor, one end of the eighth resistor being connected to one end of the first bidirectional diode, and the other end of the eighth resistor being connected to the control output interface circuit; a ninth resistor, one end of the ninth resistor being respectively connected to one end of a tenth resistor, one end of a second bidirectional diode, and the sixth pin of the communication chip, the other end of the ninth resistor being connected to the control output interface circuit, the other end of the tenth resistor being connected to one end of the eighth resistor, and the other end of the second bidirectional diode being grounded; an eleventh resistor, one end of the eleventh resistor being connected to one end of the second bidirectional diode, and the other end of the eleventh resistor being connected to the eighth pin of the communication chip and the low-power voltage output port respectively; a third capacitor, one end of the third capacitor being connected to the low-power voltage output port, and the other end of the third capacitor being grounded; The control output interface circuit includes: a relay, wherein a normally closed contact of the relay is connected to the low-power voltage output port, a normally open contact of the relay is connected to the working voltage output port, a first coil pin of the relay corresponding to the normally closed contact is connected to the anode of a diode, and a second coil pin of the relay corresponding to the normally open contact is respectively connected to the cathode of the diode and the low-power voltage output port; a transistor, wherein the collector of the transistor is respectively connected to the first coil pin and the anode of the diode, the emitter of the transistor is grounded, the base of the transistor is respectively connected to one end of a twelfth resistor and one end of a thirteenth resistor, the other end of the twelfth resistor is connected to the sixth pin of the main control chip, and the other end of the thirteenth resistor is grounded; The common end of the relay is connected to a plurality of bus communication interfaces respectively, and each of the bus communication interfaces is connected to the bus communication circuit respectively.

2. The low power consumption control system according to claim 1, characterized in that: The bus communication interface is a 4-pin interface, including: A first pin interface, connected to the bus communication circuit; A second pin interface, connected to the bus communication circuit; The third pin interface is connected to the common terminal of the relay and one end of a fourth capacitor respectively; The fourth pin interface is connected to the other end of the fourth capacitor and is grounded.

3. The low power consumption control system according to claim 1, characterized in that: There are at least two bus communication interfaces, which are respectively connected to the instruction receiving device and the instruction executing device.

4. A controller, characterized in that: The low-power control system according to any one of claims 1 to 3, wherein the controller comprises a housing, the power supply module and the low-power control module are integrated in the housing, and a side of the housing is provided with a power connection line socket for mains power access and a plurality of bus communication interfaces for accessing the instruction receiving device and each of the instruction execution devices; The power supply module is connected to the mains power through the power connection line socket, and performs AC / DC conversion and then outputs the AC / DC to the low power consumption voltage output port and the working voltage output port.

5. A linear drive device, characterized in that: Comprising the controller as claimed in claim 4.

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