Electronic package and method for manufacturing the same

Abstract

The present invention relates to an electronic package and a manufacturing method thereof, including disposing a conductive structure and a packaging layer covering the conductive structure on one side of a carrier structure having a circuit layer, and disposing an electronic component on the other side, so as to increase the rigidity of the carrier structure through the packaging layer, and solve problems such as warping or wavy deformation caused by the need to increase the volume of the electronic package according to functional requirements.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to an electronic package and a manufacturing method thereof. Background Art

[0002] With the booming development of high-speed computing application terminal products nowadays (such as autonomous driving, supercomputers, or mobile devices, etc.), the chip (IC) size and the package body appearance size in the package structure of the flip chip ball grid array (FCBGA) form are increasing day by day.

[0003] Figure 1 FIG. is a cross-sectional schematic view of a conventional semiconductor package 1. As Figure 1 shown, the semiconductor package 1 includes a package substrate 10, a system on chip (SoC) type semiconductor chip 11 mounted on the upper side of the package substrate 10 in a flip chip manner, a chip module 12 mounted on the upper side of the package substrate 10 in a flip chip manner, and a plurality of solder balls 16 implanted on the lower side of the package substrate 10, and electronic components 17 such as capacitors can be arranged on the lower side of the package substrate 10 according to requirements.

[0004] The existing semiconductor package 1 needs to increase its volume according to functional requirements, so problems such as warpage or wavy deformation are likely to occur. Therefore, the following methods are usually used to overcome them:

[0005] The first method is to use a circuit structure with a thicker core layer for the package substrate 10 to provide sufficient rigidity.

[0006] The second method is to arrange a metal stiffener (not shown in the figure) on the upper side of the package substrate 10 to provide additional rigidity.

[0007] The third method is to arrange at least one heat sink 13 on the upper side of the package substrate 10. For example, the top plate 130 of the heat sink 13 is arranged on the non-functional surface 11b of the semiconductor chip 11 via a thermal interface material (TIM) 14, and the support feet 131 of the heat sink 13 are mounted on the package substrate 10 through an adhesive layer 15.

[0008] However, the above methods will all give rise to the following problems:

[0009] In the first method, the thickness of the package substrate 10 will increase, making the electronic component 17 too far from the semiconductor chip 11, resulting in a decline in the overall electrical performance of the semiconductor package 1.

[0010] In the second method, the configuration of the strong firmware increases the cost of manufacturing the semiconductor package 1, and the packaging substrate 10 needs to be enlarged to configure the layout area for the strong firmware, increasing the overall size of the semiconductor package 1.

[0011] In the third method, the heat dissipation capacity of the heat dissipation member 13 is limited by the heat transfer capacity of the thermal interface material 14, and it also increases the cost of manufacturing the semiconductor package 1. On the other hand, since the rigidity of the packaging substrate 10 is enhanced through the heat dissipation member 13, it is impossible to directly configure the heat dissipation fins on the system side of the end product in subsequent processes.

[0012] Furthermore, due to the defects of the above methods, the industry even adopts methods such as reducing electrical and heat dissipation efficiency to replace the first to third methods. Although the above problems can be avoided, it also makes it difficult for the semiconductor package 1 to meet the multi-functional requirements.

[0013] Therefore, how to overcome the various problems of the above-mentioned prior art has actually become an urgent issue to be solved currently. Summary of the Invention

[0014] In view of the various defects of the above-mentioned prior art, the present invention provides an electronic package and a manufacturing method thereof, which can solve problems such as warping or wavy deformation caused by the need to increase the volume of the electronic package according to functional requirements.

[0015] The electronic package of the present invention includes: a carrier structure having a circuit layer, which has opposite first and second sides; a conductive structure disposed on the first side of the carrier structure and electrically connected to the circuit layer; a packaging layer disposed on the first side of the carrier structure and covering the conductive structure, and exposing a part of the surface of the conductive structure outside the packaging layer; and an electronic component disposed on the second side of the carrier structure and electrically connected to the circuit layer.

[0016] In the aforementioned electronic package, the conductive structure includes conductive posts that bond to the circuit layer. For example, the end surface of the conductive post is exposed outside the packaging layer. Alternatively, the conductive post is bonded to the circuit layer via a conductor.

[0017] In the aforementioned electronic package, it further includes a functional pad embedded in the packaging layer, and the functional pad bonds to the circuit layer. For example, a part of the surface of the functional pad is exposed outside the packaging layer.

[0018] In the aforementioned electronic package, the conductive structure includes solder balls. For example, the solder balls protrude from the packaging layer.

[0019] In the foregoing electronic package, the conductive structure includes a circuit block. For example, the circuit block includes at least one conductive post electrically connected to the circuit layer, and an end face of the conductive post is exposed outside the encapsulation layer. Alternatively, the circuit block includes at least one circuit portion electrically connected to the circuit layer, and a partial surface of the circuit portion is exposed outside the encapsulation layer.

[0020] The present invention also provides a method for manufacturing an electronic package, including: providing a conductive carrier including a plate body and a plurality of conductive posts separately disposed on the plate body; disposing the conductive carrier on a carrier structure having a circuit layer, wherein the conductive carrier is bonded to the circuit layer through a conductor by its plurality of conductive posts; forming an encapsulation layer on the carrier structure to cover the plurality of conductive posts and the conductor, and exposing the plate body of the conductive carrier outside the encapsulation layer; removing the plate body to expose an end face of the conductive post outside the encapsulation layer, wherein the conductive post and the conductor serve as a conductive structure; and disposing at least one electronic component on the carrier structure, and electrically connecting the electronic component to the circuit layer.

[0021] In the foregoing method, the conductive carrier further includes a functional pad, so that after removing the plate body, a partial surface of the functional pad is exposed outside the encapsulation layer.

[0022] The present invention further provides a method for manufacturing an electronic package, including: providing a carrier structure having a circuit layer; forming a plurality of conductive structures on the circuit layer of the carrier structure; forming an encapsulation layer on the carrier structure to cover the plurality of conductive structures, and exposing a partial surface of the conductive structure outside the encapsulation layer; and disposing at least one electronic component on the carrier structure, and electrically connecting the electronic component to the circuit layer.

[0023] The present invention further provides a method for manufacturing an electronic package, including: providing a conductive carrier including a plate body and a plurality of conductive posts separately disposed on the plate body; forming an encapsulation layer on the plate body to cover the plurality of conductive posts; forming a carrier structure having a circuit layer on the encapsulation layer to electrically connect the circuit layer to the plurality of conductive posts through a conductor; removing the plate body to expose an end face of the conductive post outside the encapsulation layer, wherein the conductive post and the conductor serve as a conductive structure; and disposing at least one electronic component on the carrier structure, and electrically connecting the electronic component to the circuit layer.

[0024] In the foregoing electronic package and its manufacturing method, it further includes embedding another electronic component electrically connected to the circuit layer in the encapsulation layer.

[0025] In the foregoing electronic package and its manufacturing method, it further includes disposing a metal frame on a second side of the carrier structure, and the metal frame surrounds and covers the electronic component.

[0026] As can be seen from the above, in the electronic package and its manufacturing method of the present invention, the rigidity of the carrier structure is mainly increased through the encapsulation layer. Therefore, there is no need to configure heat sinks or stiffeners as in the prior art, or thicken the carrier structure as in the prior art, to easily solve problems such as warping or wavy deformation caused by the need to increase the volume of the electronic package according to functional requirements. Therefore, compared with the prior art, the electronic package of the present invention can not only overcome problems such as warping or wavy deformation, but also improve electrical performance and heat dissipation ability, reduce the cost of manufacturing the electronic package, and reduce the overall size of the electronic package. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 FIG. is a cross-sectional schematic view of a conventional semiconductor package.

[0028] Figures 2A to 2E FIG. is a cross-sectional schematic view of a first embodiment of the manufacturing method of the electronic package of the present invention.

[0029] Figure 2E-1 、 Figure 2E-2 and Figure 2E-3 are Figure 2E cross-sectional schematic views of other embodiments of.

[0030] Figure 3 FIG. is a cross-sectional schematic view of a second embodiment of the manufacturing method of the electronic package of the present invention.

[0031] Figures 4A to 4B FIG. is a cross-sectional schematic view of a third embodiment of the manufacturing method of the electronic package of the present invention.

[0032] Figures 5A to 5C FIG. is a cross-sectional schematic view of a fourth embodiment of the manufacturing method of the electronic package of the present invention.

[0033] Figures 6A to 6C FIG. is a cross-sectional schematic view of a fifth embodiment of the manufacturing method of the electronic package of the present invention.

[0034] Figures 7A to 7B FIG. is a cross-sectional schematic view of a sixth embodiment of the manufacturing method of the electronic package of the present invention.

[0035] DESCRIPTION OF THE REFERENCE NUMERALS

[0036] 1: Semiconductor package

[0037] 10: Encapsulation substrate

[0038] 11: Semiconductor chip

[0039] 11b, 21b, 22b: Non-active surface

[0040] 12: Chip module

[0041] 13: Heat sink

[0042] 130: Top sheet

[0043] 131: Support leg

[0044] 14: Thermal interface material

[0045] 15: Adhesive layer

[0046] 16: Solder ball

[0047] 17: Electronic component

[0048] 2, 3, 4, 5, 6, 7: Electronic package

[0049] 2a: Conductive frame

[0050] 20, 50: Carrier structure

[0051] 20a, 50a: First side

[0052] 20b, 50b: Second side

[0053] 200, 500: Circuit layer

[0054] 201: Insulating substrate

[0055] 202: Solder mask

[0056] 21, 61: First electronic component

[0057] 21a, 22a: Active surface

[0058] 210, 220: Electrode pad

[0059] 211, 221, 510: Conductive bump

[0060] 22, 42: Second electronic component

[0061] 222: Underfill

[0062] 23, 331: Conductive post

[0063] 23a, 23b: End face

[0064] 230, 530: Conductor

[0065] 24: Plate body

[0066] 240: Recess

[0067] 25, 45: Encapsulation layer

[0068] 25a: First surface

[0069] 25b: Second surface

[0070] 27: Functional pad

[0071] 28: Passive components

[0072] 29, 29a, 39, 49, 59: Conductive structures

[0073] 31: Conductive element

[0074] 32: Underfill

[0075] 33: Insulating part

[0076] 330: Circuit part

[0077] 49: Reinforcing structure

[0078] 501: Dielectric layer

[0079] 512: Bonding layer

[0080] 600: Groove

[0081] 79, 79a: Metal frame

[0082] 790: Support leg

[0083] 791: Cover plate. Detailed implementation manners

[0084] The following illustrates the implementation manners of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0085] It should be noted that the structures, ratios, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions under which the present invention can be implemented. Therefore, they do not have any technical essence. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope that can be covered by the technical content disclosed in the present invention. At the same time, the terms such as "upper", "first", "second", and "one" cited in this specification are only for the convenience of clear description and are not used to limit the scope under which the present invention can be implemented. The change or adjustment of their relative relationships, without substantial change in the technical content, should also be regarded as the scope within which the present invention can be implemented.

[0086] Figures 2A to 2E It is a cross-sectional schematic view of the manufacturing method of the first embodiment of the electronic package 2 of the present invention.

[0087] As Figure 2A shown, a conductive frame 2a is provided, which includes a plate body 24 and a plurality of conductive columns 23 separately disposed on the plate body 24.

[0088] In this embodiment, the plate body 24 and the conductive posts 23 are integrally formed. For example, part of the material of a metal plate is removed by etching, laser or other means to form the conductive frame 2a, which forms recesses 240 for spacing the conductive posts 23.

[0089] As Figure 2B shown, the conductive frame 2a is disposed on a carrier structure 20, and at least one first electronic component 21 is disposed on the carrier structure 20.

[0090] In this embodiment, the carrier structure 20 has opposite first and second sides 20a and 20b, and the carrier structure 20 is, for example, a packaged substrate with a core layer or a coreless packaged substrate, which has an insulating matrix 201 and a circuit layer 200 bonded to the insulating matrix 201. The circuit layer 200 is, for example, a fan-out type redistribution layer (RDL), and a solder mask layer 202 can be formed on the first side 20a and the second side 20b as required. Among them, circuit layers (not shown) are disposed inside the carrier structure 20 to conduct the circuit layers 200 on the first side 20a and the second side 20b. For example, the carrier structure 20 is a packaged substrate with a core layer, and the material for forming the circuit layer 200 is, for example, copper, and the material for forming the insulating matrix 201 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), etc. It should be understood that the carrier structure can also be other carrier units for carrying electronic components such as chips, such as a lead frame or a silicon interposer, and is not limited to the above.

[0091] Furthermore, the first electronic component 21 is disposed on the first side 20a of the carrier structure 20, and the first electronic component 21 is an active component, a passive component or a combination of the two, etc. Among them, the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor. For example, the first electronic component 21 has opposite working surfaces 21a and non-working surfaces 21b, and the electrode pads 210 on its working surface 21a are disposed on the circuit layer 200 in a flip-chip manner via a plurality of conductive bumps 211 such as solder materials and are electrically connected to the circuit layer 200; alternatively, the electrode pads 210 of the first electronic component 21 can be electrically connected to the circuit layer 200 in a wire bonding manner via a plurality of bonding wires (not shown); or, the electrode pads 210 of the first electronic component 21 can be directly electrically connected to the circuit layer 200. However, the manner in which the first electronic component 21 is electrically connected to the carrier structure 20 is not limited to the above.

[0092] In addition, the conductive frame 2a is bonded to the circuit layer 200 on the first side 20a of the carrier structure 20 through the end face 23a of its conductive column 23 via a conductor 230 such as a solder material.

[0093] As Figure 2C shown, a packaging layer 25 is formed on the first side 20a of the carrier structure 20 to cover the first electronic component 21, the conductive columns 23, and the conductor 230, and the plate body 24 of the conductive frame 2a is exposed outside the packaging layer 25.

[0094] In this embodiment, the packaging layer 25 has opposite first and second surfaces 25a and 25b, and its first surface 25a is bonded to the first side 20a (or solder mask layer 202) of the carrier structure 20, and the plate body 24 is exposed outside the second surface 25b of the packaging layer 25. For example, a planarization process can be performed to make the second surface 25b of the packaging layer 25 flush with the surface of the plate body 24, so that the surface of the plate body 24 is exposed outside the packaging layer 25. Specifically, the planarization process can be performed by grinding to remove part of the material of the packaging layer 25.

[0095] Furthermore, the material formed for the packaging layer 25 is, for example, an insulating material such as polyimide (abbreviated as PI), dry film, epoxy resin, or molding compound, but is not limited to the above. For example, the packaging layer 25 can be formed on the first side 20a of the carrier structure 20 by means of lamination or molding.

[0096] In addition, the packaging layer 25 fills the space between the first electronic component 21 and the first side 20a of the carrier structure 20 to cover the conductive bumps 211; or, an underfill (not shown) can be filled between the first electronic component 21 and the first side 20a of the carrier structure 20 to cover the conductive bumps 211 first, and then the packaging layer 25 covers the underfill.

[0097] As Figure 2D shown, a planarization process is performed to remove the plate body 24 of the conductive frame 2a and part of the packaging layer 25, so that the end face 23b of the conductive column 23 is coplanar with the second surface 25b of the packaging layer 25 (i.e., the two are flush), and the end face 23b of the conductive column 23 is exposed outside the second surface 25b of the packaging layer 25, where the conductive column 23 and the conductor 230 serve as a conductive structure 29.

[0098] In this embodiment, the board body 24 and a part of the encapsulation layer 25 are removed by grinding, etching, burning, cutting or other suitable means, so that the end face 23b of the conductive column 23 is exposed outside the encapsulation layer 25, thereby facilitating subsequent configuration of related conductive paths of the electronic circuit.

[0099] As Figure 2E shown, at least one second electronic component 22 is disposed on the second side 20b of the carrier structure 20 to obtain the required electronic package 2.

[0100] In this embodiment, the second electronic component 22 is an active component, a passive component or a combination of both. Among them, the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor. For example, the second electronic component 22 is a semiconductor chip of the System on Chip (SoC) type, which has opposite active surfaces 22a and non-active surfaces 22b, and the second electronic component 22 is disposed on the circuit layer 200 in a flip-chip manner with the electrode pads 220 on its active surface 22a via a plurality of conductive bumps 221 such as solder materials and is electrically connected to the circuit layer 200, and then encapsulated with an underfill 222 formed between the second electronic component 22 and the second side 20b of the carrier structure 20 to encapsulate these conductive bumps 221; alternatively, the electrode pads 220 of the second electronic component 22 can be electrically connected to the circuit layer 200 by wire bonding via a plurality of bonding wires (not shown in the figure). Or, the electrode pads 220 of the second electronic component 22 can directly contact the circuit layer 200. However, the manner in which the second electronic component 22 is electrically connected to the carrier structure 20 is not limited to the above.

[0101] Furthermore, in subsequent processes, the electronic package 2 can be placed on a circuit board (not shown in the figure) via the end faces 23b of these conductive columns 23 with solder balls (not shown in the figure).

[0102] In addition, in other embodiments, the conductive frame 2a can also be selected to be provided with at least one functional pad (E-pad) 27 that is combined with the circuit layer 200 via a conductor 230 on the board body 24 (replacing the first electronic component 21), as Figure 2E-1 shown, so that after the board body 24 is removed, the functional pad 27 is exposed outside the second surface 25b of the encapsulation layer 25 for heat dissipation and enhanced support. Or, the functional pad 27 can be completely buried in the encapsulation layer 25 without being exposed outside the second surface 25b of the encapsulation layer 25, as Figure 2E-3 shown, for heat dissipation and enhanced support to prevent deformation of the package body.

[0103] In addition, at least one passive component 28 can be disposed on the second side 20b of the carrier structure 20 as required.

[0104] In other embodiments, asFigure 2E-2 As shown, the electronic package 2 can also adopt a conductive structure 29a such as solder balls to replace the configuration of the conductive frame 2a and the conductor 230, and the configuration of the first electronic component 21 can be omitted on the first side 20a of the carrier structure 20 as required. For example, the conductive structure 29a protrudes from the second surface 25b of the encapsulation layer 25 for placement on an electronic device (not shown) such as a circuit board.

[0105] Therefore, the manufacturing method of the present invention mainly increases the rigidity of the carrier structure 20 through the encapsulation layer 25, so there is no need to configure heat sinks, strengthening components as in the prior art, or thicken the core layer of the carrier structure 20 as in the prior art to easily solve problems such as warpage or wavy deformation caused by the need to increase the volume of the electronic package 2 according to functional requirements. Therefore, compared with the prior art, the electronic package 2 of the present invention can not only overcome problems such as warpage or wavy shape, but also improve electrical performance and heat dissipation ability, reduce the cost of manufacturing the electronic package 2, and reduce the overall size of the electronic package 2.

[0106] Figure 3 It is a cross-sectional schematic diagram of the manufacturing method of the second embodiment of the electronic package 3 of the present invention. The difference between this embodiment and the first embodiment lies in the design of the conductive structure 39, so the same parts will not be described in detail below.

[0107] As Figure 3 shown, first, in the Figure 2B process shown, a plurality of conductive structures 39 such as line blocks are used to replace the conductive frame 2a and the conductor 230, and the plurality of conductive structures 39 are arranged at intervals on the first side 20a of the carrier structure 20.

[0108] In this embodiment, the line block is an embodiment of a substrate, which has an insulating part 33 and at least one conductive column 331 embedded in the insulating part 33. For example, the conductive column 331 is a metal column such as a copper column, and the material forming the insulating part 33 such as polyimide (PI for short), dry film, encapsulation colloid or molding compound such as epoxy resin can be formed by lamination or molding, but is not limited to the above.

[0109] Furthermore, in another embodiment of the line block, a line part 330 can also be formed in the insulating part 33 in the form of a fan out type redistribution layer (RDL).

[0110] It should be understood that the circuit block may also employ a semiconductor base containing substrates such as silicon (Si), glass, or other suitable substrates to replace the insulating portion 33.

[0111] In addition, the carrier structure 20 adopts a coreless layer type packaging substrate.

[0112] Next, a process similar to Figures 2C to 2E-2 as shown is adopted. After the second electronic component 22 is disposed, an underfill 32 can be filled between the second electronic component 22 and the second side 20b of the carrier structure 20 to encapsulate the conductive bumps 221.

[0113] Furthermore, the end face of the conductive pillar 331 of the circuit block or a partial surface of the circuit portion 330 is exposed on the second surface 25b of the encapsulation layer 25 to bond a conductive element 31 such as a solder material for connecting an electronic device (not shown) such as a circuit board.

[0114] Therefore, the manufacturing method of the present invention mainly increases the rigidity of the carrier structure 20 through the encapsulation layer 25, thus eliminating the need to configure heat sinks, stiffeners as in the prior art, or thicken the carrier structure 20 as in the prior art to easily solve problems such as warpage or wavy deformation caused by the need to increase the volume of the electronic package 3 according to functional requirements. Therefore, compared with the prior art, the electronic package 3 of the present invention can not only overcome problems such as warpage or wavy shape, but also improve electrical performance and heat dissipation ability, reduce the cost of manufacturing the electronic package 3, and reduce the overall size of the electronic package 3.

[0115] Figures 4A to 4B FIG. is a cross-sectional schematic view of the manufacturing method of the third embodiment of the electronic package 4 of the present invention. The difference between this embodiment and the first embodiment lies in the design of the conductive structure 49, so the same parts will not be described in detail below.

[0116] As Figure 4A shown, the conductive structure 49 is a conductive pillar directly formed on the circuit layer 200 on the first side 20a of the carrier structure 20 by electroplating, deposition, or other methods, etc., so the height of the conductive pillar can be adjusted according to requirements (for example, increased height).

[0117] As Figure 4B shown, next, a process similar to Figures 2C to 2E-2 as shown is adopted to obtain the required electronic package 4. Among them, a second electronic component 42 such as a double data rate (DDR) type memory module can be disposed on the second side 20b of the carrier structure 20, and a stiffener 49 such as a metal ring, a metal frame, or a discontinuous metal wall can be added according to requirements to reduce the overall warpage degree of the electronic package 4.

[0118] Therefore, the manufacturing method of the present invention mainly increases the rigidity of the carrier structure 20 through the encapsulation layer 45, thus eliminating the need to configure heat dissipation components or strengthening components as in the prior art, or thickening the core layer of the carrier structure 20 as in the prior art, to easily solve problems such as warpage or wavy deformation caused by the need to increase the volume of the electronic package 4 according to functional requirements. Therefore, compared with the prior art, the electronic package 4 of the present invention can not only overcome problems such as warpage or wavy shape, but also improve electrical performance and heat dissipation ability, reduce the cost of manufacturing the electronic package 4, and reduce the overall size of the electronic package 4.

[0119] Figures 5A to 5C FIG. is a cross-sectional schematic view of a fourth embodiment of the manufacturing method of the electronic package 5 of the present invention. The difference between this embodiment and the first embodiment lies in the order of manufacturing steps. Therefore, only the differences will be described below, and the same parts will not be described again.

[0120] As Figure 5A shown, first, use the conductive carrier 2a as the carrier, and bond the first electronic component 21 to the plate body 24 of the conductive carrier 2a via a bonding layer 512, and form an encapsulation layer 45 on the plate body 24 to make the encapsulation layer 45 cover the first electronic component 21 and the conductive posts 23.

[0121] In this embodiment, the first electronic component 21 is bonded to the plate body 24 via the bonding layer 512 with its non-functional surface 21b, and conductive bumps 510 such as copper pillars may be formed on the electrode pads 210 of the functional surface 21a.

[0122] Furthermore, the encapsulation layer 45 can be formed by a lamination method, so that the encapsulation layer 45 covers the first electronic component 21 and the conductive posts 23, and the conductive bumps 510 can be exposed outside the encapsulation layer 45.

[0123] As Figure 5B shown, a circuit structure is formed on the encapsulation layer 45 to make the circuit structure serve as the carrier structure 50, which has opposite first side 50a and second side 50b, and the carrier structure 50 is bonded to the encapsulation layer 45 with its first side 50a.

[0124] In this embodiment, the fan-out redistribution layer is directly fabricated on the encapsulation layer 45 to form the circuit structure, so that the insulating matrix of the carrier structure 50 includes a plurality of dielectric layers 501, and the circuit layer 500 of the carrier structure 50 is electrically connected to the conductive bumps 510. When fabricating the circuit layer 500, some circuits (i.e., conductive blind vias or metal pillars) can be extended into the encapsulation layer 45 to serve as conductors 530, so as to electrically connect to the conductive posts 23.

[0125] It should be understood that if the conductive column 23 contacts the first side 50a of the carrier structure 50 (such as the end face of the conductive column 23 being flush with the surface of the encapsulation layer 45), the circuit layer 500 does not need to extend into the encapsulation layer 45 to contact the conductive column 23, and thus the production of the conductor 530 can be omitted.

[0126] As Figure 5C shown, one or more second electronic components 22 are disposed on the second side 50b of the carrier structure 50, and then the board body 24 is removed to form the desired electronic package 5, wherein the conductive structure 59 includes the conductive column 23 and the conductor 530, and the bonding layer 512 is exposed outside the encapsulation layer 45.

[0127] In this embodiment, the second electronic components 22 are respectively a system-on-chip (SoC) type semiconductor chip and a double data rate (DDR) type memory module.

[0128] Therefore, the manufacturing method of the present invention mainly increases the rigidity of the carrier structure 50 through the encapsulation layer 45, and thus there is no need to configure heat sinks, strengthening components as in the prior art, or thicken the carrier structure 50 as in the prior art to easily solve problems such as warpage or wavy deformation caused by the need to increase the volume of the electronic package 5 according to functional requirements. Therefore, compared with the prior art, the electronic package 5 of the present invention can not only overcome problems such as warpage or wavy shape, but also improve electrical performance and heat dissipation ability, reduce the cost of manufacturing the electronic package 5, and reduce the overall size of the electronic package 5.

[0129] Figures 6A to 6C It is a cross-sectional schematic diagram of the fifth embodiment of the manufacturing method of the electronic package 6 of the present invention. The difference between this embodiment and the first embodiment lies in the design of the first electronic component, so the same parts will not be described in detail below.

[0130] Currently, the operating voltage of active chips (ICs) is getting lower and lower as the manufacturing process is scaled down, enabling electronic products to have good performance while also increasing power consumption, and even increasing the sensitivity of the active chips to noise. Since decoupling capacitors can reduce the impedance of the power network, thereby reducing the disturbance of voltage noise to provide stable power quality, the placement position of the capacitors needs to be close to the active chips to reduce parasitic inductance and achieve the best operating effect.

[0131] As Figure 6AAs shown, on the second side 20b of the carrier structure 20, the second electronic component 22 is fixed with an underfill 222. Therefore, the underfill 222 occupies the area around the second electronic component 22, preventing other electronic components such as integrated passive devices (IPD) from approaching the second electronic component 22. Accordingly, a first electronic component 61 (i.e., a capacitor) such as an IPD is disposed on the first side 20a of the carrier structure 20 and is correspondingly located below the second electronic component 22 (i.e., an active chip), enabling the first electronic component 61 to approach the second electronic component 22 as needed, that is, shortening the distance between the second electronic component 22 and the IPD (i.e., the capacitor).

[0132] In this embodiment, the first electronic component 61 can be completely embedded in the encapsulation layer 25; alternatively, the first electronic component 61 can be exposed in the encapsulation layer 25, as Figure 6B shown.

[0133] Furthermore, to shorten the distance between the second electronic component 22 and the IPD (i.e., the capacitor), a groove 600 can be formed on the first side 20a of the carrier structure 20, as Figure 6C shown, to place the first electronic component 61, enabling the first electronic component 61 (i.e., the capacitor) to be closer to the second electronic component 22 (i.e., the active chip). Additionally, the thickness of the overall package can be further reduced to achieve a thin, light, short, and small design for use in end products.

[0134] Therefore, in this embodiment, by disposing the first electronic component 61 (i.e., the capacitor) such as an IPD on the first side 20a of the carrier structure 20, it is possible to avoid being restricted by the underfill 222 on the second side 20b of the carrier structure 20. Thus, the distance between the second electronic component 22 and the IPD (i.e., the capacitor) can be shortened as needed. Therefore, the electronic package 6 of the present invention can significantly reduce parasitic inductance and achieve the best operating effect.

[0135] Figures 7A to 7B FIG. is a cross-sectional schematic view of a sixth embodiment of the electronic package 7 of the present invention. The difference between this embodiment and the third embodiment is the addition of a metal frame, so the same parts will not be described again below.

[0136] As Figure 7A shown, a metal frame 79 is disposed on the second side 20b of the carrier structure 20 to surround and cover the second electronic components 22, 42 and the passive component 28.

[0137] In this embodiment, the metal frame 79 is a single integrated independent component; alternatively, the metal frame 79a can also be a combined type, which includes at least one support leg 790 erected on the carrier structure 20 and a cover plate 791 mounted on the support leg 790, asFigure 7B as shown, to surround and cover the second electronic components 22, 42 and the passive component 28.

[0138] Therefore, the manufacturing method of the present invention mainly provides the shielding effect of the second electronic components 22, 42 and the passive component 28 against electromagnetic interference (EMI) through the arrangement of the metal frames 79, 79a, and can also be used as a stiffener to reduce the overall warpage degree of the electronic package 7.

[0139] The present invention also provides an electronic package 2, 3, 4, 5, 6, 7, including: a carrier structure 20, 50 having circuit layers 200, 500, at least one conductive structure 29, 29a, 39, 49, 59, a packaging layer 25, 45, and at least one second electronic component 22, 42.

[0140] The carrier structures 20, 50 have opposite first sides 20a, 50a and second sides 20b, 50b.

[0141] The conductive structures 29, 29a, 39, 49, 59 are disposed on the first sides 20a, 50a of the carrier structures 20, 50 and are electrically connected to the circuit layers 200, 500.

[0142] The packaging layers 25, 45 are disposed on the first sides 20a, 50a of the carrier structures 20, 50 and cover the conductive structures 29, 29a, 39, 49, 59, and part of the surfaces of the conductive structures 29, 29a, 39, 49, 59 are exposed outside the packaging layers 25, 45.

[0143] The electronic components 22, 42 are disposed on the second sides 20b, 50b of the carrier structures 20, 50 and are electrically connected to the circuit layer 200.

[0144] In one embodiment, the conductive structures 29, 49, 59 include conductive posts 23 that are combined with the circuit layer 200. For example, the end faces 23b of the conductive posts 23 are exposed outside the packaging layer 25, 45. Alternatively, the conductive posts 23 are combined with the circuit layers 200, 500 through conductors 230, 530.

[0145] In one embodiment, the electronic package 2 further includes a functional pad 27 embedded in the packaging layer 25, and the functional pad 27 is combined with the circuit layer 200. For example, part of the surface of the functional pad 27 is exposed outside the packaging layer 25.

[0146] In one embodiment, the conductive structure 29a includes solder balls. For example, the solder balls protrude from the packaging layer 25.

[0147] In one embodiment, the conductive structure 39 includes a circuit block. For example, the circuit block includes at least one conductive post 331 electrically connected to the circuit layer 200, and an end face of the conductive post 331 is exposed outside the encapsulation layer 25. Alternatively, the circuit block includes at least one circuit portion 330 electrically connected to the circuit layer 200, and a partial surface of the circuit portion 330 is exposed outside the encapsulation layer 25.

[0148] In one embodiment, the electronic packages 2, 4, 5, 6, 7 further include first electronic components 21, 61 embedded in the encapsulation layers 25, 45, which are electrically connected to the circuit layer 200.

[0149] In one embodiment, the electronic package 7 further includes metal frames 79, 79a disposed on the second side 20b of the carrier structure 20, which surround and cover the second electronic components 22, 42.

[0150] In summary, for the electronic package and its manufacturing method of the present invention, the rigidity of the carrier structure is increased via the encapsulation layer. Therefore, there is no need to configure heat dissipation components or strengthening components as in the prior art, or thicken the carrier structure as in the prior art, so as to easily solve problems such as warping or wavy deformation caused by the need to increase the volume of the electronic package according to functional requirements. Thus, the electronic package of the present invention can not only overcome problems such as warping or wavy shape, but also improve electrical performance and heat dissipation ability, reduce the cost of manufacturing the electronic package, and reduce the overall size of the electronic package.

[0151] The above embodiments are only used to illustrate the principles and effects of the present invention by way of example, rather than to limit the present invention. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the protection of the rights of the present invention shall be as listed in the claims.

Claims

1. An electronic package, characterized in that, it includes: a carrier structure having a circuit layer, which has opposite first and second sides; a conductive structure disposed on the first side of the carrier structure and electrically connected to the circuit layer; a packaging layer disposed on the first side of the carrier structure and covering the conductive structure, and exposing a partial surface of the conductive structure outside the packaging layer; a functional pad embedded in the packaging layer, and the functional pad is combined with the circuit layer to serve as a heat dissipation and strengthening structure without electrical function; and an electronic component disposed on the second side of the carrier structure and electrically connected to the circuit layer.

2. The electronic package according to claim 1, characterized in that, the conductive structure includes conductive posts combined with the circuit layer.

3. An electronic package, characterized in that, it includes: a carrier structure having a circuit layer, which has opposite first and second sides; a conductive structure including conductive posts combined with the circuit layer, and disposed on the first side of the carrier structure by electroplating and electrically connected to the circuit layer, wherein the peripheral surface of the conductive post is planar; a packaging layer disposed on the first side of the carrier structure and covering the conductive structure, and exposing a partial surface of the conductive structure outside the packaging layer; and an electronic component disposed on the second side of the carrier structure and electrically connected to the circuit layer.

4. The electronic package according to claim 2 or 3, characterized in that, the end face of the conductive post is exposed outside the packaging layer.

5. The electronic package according to claim 2 or 3, characterized in that, the conductive post is combined with the circuit layer through a conductor.

6. The electronic package according to claim 1, characterized in that, a partial surface of the functional pad is exposed outside the packaging layer.

7. The electronic package according to claim 1, characterized in that, the conductive structure includes solder balls.

8. The electronic package according to claim 7, characterized in that, the solder balls protrude from the packaging layer.

9. The electronic package according to claim 1, characterized in that, the conductive structure includes a circuit block.

10. The electronic package according to claim 9, characterized in that, the circuit block includes at least one conductive post electrically connected to the circuit layer, and the end face of the conductive post is exposed outside the packaging layer.

11. The electronic package according to claim 9, characterized in that, the circuit block includes at least one circuit portion electrically connected to the circuit layer, and a partial surface of the circuit portion is exposed outside the packaging layer.

12. The electronic package according to claim 3, characterized in that, the electronic package further includes another electronic component embedded in the packaging layer and electrically connected to the circuit layer.

13. The electronic package according to claim 1 or 3, characterized in that, the electronic package further includes a metal frame disposed on the second side of the carrier structure, which surrounds and covers the electronic component.

14. A manufacturing method of an electronic package, characterized in that, it includes: providing a conductive frame including a plate body and a plurality of conductive posts separately disposed on the plate body; disposing a functional pad on the plate body of the conductive frame; The conductive frame is disposed on a carrier structure having a circuit layer, wherein the conductive frame is bonded to the circuit layer via a plurality of conductive posts and a conductor, and the functional pad is also bonded to the circuit layer via the conductor; An encapsulation layer is formed on the carrier structure to cover the plurality of conductive posts, the conductor, and the functional pad, and the board body of the conductive frame is exposed outside the encapsulation layer; The board body is removed to expose the end faces of the conductive posts outside the encapsulation layer, wherein the conductive posts and the conductor serve as a conductive structure, and the functional pad serves as a heat dissipation and strengthening structure and does not have an electrical function; and At least one electronic component is disposed on the carrier structure, and the electronic component is electrically connected to the circuit layer.

15. The method for manufacturing an electronic package according to claim 14, wherein, after removing the board body, a part of the surface of the functional pad is exposed outside the encapsulation layer.

16. A method for manufacturing an electronic package, wherein, comprising: providing a carrier structure having a circuit layer; forming a plurality of conductive structures on the circuit layer of the carrier structure by electroplating, wherein the plurality of conductive structures include conductive posts bonded to the circuit layer, and the peripheral surface of the conductive posts is planar; forming an encapsulation layer on the carrier structure to cover the plurality of conductive structures, and exposing a part of the surface of the conductive structures outside the encapsulation layer; and disposing at least one electronic component on the carrier structure, and the electronic component is electrically connected to the circuit layer.

17. A method for manufacturing an electronic package, wherein, comprising: providing a conductive frame including a board body and a plurality of conductive posts separately disposed on the board body; disposing a functional pad on the board body of the conductive frame; forming an encapsulation layer on the board body to cover the plurality of conductive posts and the functional pad; forming a carrier structure having a circuit layer on the encapsulation layer to electrically connect the circuit layer to the plurality of conductive posts and connect the functional pad via a conductor; removing the board body to expose the end faces of the conductive posts outside the encapsulation layer, wherein the conductive posts and the conductor serve as a conductive structure, and the functional pad serves as a heat dissipation and strengthening structure and does not have an electrical function; and disposing at least one electronic component on the carrier structure, and the electronic component is electrically connected to the circuit layer.

18. The method for manufacturing an electronic package according to claim 16, wherein, the method includes embedding another electronic component electrically connected to the circuit layer in the encapsulation layer.

19. The method for manufacturing an electronic package according to claim 16 or 17, wherein, the method further includes disposing a metal frame on the second side of the carrier structure, and the metal frame surrounds and covers the electronic component.

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