Component substrate

Abstract

The present invention discloses a component substrate, comprising a substrate, a bonding structure, a first insulating layer and a side electrode. The bonding structure includes a conductive layer, a contact pad layer and an extension layer located between the conductive layer and the contact pad layer. The first insulating layer is located between the extension layer and the conductive layer and has a first opening overlapping the conductive layer. The side electrode extends from a first side of the substrate to the contact pad layer. The extension layer includes a connecting portion, a first extension portion and a second extension portion. The connecting portion fills the first opening. The first extension portion and the second extension portion extend from the first opening along a first direction and a second direction respectively. The first extension portion extends from the first opening towards the first side of the substrate. The length of the first extension portion is greater than the length of the second extension portion. The first extension portion is located between one end of the contact pad layer close to the first side and the top surface of the substrate.

Description

Technical Field

[0001] The present invention relates to a component substrate, and particularly to a component substrate including a bonding structure. Background Art

[0002] In existing display panels, in order to reduce the border width of the display panel, part of the chips and circuits are usually disposed on the back surface of the display panel. Generally, a driving chip is integrated into a flexible circuit board through a film flip-chip package, and then the flexible circuit board is bonded to pads on the front surface of the pixel array substrate. The flexible circuit board can be bent to the back surface of the pixel array substrate, thereby enabling the driving chip to be disposed on the back surface of the pixel array substrate.

[0003] However, even if the flexible circuit board is bent to the back surface of the pixel array substrate, the flexible circuit board cannot be completely attached to the side surface of the pixel array substrate after bending, resulting in a certain border width still being retained in the finally formed display panel. In addition, the flexible circuit board is often bonded to the pixel array substrate through silver paste or other conductive materials. However, the bonding position between the flexible circuit board and the pixel array substrate is prone to breakage or cracking due to stress concentration. Summary of the Invention

[0004] The present invention provides a component substrate, which has the advantage of a small border width, and the design of the extension layer can improve the problem that the side electrodes are prone to breakage.

[0005] At least one embodiment of the present invention provides a component substrate. The component substrate includes a substrate, a bonding structure, a first insulating layer, and side electrodes. The bonding structure includes a conductive layer, a pad layer, and an extension layer located between the conductive layer and the pad layer, which are electrically connected to each other. The first insulating layer is located between the extension layer and the conductive layer and has a first opening overlapping the conductive layer. The side electrodes extend from a first side of the substrate to the pad layer and are connected to the pad layer. The extension layer includes a connecting portion, a first extension portion, and a second extension portion. The connecting portion fills the first opening. The first extension portion and the second extension portion are located outside the first opening. The first extension portion and the second extension portion extend along a first direction and a second direction respectively from the first opening. The first extension portion extends from the first opening toward the first side of the substrate. The length of the first extension portion is greater than the length of the second extension portion. The first extension portion is located between one end of the pad layer close to the first side and the top surface of the substrate. Description of the Drawings

[0006] Figure 1A is a top view schematic diagram of a component substrate according to an embodiment of the present invention;

[0007] Figure 1B is Figure 1A a cross-sectional schematic diagram taken along line A-A' of

[0008] Figure 1C is Figure 1A a schematic cross-sectional view of line B-B'

[0009] Figure 2 is a schematic cross-sectional view of an element substrate according to an embodiment of the present invention;

[0010] Figure 3 is a schematic cross-sectional view of an element substrate according to an embodiment of the present invention;

[0011] Figure 4 is a schematic cross-sectional view of an element substrate according to an embodiment of the present invention;

[0012] Figure 5 is a schematic cross-sectional view of an element substrate according to an embodiment of the present invention;

[0013] Figure 6 is an electron micrograph of a bonding structure of an element substrate according to an embodiment of the present invention.

[0014] Symbol Explanation

[0015] 1, 2, 3, 4, 5: Element substrate

[0016] 110: First insulating layer

[0017] 120: Second insulating layer

[0018] 130: Third insulating layer

[0019] 140: Fourth insulating layer

[0020] 150: Protective layer

[0021] 210: Conductive layer

[0022] 212: First circuit layer

[0023] 214: Gate

[0024] 220: Extension layer

[0025] 220A: Connection part

[0026] 220B: First extension part

[0027] 220C: Second extension part

[0028] 220D: Third extension part

[0029] 220E: Fourth extension part

[0030] 222: Second circuit layer

[0031] 224: Drain

[0032] 226: Source electrode

[0033] 230: First conductive layer

[0034] 232: Third wiring layer

[0035] 240: Second conductive layer

[0036] 242: Fourth wiring layer

[0037] 250: Contact pad layer

[0038] 250s: Inclined surface

[0039] 252: Fifth wiring layer

[0040] 310: Backside wiring layer

[0041] 320: Insulating layer

[0042] 330: Cover layer

[0043] 340: Backside contact pad

[0044] AA: Active area

[0045] A - A’, B - B’: Line

[0046] BL: Buffer layer

[0047] BS: Bonding structure

[0048] CH: Channel layer

[0049] D1: First direction

[0050] D2: Second direction

[0051] D3: Third direction

[0052] D4: Fourth direction

[0053] GI: Gate insulating layer

[0054] IS: Insulating structure

[0055] PA: Peripheral area

[0056] PL1: First flat layer

[0057] PL2: Second flat layer

[0058] PL3: Third flat layer

[0059] SB: Substrate

[0060] SBb: Bottom surface

[0061] SBt: Top surface

[0062] SE: Side electrode

[0063] S1: First side

[0064] T: Active element

[0065] O1: First opening

[0066] O2: Second opening

[0067] O3: Third opening

[0068] O4: Fourth opening

[0069] W: Contact window

[0070] θ: Tilt angle Detailed implementation manner

[0071] Figure 1A is a top view schematic diagram of an element substrate according to an embodiment of the present invention. Figure 1B is Figure 1A a cross-sectional schematic diagram of line A - A' of Figure 1C is Figure 1A a cross-sectional schematic diagram of line B - B' of . For the sake of clarity of the drawings, Figure 1A some components in Figure 1B and Figure 1C are omitted from the illustration.

[0072] Please refer to Figures 1A to 1C , the element substrate 1 includes a substrate SB, a bonding structure BS, a first insulating layer 110, and a side electrode SE. In this embodiment, the element substrate 1 further includes a buffer layer BL, a gate insulating layer GI, a second insulating layer 120, a third insulating layer 130, a fourth insulating layer 140, a protective layer 150, a first planarizing layer PL1, a second planarizing layer PL2, a third planarizing layer PL3, an active element T, a first wiring layer 212, a second wiring layer 222, a third wiring layer 232, a fourth wiring layer 242, a fifth wiring layer 252, a cover layer 330, a back wiring layer 310, an insulating layer 320, and a back pad 340.

[0073] The substrate SB includes an active region AA and a peripheral region PA. The peripheral region PA is located on at least one side of the active region AA. In this embodiment, the peripheral region PA surrounds the active region AA. The material of the substrate SB can be glass, quartz, organic polymer, or light-blocking / reflective material (such as: conductive material, metal, wafer, ceramic, or other applicable materials) or other applicable materials. If a conductive material or metal is used, an insulating layer (not shown) is covered on the substrate SB to avoid short-circuit problems.

[0074] A buffer layer BL is formed on a substrate SB. A gate insulating layer GI is formed on the buffer layer BL. The buffer layer BL and the gate insulating layer GI are located above an active region AA and a peripheral region PA of the substrate SB. The buffer layer BL and the gate insulating layer GI are each a single-layer or multi-layer structure. In some embodiments, the buffer layer BL and the gate insulating layer GI each include an organic material or an inorganic material.

[0075] A bonding structure BS is located above the peripheral region PA of the substrate SB. The bonding structure BS includes a conductive layer 210, an extension layer 220, a first conductive layer 230, a second conductive layer 240, and a pad layer 250 that are electrically connected to each other. The extension layer 220, the first conductive layer 230, and the second conductive layer 240 are located between the conductive layer 210 and the pad layer 250. In this embodiment, the conductive layer 210, the extension layer 220, the first conductive layer 230, the second conductive layer 240, and the pad layer 250 are stacked in sequence.

[0076] The conductive layer 210 is connected to a first circuit layer 212. In some embodiments, the first circuit layer 212 extends from the peripheral region PA to the active region AA.

[0077] An insulating structure IS surrounds the bonding structure BS. In this embodiment, the insulating structure IS includes a first insulating layer 110, a second insulating layer 120, a third insulating layer 130, a fourth insulating layer 140, and a protective layer 150 that are stacked in sequence. In this embodiment, the first insulating layer 110, the second insulating layer 120, the third insulating layer 130, the fourth insulating layer 140, and the protective layer 150 extend from the peripheral region PA to the active region AA.

[0078] The first insulating layer 110 is located on the conductive layer 210, the first circuit layer 212, and the gate insulating layer GI. The first insulating layer 110 is located between the extension layer 220 and the conductive layer 210. The first insulating layer 110 has a first opening O1 that overlaps the conductive layer 210. In this embodiment, the first insulating layer 110 is directly formed on the conductive layer 210, the first circuit layer 212, and the gate insulating layer GI, but the present invention is not limited thereto. In other embodiments, other insulating layers may also be included between the first insulating layer 110 and the conductive layer 210 and between the first insulating layer 110 and the first circuit layer 212. In some embodiments, the material of the first insulating layer 110 includes an inorganic material, such as silicon nitride, silicon oxide, aluminum oxide, a stack of silicon nitride and silicon oxide, or other suitable materials. In some embodiments, the thickness of the first insulating layer 110 is 600 nanometers to 750 nanometers.

[0079] The extension layer 220 is formed on the first insulating layer 110. The extension layer 220 includes a connection portion 220A, a first extension portion 220B, a second extension portion 220C, a third extension portion 220D, and a fourth extension portion 220E. The connection portion 220A fills the first opening O1 of the first insulating layer 110. In some embodiments, the connection portion 220A is connected to the conductive layer 210 through the first opening O1. The first extension portion 220B, the second extension portion 220C, the third extension portion 220D, and the fourth extension portion 220E are located outside the first opening O1. The first extension portion 220B, the second extension portion 220C, the third extension portion 220D, and the fourth extension portion 220E extend along a first direction D1, a second direction D2, a third direction D3, and a fourth direction D4 from the first opening O1, respectively. The first extension portion 220B extends from the first opening O1 toward the first side S1 of the substrate SB. The second extension portion 220C extends from the first opening O1 toward the active region AA. The third extension portion 220D and the fourth extension portion 220E extend toward other adjacent bonding structures BS.

[0080] In some embodiments, the length of the first extension portion 220B is greater than the lengths of the second extension portion 220C, the third extension portion 220D, and the fourth extension portion 220E. In some embodiments, the lengths of the third extension portion 220D and the fourth extension portion 220E are less than the length of the first extension portion 220B, thereby reducing the risk of short circuits occurring between adjacent bonding structures BS.

[0081] The second insulating layer 120 is located on the extension layer 220 and the first insulating layer 110. The second insulating layer 120 is located between the first conductive layer 230 and the extension layer 220. The second insulating layer 120 has a second opening O2 that overlaps the extension layer 220. In the present embodiment, the second insulating layer 120 is directly formed on the extension layer 220 and the first insulating layer 110, but the present invention is not limited thereto. In other embodiments, other insulating layers may also be included between the second insulating layer 120 and the extension layer 220. In some embodiments, the material of the second insulating layer 120 includes an inorganic material, such as silicon nitride, silicon oxide, aluminum oxide, or other suitable materials. In some embodiments, the thickness of the second insulating layer 120 is 100 nanometers to 300 nanometers.

[0082] The first conductive layer 230 is located on the second insulating layer 120. In the present embodiment, the first conductive layer 230 is directly formed on the second insulating layer 120. The first conductive layer 230 is connected to the extension layer 220 through the second opening O2 of the second insulating layer 120.

[0083] The third insulating layer 130 is located on the first conductive layer 230 and the second insulating layer 120. The third insulating layer 130 is located between the second conductive layer 240 and the first conductive layer 230. The third insulating layer 130 has a third opening O3 overlapping the first conductive layer 230. In this embodiment, the third insulating layer 130 is directly formed on the first conductive layer 230 and the second insulating layer 120, but the present invention is not limited thereto. In other embodiments, other insulating layers may also be included between the third insulating layer 130 and the first conductive layer 230. In some embodiments, the material of the third insulating layer 130 includes inorganic materials, such as silicon nitride, silicon oxide, aluminum oxide, or other suitable materials. In some embodiments, the thickness of the third insulating layer 130 is 100 nanometers to 300 nanometers.

[0084] The second conductive layer 240 is located on the third insulating layer 130. In this embodiment, the second conductive layer 240 is directly formed on the third insulating layer 130. The second conductive layer 240 is connected to the first conductive layer 230 through the third opening O3 of the third insulating layer 130.

[0085] The fourth insulating layer 140 is located on the third insulating layer 130 and the second conductive layer 240. The fourth insulating layer 140 is located between the contact pad layer 250 and the second conductive layer 240. The fourth insulating layer 140 has a fourth opening O4 overlapping the second conductive layer 240. In this embodiment, the fourth insulating layer 140 is directly formed on the second conductive layer 240 and the third insulating layer 130, but the present invention is not limited thereto. In other embodiments, other insulating layers may also be included between the fourth insulating layer 140 and the second conductive layer 240. In some embodiments, the material of the fourth insulating layer 140 includes inorganic materials, such as silicon nitride, silicon oxide, aluminum oxide, or other suitable materials. In some embodiments, the thickness of the fourth insulating layer 140 is 100 nanometers to 300 nanometers.

[0086] The contact pad layer 250 is located on the fourth insulating layer 140. In this embodiment, the contact pad layer 250 is directly formed on the fourth insulating layer 140. The contact pad layer 250 is connected to the second conductive layer 240 through the fourth opening O4 of the fourth insulating layer 140.

[0087] The protective layer 150 is located on the fourth insulating layer 140 and the contact pad layer 250. The protective layer 150 is directly formed on the fourth insulating layer 140 and the contact pad layer 250. The protective layer 150 has a contact window W overlapping the contact pad layer 250. In some embodiments, the material of the protective layer 150 includes inorganic materials, such as silicon nitride, silicon oxide, aluminum oxide, or other suitable materials. In some embodiments, the thickness of the protective layer 150 is 100 nanometers to 300 nanometers.

[0088] In some embodiments, the widths of the first opening O1, the second opening O2, the third opening O3, the fourth opening O4, and the contact window W increase in sequence.

[0089] The side electrode SE extends from the first side S1 of the substrate SB to the contact pad layer 250 and is connected to the contact pad layer 250. In some embodiments, the contact window W has a relatively large width, so that the side electrode SE can more easily contact the contact pad layer 250 through the contact window W. The side electrode SE contacts the first side S1 of the substrate SB. In some embodiments, the side electrode SE partially fills or completely fills the contact window W. In some embodiments, the contact pad layer 250 includes an inclined surface 250s near the first side S1 of the substrate 100, where the inclined surface 250s has an inclination angle θ with respect to the top surface SBt of the substrate 100. The protective layer 150 and the side electrode SE overlap the inclined surface 250s, and the side electrode SE extends along the inclined surface 250s to the contact window W of the protective layer 150. In some embodiments, the inclination angle θ is from 20 degrees to 40 degrees. It should be noted that the inclination angle θ of the inclined surface 250s in the drawings is only for illustration, and the inclination angle θ of the actual device may be smaller than the angle shown in the drawings. In some embodiments, the method of forming the side electrode SE includes sputtering or other suitable manufacturing processes.

[0090] In this embodiment, the first extension portion 220B of the extension layer 220 extends between the end of the contact pad layer 250 near the first side S1 and the top surface SBt of the substrate SB. In other words, the extension layer 220 is located between the end of the contact pad layer 250 near the first side S1 and the top surface SBt of the substrate SB. In this embodiment, a part of the first extension portion 220B does not overlap the first conductive layer 230 and the second conductive layer 240 in the normal direction of the top surface SBt of the substrate 100. In this embodiment, by providing the first extension portion 220B, the inclination angle θ of the inclined surface 250s of the contact pad layer 250 can be reduced, thereby improving the problem that the protective layer 150 and the side electrode SE are broken due to climbing.

[0091] The backside circuit layer 310 is located on the bottom surface SBb of the substrate 100. The insulating layer 320 is located on the backside circuit layer 310. The side electrode SE extends along the first side S1 of the substrate 100 to the bottom surface SBb of the substrate 100, and the side electrode SE is electrically connected to the backside circuit layer 310. The cover layer 330 covers the side electrode SE. The backside pad 340 is located on the insulating layer 320 and is connected to the backside circuit layer 310. The backside pad 340 is suitable for connecting other components, such as chips, circuit boards, or other electronic components.

[0092] The active element T is located above the active region AA of the substrate SB. The active element T includes a channel layer CH, a gate 214, a drain 224, and a source 226. The channel layer CH is formed on the buffer layer BL. The channel layer CH is a single-layer or multi-layer structure, which includes amorphous silicon, polycrystalline silicon, microcrystalline silicon, single-crystalline silicon, organic semiconductor materials, oxide semiconductor materials (such as indium zinc oxide, indium gallium zinc oxide, or other suitable materials or combinations of the above materials), or other suitable materials or combinations of the above materials.

[0093] The gate 214 overlaps the channel layer CH, and a gate insulating layer GI is sandwiched between the gate 214 and the channel layer CH. The first insulating layer 110 covers the gate 214. The source 226 and the drain 224 are located on the first insulating layer 110 and are electrically connected to the channel layer CH respectively.

[0094] In this embodiment, the active element T takes the top-gate type thin-film transistor as an example, but the present invention is not limited thereto. In other embodiments, the active element T can also be a bottom-gate type thin-film transistor, a double-gate type, or other types of thin-film transistors.

[0095] In some embodiments, the conductive layer 210, the first wiring layer 212, and the gate 214 belong to the same patterned layer. For example, the conductive layer 210, the first wiring layer 212, and the gate 214 are defined by the same photolithography and etching manufacturing process. In some embodiments, the conductive layer 210, the first wiring layer 212, and the gate 214 are single-layer or multi-layer structures. For example, the conductive layer 210, the first wiring layer 212, and the gate 214 include molybdenum, titanium, aluminum, copper, or alloys of the foregoing materials, or other conductive materials, or stacked layers of the foregoing materials. In some embodiments, the thickness of the conductive layer 210, the first wiring layer 212, and the gate 214 is 200 nanometers to 300 nanometers.

[0096] In some embodiments, the extension layer 220, the second wiring layer 222, the drain 224, and the source 226 belong to the same patterned layer. For example, the extension layer 220, the second wiring layer 222, the drain 224, and the source 226 are defined by the same photolithography and etching manufacturing process. In some embodiments, the extension layer 220, the second wiring layer 222, the drain 224, and the source 226 are single-layer or multi-layer structures. For example, the extension layer 220, the second wiring layer 222, the drain 224, and the source 226 include molybdenum, titanium, aluminum, copper, or alloys of the foregoing materials, or other conductive materials, or stacked layers of the foregoing materials. In some embodiments, the thickness of the extension layer 220, the second wiring layer 222, the drain 224, and the source 226 is 400 nanometers to 600 nanometers.

[0097] The first planar layer PL1 is located above the active area AA of the substrate SB. In some embodiments, the first planar layer PL1 does not extend to the peripheral area PA. In some embodiments, the first planar layer PL1 includes an organic material.

[0098] The second insulating layer 120 extends onto the first planar layer PL1. The third wiring layer 232 is located on the second insulating layer 120 and is connected to at least one of the second wiring layer 222, the drain 224, or the source 226 through a via hole in the first planar layer PL1. In some embodiments, the second insulating layer 120 extends into the via hole in the first planar layer PL1.

[0099] In some embodiments, the first conductive layer 230 and the third wiring layer 232 belong to the same patterned layer. For example, the first conductive layer 230 and the third wiring layer 232 are defined by the same photolithography etching manufacturing process. In some embodiments, the first conductive layer 230 and the third wiring layer 232 are single-layer or multi-layer structures. For example, the first conductive layer 230 and the third wiring layer 232 include molybdenum, titanium, aluminum, copper, or an alloy of the foregoing materials or other conductive materials or a stacked layer of the foregoing materials. In some embodiments, the thickness of the first conductive layer 230 and the third wiring layer 232 is 400 nanometers to 600 nanometers.

[0100] The second planar layer PL2 is located above the active area AA of the substrate SB. In some embodiments, the second planar layer PL2 does not extend to the peripheral area PA. In some embodiments, the second planar layer PL2 includes an organic material.

[0101] The third insulating layer 130 extends onto the second planar layer PL2. The fourth wiring layer 242 is located on the third insulating layer 130 and is connected to the third wiring layer 232 through a via hole in the second planar layer PL2. In some embodiments, the third insulating layer 130 extends into the via hole in the second planar layer PL2.

[0102] In some embodiments, the second conductive layer 240 and the fourth wiring layer 242 belong to the same patterned layer. For example, the second conductive layer 240 and the fourth wiring layer 242 are defined by the same photolithography etching manufacturing process. In some embodiments, the second conductive layer 240 and the fourth wiring layer 242 are single-layer or multi-layer structures. For example, the second conductive layer 240 and the fourth wiring layer 242 include molybdenum, titanium, aluminum, copper, or other conductive materials or an alloy of the foregoing materials or a stacked layer of the foregoing materials. In some embodiments, the thickness of the second conductive layer 240 and the fourth wiring layer 242 is 400 nanometers to 600 nanometers.

[0103] The third planar layer PL3 is located above the active area AA of the substrate SB. In some embodiments, the third planar layer PL3 does not extend to the peripheral area PA. In some embodiments, the third planar layer PL3 comprises an organic material.

[0104] The fourth insulating layer 140 extends onto the third planar layer PL3. The fifth wiring layer 252 is located on the fourth insulating layer 140 and is connected to the fourth wiring layer 242 through a via hole in the third planar layer PL3. In some embodiments, the fourth insulating layer 140 extends into the via hole of the third planar layer PL3. In some embodiments, the protective layer 150 extends to the active area AA of the substrate SB and covers the sidewalls of the fifth wiring layer 252. In some embodiments, the top surface of a part of the fifth wiring layer 252 is exposed by the protective layer 150.

[0105] In some embodiments, the contact pad layer 250 and the fifth wiring layer 252 belong to the same patterned layer. For example, the contact pad layer 250 and the fifth wiring layer 252 are defined by the same photolithography etching process. In some embodiments, the contact pad layer 250 and the fifth wiring layer 252 are single-layer or multi-layer structures. For example, the contact pad layer 250 and the fifth wiring layer 252 include molybdenum, titanium, aluminum, copper, or an alloy of the foregoing materials or other conductive materials or a stacked layer of the foregoing materials. In some embodiments, the thickness of the contact pad layer 250 and the fifth wiring layer 252 is 400 nanometers to 600 nanometers.

[0106] Figure 2 is a cross-sectional schematic view of an element substrate according to an embodiment of the present invention. It must be noted here that Figure 2 The embodiments of Figures 1A to 1C adopt the element numbers and some contents of the embodiments of

[0107] Figure 2 wherein the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted part, reference can be made to the foregoing embodiments, which will not be elaborated here. Figures 1A to 1C The main difference between the element substrate 2 of

[0108] Please refer to Figure 2 In, the insulating structure IS includes a second insulating layer 120, a first insulating layer 110, a third insulating layer 130, a fourth insulating layer 140, and a protective layer 150 stacked in sequence.

[0109] The first conductive layer 230 is located on the second insulating layer 120 and is connected to the conductive layer 210 through the second opening O2 of the second insulating layer 120. The extension layer 220 is located on the first insulating layer 110 and is connected to the first conductive layer 230 through the first opening O1 of the first insulating layer 110. The second conductive layer 240 is located on the third insulating layer 130 and is connected to the extension layer 220 through the third opening O3 of the third insulating layer 130. The pad connection layer 250 is located on the fourth insulating layer 140 and is connected to the second conductive layer 240 through the fourth opening O4 of the fourth insulating layer 140.

[0110] In this embodiment, the first conductive layer 230, the second wiring layer 222, the drain 224, and the source 226 are formed on the second insulating layer 120 and belong to the same patterned layer. In this embodiment, the extension layer 220 and the third wiring layer 232 are formed on the first insulating layer 110 and belong to the same patterned layer. In this embodiment, the second conductive layer 240 and the fourth wiring layer 242 are formed on the third insulating layer 130 and belong to the same patterned layer. In this embodiment, the pad connection layer 250 and the fifth wiring layer 252 are formed on the fourth insulating layer 140 and belong to the same patterned layer.

[0111] In some embodiments, the widths of the second opening O2, the first opening O1, the third opening O3, the fourth opening O4, and the contact window W increase in sequence.

[0112] In this embodiment, the first extension portion 220B of the extension layer 220 extends between one end of the pad connection layer 250 near the first side S1 and the top surface SBt of the substrate SB. In other words, the extension layer 220 is located between one end of the pad connection layer 250 near the first side S1 and the top surface SBt of the substrate SB. In this embodiment, a part of the first extension portion 220B does not overlap with the first conductive layer 230 and the second conductive layer 240 in the normal direction of the top surface SBt of the substrate 100. In this embodiment, by providing the first extension portion 220B, the inclination angle θ of the inclined surface 250s of the pad connection layer 250 can be reduced, thereby improving the problem that the protective layer 150 and the side electrode SE are broken due to climbing.

[0113] Figure 3 It is a cross-sectional schematic diagram of an element substrate according to an embodiment of the present invention. It must be noted here that Figure 3 The embodiments of Figures 1A to 1C adopt the component numbers and partial contents of the embodiments of

[0114] Figure 3 The element substrate 3 ofFigures 1A to 1C The main difference from the component substrate 1 is that in the bonding structure BS of the component substrate 3, the conductive layer 210, the first conductive layer 230, the second conductive layer 240, the extension layer 220, and the contact pad layer 250 are stacked in sequence.

[0115] Please refer to Figure 3 , the insulation structure IS includes a second insulation layer 120, a third insulation layer 130, a first insulation layer 110, a fourth insulation layer 140, and a protection layer 150 stacked in sequence.

[0116] The first conductive layer 230 is located on the second insulation layer 120 and is connected to the conductive layer 210 through the second opening O2 of the second insulation layer 120. The second conductive layer 240 is located on the third insulation layer 130 and is connected to the first conductive layer 230 through the third opening O3 of the third insulation layer 130. The extension layer 220 is located on the first insulation layer 110 and is connected to the second conductive layer 240 through the first opening O1 of the first insulation layer 110. The contact pad layer 250 is located on the fourth insulation layer 140 and is connected to the extension layer 220 through the fourth opening O4 of the fourth insulation layer 140.

[0117] In this embodiment, the first conductive layer 230, the second circuit layer 222, the drain 224, and the source 226 are formed on the second insulation layer 120 and belong to the same patterned layer. In this embodiment, the second conductive layer 240 and the third circuit layer 232 are formed on the third insulation layer 130 and belong to the same patterned layer. In this embodiment, the extension layer 220 and the fourth circuit layer 242 are formed on the first insulation layer 110 and belong to the same patterned layer. In this embodiment, the contact pad layer 250 and the fifth circuit layer 252 are formed on the fourth insulation layer 140 and belong to the same patterned layer.

[0118] In some embodiments, the width of the second opening O2, the width of the third opening O3, the width of the first opening O1, the width of the fourth opening O4, and the width of the contact window W increase in sequence.

[0119] In this embodiment, the first extension portion 220B of the extension layer 220 extends to between one end of the contact pad layer 250 near the first side S1 and the top surface SBt of the substrate SB. In other words, the extension layer 220 is located between one end of the contact pad layer 250 near the first side S1 and the top surface 100t of the substrate SB. In this embodiment, a part of the first extension portion 220B does not overlap with the first conductive layer 230 and the second conductive layer 240 in the normal direction of the top surface SBt of the substrate 100. In this embodiment, by providing the first extension portion 220B, the inclination angle θ of the inclined surface 250s of the contact pad layer 250 can be reduced, thereby improving the problem that the protection layer 150 and the side electrode SE are broken due to climbing.

[0120] Figure 4 is a cross-sectional schematic view of an element substrate according to an embodiment of the present invention. It should be noted here that Figure 4 the embodiment of Figures 1A to 1C adopts the element numbers and partial contents of the embodiment of

[0121] Figure 4 the element substrate 4 of Figures 1A to 1C and the main difference between the element substrate 1 of

[0122] Figure 5 is a cross-sectional schematic view of an element substrate according to an embodiment of the present invention. It should be noted here that Figure 5 the embodiment of Figures 1A to 1C adopts the element numbers and partial contents of the embodiment of

[0123] Figure 5 shows a part of the element substrate 5 near the bonding structure BS, and other parts of the element substrate 5 are omitted from the illustration. For other parts of the element substrate 5, reference can be made to Figures 1A to 1C the embodiment of

[0124] In this embodiment, the conductive layer 210 includes opposite first side 210a and second side 210b. The first side 210a of the conductive layer 210 is closer to the first side S1 of the substrate SB than the second side 210b. In some embodiments, a first wiring layer (not shown) is connected to the second side 210b of the conductive layer 210, and the width (width in the direction perpendicular to the paper surface) of the first wiring layer at the connection with the conductive layer 210 is smaller than the width of the conductive layer 210 itself.

[0125] The horizontal distance HD1 between the first opening O1 and the first side 210a of the conductive layer 210 is greater than the horizontal distance HD2 between the first opening O1 and the second side 210b of the conductive layer 210. In some embodiments, the horizontal distance HD1 is 4 micrometers to 6 micrometers. Based on the foregoing, the width of the part of the first extension 220B overlapping the conductive layer 210 is greater than the width of the part of the second extension 220C overlapping the conductive layer 210, thereby reducing the risk of the side electrode SE breaking due to climbing.

[0126] Figure 6 is an electron micrograph of a bonding structure of an element substrate according to an embodiment of the present invention.

[0127] Please refer to Figure 6 , the first extension portion 220B of the extension layer 220 extends between one end of the connection cushion layer 250 near the first side and the top surface of the substrate. In other words, the extension layer 220 is located between one end of the connection cushion layer 250 near the first side and the top surface of the substrate. In this embodiment, a part of the first extension portion 220B does not overlap with the first conductive layer 230 and the second conductive layer 240 in the normal direction of the top surface of the substrate. In this embodiment, by providing the first extension portion 220B, the inclination angle θ of the inclined surface 250s of the connection cushion layer 250 can be reduced, thereby improving the problem that the protective layer 150 and the side electrodes are broken due to climbing.

[0128] In this embodiment, the insulating structure IS includes a first insulating layer 110, a second insulating layer 120, a third insulating layer 130, a fourth insulating layer 140, and a protective layer 150 stacked in sequence. The first insulating layer 110, the second insulating layer 120, the third insulating layer 130, the fourth insulating layer 140, and the protective layer 150 include, for example, the same or similar materials, so the interfaces between the first insulating layer 110, the second insulating layer 120, the third insulating layer 130, the fourth insulating layer 140, and the protective layer 150 are not obvious or do not have interfaces.

Claims

1. A component substrate, comprising: A substrate; A bonding structure, including a conductive layer, a pad layer electrically connected to each other, and an extension layer located between the conductive layer and the pad layer; A first insulating layer, located between the extension layer and the conductive layer, and having a first opening overlapping the conductive layer; A side electrode, extending from a first side of the substrate to the pad layer and connecting the pad layer, wherein the extension layer includes: A connecting portion filling the first opening; A first extension portion and a second extension portion, located outside the first opening, wherein the first extension portion and the second extension portion respectively extend along a first direction and a second direction from the first opening, and the first extension portion extends from the first opening toward the first side of the substrate, wherein the length of the first extension portion is greater than the length of the second extension portion, and the first extension portion is located between one end of the pad layer near the first side and the top surface of the substrate; Wherein the pad layer includes an inclined surface near the first side of the substrate, wherein the side electrode overlaps the inclined surface, and the inclined surface has an inclination angle relative to the top surface of the substrate, and the inclination angle is 20 degrees to 40 degrees.

2. The component substrate according to claim 1, wherein the insulating structure includes the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer stacked in sequence, and wherein the bonding structure further includes: A first conductive layer, located on the second insulating layer and connected to the extension layer through a second opening of the second insulating layer; And A second conductive layer, located on the third insulating layer and connected to the first conductive layer through a third opening of the third insulating layer, and wherein the pad layer is located on the fourth insulating layer and connected to the second conductive layer through a fourth opening of the fourth insulating layer.

3. The component substrate according to claim 2, wherein the widths of the first opening, the second opening, the third opening, and the fourth opening increase in sequence.

4. The component substrate according to claim 2, wherein a part of the first extension portion does not overlap the first conductive layer and the second conductive layer.

5. The component substrate according to claim 1, wherein the insulating structure includes the second insulating layer, the first insulating layer, the third insulating layer, and the fourth insulating layer stacked in sequence, and wherein the bonding structure further includes: A first conductive layer, located on the second insulating layer and connected to the conductive layer through a second opening of the second insulating layer, and wherein the extension layer is located on the first insulating layer and connected to the first conductive layer through the first opening; And A second conductive layer, located on the third insulating layer and connected to the extension layer through a third opening of the third insulating layer, and wherein the pad layer is located on the fourth insulating layer and connected to the second conductive layer through a fourth opening of the fourth insulating layer.

6. The component substrate according to claim 5, wherein the widths of the second opening, the first opening, the third opening, and the fourth opening increase in sequence.

7. The component substrate according to claim 5, wherein a part of the first extension portion does not overlap the first conductive layer and the second conductive layer.

8. The component substrate as described in claim 1, wherein the insulating structure includes a second insulating layer, a third insulating layer, the first insulating layer, and a fourth insulating layer stacked in sequence, and wherein the bonding structure further includes: a first conductive layer, located on the second insulating layer and connected to the conductive layer through a second opening in the second insulating layer; and a second conductive layer, located on the third insulating layer and connected to the first conductive layer through a third opening in the third insulating layer, and wherein the extension layer is located on the first insulating layer and connected to the second conductive layer through the first opening, and wherein the contact pad layer is located on the fourth insulating layer and connected to the extension layer through a fourth opening in the fourth insulating layer.

9. The component substrate as described in claim 8, wherein the widths of the second opening, the third opening, the first opening, and the fourth opening increase in sequence.

10. The component substrate as described in claim 8, wherein a part of the first extension portion does not overlap the first conductive layer and the second conductive layer in the normal direction of the top surface of the substrate.

11. The component substrate as described in claim 1, further including: a protective layer, located on the contact pad layer and having a contact window overlapping the contact pad layer, wherein the side electrode partially fills or completely fills the contact window.

12. The component substrate as described in claim 1, wherein the horizontal distance between the first opening and the side of the conductive layer close to the first side is 4 micrometers to 6 micrometers.

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