A self-biased split-insulated gate bipolar transistor with full trench structure

Abstract

The present invention belongs to the technical field of power semiconductor devices and relates to a self-biased split-insulated gate bipolar transistor with a full-trench structure and a method for manufacturing the same. The present invention uses layout routing to lead out the floating P-region potential in the transition region, and integrates the diode and capacitor through module packaging, so that C is connected in series between the split gates 11-1, 11-2, 11-3, 11-4, 11-5, 11-6 and the emitter metal 1. The floating P-region potential is used to charge the capacitor when the device is blocked, thereby providing a bias potential for the split gate. Therefore, the split gate also has a stable potential. This potential attracts electrons near the split gate to accumulate and form an electron accumulation layer. This accumulation layer improves the injection efficiency of the channel, further enhances the drift region conductivity modulation effect, and reduces the forward conduction voltage drop of the device.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductor devices, and in particular relates to a self-biased split insulated gate bipolar transistor with a full trench structure. Background Art

[0002] The advent of electricity has fueled the rapid development of science and technology in modern society. The ability to process electricity more efficiently has long been a hot topic of scientific research worldwide. The efficient use of electricity relies heavily on power electronics systems, the core electronic components of which are semiconductor power devices. These devices are widely used in a variety of applications, including household appliances and power-intensive industrial equipment. Since the beginning of the 21st century, global warming has garnered increasing attention, making energy conservation, emission reduction, and improving energy efficiency increasingly important. As clean and renewable energy sources contribute to an increasing share of energy, society has higher expectations for energy conversion efficiency, placing even higher demands on the performance of power semiconductors, the core of energy control.

[0003] As a new generation of power electronic devices, the insulated-gate bipolar transistor (IGBT) combines the advantages of the field-effect transistor (MOSFET) and the bipolar junction transistor (BJT). It combines the MOSFET's ease of driving, low input impedance, and fast switching speed with the BJT's high on-state current density, low on-state voltage drop, low losses, and excellent stability. As a result, it has become one of the core electronic components in modern power electronic circuits and is widely used in transportation, power grids, communications, household appliances, and aerospace. The use of IGBTs has greatly improved the performance of power electronic systems.

[0004] Since the invention of IGBT, people have been committed to improving the performance of IGBT. After more than 20 years of development, multiple generations of IGBT device structures have been proposed, and the device performance has been steadily improved. Figure 1 ) By transforming the gate from a horizontal planar MOS to a vertical trench MOS structure, not only the power density and structural design space are improved, but also the adverse effects of the JFET region and the holding effect caused by the parasitic NPN are eliminated. The shielded gate trench IGBT (such as Figure 2 ) has lower gate capacitance, resulting in faster switching speeds and lower switching losses. Furthermore, compared to the high peak electric field at the bottom of the traditional trench gate structure, the SGT structure optimizes the electric field and increases the withstand voltage. Therefore, SGT-IGBTs have greater application value in high-reliability and high-performance applications. Figure 2The cellular structure of a traditional SGT-IGBT device is demonstrated. As an insulated gate-controlled IGBT, while forming the channel, the gate attracts electrons in the non-channel region through the gate voltage, forming an electron accumulation layer and further reducing the forward voltage drop. However, in an SGT-IGBT, since the shield gate is connected to the emitter, it cannot attract electrons to form an electron accumulation layer, reducing the channel electron injection efficiency. As a result, its conductivity modulation effect is weaker than that of a traditional trench IGBT, and the forward voltage drop is increased. Summary of the Invention

[0005] In order to reduce the on-state voltage drop of the device and improve the performance of the device, the present invention proposes a self-biased split insulated gate bipolar transistor with a full trench structure. The design of the multi-trench cell of the present invention improves the peak electric field at the chamfer of the gate trench, and due to the structural design of the virtual trench, the short-circuit resistance of the device is significantly improved. The present invention draws the potential from the floating P region 13 in the transition region, charges the capacitor through the diode when the IGBT is blocked, and uses the voltage on the capacitor to provide a self-biased potential for SG when the IGBT is turned on, so that electrons accumulate under the separation gates 11-1, 11-2, 11-3, 11-4, 11-5, and 11-6, thereby enhancing the forward conduction capability of the IGBT device. Its equivalent circuit is as follows Figure 7 As shown in the figure, the split gates 11-1, 11-2, 11-3, 11-4, 11-5, and 11-6 form an internal field plate structure when blocking, optimizing the peak electric field at the bottom of the trench and improving the forward voltage withstand capability of the IGBT. Furthermore, the presence of the split gates 11-1, 11-2, 11-3, 11-4, 11-5, and 11-6 weakens the capacitance effect between the gate and the collector, accelerating the switching speed of the IGBT, reducing switching losses, and further optimizing the device's characteristics.

[0006] To solve the above technical problems, an embodiment of the present invention provides a self-biased split insulated gate bipolar transistor with a full trench structure, including an active region and a transition region arranged adjacent to each other, wherein the cellular structure of the active region includes: a collector metal 10, a P-type collector region 9, an N-type electric field stop layer 8, an N-drift region 7, a P-type base region 4, an N+ emitter region 3, a P+ emitter region 2, a floating P region 13, a split gate structure, first to fifth trench emitter structures, and a first emitter metal 1-1; the collector metal 10, the P-type collector region 9, the N-type electric field stop layer 8, and the N-drift region 7 are stacked in sequence from bottom to top;

[0007] The split gate structure is located on one side of the top layer of the N-drift region 7. The first to fifth trench emitter structures are sequentially spaced and located on the other side of the top layer of the N-drift region 7. The top layer of the N-drift region 7 between adjacent trench emitter structures has a floating P region 13. The P-type base region 4 is located on the top layer of the N-drift region 7 between the first trench emitter structure and the split gate structure. The N+ emitter region 3 and the P+ emitter region 2 are in contact with each other on the side surfaces and are located on the top layer of the P-type base region 4. The first emitter metal 1-1 is located on the N+ emitter region 3 and the P+ emitter region 22.

[0008] The split gate structure includes a first split gate 11-1 and a trench gate 5, wherein the trench gate 5 is located on the first split gate 11-1, and a trench oxide layer 6 is provided between the first split gate 11-1 and the trench gate 5, and a trench oxide layer 6 is provided between the first split gate 11-1 and the trench gate 5 and the N-drift region 7, the P-type base region 4 and the N+ emitter region 3;

[0009] The cell structure of the transition region includes: a collector metal 10, a P-type collector region 9, an N-type electric field stop layer 8, an N-drift region 7, a floating P region 13, sixth to eighth trench emitter structures, a metal layer 14 and a second emitter metal 1-2; the collector metal 10, the P-type collector region 9, the N-type electric field stop layer 8 and the N-drift region 7 are stacked in sequence from bottom to top;

[0010] The sixth to eighth trench emitter structures are sequentially spaced apart and located on one side of the top layer of the N-drift region 7. A floating P region 13 is provided in the top layer of the N-drift region 7 between adjacent trench emitter structures. A floating P region 13 is also provided on the other side of the top layer of the N-drift region 7. A second emitter metal 1-2 is located on the floating P region 13 between the sixth trench emitter structure and the seventh trench emitter structure. A metal layer 14 is located on the floating P region 13 between the seventh trench emitter structure and the eighth trench emitter structure.

[0011] The first to eighth trench emitter structures each include a trench emitter, a split gate, and a trench oxide layer 6, wherein the split gate is located below the trench emitter, and the side surfaces of the fifth trench emitter 12-5 and the sixth split gate 11-6 are in contact with the side surfaces of the sixth trench emitter 12-6 and the seventh split gate 11-7, respectively, and a trench oxide layer 6 is provided between the trench emitter and the split gate and on the side surfaces of the trench emitter and the split gate;

[0012] The floating P region 13 in the transition region cell structure is connected to the P region of the external diode through the metal layer 14, the split gate in the active region cell structure is connected to the N region of the external diode, and the external capacitor is connected between the first split gate 11-1 and the first emitter metal 1-1.

[0013] To solve the above technical problems, an embodiment of the present invention provides a self-biased split insulated gate bipolar transistor with a full trench structure, including an active region and a transition region arranged adjacent to each other, wherein the cellular structure of the active region includes: a collector metal 10, a P-type collector region 9, an N-type electric field stop layer 8, an N-drift region 7, a P-type base region 4, an N+ emitter region 3, a P+ emitter region 2, a floating P region 13, a split gate structure, first to fifth trench emitter structures, and a first emitter metal 1-1; the collector metal 10, the P-type collector region 9, the N-type electric field stop layer 8, and the N-drift region 7 are stacked in sequence from bottom to top;

[0014] The split gate structure is located on one side of the top layer of the N-drift region 7. The first to fifth trench emitter structures are sequentially spaced and located on the other side of the top layer of the N-drift region 7. The top layer of the N-drift region 7 between adjacent trench emitter structures has a floating P region 13. The P-type base region 4 is located on the top layer of the N-drift region 7 between the first trench emitter structure and the split gate structure. The N+ emitter region 3 and the P+ emitter region 2 are in contact with each other on the side surfaces and are located on the top layer of the P-type base region 4. The first emitter metal 1-1 is located on the N+ emitter region 3 and the P+ emitter region 22.

[0015] The split gate structure includes a first split gate 11-1 and a trench gate 5, wherein the trench gate 5 is located on the first split gate 11-1, and a trench oxide layer 6 is provided between the first split gate 11-1 and the trench gate 5, and a trench oxide layer 6 is provided between the first split gate 11-1 and the trench gate 5 and the N-drift region 7, the P-type base region 4 and the N+ emitter region 3;

[0016] The cell structure of the transition region includes: a collector metal 10, a P-type collector region 9, an N-type electric field stop layer 8, an N-drift region 7, a floating P region 13, a sixth trench emitter structure, a seventh trench emitter structure, a polysilicon diode structure, a metal layer 14 and a second emitter metal 1-2; the collector metal 10, the P-type collector region 9, the N-type electric field stop layer 8 and the N-drift region 7 are stacked in sequence from bottom to top;

[0017] A sixth trench emitter structure and a seventh trench emitter structure are spaced apart and located on one side of the top layer of the N-drift region 7. A floating P region 13 is provided in the top layer of the N-drift region 7 between adjacent trench emitter structures. A floating P region 13 is also provided in the other side of the top layer of the N-drift region 7. A polysilicon diode structure is provided in the floating P region 13 in the other side of the top layer of the N-drift region 7. A second emitter metal 1-2 is located on the floating P region 13 between the sixth trench emitter structure and the seventh trench emitter structure. A metal layer 14 is located on the floating P region 13 between the seventh trench emitter structure and the polysilicon diode structure.

[0018] The first to seventh trench emitter structures each include a trench emitter, a split gate, and a trench oxide layer 6, wherein the split gate is located below the trench emitter, and the side surfaces of the fifth trench emitter 12-5 and the sixth split gate 11-6 are in contact with the side surfaces of the sixth trench emitter 12-6 and the seventh split gate 11-7, respectively. Trench oxide layers 6 are provided between the trench emitter and the split gate, as well as on the side surfaces of the trench emitter and the split gate. The polycrystalline silicon diode structure includes a polycrystalline silicon diode P-type region 16 and a polycrystalline silicon diode N-type region 17. The polycrystalline silicon diode P-type region 16 is located on the polycrystalline silicon diode N-type region 17, and the side surfaces of the polycrystalline silicon diode P-type region 16 and the polycrystalline silicon diode N-type region 17 are both provided with trench oxide layers 6.

[0019] The floating P region 13 in the transition region cell structure is connected to the P region of the external diode through the metal layer 14, the split gate in the active region cell structure is connected to the N region of the external diode, and the external capacitor is connected between the first split gate 11-1 and the first emitter metal 1-1.

[0020] On the basis of the above technical solution, the present invention can also be improved as follows.

[0021] Furthermore, an N-type carrier storage layer 18 is provided below the P-type base region 4 .

[0022] Furthermore, the N-type electric field stop layer 8 is formed by a multi-step hydrogen implantation process.

[0023] Furthermore, a superjunction structure is introduced in the N-drift region 7, and the superjunction structure includes a P column 19 and an N column 20. The P column 19 and the N column 20 are located in the N-drift region 7 with their sides in contact with each other. The P-type base region 4 is located above the N column 20, and the contact surface between the P column 19 and the N column 20 is located below the trench emitter structure.

[0024] Furthermore, one side of the P-type collector region 9 has an N region 21 .

[0025] Furthermore, the floating P region 13 of the active area is replaced by a P-type base region 4, and the trench emitter of the active area is replaced by a trench gate 5. The N+ emitter region 3 and the P+ emitter region 2 are in contact with each other on the side and are located on the top layer of the P-type base region 4, and the N+ emitter region 3 is located on both sides of the P+ emitter region 2, and the emitter metal 1 is located on the N+ emitter region 3 and the P+ emitter region 2.

[0026] Furthermore, the materials used for the device structure include silicon, silicon carbide, gallium nitride, gallium oxide or diamond.

[0027] To solve the above technical problems, an embodiment of the present invention provides a method for manufacturing the self-biased split-insulated gate bipolar transistor with a full trench structure, comprising the following steps:

[0028] Step 1: Select an N-type lightly doped FZ silicon wafer as the N-drift region 7 of the device;

[0029] Step 2: Using a photolithography process, high-temperature ion implantation of P-type impurities into the N-drift region 7 is followed by annealing to form a floating P region 13 of the device, and a pre-oxidation layer is grown on the surface of the silicon wafer;

[0030] Step 3: using a photolithography process to form the first to sixth trenches, and forming a trench oxide layer 6 on the sidewalls and bottoms of the first to sixth trenches through a thermal oxidation process;

[0031] Step 4: Depositing N-doped polysilicon in the first trench to the sixth trench to form a polysilicon trench gate 29;

[0032] Step 5: forming an oxidation shield layer a by a thermal oxidation process, etching away the oxide layer on the surface of the polysilicon trench gate and the polysilicon on the polysilicon trench gate by a photolithography process to form split gates 11-1 to 11-6, thermally oxidizing the surfaces of the split gates 11-1 to 11-6 to form an oxide isolation layer, and depositing the layer again to form a trench gate 5 in the first trench, and forming first trench emitters 12-1 to fifth trench emitters 12-5 in the second to sixth trenches;

[0033] Step 6: Using a photolithography process, high-temperature ion implantation of P-type impurities followed by annealing to form the P-type base region 4 of the device;

[0034] Step 7: Implant N-type impurities by high-temperature ion implantation and annealing to form the N+ emitter region 3 of the device;

[0035] Step 8: Produce the P+ emitter region 2 of the device by high-temperature ion implantation of P-type impurities and annealing;

[0036] Step 9: Depositing Al metal to form emitter metal 1;

[0037] Step 10: Flip the silicon wafer, thin the wafer, and implant N-type impurities and P-type impurities on the back of the wafer through high-energy ion implantation and annealing to form an N-type electric field stop layer 8 and a P-type collector region 9 on its surface;

[0038] Step 11: Deposit metal on the back side of the silicon wafer to form collector metal 10 on the surface of the P-type collector region 9.

[0039] Furthermore, in order to simplify the description, the above device structure and preparation method are described by taking an N-channel IGBT device as an example, but the present invention is also applicable to the preparation of a P-channel IGBT device.

[0040] The working principle of the present invention is: when the gate electrode 5 is connected to a high potential higher than the device threshold voltage, the collector 10 is connected to a high potential, and the emitter 1 is connected to a low potential, the device operates in the on state, the P+ collector region 9 injects holes into the N-drift region 7, and the N+ emitter region 3 injects electrons into the N-drift region 7. The existence of electron-hole pairs causes a conductivity modulation effect to occur in the drift region.

[0041] The present invention uses layout routing to lead out the potential of the floating P region in the transition region, and integrates the diode and capacitor through modular packaging, so that C is connected in series between the split gates 11-1, 11-2, 11-3, 11-4, 11-5, and 11-6 and the emitter metal 1. When the device is blocked, the floating P region potential is used to charge the capacitor, thereby providing a bias potential for the split gate. As a result, the SG gate also has a stable potential. This potential attracts electrons near the SG gate to accumulate, forming an electron accumulation layer. This accumulation layer improves the injection efficiency of the channel, further enhances the drift region conductivity modulation effect, and reduces the forward conduction voltage drop of the device.

[0042] Beneficial effects of the present invention:

[0043] The present invention utilizes the potential of the floating P region in the transition region to provide a bias potential for the split gates 11-1, 11-2, 11-3, 11-4, 11-5, and 11-6. This creates an electron accumulation capacity beneath the trench, enhancing the conductivity modulation effect and, consequently, the forward conduction capability of the device. Compared to traditional split-gate structures, the introduction of a self-biased structure simultaneously improves both the device's conduction capability and switching performance, eliminating the negative effects of the split gate. While improving switching losses and increasing switching speed, it also optimizes the device's forward conduction capability, improving the trade-off between the device's forward voltage drop and turn-off losses.

[0044] The gate oxide layer 6 around the separated polysilicon gate 11 is not limited by the threshold voltage design, so its thickness can be further increased to improve the device's withstand voltage and oxide layer reliability, thereby enhancing device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 Schematic diagram of the cell structure of a traditional trench gate IGBT;

[0046] Figure 2 Schematic diagram of the cell structure of a traditional shielded gate trench IGBT;

[0047] Figure 3 Schematic diagram of the layout structure of a self-biased split insulated gate bipolar transistor with a full trench structure according to the first embodiment of the present invention;

[0048] Figure 4 For the Figure 3Schematic diagram of the cell structure of the active area and transition area after cutting along the cutting line AA' shown;

[0049] Figure 5 Schematic diagram of a cell structure of an active region of a self-biased split insulated gate bipolar transistor with a full trench structure according to a first embodiment of the present invention;

[0050] Figure 6 A schematic diagram of a cell structure of a transition region of a self-biased split insulated gate bipolar transistor with a full trench structure according to a first embodiment of the present invention;

[0051] Figure 7 FIG1 is an equivalent circuit diagram of a self-biased split insulated gate bipolar transistor with a full trench structure according to the first embodiment of the present invention;

[0052] Figure 8 A schematic diagram of a cell structure of a transition region of a self-biased split insulated gate bipolar transistor with a full trench structure according to a second embodiment of the present invention;

[0053] Figure 9 Schematic diagram of a cell structure of an active region of a self-biased split insulated gate bipolar transistor with a full trench structure according to a third embodiment of the present invention;

[0054] Figure 10 Schematic diagram of a cell structure of an active region of a self-biased split insulated gate bipolar transistor with a full trench structure according to a fourth embodiment of the present invention;

[0055] Figure 11 Schematic diagram of a cell structure of an active region of a self-biased split insulated gate bipolar transistor with a full trench structure according to a fifth embodiment of the present invention;

[0056] Figure 12 Schematic diagram of a cell structure of an active region of a self-biased split insulated gate bipolar transistor with a full trench structure according to a sixth embodiment of the present invention;

[0057] Figure 13 Schematic diagram of a cell structure of an active region of a self-biased split insulated gate bipolar transistor with a full trench structure according to a seventh embodiment of the present invention;

[0058] Figure 14-Figure 25 1 is a schematic diagram of a process flow of a method for manufacturing a self-biased split insulated gate bipolar transistor with a full trench structure according to an eighth embodiment of the present invention.

[0059] In the accompanying drawings, the components represented by the reference numerals are as follows:

[0060] 1. Emitter metal, 1-1. First emitter metal, 1-2. Second emitter metal, 2. P+ emitter region, 3. N+ emitter region, 4. P-type base region, 5. Trench gate, 6. Trench oxide layer, 7. N-drift region, 8. N-type electric field stop layer, 9. P-type collector region, 10. Collector metal, 11-1 to 11-9, first split gate to ninth split gate, 12-1 to 12-8, first trench emitter to eighth trench emitter, 13. Floating P region, 14. Metal layer, 16. Polysilicon diode P-type region, 17. Polysilicon diode N-type region, 18. N-type carrier storage layer, 19. P column, 20. N column, 21. N region, 29. Polysilicon trench gate 29. DETAILED DESCRIPTION

[0061] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0062] like Figure 3-7 As shown, the first embodiment of the present invention provides a self-biased split insulated gate bipolar transistor with a full trench structure, including an active region and a transition region arranged adjacent to each other, such as Figure 3 As shown, the cell structure of the active region is as follows: Figure 4-5 As shown, it includes: a collector metal 10, a P-type collector region 9, an N-type electric field stop layer 8, an N-drift region 7, a P-type base region 4, an N+ emitter region 3, a P+ emitter region 2, a floating P region 13, a split gate structure, first to fifth trench emitter structures and a first emitter metal 1-1; the collector metal 10, the P-type collector region 9, the N-type electric field stop layer 8 and the N-drift region 7 are stacked in sequence from bottom to top;

[0063] The split gate structure is located on one side of the top layer of the N-drift region 7. The first to fifth trench emitter structures are sequentially spaced and located on the other side of the top layer of the N-drift region 7. The top layer of the N-drift region 7 between adjacent trench emitter structures has a floating P region 13. The P-type base region 4 is located on the top layer of the N-drift region 7 between the first trench emitter structure and the split gate structure. The N+ emitter region 3 and the P+ emitter region 2 are in contact with each other on the side surfaces and are located on the top layer of the P-type base region 4. The first emitter metal 1-1 is located on the N+ emitter region 3 and the P+ emitter region 22.

[0064] The split gate structure includes a first split gate 11-1 and a trench gate 5, wherein the trench gate 5 is located on the first split gate 11-1, and a trench oxide layer 6 is provided between the first split gate 11-1 and the trench gate 5, and a trench oxide layer 6 is provided between the first split gate 11-1 and the trench gate 5 and the N-drift region 7, the P-type base region 4 and the N+ emitter region 3;

[0065] The cellular structure of the transition zone is as follows: Figure 4 and Figure 6 As shown, it includes: a collector metal 10, a P-type collector region 9, an N-type electric field stop layer 8, an N-drift region 7, a floating P region 13, the sixth to eighth trench emitter structures, a metal layer 14 and a second emitter metal 1-2; the collector metal 10, the P-type collector region 9, the N-type electric field stop layer 8 and the N-drift region 7 are stacked in sequence from bottom to top;

[0066] The sixth to eighth trench emitter structures are sequentially spaced apart and located on one side of the top layer of the N-drift region 7. A floating P region 13 is provided in the top layer of the N-drift region 7 between adjacent trench emitter structures. A floating P region 13 is also provided on the other side of the top layer of the N-drift region 7. A second emitter metal 1-2 is located on the floating P region 13 between the sixth trench emitter structure and the seventh trench emitter structure. A metal layer 14 is located on the floating P region 13 between the seventh trench emitter structure and the eighth trench emitter structure.

[0067] The first to eighth trench emitter structures each include a trench emitter, a split gate, and a trench oxide layer 6, wherein the split gate is located below the trench emitter, the side surfaces of the fifth trench emitter 12-5 and the sixth split gate 11-6 are in contact with the side surfaces of the sixth trench emitter 12-6 and the seventh split gate 11-7, and a trench oxide layer 6 is provided between the trench emitter and the split gate and on the side surfaces of the trench emitter and the split gate;

[0068] The floating P region 13 in the transition region cell structure is connected to the P region of the external diode through the metal layer 14, the split gate in the active region cell structure is connected to the N region of the external diode, and the external capacitor is connected between the first split gate 11-1 and the first emitter metal 1-1.

[0069] In this embodiment, the doping concentration of the P-type base region 4 is 3×10 16 cm -3 ~2×10 17 cm -3 , with a depth of 3 to 3.5 μm; the doping concentration of the N+ emitter region 3 is 5×10 18 cm -3 ~1×10 21 cm -3 , with a depth of 0.2 to 0.5 μm; the thickness of the gate dielectric layer 6 is 80 to 120 nm; the depth of the trench gate electrode 5 is 4 to 6 μm; the depth of the split gate electrodes 11-1, 11-2, 11-3, 11-4, 11-5, and 11-6 is 0.5 to 2 μm; the depth of the trench emitters 12-1, 12-2, 12-3, 12-4, and 12-5 is 5 to 8 μm; the doping concentration of the N-drift region 7 is 5×1012 cm -3 ~2×10 14 cm -3 , with a thickness of 60 to 700 μm; the doping concentration of the N-type electric field stop layer 8 is 5×10 15 cm -3 ~5×10 16 cm -3 , with a thickness of 5 to 20 μm; the doping concentration of the P-type collector region 9 is 1×10 17 cm -3 ~1×10 19 cm -3 , thickness is 0.5~5μm; cell width is 20~40μm.

[0070] like Figure 8 As shown, a self-biased split insulated gate bipolar transistor with a full trench structure provided by the second embodiment of the present invention includes an active region and a transition region arranged adjacent to each other. The cellular structure of the active region includes: a collector metal 10, a P-type collector region 9, an N-type electric field stop layer 8, an N-drift region 7, a P-type base region 4, an N+ emitter region 3, a P+ emitter region 2, a floating P region 13, a split gate structure, first to fifth trench emitter structures, and a first emitter metal 1-1; the collector metal 10, the P-type collector region 9, the N-type electric field stop layer 8, and the N-drift region 7 are stacked in sequence from bottom to top;

[0071] The split gate structure is located on one side of the top layer of the N-drift region 7. The first to fifth trench emitter structures are sequentially spaced and located on the other side of the top layer of the N-drift region 7. The top layer of the N-drift region 7 between adjacent trench emitter structures has a floating P region 13. The P-type base region 4 is located on the top layer of the N-drift region 7 between the first trench emitter structure and the split gate structure. The N+ emitter region 3 and the P+ emitter region 2 are in contact with each other on the side surfaces and are located on the top layer of the P-type base region 4. The first emitter metal 1-1 is located on the N+ emitter region 3 and the P+ emitter region 22.

[0072] The split gate structure includes a first split gate 11-1 and a trench gate 5, wherein the trench gate 5 is located on the first split gate 11-1, and a trench oxide layer 6 is provided between the first split gate 11-1 and the trench gate 5, and a trench oxide layer 6 is provided between the first split gate 11-1 and the trench gate 5 and the N-drift region 7, the P-type base region 4 and the N+ emitter region 3;

[0073] The cell structure of the transition region includes: a collector metal 10, a P-type collector region 9, an N-type electric field stop layer 8, an N-drift region 7, a floating P region 13, a sixth trench emitter structure, a seventh trench emitter structure, a polysilicon diode structure, a metal layer 14 and a second emitter metal 1-2; the collector metal 10, the P-type collector region 9, the N-type electric field stop layer 8 and the N-drift region 7 are stacked in sequence from bottom to top;

[0074] A sixth trench emitter structure and a seventh trench emitter structure are spaced apart and located on one side of the top layer of the N-drift region 7. A floating P region 13 is provided in the top layer of the N-drift region 7 between adjacent trench emitter structures. A floating P region 13 is also provided in the other side of the top layer of the N-drift region 7. A polysilicon diode structure is provided in the floating P region 13 in the other side of the top layer of the N-drift region 7. A second emitter metal 1-2 is located on the floating P region 13 between the sixth trench emitter structure and the seventh trench emitter structure. A metal layer 14 is located on the floating P region 13 between the seventh trench emitter structure and the polysilicon diode structure.

[0075] The first to seventh trench emitter structures each include a trench emitter, a split gate, and a trench oxide layer 6, wherein the split gate is located below the trench emitter, and the side surfaces of the fifth trench emitter 12-5 and the sixth split gate 11-6 are in contact with the side surfaces of the sixth trench emitter 12-6 and the seventh split gate 11-7, respectively. Trench oxide layers 6 are provided between the trench emitter and the split gate, as well as on the side surfaces of the trench emitter and the split gate. The polycrystalline silicon diode structure includes a polycrystalline silicon diode P-type region 16 and a polycrystalline silicon diode N-type region 17. The polycrystalline silicon diode P-type region 16 is located on the polycrystalline silicon diode N-type region 17, and the side surfaces of the polycrystalline silicon diode P-type region 16 and the polycrystalline silicon diode N-type region 17 are both provided with trench oxide layers 6.

[0076] The floating P region 13 in the transition region cell structure is connected to the P region of the external diode through the metal layer 14, the split gate in the active region cell structure is connected to the N region of the external diode, and the external capacitor is connected between the first split gate 11-1 and the first emitter metal 1-1.

[0077] In the above embodiment, a polycrystalline diode structure is fabricated in the emitter trench. 16 is the polycrystalline silicon diode P-type region, which has the same potential as the floating P-region 13. 17 is the polycrystalline silicon diode N-type region, which has the same potential as the separated gate, thereby realizing internal integration of the diode structure.

[0078] like Figure 9 As shown, the third embodiment of the present invention provides a self-biased split insulated gate bipolar transistor with a full trench structure. Based on the first embodiment, an N-type carrier storage layer 18 is provided below the P-type base region 4.

[0079] The above embodiment can prevent holes from the drift region 7 from being extracted by the P-type base region 4 during forward conduction, thereby increasing the carrier concentration in the drift region 7 and enhancing the conductivity modulation effect.

[0080] like Figure 10 As shown, the fourth embodiment of the present invention provides a self-biased split insulated gate bipolar transistor with a full trench structure. On the basis of the first embodiment, a super junction structure is introduced in the N-drift region 7. The super junction structure includes a P column 19 and an N column 20. The P column 19 and the N column 20 are located in the N-drift region 7 with their sides in contact with each other. Above the N column 20 is a P-type base region 4. The contact surface between the P column 19 and the N column 20 is below the trench emitter structure.

[0081] The above embodiment replaces the N-drift region 7 with a super junction structure of N / P columns with a higher concentration on the basis of embodiment 1. The N column 20 is the substrate, and the P column 19 is realized by trenching and filling single crystal silicon or multiple epitaxy and ion implantation. The concentrations of the two are similar, and the doping concentration is set to 1×10 14 cm -3 -5×10 16 cm -3 The column width is 2μm-12μm, and the drift region thickness is reduced by 20-30% according to the voltage resistance requirements.

[0082] Compared with Example 1, the introduction of the super junction structure is beneficial to improving the withstand voltage and trade-off performance of the device. At the same time, the laterally depleted drift column region assists the longitudinal depletion layer expansion during device switching, further improving the switching speed of the device.

[0083] like Figure 11 As shown, the fifth embodiment of the present invention provides a self-biased split insulated gate bipolar transistor with a full trench structure. Based on the first embodiment, the N-type electric field stop layer 8 is formed by a multi-step hydrogen implantation process.

[0084] The above embodiment introduces a thick FS layer 8 for hydrogen implantation between the N-drift region and the P+ collector region based on the embodiment 1. The hydrogen implantation process has the advantages of large implantation depth at low energy and low annealing temperature, and is very suitable for replacing the high temperature pre-diffusion process to form deep implantation of IGBT. The number of back high energy H implantation is set to four, using 1×10 12 cm -3 -1×10 15 cm -3 The implantation dose range is within 20-200keV and the implantation energy range is 20-200keV.

[0085] Compared with Example 1, the N-drift region formed by the hydrogen-implanted field stop layer and the NN-junction of the N+FS layer have a gentler concentration gradient, which can effectively increase the dynamic avalanche withstand capability of the device.

[0086] like Figure 12 As shown, the sixth embodiment of the present invention provides a self-biased split insulated gate bipolar transistor with a full trench structure. Based on the first embodiment, an N region 21 is provided on one side of the P-type collector region 9.

[0087] The above embodiment introduces a portion of the N region 18 into the collector P region 9 on the basis of embodiment 1 to realize the RC-IGBT structure, thereby integrating the diode in the IGBT module into the IGBT structure. The N region 18 is realized by back injection, and the doping concentration is 1×10 17 cm -3 ~1×10 19 cm -3 .

[0088] Compared with Example 1, the introduction of the collector N region integrates the diode in the IGBT module into the IGBT structure, thereby improving the module integration.

[0089] like Figure 13 As shown, the seventh embodiment of the present invention provides a self-biased split insulated gate bipolar transistor with a full trench structure. On the basis of the first embodiment, the floating P region 13 of the active region is replaced by a P-type base region 4, and the trench emitter of the active region is replaced by a trench gate 5. The N+ emitter region 3 and the P+ emitter region 2 are in contact with each other on the side and are located on the top layer of the P-type base region 4. The N+ emitter region 3 is located on both sides of the P+ emitter region 2, and the emitter metal 1 is located on the N+ emitter region 3 and the P+ emitter region 2.

[0090] This embodiment can significantly improve the conduction performance of the device through full connection in an application environment without short-circuit capability requirements, thereby effectively reducing the operating loss of the device.

[0091] An eighth embodiment of the present invention provides a method for manufacturing the self-biased split-insulated gate bipolar transistor with a full trench structure, comprising the following steps:

[0092] Step 1: Select an N-type lightly doped FZ silicon wafer as the N-drift region 7 of the device, such as Figure 14 As shown;

[0093] Step 2: Using a photolithography process, high-temperature ion implantation of P-type impurities into the N-drift region 7 followed by annealing forms a floating P region 13 of the device, as shown in FIG. Figure 15 As shown, a pre-oxidation layer is grown on the surface of the silicon wafer;

[0094] Step 3: Use photolithography to etch the active area around the field oxide to form an oxide layer, and use photolithography to form the first to sixth trenches, such as Figure 16 As shown, sacrificial oxygen is grown to remove surface contamination after etching, and then a trench oxide layer 6 is formed on the sidewalls and bottom of the first to sixth trenches through a thermal oxidation process;

[0095] Step 4: Deposit N-doped polysilicon in the first trench to the sixth trench, and etch it by photolithography to form a polysilicon trench gate, such as Figure 17 As shown;

[0096] Step 5: Form an oxidation shield layer a by a thermal oxidation process, and etch away the oxide layer on the surface of the polysilicon trench gate and the polysilicon on the polysilicon trench gate by a photolithography process to form the first split gate 11-1 to the sixth split gate 11-6. Thermal oxidation is performed on the surface of the first split gate 11-1 to the sixth split gate 11-6 to form an oxide isolation layer and deposited again to form a trench gate 5 in the first trench, and form the first trench emitter 12-1 to the fifth trench emitter 12-5 in the second to sixth trenches, as shown in FIG. Figure 18-19 As shown;

[0097] Step 6: Use photolithography process and anneal after high temperature ion implantation of P-type impurities to form the P-type base region 4 of the device, as shown in FIG. Figure 20 As shown;

[0098] Step 7: Make the N+ emitter region 3 of the device by high temperature ion implantation of N-type impurities and annealing, as shown in FIG. Figure 21 As shown;

[0099] Step 8: Make the P+ emitter region 2 of the device by high temperature ion implantation of P-type impurities and annealing, as shown in Figure 22 As shown;

[0100] Step 9: Al metal deposition is performed to form emitter metal 1, such as Figure 23 As shown;

[0101] Step 10: Flip the silicon wafer, reduce the thickness of the silicon wafer, and form an N-type electric field stop layer 8 and a P-type collector region 9 on the back of the silicon wafer by high-energy ion implantation of N-type impurities and ion implantation of P-type impurities and annealing. Figure 24 As shown;

[0102] Step 11: Deposit metal on the back of the silicon wafer to form collector metal 10 on the surface of the P-type collector region 9, as shown in FIG. Figure 25 shown.

[0103] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0104] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0105] In the present invention, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0106] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0107] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0108] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A self-biased split-insulated gate bipolar transistor with a full trench structure, characterized in that: The invention comprises an active region and a transition region arranged adjacent to each other, wherein the cell structure of the active region comprises: a collector metal (10), a P-type collector region (9), an N-type electric field stop layer (8), an N-drift region (7), a P-type base region (4), an N+ emitter region (3), a P+ emitter region (2), a floating P region (13), a split gate structure, first to fifth trench emitter structures and a first emitter metal (1-1); the collector metal (10), the P-type collector region (9), the N-type electric field stop layer (8) and the N-drift region (7) are stacked in sequence from bottom to top; The split gate structure is located on one side of the top layer of the N-drift region (7); the first to fifth trench emitter structures are sequentially spaced and located on the other side of the top layer of the N-drift region (7); the top layer of the N-drift region (7) between adjacent trench emitter structures has a floating P region (13); the P-type base region (4) is located on the top layer of the N-drift region (7) between the first trench emitter structure and the split gate structure; the N+ emitter region (3) and the P+ emitter region (2) are in contact with each other on the side surface and are located on the top layer of the P-type base region (4); and the first emitter metal (1-1) is located on the N+ emitter region (3) and the P+ emitter region (2); The split gate structure comprises a first split gate (11-1) and a trench gate (5), wherein the trench gate (5) is located on the first split gate (11-1), a trench oxide layer (6) is provided between the first split gate (11-1) and the trench gate (5), and a trench oxide layer (6) is provided between the first split gate (11-1) and the trench gate 5 and the N-drift region (7), the P-type base region (4) and the N+ emitter region (3); The cell structure of the transition region comprises: a collector metal (10), a P-type collector region (9), an N-type electric field stop layer (8), an N-drift region (7), a floating P region (13), sixth to eighth trench emitter structures, a metal layer (14) and a second emitter metal (1-2); the collector metal (10), the P-type collector region (9), the N-type electric field stop layer (8) and the N-drift region (7) are stacked in sequence from bottom to top; The sixth to eighth trench emitter structures are sequentially spaced apart and located on one side of the top layer of the N-drift region (7); a floating P region (13) is provided in the top layer of the N-drift region (7) between adjacent trench emitter structures; a floating P region (13) is also provided on the other side of the top layer of the N-drift region (7); a second emitter metal (1-2) is located on the floating P region (13) between the sixth trench emitter structure and the seventh trench emitter structure; and a metal layer (14) is located on the floating P region (13) between the seventh trench emitter structure and the eighth trench emitter structure; The first to eighth trench emitter structures each include a trench emitter, a split gate, and a trench oxide layer (6); the split gate is located below the trench emitter; the side surfaces of the fifth trench emitter (12-5) and the sixth split gate (11-6) are in contact with the side surfaces of the sixth trench emitter (12-6) and the seventh split gate (11-7), respectively; and a trench oxide layer (6) is provided between the trench emitter and the split gate, and on the side surfaces of the trench emitter and the split gate; The floating P region 13 in the transition region cell structure is connected to the P region of the external diode through a metal layer (14), the split gate in the active region cell structure is connected to the N region of the external diode, and the external capacitor is connected between the first split gate (11-1) and the first emitter metal (1-1).

2. A self-biased split-insulated gate bipolar transistor with a full trench structure, characterized in that: The invention comprises an active region and a transition region arranged adjacent to each other, wherein the cell structure of the active region comprises: a collector metal (10), a P-type collector region (9), an N-type electric field stop layer (8), an N-drift region (7), a P-type base region (4), an N+ emitter region (3), a P+ emitter region (2), a floating P region (13), a split gate structure, first to fifth trench emitter structures and a first emitter metal (1-1); the collector metal (10), the P-type collector region (9), the N-type electric field stop layer (8) and the N-drift region (7) are stacked in sequence from bottom to top; The split gate structure is located on one side of the top layer of the N-drift region (7); the first to fifth trench emitter structures are sequentially spaced and located on the other side of the top layer of the N-drift region (7); the top layer of the N-drift region (7) between adjacent trench emitter structures has a floating P region (13); the P-type base region (4) is located on the top layer of the N-drift region (7) between the first trench emitter structure and the split gate structure; the N+ emitter region (3) and the P+ emitter region (2) are in contact with each other on the side surface and are located on the top layer of the P-type base region (4); and the first emitter metal (1-1) is located on the N+ emitter region (3) and the P+ emitter region (2); The split gate structure comprises a first split gate (11-1) and a trench gate (5), wherein the trench gate (5) is located on the first split gate (11-1), a trench oxide layer (6) is provided between the first split gate (11-1) and the trench gate (5), and a trench oxide layer (6) is provided between the first split gate (11-1) and the trench gate (5) and an N-drift region (7), a P-type base region (4), and an N+ emitter region (3); The cell structure of the transition region comprises: a collector metal (10), a P-type collector region (9), an N-type electric field stop layer (8), an N-drift region (7), a floating P region (13), a sixth trench emitter structure, a seventh trench emitter structure, a polysilicon diode structure, a metal layer (14) and a second emitter metal (1-2); the collector metal (10), the P-type collector region (9), the N-type electric field stop layer (8) and the N-drift region (7) are stacked in sequence from bottom to top; The sixth trench emitter structure and the seventh trench emitter structure are spaced apart and located on one side of the top layer of the N-drift region (7); a floating P region (13) is provided in the top layer of the N-drift region (7) between adjacent trench emitter structures; a floating P region (13) is also provided in the other side of the top layer of the N-drift region (7); a polysilicon diode structure is provided in the floating P region (13) in the other side of the top layer of the N-drift region (7); a second emitter metal (1-2) is located on the floating P region (13) between the sixth trench emitter structure and the seventh trench emitter structure; and a metal layer (14) is located on the floating P region (13) between the seventh trench emitter structure and the polysilicon diode structure; The first to seventh trench emitter structures each include a trench emitter, a split gate, and a trench oxide layer (6); the split gate is located below the trench emitter; the side surfaces of the fifth trench emitter (12-5) and the sixth split gate (11-6) are in contact with the side surfaces of the sixth trench emitter (12-6) and the seventh split gate (11-7), respectively; and the trench emitter and the split gates, as well as the side surfaces of the trench emitter and the split gates, all have a trench oxide layer (6); the polycrystalline silicon diode structure includes a polycrystalline silicon diode P-type region (16) and a polycrystalline silicon diode N-type region (17); the polycrystalline silicon diode P-type region (16) is located on the polycrystalline silicon diode N-type region (17), and the side surfaces of the polycrystalline silicon diode P-type region (16) and the polycrystalline silicon diode N-type region (17) all have a trench oxide layer (6); A floating P region (13) in the transition region cell structure is connected to the P region of an external diode through a metal layer (14), a split gate in the active region cell structure is connected to the N region of the external diode, and an external capacitor is connected between the first split gate (11-1) and the first emitter metal (1-1).

3. A self-biased split-insulated gate bipolar transistor with a full trench structure according to any one of claims 1 to 2, characterized in that: An N-type carrier storage layer (18) is provided below the P-type base region 4.

4. A self-biased split-insulated gate bipolar transistor with a full trench structure according to any one of claims 1 to 2, characterized in that: The N-type electric field stopping layer (8) is formed by a multi-step hydrogen implantation process.

5. A self-biased split insulated gate bipolar transistor with a full trench structure according to any one of claims 1 to 2, characterized in that: A superjunction structure is introduced into the N-drift region (7), the superjunction structure comprising a P column (19) and an N column (20), the P column 19 and the N column (20) being located in the N-drift region (7) with their sides in contact with each other, a P-type base region 4 being located above the N column (20), and a contact surface between the P column (19) and the N column (20) being located below the trench emitter structure.

6. A self-biased split-insulated gate bipolar transistor with a full trench structure according to any one of claims 1 to 2, characterized in that: One side of the P-type collector region 9 has an N region (21).

7. A self-biased split-insulated gate bipolar transistor with a full trench structure according to any one of claims 1 to 2, characterized in that: The floating P region (13) of the active region is replaced by a P-type base region (4), the trench emitter of the active region is replaced by a trench gate (5), the N+ emitter region (3) and the P+ emitter region (2) are in contact with each other on the side and are located on the top layer of the P-type base region (4), and the N+ emitter region (3) is located on both sides of the P+ emitter region (2), and the emitter metal (1) is located on the N+ emitter region (3) and the P+ emitter region (2).

8. A method for manufacturing a self-biased split insulated gate bipolar transistor with a full trench structure according to any one of claims 1 to 7, characterized in that: The following steps are involved: Step 1: Select an N-type lightly doped FZ silicon wafer as the N-drift region of the device (7); Step 2: using a photolithography process and performing high-temperature ion implantation of P-type impurities in the N-drift region (7) followed by annealing to form a floating P region (13) of the device; Step 3: using a photolithography process to form the first trench to the sixth trench, and using a thermal oxidation process to form a trench oxide layer (6) on the sidewalls and bottom of the first trench to the sixth trench; Step 4: depositing N-doped polysilicon in the first trench to the sixth trench to form a polysilicon trench gate (29); Step 5: forming an oxidation shield layer by a thermal oxidation process, etching away the oxide layer on the surface of the polysilicon trench gate and the polysilicon on the upper layer of the polysilicon trench gate by a photolithography process, forming the first split gate (11-1) to the sixth split gate (11-6), thermally oxidizing the surfaces of the first split gate (11-1) to the sixth split gate (11-6) to form an oxide isolation layer and depositing it again, forming a trench gate 5 in the first trench, and forming the first trench emitter (12-1) to the fifth trench emitter (12-5) in the second to sixth trenches; Step 6: Using a photolithography process, and performing high-temperature ion implantation of P-type impurities followed by annealing, to form a P-type base region (4) of the device; Step 7: Produce the N+ emitter region (3) of the device by high-temperature ion implantation of N-type impurities and annealing; Step 8: Produce the P+ emitter region (2) of the device by high-temperature ion implantation of P-type impurities and annealing; Step 9: Depositing Al metal to form emitter metal (1); Step 10: flipping the silicon wafer, reducing the thickness of the silicon wafer, and implanting N-type impurities and P-type impurities on the back of the silicon wafer by high-energy ion implantation and annealing to form an N-type electric field stop layer (8) and a P-type collector region (9) on its surface; Step 11: Deposit metal on the back of the silicon wafer to form collector metal (10) on the surface of the P-type collector region (9).

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