A self-biased split-gate bipolar transistor

Abstract

The application belongs to the technical field of power semiconductor devices, and relates to a self-bias split insulated gate bipolar transistor and a manufacturing method thereof. The application is characterized in that a diode is connected in series between a split polysilicon gate 11 and a floating P region 13, the diode cathode is connected with the split polysilicon gate 11, the diode anode is connected with the floating P region 13, a capacitor is connected in series between the split gate 11 and the emitter metal 1, and the floating P region 13 is clamped by an active region to obtain a higher potential at the time of IGBT turn-off. The potential makes the diode open, thereby charging the capacitor and making the capacitor obtain a stable potential. The split gate 11 is connected with the capacitor, so that the split gate also has a stable potential, the potential attracts the electrons near the split gate to accumulate to form an electron accumulation layer, the accumulation layer improves the injection efficiency of the channel, further improves the drift region conductance modulation effect, and reduces the forward conduction voltage drop of the device.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power semiconductor devices, and particularly relates to a self-biased split gate bipolar transistor. BACKGROUND

[0002] The emergence of electric energy has promoted the rapid development of modern social science and technology, and how to more efficiently handle electric energy has always been a popular topic of scientific research all over the world. Efficient use of electric energy highly depends on power electronic systems, and the core electronic components of various power electronic systems are semiconductor power devices. Semiconductor power devices are widely used in various household appliances, various industrial equipment and other fields dominated by electric power. In the 21st century, global climate warming has attracted more and more attention, and energy saving and emission reduction and improvement of energy utilization efficiency are becoming increasingly important. Today, as the proportion of clean and renewable energy is increasing, society has higher expectations for energy conversion efficiency, and higher requirements are put forward for the performance of power semiconductor devices, which are the core of energy control.

[0003] Insulated gate bipolar transistors (IGBTs) are a new generation of power electronic devices because they combine the advantages of field effect transistors (MOSFETs) and bipolar junction transistors (BJTs). They have the advantages of MOSFETs, such as easy driving, low input impedance, and fast switching speed, and the advantages of BJTs, such as large on-state current density, low on-state voltage drop, small loss, and good stability. Therefore, they have developed into one of the core electronic components in modern power electronic circuits and are widely used in transportation, power grids, communications, household appliances, and aerospace fields. The use of IGBTs has greatly improved the performance of power electronic systems.

[0004] Since the invention of IGBT, people have been committed to improving the performance of IGBT. After more than 20 years of development, multiple generations of IGBT device structures have been proposed, and the performance of the devices has been steadily improved. Traditional trench IGBT (such as Figure 1 ) changes the gate from a horizontal planar MOS to a vertical trench MOS structure, which not only improves the power density and structural design space, but also eliminates the adverse effects of the JFET region and the latch-up effect caused by the parasitic NPN. Shielded gate trench IGBT (such as Figure 2 ) based on trench IGBT has lower gate capacitance, so it has faster switching speed and lower switching loss. Moreover, compared with the high peak electric field at the bottom of the traditional trench gate structure, the SGT structure has the advantage of optimizing the electric field to increase the withstand voltage, so the SGT-IGBT has greater application value in high-reliability high-performance application fields. Figure 2A cell structure of a conventional SGT-IGBT device is shown. The IGBT is an insulated gate controlled structure, and the gate forms a channel while attracting electrons in the non-channel area through the gate voltage to form an electron accumulation layer, further reducing the forward conduction voltage drop. However, in the SGT-IGBT, since the shielding gate is connected to the emitter, it cannot attract electrons to form an electron accumulation layer, and the channel electron injection efficiency is reduced, so the conductance modulation effect is weaker than that of the conventional trench IGBT, and the forward conduction voltage drop is increased. SUMMARY

[0005] To reduce the on-state voltage drop of the device and improve the performance of the device, the present application provides a self-biased split gate bipolar transistor. The present application connects a diode in series between the split polysilicon gate 11 and the floating P region 13, the diode cathode is connected to the split polysilicon gate 11, the diode anode is connected to the floating P region 13, a capacitor is connected in series between the split gate 11 and the emitter metal 1, and the floating P region 13 is clamped by the active region to obtain a relatively stable potential at the time of IGBT turn-off. This potential makes the diode open, thereby charging the capacitor and making the capacitor obtain a stable potential. The split gate 11 is connected to the capacitor, so the split gate also has a stable potential, which attracts electrons near the split gate to form an electron accumulation layer, which improves the channel injection efficiency and further improves the drift region conductance modulation effect, thereby reducing the on-state voltage drop of the device.

[0006] To solve the above technical problems, the present application provides a self-biased split gate bipolar transistor, which has a cell structure including: a collector metal 10, a P-type collector region 9, an N-type field stop layer 8, an N-drift region 7, a P-type base region 4, an N+ emitter region 3, an emitter ohmic contact P+ region 2, a floating P region 13, a Schottky diode metal layer 14, a field oxide layer 15, an integrated capacitor trench emitter structure, a split gate structure and an emitter metal 1; the collector metal 10, the P-type collector region 9, the N-type field stop layer 8 and the N-drift region 7 are sequentially stacked from bottom to top.

[0007] The split gate structure is located on one side of the top layer of the N-drift region 7, the floating P region 13 is located on the other side of the top layer of the N-drift region 7, the trench emitter structure is located on the top layer of the N-drift region 7 between the split gate structure and the floating P region 13, the P-type base region 4 is located on the top layer of the N-drift region 7 between the trench emitter structure and the split gate structure, the N+ emitter region 3 and the emitter ohmic contact P+ region 2 are located on the top layer of the P-type base region 4 and contact each other, and the emitter metal 1 is located on the N+ emitter region 3 and the emitter ohmic contact P+ region 2; the floating P region 13 is provided with a Schottky diode metal layer 14 on the side away from the trench emitter structure; the Schottky diode metal layer 14 is connected with the split polysilicon gate 11; a field oxide layer 15 is located on the floating P region 13 between the Schottky diode metal layer 14 and the trench emitter structure;

[0008] The integrated capacitor comprises an integrated capacitor polysilicon plate 16, an integrated capacitor dielectric layer 17 and an integrated capacitor metal plate 18; the integrated capacitor polysilicon plate 16 is located on the trench emitter structure and the field oxide layer 15; the integrated capacitor dielectric layer 17 is located on the integrated capacitor polysilicon plate 16, and the integrated capacitor polysilicon plate 16 is provided with the integrated capacitor dielectric layer 17 between the integrated capacitor dielectric layer 17 and the Schottky diode metal layer 14; and the integrated capacitor metal plate 18 is located on the integrated capacitor dielectric layer 17 and the Schottky diode metal layer 14.

[0009] The trench emitter structure comprises a trench emitter 12 and a trench oxide layer 6 located on the side and bottom of the trench emitter 12; the split gate structure comprises a split polysilicon gate 11 and a polysilicon gate 5; the polysilicon gate 5 is located on the split polysilicon gate 11, and the split polysilicon gate 11 and the polysilicon gate 5 are provided with the trench oxide layer 6 therebetween; and the split polysilicon gate 11 and the polysilicon gate 5 are provided with the trench oxide layer 6 between the N-drift region 7, the P-type base region 4 and the N+ emitter region 3.

[0010] To solve the above technical problems, the embodiment of the present application provides a self-biased split insulated gate bipolar transistor, which comprises a collector metal 10, a P-type collector region 9, an N-type electric field blocking layer 8, an N-drift region 7, a P-type base region 4, an N+ emitter region 3, an emitter ohmic contact P+ region 2, a floating P region 13, a Schottky diode metal layer 14, a field oxide layer 15, an integrated capacitor, a trench emitter structure, a split gate structure and an emitter metal 1; the collector metal 10, the P-type collector region 9, the N-type electric field blocking layer 8 and the N-drift region 7 are sequentially stacked from bottom to top.

[0011] The split gate structure is located on one side of the top layer of the N-drift region 7, the floating P region 13 is located on the other side of the top layer of the N-drift region 7, the trench emitter structure is located on the top layer of the N-drift region 7 between the split gate structure and the floating P region 13, the P-type base region 4 is located on the top layer of the N-drift region 7 between the trench emitter structure and the split gate structure, the N+ emitter region 3 and the emitter ohmic contact P+ region 2 are located on the top layer of the P-type base region 4 and contact each other, and the emitter metal 1 is located on the N+ emitter region 3 and the emitter ohmic contact P+ region 2; the floating P region 13 has an N-type region 19 with a PN junction on the top layer of the side away from the trench emitter structure, and the N-type region 19 with the PN junction has an ohmic contact metal layer 20 with a PN junction; the field oxide layer 15 is located on the floating P region 13 between the ohmic contact metal layer 20 with the PN junction and the trench emitter structure;

[0012] The integrated capacitor includes an integrated capacitor polycrystal plate 16, an integrated capacitor dielectric layer 17 and an integrated capacitor metal plate 18; the integrated capacitor polycrystal plate 16 is located on the trench emitter structure and the field oxide layer 15, the integrated capacitor dielectric layer 17 is located on the integrated capacitor polycrystal plate 16, and the integrated capacitor polycrystal plate 16 and the ohmic contact metal layer 20 with the PN junction have the integrated capacitor dielectric layer 17 therebetween, and the integrated capacitor metal plate 18 is located on the integrated capacitor dielectric layer 17 and the ohmic contact metal layer 20 with the PN junction;

[0013] The trench emitter structure includes a trench emitter 12 and a trench oxide layer 6 located on the side and bottom of the trench emitter 12; the split gate structure includes a split polycrystal silicon gate 11 and a polycrystal silicon gate 5, the polycrystal silicon gate 5 is located on the split polycrystal silicon gate 11, and the split polycrystal silicon gate 11 and the polycrystal silicon gate 5 have the trench oxide layer 6 therebetween, and the split polycrystal silicon gate 11 and the polycrystal silicon gate 5 have the trench oxide layer 6 therebetween; the split polycrystal silicon gate 11 is connected with the ohmic contact metal layer 20 with the PN junction.

[0014] On the basis of the above technical solution, the application can be further improved as follows.

[0015] Further, the materials of the structure include silicon, silicon carbide, gallium nitride, gallium oxide, diamond and the like; the Schottky contact diode metal layer 14 adopts titanium, nickel, copper or aluminum.

[0016] Further, the integrated capacitor dielectric layer 17 adopts high dielectric constant materials, including aluminum oxide, hafnium oxide, zirconium dioxide, titanium dioxide, lanthanum trioxide, lutetium trioxide, niobium pentoxide or tantalum pentoxide.

[0017] Furthermore, an N-type carrier storage layer 21 is located below the P-type base region 4.

[0018] Furthermore, a P-type region 22 is located below the N-type carrier storage layer 21, the trench emitter structure, and the floating P-region 13, and an N-drift region 7 is located between the split gate structure and the P-type region 22.

[0019] Furthermore, the trench emitter structure also has a split emitter 12-1, which is located below the trench emitter 12, and a trench oxide layer 6 is present between the split emitter 12-1 and the trench emitter 12.

[0020] Furthermore, the N-type electric field blocking layer 8 is formed using a multi-step hydrogen implantation process.

[0021] Furthermore, a superjunction structure is introduced in the N-drift region 7. The superjunction structure includes P-pillars 23 and N-pillars 24. The P-pillars 23 and N-pillars 24 are located in the N-drift region 7 with their sides in contact with each other. The P-pillars 23 are connected to the floating P-region 13. The P-type base region 4 is above the N-pillars 24. The contact surface between the P-pillars 23 and N-pillars 24 is located below the trench emitter structure.

[0022] Furthermore, one side of the P-type collector region 9 has an N-region 25.

[0023] To address the aforementioned technical problems, this invention provides a method for fabricating the self-biased split insulated gate bipolar transistor, comprising the following steps:

[0024] Step 1: Select an N-type lightly doped FZ silicon wafer as the N-drift region 7 of the device;

[0025] Step 2: A field oxide layer 27 is grown on the silicon wafer surface using photolithography. After high-temperature ion implantation of P-type impurities in the N-drift region 7 and subsequent annealing, a floating P-region 13 of the device is formed. A pre-oxide layer 28 is grown on the silicon wafer surface.

[0026] Step 3: Using photolithography, the first trench and the second trench are formed, and through thermal oxidation, the trench oxide layer 6 is formed on the sidewalls and bottom of the first trench and the second trench;

[0027] Step 4: N-doped polysilicon is deposited in the first trench and the second trench. A polysilicon trench gate 29 is formed in the first trench, a trench emitter 12 is formed in the second trench, and a field oxide layer 15 and an integrated capacitor polysilicon plate 16 are formed on the surface of the floating P region 13.

[0028] Step 5: An oxide shielding layer a is formed by thermal oxidation process. The oxide layer on the surface of the polysilicon trench gate 29 and the polysilicon on the upper layer of the polysilicon trench gate 29 are etched away by photolithography process to form a split polysilicon gate 11. An oxide isolation layer is formed on the surface of the split polysilicon gate 11 by thermal oxidation and then deposited again to form a polysilicon gate 5.

[0029] Step 6: The P-type base region 4 of the device is formed by photolithography and high-temperature ion implantation of P-type impurities followed by annealing.

[0030] Step 7: Fabricate the N+ emitter region 3 of the device by high-temperature ion implantation of N-type impurities and annealing;

[0031] Step 8: Fabricate the emitter ohmic contact P+ region 2 of the device by high-temperature ion implantation of P-type impurities and annealing;

[0032] Step 9: Deposit a high dielectric constant dielectric layer to form the integrated capacitor dielectric layer 17;

[0033] Step 10: Perform Al metal deposition to form emitter metal 1;

[0034] Step 11: Perform Schottky metal deposition to form the Schottky diode metal layer 14;

[0035] Step 12: Perform metal deposition to form the integrated capacitor metal plate 18;

[0036] Step 13: Flip the silicon wafer, reduce the thickness of the silicon wafer, implant N-type impurities with high-energy ions and P-type impurities on the back of the silicon wafer and anneal it to form an N-type electric field blocking layer 8 and a P-type collector region 9 on its surface.

[0037] Step 14: Deposit metal on the back side of the silicon wafer to form collector metal 10 on the surface of the P-type collector region 9.

[0038] The working principle of this invention is as follows: when the polysilicon gate 5 is connected to a high potential higher than the device threshold voltage, the collector metal 10 is connected to a high potential, and the emitter metal 1 is connected to a low potential, the device operates in the on state. The P-type collector region 9 injects holes into the N-drift region 7, and the N+ emitter region 3 injects electrons into the N-drift region 7. The presence of electron-hole pairs causes a conductivity modulation effect in the drift region.

[0039] When a capacitor is formed on the field oxide layer 15 on the surface of the floating P region 13 through a polycrystalline silicon emitter plate 16, a high dielectric constant dielectric layer 17, and a metal plate 18, it is used to integrate a self-biased structure in the IGBT structure. Since the capacitor is directly connected to the emitter and the floating P region, the integrated capacitor structure can effectively reduce parasitic metal trace resistance and capacitance compared to the structure of an external capacitor.

[0040] When the floating p-region 13 and the metal layer 14 form a Schottky diode, the potential below the floating p-region 13 is clamped by the reverse-biased PN junction formed by the P-type base region 4 and the N-drift region 7. This potential charges the integrated capacitor through the Schottky diode. Since the diode can maintain the charge on the capacitor and the floating p-region 13 has a relatively stable clamping voltage, the metal layer 14 of the Schottky diode is kept at a stable value. The metal layer 14 of the Schottky diode is connected to the SG gate 11, so the SG gate 11 also has a stable potential. This potential attracts electrons near the SG gate 11 to accumulate and form an electron accumulation layer. This accumulation layer improves the channel injection efficiency, further enhances the drift region conductance modulation effect, and reduces the forward conduction voltage drop of the device.

[0041] The beneficial effects of this invention are:

[0042] This invention utilizes the potential of the floating P-region 13 to provide a bias potential for the split polysilicon gate 11, thereby creating electron accumulation capability below the trench, enhancing the conductivity modulation effect, and thus improving the forward conduction capability of the device. Compared to the traditional split gate structure, the introduction of the self-biased structure is beneficial in simultaneously improving the device's conduction capability and switching performance, eliminating the negative impact of the split gate. While improving switching losses and increasing switching speed, it also optimizes the device's forward conduction capability, improving the trade-off characteristics between the device's forward conduction voltage drop and turn-off loss.

[0043] The gate oxide layer 6 surrounding the isolated polysilicon gate 11 is not limited by the threshold voltage design, so its thickness can be further increased to improve the device's withstand voltage and oxide layer reliability, thereby enhancing device performance. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the cell structure of a traditional trench gate IGBT;

[0045] Figure 2 This is a schematic diagram of the cellular structure of a traditional shielded trench IGBT.

[0046] Figure 3 This is a schematic diagram of the cell structure of a self-biased split insulated gate bipolar transistor according to the first embodiment of the present invention;

[0047] Figure 4 This is an equivalent circuit diagram of a self-biased split insulated gate bipolar transistor according to the first embodiment of the present invention;

[0048] Figure 5 This is a schematic diagram of the cell structure of a self-biased split insulated gate bipolar transistor according to a second embodiment of the present invention.

[0049] Figure 6This is a schematic diagram of the cell structure of a self-biased split insulated gate bipolar transistor according to a third embodiment of the present invention.

[0050] Figure 7 This is a schematic diagram of the cell structure of a self-biased split insulated gate bipolar transistor according to the fourth embodiment of the present invention.

[0051] Figure 8 This is a schematic diagram of the cell structure of a self-biased split insulated gate bipolar transistor according to the fifth embodiment of the present invention;

[0052] Figure 9 This is a schematic diagram of the cell structure of a self-biased split insulated gate bipolar transistor according to the sixth embodiment of the present invention;

[0053] Figure 10 This is a schematic diagram of the cell structure of a self-biased split insulated gate bipolar transistor according to the seventh embodiment of the present invention.

[0054] Figure 11 This is a schematic diagram of the cell structure of a self-biased split insulated gate bipolar transistor according to the eighth embodiment of the present invention.

[0055] Figures 12-23 This is a schematic diagram of the process flow for fabricating a self-biased split insulated gate bipolar transistor according to the ninth embodiment of the present invention.

[0056] The attached diagram lists the components represented by each number as follows:

[0057] 1. Emitter metal, 2. Emitter ohmic contact P+ region, 3. N+ emitter region, 4. P-type base region, 5. Polysilicon gate, 6. Trench oxide layer, 7. N- drift region, 8. N-type electric field blocking layer, 9. P-type collector region, 10. Collector metal, 11. Split polysilicon gate, 12. Trench emitter, 13. Floating P region, 14. Schottky contact diode metal layer, 15. Field oxide layer, 16. Integrated capacitor polysilicon plate, 17. Integrated capacitor dielectric layer, 18. Integrated capacitor metal plate, 19. N-type region of PN junction, 20. Ohmic contact metal layer of PN junction, 21. N-type carrier storage layer, 22. P-type region, 23. P-pillar, 24. N-pillar, 25. N region, 29. Polysilicon trench gate. Detailed Implementation

[0058] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0059] like Figures 3-4As shown, the first embodiment of the present invention provides a self-biased split-gate bipolar transistor, the cell structure of which includes: collector metal 10, P-type collector region 9, N-type electric field blocking layer 8, N-drift region 7, P-type base region 4, N+ emitter region 3, emitter ohmic contact P+ region 2, floating P region 13, Schottky diode metal layer 14, field oxide layer 15, integrated capacitor, trench emitter structure, split gate structure and emitter metal 1; collector metal 10, P-type collector region 9, N-type electric field blocking layer 8 and N-drift region 7 are stacked sequentially from bottom to top;

[0060] The split gate structure is located on one side of the top layer of the N-drift region 7, the floating P-region 13 is located on the other side of the top layer of the N-drift region 7, the trench emitter structure is located on the top layer of the N-drift region 7 between the split gate structure and the floating P-region 13, the P-type base region 4 is located on the top layer of the N-drift region 7 between the trench emitter structure and the split gate structure, the N+ emitter region 3 and the emitter ohmic contact P+ region 2 are in side contact with each other and are located on the top layer of the P-type base region 4, the emitter metal 1 is located on the N+ emitter region 3 and the emitter ohmic contact P+ region 2; the floating P-region 13 has a Schottky diode metal layer 14 on the side away from the trench emitter structure; the Schottky diode metal layer 14 is connected to the split polysilicon gate 11; the field oxide layer 15 is located on the floating P-region 13 between the Schottky diode metal layer 14 and the trench emitter structure;

[0061] The integrated capacitor includes an integrated capacitor polycrystalline plate 16, an integrated capacitor dielectric layer 17, and an integrated capacitor metal plate 18. The integrated capacitor polycrystalline plate 16 is located on the trench emitter structure and the field oxide layer 15. The integrated capacitor dielectric layer 17 is located on the integrated capacitor polycrystalline plate 16, and there is an integrated capacitor dielectric layer 17 between the integrated capacitor polycrystalline plate 16 and the Schottky diode metal layer 14. The integrated capacitor metal plate 18 is located on the integrated capacitor dielectric layer 17 and the Schottky diode metal layer 14.

[0062] The trench emitter structure includes a trench emitter 12 and trench oxide layers 6 located on its sides and bottom; the split gate structure includes a split polysilicon gate 11 and a polysilicon gate 5, the polysilicon gate 5 being located on the split polysilicon gate 11, and a trench oxide layer 6 being present between the split polysilicon gate 11 and the polysilicon gate 5, and a trench oxide layer 6 being present between the split polysilicon gate 11 and the polysilicon gate 5 and the N-drift region 7, the P-type base region 4 and the N+ emitter region 3.

[0063] In this embodiment, the doping concentration of the P-type base region 4 is 3 × 10⁻⁶. 16 cm -3 ~2×1017 cm -3 The depth is 3–3.5 μm; the doping concentration of N+ emitter region 3 is 5 × 10⁻⁶. 18 cm -3 ~1×10 21 cm -3 The depth of the gate dielectric layer 6 is 0.2–0.5 μm; the thickness of the gate dielectric layer 6 is 80–120 nm; the depth of the trench gate electrode 5 is 4–6 μm; the depth of the split gate electrode 11 is 0.5–2 μm; the depth of the trench emitter 12 is 5–8 μm; and the doping concentration of the N-drift region 7 is 5 × 10⁻⁶. 12 cm -3 ~2×10 14 cm -3 The thickness is 60–700 μm; the doping concentration of the N-type electric field blocking layer 8 is 5 × 10⁻⁶. 15 cm -3 ~5×10 16 cm -3 The thickness is 5–20 μm; the doping concentration of the P-type collector region 9 is 1 × 10⁻⁶. 17 cm -3 ~1×10 19 cm -3 The thickness is 0.5–5 μm; the cell width is 20–40 μm.

[0064] like Figure 5 As shown, the second embodiment of the present invention provides a self-biased split-gate bipolar transistor, the cell structure of which includes: collector metal 10, P-type collector region 9, N-type electric field blocking layer 8, N-drift region 7, P-type base region 4, N+ emitter region 3, emitter ohmic contact P+ region 2, floating P region 13, Schottky diode metal layer 14, field oxide layer 15, integrated capacitor, trench emitter structure, split gate structure and emitter metal 1; collector metal 10, P-type collector region 9, N-type electric field blocking layer 8 and N-drift region 7 are stacked sequentially from bottom to top;

[0065] The split gate structure is located on one side of the top layer of the N-drift region 7, the floating P-region 13 is located on the other side of the top layer of the N-drift region 7, the trench emitter structure is located on the top layer of the N-drift region 7 between the split gate structure and the floating P-region 13, the P-type base region 4 is located on the top layer of the N-drift region 7 between the trench emitter structure and the split gate structure, the N+ emitter region 3 and the emitter ohmic contact P+ region 2 are in side contact with each other and are located on the top layer of the P-type base region 4, the emitter metal 1 is located on the N+ emitter region 3 and the emitter ohmic contact P+ region 2; the floating P-region 13 has an N-type region 19 of a PN junction in the top layer on the side away from the trench emitter structure, and the N-type region 19 of the PN junction has an ohmic contact metal layer 20 of the PN junction; the field oxide layer 15 is located on the floating P-region 13 between the ohmic contact metal layer 20 of the PN junction and the trench emitter structure;

[0066] The integrated capacitor includes an integrated capacitor polycrystalline plate 16, an integrated capacitor dielectric layer 17, and an integrated capacitor metal plate 18. The integrated capacitor polycrystalline plate 16 is located on the trench emitter structure and the field oxide layer 15. The integrated capacitor dielectric layer 17 is located on the integrated capacitor polycrystalline plate 16, and there is an integrated capacitor dielectric layer 17 between the integrated capacitor polycrystalline plate 16 and the ohmic contact metal layer 20 of the PN junction. The integrated capacitor metal plate 18 is located on the integrated capacitor dielectric layer 17 and the ohmic contact metal layer 20 of the PN junction.

[0067] The trench emitter structure includes a trench emitter 12 and trench oxide layers 6 located on its sides and bottom; the split gate structure includes a split polysilicon gate 11 and a polysilicon gate 5, the polysilicon gate 5 being located on the split polysilicon gate 11, and a trench oxide layer 6 being present between the split polysilicon gate 11 and the polysilicon gate 5, and a trench oxide layer 6 being present between the split polysilicon gate 11 and the polysilicon gate 5 and the N-drift region 7, the P-type base region 4 and the N+ emitter region 3; the split polysilicon gate 11 is connected to the ohmic contact metal layer 20 of the PN junction.

[0068] like Figure 6 As shown, the third embodiment of the present invention provides a self-biased split insulated gate bipolar transistor, which is based on the first embodiment, by having an N-type carrier storage layer 21 below the P-type base region 4.

[0069] The above embodiments can prevent holes from the drift region 7 from being extracted by the P-type base region 4 during forward conduction, thereby increasing the carrier concentration in the drift region 7 and enhancing the conductivity modulation effect.

[0070] like Figure 7As shown, the fourth embodiment of the present invention provides a self-biased split-gate bipolar transistor, which is based on the third embodiment, with a P-type region 22 below the N-type carrier storage layer 21, the trench emitter structure and the floating P-region 13, and an N-drift region 7 between the split gate structure and the P-type region 22.

[0071] The above embodiment can shield the influence of the N-type carrier storage layer 21 on the structural withstand voltage, and at the same time, it cooperates with the trench emitter 12 to provide a hole extraction path in the drift region 7 during turn-off, thereby accelerating the turn-off speed.

[0072] like Figure 8 As shown, the fifth embodiment of the present invention provides a self-biased split insulated gate bipolar transistor, which is based on the first embodiment, wherein the N-type electric field blocking layer 8 is formed by a multi-step hydrogen implantation process.

[0073] In the above embodiments, a gradually changing field cutoff layer can be achieved by four different doses and different injection energies, or by N-type silicon epitaxy, or by co-implantation of phosphorus and hydrogen.

[0074] By introducing a thick FS layer 8 for hydrogen implantation between the N-drift region and the P+ collector region, the hydrogen implantation process is well-suited to replace the high-temperature pre-diffusion process for deep implantation of IGBTs due to its advantages of large implantation depth at lower energies and low annealing temperatures. The number of high-energy H implantations on the back side is set to four, each using 1×102... 12 cm -3 -1×10 15 cm -3 Selection of injection dose within the range and injection energy from 20 to 200 keV.

[0075] Compared with Example 1, the N-drift region formed by the hydrogen-injected field stop layer and the NN-junction of the N+FS layer have a gentler concentration gradient, which can effectively increase the dynamic avalanche tolerance of the device.

[0076] like Figure 9 As shown, the sixth embodiment of the present invention provides a self-biased split insulated gate bipolar transistor, which is based on the first embodiment, by introducing a superjunction structure in the N-drift region 7. The superjunction structure includes P-pillar 23 and N-pillar 24. The P-pillar 23 and N-pillar 24 are located in the N-drift region 7 with their sides in contact with each other. The P-pillar 23 is connected to the floating P-region 13. The P-type base region 4 is above the N-pillar 24. The contact surface of the P-pillar 23 and N-pillar 24 is located below the trench emitter structure.

[0077] In the above embodiment, the N-drift region 7 is replaced with a superjunction structure of N / P pillars with a higher concentration. The N pillar 25 serves as the substrate, and the P pillar 24 is achieved through trench filling or multiple epitaxial growth followed by ion implantation, with similar concentrations. The doping concentration is set to 1×10⁻⁶. 14 cm -3 -5×10 16 cm -3 The column width is 2μm-12μm, and the thickness of the drift region is reduced by 20-30% according to the pressure resistance requirements.

[0078] Compared with Example 1, the introduction of the superjunction structure is beneficial to improving the device's breakdown voltage and trade-off performance. At the same time, the laterally depleted drift pillar region assists in the longitudinal depletion layer expansion during device switching, further improving the device's switching speed.

[0079] like Figure 10 As shown, the seventh embodiment of the present invention provides a self-biased split-gate bipolar transistor, which is based on the first embodiment. In this embodiment, the trench emitter structure further includes a split emitter 12-1, the split emitter 12-1 is located below the trench emitter 12, and a trench oxide layer 6 is present between the split emitter 12-1 and the trench emitter 12.

[0080] In the above embodiment, the thickness of the emitter 12-1 at the bottom of the trench is the same as the thickness of the split gate electrode 11, which is 0.5 to 2 μm, and the thickness of the emitter 12 at the top is the same as the thickness of the trench gate electrode 5, which is 4 to 6 μm.

[0081] In this embodiment, the emitter trench and the gate trench are symmetrical and can be achieved through a unified process.

[0082] like Figure 11 As shown, the eighth embodiment of the present invention provides a self-biased split insulated gate bipolar transistor, which is based on the second embodiment, by having an N region 25 in one side of the P-type collector region 9.

[0083] The above embodiment introduces a portion of the N-region 25 into the collector region P-region 9 to realize an RC-IGBT structure, thereby integrating the diodes within the IGBT module into the IGBT structure. The N-region 25 is achieved through back-side implantation with a doping concentration of 1×10⁻⁶. 17 cm -3 ~1×10 19 cm -3 .

[0084] Compared to Example 1, the introduction of the N-region collector integrates the diodes within the IGBT module into the IGBT structure, thereby improving the module integration.

[0085] Optionally, the material of the Schottky diode metal layer 14 is titanium, nickel, copper or aluminum.

[0086] Optionally, the integrated capacitor dielectric layer 17 is made of a high dielectric constant material, including: aluminum oxide, hafnium oxide, zirconium dioxide, titanium dioxide, lanthanum trioxide, lutetium trioxide, niobium pentoxide, or tantalum pentoxide.

[0087] The ninth embodiment of the present invention provides a method for fabricating the above-described self-biased split insulated gate bipolar transistor, comprising the following steps:

[0088] This invention provides a method for fabricating the above-described self-biased split insulated gate bipolar transistor, comprising the following steps:

[0089] Step 1: Select an N-type lightly doped FZ silicon wafer as the N-drift region 7 of the device, such as... Figure 12 As shown;

[0090] Step 2: A field oxide layer 27 is grown on the silicon wafer surface using photolithography. Following high-temperature ion implantation of P-type impurities in the N-drift region 7 and annealing, a floating P-region 13 of the device is formed. Figure 13 As shown, a pre-oxidized layer 28 is grown on the surface of the silicon wafer;

[0091] Step 3: Using photolithography, form the first trench and the second trench, such as... Figure 14 As shown, a trench oxide layer 6 is formed on the sidewalls and bottom of the first and second trenches through a thermal oxidation process.

[0092] Step 4: N-doped polysilicon is deposited in the first and second trenches. A polysilicon trench gate 29 is formed in the first trench, and a trench emitter 12 is formed in the second trench. A field oxide layer 15 and an integrated capacitor polysilicon plate 16 are formed on the surface of the floating P-region 13. Figure 15 As shown;

[0093] Step 5: An oxide shielding layer a is formed using a thermal oxidation process. The oxide layer on the surface of the polysilicon trench gate 29 and the polysilicon layer on top of the polysilicon trench gate 29 are etched away using a photolithography process to form a split polysilicon gate 11. An oxide isolation layer is formed on the surface of the split polysilicon gate 11 by thermal oxidation and then deposited again to form the polysilicon gate 5, as shown below. Figures 16-17 As shown;

[0094] Step 6: Using photolithography, and after high-temperature ion implantation of P-type impurities followed by annealing, the P-type base region 4 of the device is formed, as shown below. Figure 18 As shown;

[0095] Step 7: Fabricate the N+ emitter region 3 of the device by high-temperature ion implantation of N-type impurities and annealing, as shown below. Figure 19 As shown;

[0096] Step 8: Fabricate the emitter ohmic contact P+ region 2 of the device by high-temperature ion implantation of P-type impurities and annealing, as shown. Figure 20 As shown;

[0097] Step 9: Deposit a high dielectric constant dielectric layer to form the integrated capacitor dielectric layer 17, such as... Figure 21 As shown;

[0098] Step 10: Perform Al metal deposition to form emitter metal 1;

[0099] Step 11: Perform Schottky metal deposition to form the Schottky diode metal layer 14;

[0100] Step 12: Perform metal deposition to form the integrated capacitor metal plate 18, such as... Figure 22 As shown;

[0101] Step 13: Flip the silicon wafer, reduce the thickness of the silicon wafer, implant N-type impurities with high-energy ions and P-type impurities on the back of the silicon wafer and anneal it to form an N-type electric field blocking layer 8 and a P-type collector region 9 on its surface.

[0102] Step 14: Deposit metal on the back side of the silicon wafer, forming collector metal 10 on the surface of the P-type collector region 9, such as... Figure 23 As shown.

[0103] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0104] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0105] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0106] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0107] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0108] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A self-biased split-gate insulated-gate bipolar transistor, characterized in that, Its cell structure includes: collector metal (10), P-type collector region (9), N-type electric field blocking layer (8), N-drift region (7), P-type base region (4), N+ emitter region (3), emitter ohmic contact P+ region (2), floating P region (13), Schottky diode metal layer (14), field oxide layer (15), integrated capacitor, trench emitter structure, split gate structure and emitter metal (1); collector metal (10), P-type collector region (9), N-type electric field blocking layer (8) and N-drift region (7) are stacked sequentially from bottom to top; The split gate structure is located on one side of the top layer of the N-drift region (7), the floating P region (13) is located on the other side of the top layer of the N-drift region (7), the trench emitter structure is located on the top layer of the N-drift region (7) between the split gate structure and the floating P region (13), the P-type base region (4) is located on the top layer of the N-drift region (7) between the trench emitter structure and the split gate structure, and the N+ emitter region (3) and the emitter ohmic contact P+ region (2) are in contact with each other. The emitter metal (1) is located on the top layer of the P-type base region (4), and the emitter metal (1) is located on the N+ emitter region (3) and the emitter ohmic contact P+ region (2); the floating P region (13) has a Schottky diode metal layer (14) on the side away from the trench emitter structure; the Schottky diode metal layer (14) is connected to the split polysilicon gate (11); the field oxide layer (15) is located on the floating P region (13) between the Schottky diode metal layer (14) and the trench emitter structure; The integrated capacitor includes an integrated capacitor polycrystalline plate (16), an integrated capacitor dielectric layer (17), and an integrated capacitor metal plate (18). The integrated capacitor polycrystalline plate (16) is located on the trench emitter structure and the field oxide layer (15). The integrated capacitor dielectric layer (17) is located on the integrated capacitor polycrystalline plate (16), and there is an integrated capacitor dielectric layer (17) between the integrated capacitor polycrystalline plate (16) and the Schottky diode metal layer (14). The integrated capacitor metal plate (18) is located on the integrated capacitor dielectric layer (17) and the Schottky diode metal layer (14). The trench emitter structure includes a trench emitter (12) and trench oxide layers (6) located on its sides and bottom; the split gate structure includes a split polysilicon gate (11) and a polysilicon gate (5), the polysilicon gate (5) being located on the split polysilicon gate (11), and a trench oxide layer (6) being present between the split polysilicon gate (11) and the polysilicon gate (5), and a trench oxide layer (6) being present between the split polysilicon gate (11) and the polysilicon gate (5) and the N-drift region (7), the P-type base region (4) and the N+ emitter region (3).

2. The self-biased split-gate bipolar transistor according to claim 1, characterized in that, The material of the Schottky diode metal layer (14) is titanium, nickel, copper or aluminum.

3. A self-biased split-gate bipolar transistor according to claim 1, characterized in that, The integrated capacitor dielectric layer (17) is made of a high dielectric constant material, including: aluminum oxide, hafnium oxide, zirconium dioxide, titanium dioxide, lanthanum trioxide, lutetium trioxide, niobium pentoxide or tantalum pentoxide.

4. A self-biased split-gate bipolar transistor according to any one of claims 1-3, characterized in that, Below the P-type base region (4) is an N-type carrier storage layer (21).

5. A self-biased split-gate bipolar transistor according to claim 4, characterized in that, The N-type carrier storage layer (21), the trench emitter structure and the floating P-region (13) have a P-type region (22) below them, and the split gate structure has an N-drift region (7) between it and the P-type region (22).

6. A self-biased split-gate bipolar transistor according to any one of claims 1-3, characterized in that, The trench emitter structure also has a split emitter (12-1), which is located below the trench emitter (12), and a trench oxide layer (6) is present between the split emitter (12-1) and the trench emitter (12).

7. A self-biased split-gate bipolar transistor according to any one of claims 1-3, characterized in that, The N-type electric field blocking layer (8) is formed using a multi-step hydrogen injection process.

8. A self-biased split-gate bipolar transistor according to any one of claims 1-3, characterized in that, A superjunction structure is introduced in the N-drift region (7). The superjunction structure includes a P-pillar (23) and an N-pillar (24). The P-pillar (23) and the N-pillar (24) are located in the N-drift region (7) with their sides in contact with each other. The P-pillar (23) is connected to the floating P-region (13). The N-pillar (24) is located above a P-type base region (4). The contact surface of the P-pillar (23) and the N-pillar (24) is located below the trench emitter structure.

9. A self-biased split-gate bipolar transistor according to any one of claims 1-3, characterized in that, The P-type collector region (9) has an N-region (25) on one side.

10. A self-biased split-gate insulated-gate bipolar transistor, characterized in that, Its cell structure includes: collector metal (10), P-type collector region (9), N-type electric field blocking layer (8), N-drift region (7), P-type base region (4), N+ emitter region (3), emitter ohmic contact P+ region (2), floating P region (13), Schottky diode metal layer (14), field oxide layer (15), integrated capacitor, trench emitter structure, split gate structure and emitter metal (1); collector metal (10), P-type collector region (9), N-type electric field blocking layer (8) and N-drift region (7) are stacked sequentially from bottom to top; The split gate structure is located on one side of the top layer of the N-drift region (7), the floating P region (13) is located on the other side of the top layer of the N-drift region (7), the trench emitter structure is located on the top layer of the N-drift region (7) between the split gate structure and the floating P region (13), the P-type base region (4) is located on the top layer of the N-drift region (7) between the trench emitter structure and the split gate structure, and the N+ emitter region (3) and the emitter ohmic contact P+ region (2) are in contact with each other at the position. At the top layer of the P-type base region (4), the emitter metal (1) is located on the N+ emitter region (3) and the emitter ohmic contact P+ region (2); the floating P region (13) has an N-type region (19) of a PN junction in the top layer on the side away from the trench emitter structure, and an ohmic contact metal layer (20) of a PN junction is located on the N-type region (19) of the PN junction; the field oxide layer (15) is located on the floating P region (13) between the ohmic contact metal layer (20) of the PN junction and the trench emitter structure; The integrated capacitor includes an integrated capacitor polycrystalline plate (16), an integrated capacitor dielectric layer (17), and an integrated capacitor metal plate (18). The integrated capacitor polycrystalline plate (16) is located on the trench emitter structure and the field oxide layer (15). The integrated capacitor dielectric layer (17) is located on the integrated capacitor polycrystalline plate (16), and there is an integrated capacitor dielectric layer (17) between the integrated capacitor polycrystalline plate (16) and the ohmic contact metal layer (20) of the PN junction. The integrated capacitor metal plate (18) is located on the integrated capacitor dielectric layer (17) and the ohmic contact metal layer (20) of the PN junction. The trench emitter structure includes a trench emitter (12) and trench oxide layers (6) located on its sides and bottom; the split gate structure includes a split polysilicon gate (11) and a polysilicon gate (5), the polysilicon gate (5) being located on the split polysilicon gate (11), and a trench oxide layer (6) being present between the split polysilicon gate (11) and the polysilicon gate (5), and a trench oxide layer (6) being present between the split polysilicon gate (11) and the polysilicon gate (5) and the N-drift region (7), the P-type base region (4) and the N+ emitter region (3); the split polysilicon gate (11) is connected to the ohmic contact metal layer (20) of the PN junction.

11. A self-biased split-gate bipolar transistor according to claim 10, characterized in that, Below the P-type base region (4) is an N-type carrier storage layer (21).

12. A self-biased split-gate bipolar transistor according to claim 11, characterized in that, The N-type carrier storage layer (21), the trench emitter structure and the floating P-region (13) have a P-type region (22) below them, and the split gate structure has an N-drift region (7) between it and the P-type region (22).

13. A self-biased split-gate bipolar transistor according to claim 10, characterized in that, The trench emitter structure also has a split emitter (12-1), which is located below the trench emitter (12), and a trench oxide layer (6) is present between the split emitter (12-1) and the trench emitter (12).

14. A self-biased split-gate bipolar transistor according to claim 10, characterized in that, The N-type electric field blocking layer (8) is formed using a multi-step hydrogen injection process.

15. A self-biased split-gate bipolar transistor according to claim 10, characterized in that, A superjunction structure is introduced in the N-drift region (7). The superjunction structure includes a P-pillar (23) and an N-pillar (24). The P-pillar (23) and the N-pillar (24) are located in the N-drift region (7) with their sides in contact with each other. The P-pillar (23) is connected to the floating P-region (13). The N-pillar (24) is located above a P-type base region (4). The contact surface of the P-pillar (23) and the N-pillar (24) is located below the trench emitter structure.

16. A self-biased split-gate bipolar transistor according to claim 10, characterized in that, The P-type collector region (9) has an N-region (25) on one side.

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