A wiring substrate and an electronic device

Abstract

The present application discloses a wiring substrate and an electronic device for reducing the size of the border area. A wiring substrate provided by an embodiment of the present application includes: a substrate, a plurality of pad groups arranged in an array on one side of the substrate, a plurality of constant voltage signal lines, and a plurality of common voltage signal lines; the plurality of pad groups include a plurality of pad group columns arranged along a first direction and extending along a second direction, the first direction intersecting the second direction; the plurality of constant voltage signal lines and the plurality of common voltage signal lines both extend along the second direction, and each pad group column in the plurality of pad group columns corresponds to one constant voltage signal line and one common voltage signal line; in the first direction, the constant voltage signal line or the common voltage signal line corresponding to the pad group column located at the edge among the plurality of pad group columns passes through the orthographic projection of the pad located at the edge on the substrate.

Description

Technical Field

[0001] This application relates to the field of display technologies, and in particular, to a wiring substrate and an electronic device. Background Art

[0002] Due to advantages such as smaller size, ultra-high brightness, and long lifespan, the trend of using micro light-emitting diodes in the display field has increased significantly. Summary of the Invention

[0003] Embodiments of this application provide a wiring substrate and an electronic device to reduce the size of the border area.

[0004] A wiring substrate provided by an embodiment of this application includes: a substrate, a plurality of pad groups arranged in an array on one side of the substrate, a plurality of constant voltage signal lines, and a plurality of common voltage signal lines; the plurality of pad groups include a plurality of pad group columns arranged in a first direction and extending in a second direction, the first direction intersecting the second direction; the plurality of constant voltage signal lines and the plurality of common voltage signal lines both extend in the second direction, and each pad group column in the plurality of pad group columns corresponds to one constant voltage signal line and one common voltage signal line;

[0005] In the first direction, the constant voltage signal line or the common voltage signal line corresponding to the pad group column located at the edge among the plurality of pad group columns passes through the orthographic projection of the pad group located at the edge on the substrate.

[0006] In some embodiments, the pad group columns located at the edge among the plurality of pad group columns are respectively the first pad group column and the last pad group column;

[0007] The orthographic projection of the constant voltage signal line corresponding to the first pad group column on the substrate passes through the orthographic projection of the pad groups included in the first pad group column on the substrate, and the common voltage signal line corresponding to the first pad group column is located between the first pad group column and the second pad group column;

[0008] The orthographic projection of the common voltage signal line corresponding to the last pad group column on the substrate passes through the orthographic projection of the pad groups included in the last pad group column on the substrate, and the constant voltage signal line corresponding to the last pad group column is located between the last pad group column and the penultimate pad group column.

[0009] In some embodiments, the pad group includes: a first pad group and a second pad group;

[0010] The first pad group includes a plurality of first pads connected in series, and the constant voltage signal line is electrically connected to one of the plurality of first pads;

[0011] The second pad group includes a ground pad, and the ground pad is electrically connected to the common voltage signal line;

[0012] In the orthographic projection of the substrate, the constant voltage signal line or the common voltage signal line in the pad group column located at the edge passes through the orthographic projection of the first pad group on the substrate.

[0013] In some embodiments, the second pad group further includes: an output pad, an address pad, and a power supply pad; the output pad and the ground pad are arranged in a first row of pads along a first direction, and the address pad and the power supply pad are arranged in a second row of pads along the first direction;

[0014] The wiring substrate further includes: a plurality of first connection leads; the ground pad and the common voltage signal line are electrically connected through the first connection leads; in the last pad group column, in the first direction, the output pad is located between the common voltage signal line and the address pad, and the orthographic projection of the first connection lead on the substrate is located in the area between the orthographic projections of the first row of pad rows and the second row of pad rows on the substrate.

[0015] In some embodiments, the first pad group further includes second connection leads, and a plurality of first pads are electrically connected through the second connection leads;

[0016] The orthographic projection of the constant voltage signal line or the common voltage signal line passing through the orthographic projection of the pad group on the substrate overlaps with the orthographic projection of some of the second connection leads in the first pad group on the substrate;

[0017] The second connection leads and the constant voltage signal line with overlapping orthographic projections on the substrate are located on different layers;

[0018] The second connection leads and the common voltage signal line with overlapping orthographic projections on the substrate are located on different layers.

[0019] In some embodiments, in the remaining pad group columns except the pad group column located at the edge among the plurality of pad group columns, the orthographic projection of one of the constant voltage signal line and the common voltage signal line on the substrate passes through the orthographic projection of the pad group on the substrate.

[0020] In some embodiments, in the plurality of pad group columns, the orthographic projection of the constant voltage signal line corresponding to the remaining pad group columns except the last pad group column on the substrate passes through the orthographic projection of the pad group on the substrate.

[0021] In some embodiments, among the plurality of pad group columns, the common voltage signal line corresponding to the penultimate pad group column is the first type of common voltage signal line, and the common voltage signal lines corresponding to the remaining pad group columns except the last pad group column and the penultimate pad group column are the second type of common voltage signal lines;

[0022] In the first direction, the width of the second type of common voltage signal line is greater than the width of the first type of common voltage signal line.

[0023] In some embodiments, in the first direction, the width of the constant voltage signal line passing through the orthographic projection of the pad group on the substrate is greater than the width of the remaining constant voltage signal lines.

[0024] In some embodiments, in the first direction, the width of the common voltage signal line passing through the orthographic projection of the pad group on the substrate is greater than the width of the remaining common voltage signal lines.

[0025] In some embodiments, in the first direction, the width of the constant voltage signal line passing through the orthographic projection of the pad group on the substrate is equal to the width of the common voltage signal line passing through the orthographic projection of the pad group on the substrate.

[0026] In some embodiments, in the first direction, the distance between the constant voltage signal line or the common voltage signal line passing through the orthographic projection of the pad group on the substrate and the first pad is greater than or equal to 200 microns.

[0027] An electronic device provided by an embodiment of the present application, the electronic device includes: a wiring substrate provided by an embodiment of the present application, and a plurality of electronic components located on one side of the wiring substrate; the electronic components are electrically connected to the pad group.

[0028] In some embodiments, the pad group includes a first pad group and a second pad group; the first pad group includes a plurality of first pads, and the electronic components are electrically connected to the first pads one by one; the electronic device further includes: a driving chip electrically connected to the second pad group one by one.

[0029] In some embodiments, the electronic component is a micro-sized inorganic light-emitting diode.

[0030] For the wiring substrate and the electronic device provided by the embodiment of the present application, the orthographic projection of the constant voltage signal line or the common voltage signal line corresponding to the pad group column at the edge on the substrate passes through the orthographic projection of the pad group located at the edge on the substrate, that is, the constant voltage signal line or the common voltage signal line corresponding to the edge pad group column is arranged within the area where the edge pad group column is located. Therefore, the constant voltage signal line or the common voltage signal line corresponding to the edge pad group column does not need to be arranged in the border area, which is beneficial to realizing a narrow border. The size of the border area does not affect the line width of the constant voltage signal line or the common voltage signal line, and there is no need to increase the thickness of the constant voltage signal line or the common voltage signal line, let alone adopt double-layer wiring, which can avoid increasing costs. Moreover, since the area space corresponding to the pad group is sufficient, the line width of the constant voltage signal line or the common voltage signal line arranged within the area where the edge pad group column is located can be increased, thereby reducing the resistance of the constant voltage signal line or the common voltage signal line, reducing the voltage drop of the constant voltage signal line or the common voltage signal line, and improving the performance of the wiring substrate. Description of the Drawings

[0031] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0032] Figure 1 Structural schematic diagram of a wiring substrate provided by an embodiment of the present application;

[0033] Figure 2 For the embodiment of the present application along Figure 1 Cross-sectional view of BB' in;

[0034] Figure 3 For the embodiment of the present application along Figure 1 Cross-sectional view of CC' in;

[0035] Figure 4 Structural schematic diagram of another wiring substrate provided by an embodiment of the present application;

[0036] Figure 5 Structural schematic diagram of yet another wiring substrate provided by an embodiment of the present application;

[0037] Figure 6 Structural schematic diagram of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions of the embodiments of the present application in conjunction with the drawings of the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. And without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. Based on the described embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present application.

[0039] Unless otherwise defined, the technical terms or scientific terms used in the present application should have the ordinary meaning understood by those of ordinary skill in the art to which the present application belongs. The "first", "second", and similar terms used in the present application do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or objects appearing before this term cover the elements or objects listed after this term and their equivalents, without excluding other elements or objects. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0040] It should be noted that the sizes and shapes of the various figures in the drawings do not reflect the true proportions, and the purpose is only to schematically illustrate the content of this application. Also, the same or similar reference numerals throughout indicate the same or similar elements or elements having the same or similar functions.

[0041] In the related art, the wiring substrate of a micro light-emitting diode includes a plurality of constant-voltage signal lines and a plurality of common-voltage signal lines. The leftmost constant-voltage signal line needs to be arranged in the left border area, and the rightmost common-voltage signal line needs to be arranged in the right border area. Therefore, the width of the border area affects the line width of the constant-voltage signal line and the line width of the common-voltage signal line. For a narrow-border product with a border area width of 3 mm, the line widths of the constant-voltage signal line and the common-voltage signal line need to be greatly compressed. In order to ensure the electrical performance of the constant-voltage signal line and the common-voltage signal line, the constant-voltage signal line and the common-voltage signal line need to be thickened, resulting in an increase in material costs. For an extremely narrow-border product with a border area width less than 2 mm, compressing the line widths of the constant-voltage signal line and the common-voltage signal line will not meet the electrical requirements of the signal lines, and both the constant-voltage signal line and the common-voltage signal line need to adopt a double-layer wiring arrangement, resulting in a significant increase in costs.

[0042] An embodiment of the present application provides a wiring substrate, as Figure 1 shown, the wiring substrate includes: a substrate 1, a plurality of pad groups 2 arranged in an array on one side of the substrate 1, a plurality of constant-voltage signal lines VLED, and a plurality of common-voltage signal lines GND; the plurality of pad groups 2 include a plurality of pad group columns 3 arranged along a first direction X and extending along a second direction Y, and the first direction X intersects the second direction Y; the plurality of constant-voltage signal lines VLED and the plurality of common-voltage signal lines GND both extend along the second direction Y, and each pad group column 3 in the plurality of pad group columns 3 corresponds to a constant-voltage signal line VLED and a common-voltage signal line GND;

[0043] In the first direction X, the constant-voltage signal line VLED or the common-voltage signal line GND corresponding to the pad group column 3 located at the edge among the plurality of pad group columns 3 has a positive projection on the substrate 1 that passes through the positive projection of the pad group 2 located at the edge on the substrate 1.

[0044] In a specific implementation, as Figure 1 shown, the wiring substrate is divided into an effective area 4 and a border area 5; the border area 5 includes: a first border area 501 and a second border area 502 respectively located on both sides of the effective area 4 in the first direction X. The plurality of pad groups are located in the effective area 4.

[0045] In the wiring substrate provided by the embodiment of the present application, the constant voltage signal line or the common voltage signal line corresponding to the pad group array at the edge passes through the orthographic projection of the pad group located at the edge on the substrate, that is, the constant voltage signal line or the common voltage signal line corresponding to the edge pad group array is arranged within the area where the edge pad group array is located. Therefore, the constant voltage signal line or the common voltage signal line corresponding to the edge pad group array does not need to be arranged in the border area, which is beneficial to realizing a narrow border. The size of the border area does not affect the line width of the constant voltage signal line or the common voltage signal line, and there is no need to increase the thickness of the constant voltage signal line or the common voltage signal line, let alone adopt double-layer wiring, which can avoid increasing costs. Moreover, since there is sufficient space in the area corresponding to the pad group, the line width of the constant voltage signal line or the common voltage signal line arranged within the area where the edge pad group array is located can be increased, thereby reducing the resistance of the constant voltage signal line or the common voltage signal line, reducing the voltage drop of the constant voltage signal line or the common voltage signal line, and improving the performance of the wiring substrate.

[0046] It should be noted that the constant voltage signal line corresponding to the pad group array refers to the constant voltage signal line electrically connected to the pad group in the pad group array, and the common voltage signal line corresponding to the pad group array refers to the common voltage signal line electrically connected to the pad group in the pad group array.

[0047] It should be noted that the line width refers to the width of various signal lines in the first direction X.

[0048] In some embodiments, as Figure 1 shown, the pad group arrays 3 located at the edge among the multiple pad group arrays 3 are the first pad group array 301 and the last pad group array 302 respectively;

[0049] The orthographic projection of the constant voltage signal line VLED1 corresponding to the first pad group array 301 on the substrate 1 passes through the orthographic projection of the pad group 2 included in the first pad group array 301 on the substrate 1;

[0050] The orthographic projection of the common voltage signal line GNDn corresponding to the last pad group array 302 on the substrate 1 passes through the orthographic projection of the pad group 2 included in the last pad group array 302 on the substrate 1.

[0051] It should be noted that Figure 1 in the example, the first pad group array is located on the leftmost side and the last pad group array is located on the rightmost side. The first pad group array 301 is adjacent to the first border area 501, and the last pad group array 302 is adjacent to the second border area 502.

[0052] It should be noted that in the related art, the constant voltage signal line corresponding to the first pad group column is located in the first border area, and the common voltage signal line corresponding to the last pad group column is located in the second border area. Compressing the widths of the first border area and the second border area in the first direction (i.e., the sizes of the first border area and the second border area) requires reducing the routing space for the constant voltage signal line corresponding to the first pad group column and the common voltage signal line corresponding to the last pad group column. The constant voltage signal line corresponding to the first pad group column and the common voltage signal line corresponding to the last pad group column need double-layer routing, which affects the cost. Moreover, if the reserved routing space for the constant voltage signal line corresponding to the first pad group column and the common voltage signal line corresponding to the last pad group column is small, the conductivity of the constant voltage signal line corresponding to the first pad group column and the common voltage signal line corresponding to the last pad group column cannot be satisfied.

[0053] In the display panel provided by the embodiment of the present application, the orthographic projection of the constant voltage signal line corresponding to the first pad group column on the substrate passes through the orthographic projection of the pad groups included in the first pad group column on the substrate, that is, the constant voltage signal line corresponding to the first pad group column is arranged in the area where the first pad group is located. The constant voltage signal line corresponding to the first pad group column does not need to be arranged in the first border area. Even if the size of the first border area is compressed, it will not affect the line width of the constant voltage signal line corresponding to the first pad group column, which is beneficial to realizing a narrow border. Moreover, since the area space corresponding to the pad group is sufficient, the line width of the constant voltage signal line corresponding to the first pad group column can be increased, thereby reducing the resistance and voltage drop of the constant voltage signal line corresponding to the first pad group column. The orthographic projection of the common voltage signal line corresponding to the last pad group column on the substrate passes through the orthographic projection of the pad groups included in the last pad group column on the substrate, that is, the common voltage signal line corresponding to the last pad group column is arranged in the area where the last pad group is located. The common voltage signal line corresponding to the last pad group column does not need to be arranged in the second border area. Even if the size of the second border area is compressed, it will not affect the line width of the common voltage signal line corresponding to the last pad group column, which is beneficial to realizing a narrow border. Moreover, since the area space corresponding to the pad group is sufficient, the line width of the common voltage signal line corresponding to the last pad group column can be increased, thereby reducing the resistance and voltage drop of the constant voltage signal line corresponding to the last pad group column.

[0054] In some embodiments, as Figure 1 shown, the common voltage signal line GND1 corresponding to the first pad group column 301 is located between the first pad group column 301 and the second pad group column (not shown); the constant voltage signal line VLEDn corresponding to the last pad group column 302 is located between the last pad group column 302 and the penultimate pad group column (not shown).

[0055] In some embodiments, as Figure 1As shown, the pad group 2 includes: a first pad group 201 and a second pad group 202;

[0056] The first pad group 201 includes a plurality of first pads A connected in series, and the constant voltage signal line VLED is electrically connected to one of the plurality of first pads A;

[0057] The second pad group 202 includes a ground pad 2021, and the ground pad 2021 is electrically connected to the common voltage signal line GND;

[0058] In the pad group column 3 at the edge, the constant voltage signal line VLED or the common voltage signal line GND passes through the orthographic projection of the first pad group 201 on the substrate 1.

[0059] Specifically, as Figure 1 shown, the orthographic projection of the constant voltage signal line VLED1 corresponding to the first pad group column 301 on the substrate 1 passes through the orthographic projection of the first pad group 201 included in the first pad group column 301 on the substrate 1, and the orthographic projection of the common voltage signal line GNDn corresponding to the last pad group column 302 on the substrate 1 passes through the orthographic projection of the first pad group 201 included in the last pad group column 302 on the substrate 1.

[0060] It should be noted that the wiring substrate provided in the embodiment of the present application can be used to drive a light-emitting device to emit light. In a specific implementation, the first pads are electrically connected to the light-emitting devices one by one, the first pads are used to supply power to the light-emitting devices, the first sub-pads are electrically connected to the anodes of the light-emitting devices, and the second sub-pads are electrically connected to the cathodes of the light-emitting devices, for example.

[0061] In some embodiments, as Figure 1 shown, the first pad group 2 includes 4 first pads A connected in series, namely A1, A2, A3, and A4; the four pads are arranged in two rows × two columns, A1 and A2 are in the first column, A3 and A4 are in the second column, A1, A2, A3, and A4 enclose a rectangular area, and the constant voltage signal line VLED or the common voltage signal line GND corresponding to the edge pad group column passes through the area between the first column and the second column; wherein, each first pad A includes: a first sub-pad 2011 and a second sub-pad 2012; the constant voltage signal line VLED is electrically connected to the first sub-pad 2011 of the first pad A1, the second sub-pad 2012 of the first pad A1 is electrically connected to the first sub-pad 2011 of the first pad A2, the second sub-pad 2012 of the first pad A2 is electrically connected to the first sub-pad 2011 of the first pad A3, and the second sub-pad 2012 of the first pad A3 is electrically connected to the first sub-pad 2011 of the first pad A4.

[0062] In some embodiments, as Figure 1As shown, the second pad group 202 further includes: an output pad 2023, an address pad 2024, and a power supply pad 2022; the output pad 2023 and the ground pad 2021 are arranged in a first row of pad rows 12 along a first direction X, and the address pad 2024 and the power supply pad 2022 are arranged in a second row of pad rows 13 along the first direction X; the output pad 2023 is located at the upper left corner of the second pad group 202, the address pad 2024 is located at the lower left corner of the second pad group 202, the ground pad 2021 is located at the upper right corner of the second pad group 202, and the power supply pad 2022 is located at the lower right corner of the second pad group 202.

[0063] In a specific implementation, the first pad group can be electrically connected to multiple electronic components, and the second pad group can be electrically connected to a driving chip. The address pad can receive an address signal for selecting a driving chip corresponding to an address. The power supply pad can provide a working voltage and communication data for the driving chip, and the communication data can be used to control the working state of the corresponding electronic component. The output pad can output a relay signal and a driving signal at different time intervals. For example, the relay signal is an address signal provided to the address pad in the next-level second pad group, and the driving signal is a driving current for driving an electronic component electrically connected to the second pad group where the output pad is located. The ground pad receives a common voltage signal transmitted by a common voltage signal line.

[0064] In a specific implementation, as Figure 1 shown, the display panel further includes: a plurality of address signal lines 10, a plurality of cascade lines 7, a plurality of power supply signal lines 6, and a feedback signal line 8. Among them, the feedback signal line 8 is located in the second border area 502, and the address signal lines 10, the cascade lines 7, and the power supply signal lines 6 all include portions located in the active area 4. A plurality of second pad groups 202 in a pad column 3 can be cascaded. The address pad 2024 of the first-level second pad group 202 in the same column is connected to the address signal line 10, the output pad 2023 of the kth (k is a positive integer) - level second pad group 202 and the address pad 2024 of the (k + 1) - level second pad group 202 are connected by the cascade line 7, and the output pad 2023 of the last-level second pad group 202 is connected to the feedback signal line 8; the cascade line 7 is also electrically connected to a first pad A ( Figure 1 A4 in it) in the first pad group 201; the power supply pads 2022 in each pad column 3 in a column are connected to the same power supply signal line 6; the ground pads 2021 in each pad column 3 in a column are connected to the same common voltage signal line GND.

[0065] In a specific implementation, as Figure 1 shown, among various types of traces electrically connected to a pad column 3, the cascade line 7 is located in the area between the power supply signal line 6 and the first pad group 201, and the address signal line 10 is located on the side of the power supply signal line 6 close to the first border area 501.

[0066] In some embodiments, as Figure 1 shown, the first border area 501 and the second border area 502 further include an electrostatic shielding line 9. That is, for the wiring substrate provided by the embodiments of the present application, only the electrostatic shielding line is included in the first border area; the second border area: includes an electrostatic shielding line, a power signal line, and a feedback signal line.

[0067] In specific implementation, the line width of the electrostatic shielding line and the line width of the feedback signal line are about 200 microns, and the line width of the power signal line is about 350 microns. For a wiring substrate of a related technology with a width of 4000 microns in the first direction of the border area, the line width of the constant voltage signal line in the border area is about 1400 microns, and the line width of the common voltage signal line in the border area is about 2000 microns. If the materials of the common voltage signal line and the constant voltage signal line are both copper and the sheet resistance is 0.011 ohm / square, the resistance of the constant voltage signal line in the border area is 0.1137 ohm, and the resistance of the common voltage signal line in the border area is 0.1213 ohm. It can be seen that, compared with other signal lines, the constant voltage signal line and the common voltage signal line occupy a relatively large space in the border area. For the wiring substrate provided by the embodiments of the present application, there is no need to set a constant voltage signal line and a common voltage signal line in the border area, which can greatly reduce the width of the border area in the first direction X (such as Figure 1 h5 and h6 in). The width of the first border area in the first direction X can be reduced by at least 1400 microns, the width of the second border area in the first direction X can be reduced by at least 2000 microns, and the width of the border area in the first direction X can be reduced by 50% - 70%. Moreover, since there is sufficient wiring space in the area corresponding to the first pad group, the distance between the first pad A2 and the first pad A3 is usually greater than 5000 microns, and the line width of the constant voltage signal line (such as h1 in the figure) or the line width of the common voltage signal line (such as Figure 1 h2 in) located between the first pad A2 and the first pad A3 can be set to be greater than 4700 microns, for example, 4727 microns. The resistance of the constant voltage signal line and the resistance of the common voltage signal line are reduced to 0.0385 ohm. The resistance of the constant voltage signal line is reduced by 66.1%, and the resistance of the common voltage signal line is reduced by 68.3%. That is, compared with the case of setting a constant voltage signal line and a common voltage signal line in the border area, the embodiments of the present application can greatly increase the line width of the constant voltage signal line corresponding to the first pad group column and the line width of the common voltage signal line corresponding to the last pad group column, thereby reducing the resistance and voltage drop of the constant voltage signal line corresponding to the first pad group column and the common voltage signal line corresponding to the last pad group column.

[0068] In some embodiments, as Figure 1 shown, the wiring substrate further includes: a plurality of first connection leads 11; the ground pad 2021 is electrically connected to the common voltage signal line GND through the first connection leads 11;

[0069] The ground pad 2021 in the last pad group column 302 is electrically connected to the common voltage signal line GND through the first connecting lead 11; in the last pad group column 3, in the first direction X, the output pad 2023 is located between the common voltage signal line GND and the address pad 2022, and the orthographic projection of the first connecting lead 11 on the substrate substrate 1 is located in the area between the orthographic projections of the first row of pads 12 and the second row of pads 13 on the substrate substrate 1.

[0070] In some embodiments, Figure 1 As shown, the power signal line 6 is integrally connected to the power supply pad 2022; in the first pad group column 301, the power signal line 6 passes through the area between the ground pad 2021 and the output pad 2023 and is electrically connected to the power supply pad 2022, and the ground pad 2021 is electrically connected to the common voltage signal line GND on the side away from the first border area 501; and for the last pad group column 302, since the common voltage signal line GND needs to pass through the first pad group 201, the power supply pad 2022 is connected to the power signal line 6 on the side close to the second border area 502, thereby reserving space for the first connecting lead 11, so that the first connecting lead 11 passes through the area between the first row of pads 12 and the second row of pads 13 and is electrically connected to the common voltage signal line GND passing through the first pad group 201.

[0071] In some embodiments, Figure 1 As shown, the first pad group 201 further includes a second connecting lead 2013, and the plurality of first pads A are electrically connected via the second connecting lead 2013;

[0072] The orthographic projection of the constant voltage signal line VLED or the common voltage signal line GND passing through the orthographic projection of the pad group 2 on the base substrate 1 overlaps with the orthographic projection of part of the second connecting lead 2013 in the first pad group 2 on the base substrate 1;

[0073] like Figure 2 As described above, in the orthographic projection of the base substrate 1, the second connecting lead 2013 and the constant voltage signal line VLED which overlap each other are located in different layers;

[0074] In the orthographic projection of the base substrate 1 , the second connecting lead 2013 and the common voltage signal line GND which overlap each other are located in different layers.

[0075] In the display panel provided by the embodiment of the present application, when the orthographic projection of the constant voltage signal line or the common voltage signal line on the substrate passes through the orthographic projection of the first pad group on the substrate, the constant voltage signal line or the common voltage signal line and the second horizontal connecting lead are located in different layers to avoid the constant voltage signal line or the common voltage signal line arranged in the pad group column area affecting the electrical connection of the first pad.

[0076] It should be noted that Figure 2 is a sectional view along Figure 1 BB' in

[0077] In some embodiments, as Figure 1 shown, a plurality of first pads A are connected in series through second connection leads 2013

[0078] In specific implementation, as Figure 1 shown, the first pad group 201 includes three second connection leads 2013, two longitudinal second connection leads 20131 extending along the second direction Y, and one transverse second connection lead 20132 extending along the first direction X. A1 and A2 are electrically connected through the longitudinal second connection lead 20131, A3 and A4 are electrically connected through the longitudinal second connection lead 20131, and A2 and A3 are electrically connected through the transverse second connection lead 20132; the orthographic projection of the transverse second connection lead 20132 on the substrate 1 overlaps with the orthographic projection of the constant voltage signal line VLED on the substrate 1 or the orthographic projection of the common voltage signal line GND on the substrate 1, and the orthographic projections of the longitudinal second connection leads 20131 on the substrate 1 or the orthographic projection of the common voltage signal line GND on the substrate 1 do not overlap with each other. Therefore, the longitudinal second connection leads 20131 can be arranged on the same layer as the common voltage signal line GND or the constant voltage signal line VLED. The transverse second connection lead 20132 and the constant voltage signal line VLED or the common voltage signal line GND whose orthographic projection overlaps with it are located on different layers

[0079] It should be noted that Figure 1 Taking the series connection of a plurality of first pads as an example for illustration, of course, in specific implementation, it can also be the parallel connection of a plurality of first pads. No matter how the plurality of first pads are connected, it is necessary to arrange that the second connection lead whose orthographic projection on the substrate overlaps with the constant voltage signal line is on a different layer, and the second connection lead whose orthographic projection on the substrate overlaps with the common voltage signal line is on a different layer

[0080] In specific implementation, to reduce process steps and save manufacturing costs, various pads, constant-voltage signal lines, cascade lines, address signal lines, feedback signal lines, power signal lines, second connection leads that do not overlap with the orthographic projection of the constant-voltage signal line or the common-voltage signal line, and the common-voltage signal line can be arranged on the same layer, that is, the above structures are located on the same conductive layer. It should be noted that in this application, "arranged on the same layer" means forming a film layer for making a specific pattern using the same film-forming process, and then forming a layer structure through a single lithography process using the same mask. That is, a single lithography process corresponds to one mask. Depending on the different specific patterns, the single lithography process may include exposure, development, or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may be at the same height or have the same thickness, or may be at different heights or have different thicknesses.

[0081] In specific implementation, as Figure 2 shown, the lateral second connection lead 20132 that overlaps with the orthographic projection of the constant-voltage signal line (not shown) or the common-voltage signal line GND is located, for example, in the region on the side of the constant-voltage signal line (not shown) and the common-voltage signal line GND away from the substrate 1. A first insulating layer 15 is provided between the lateral second connection lead 20132 and the constant-voltage signal line (not shown) or the common-voltage signal line GND. The lateral second connection lead 20132 is electrically connected to the first pad A through a via hole penetrating the first insulating layer 15. In some embodiments, the lateral second connection lead 20132 includes a jumper resistor and connection terminals at both ends of the jumper resistor. The jumper resistor is arranged parallel to the substrate 1, and the two connection terminals are respectively electrically connected to the first pads A2 and A3 through via holes penetrating the first insulating layer 15. The jumper resistor, that is, a zero-ohm resistor, is a resistor for special purposes with a very small resistance value. An automatic placement machine or an automatic insertion machine can be used to set the jumper resistor between two points in the wiring substrate that cannot be directly connected by a circuit to achieve electrical connection between the two points; that is, the lateral second connection lead 20132 can be connected to the corresponding pads in the wiring substrate in the same process step as the driving chip or the micro-sized inorganic light-emitting diode. In some embodiments, the lateral second connection lead 20132 is prepared by a film-forming and patterning process. As Figure 2 shown, a second insulating layer 16 can also be provided on the side of the lateral second connection lead 20132 away from the substrate 1 to protect it.

[0082] In specific implementation, as Figure 3As shown, the second insulating layer 16 and the first insulating layer 15 also have a plurality of vias 17, and the plurality of vias 17 respectively expose the regions of the first sub-pad 2011, the second sub-pad 2012, and the pads included in the second pad group (not shown). Thus, the electronic components can be electrically connected to the first pad group through the vias, and the driving chip can be electrically connected to the second pad group through the vias. It should be noted that Figure 1 In Figure 1 , the regions outlined by the dashed circles at the first sub-pad 2011, the second sub-pad 2012, the ground pad 2021, the output pad 2023, the address pad 2024, and the power supply pad 2022 included in the second pad group 202 are the positions where the corresponding vias are located.

[0083] It should be noted that Figure 3 is a cross-sectional view along Figure 1 CC'. As Figure 2 、 Figure 3 shown, the wiring substrate further includes a buffer layer 14 located between the substrate 1 and the first pad A. Thus, it is avoided that the conductive layers such as the first pad are easily detached when directly disposed on the substrate.

[0084] In some embodiments, as Figure 4 、 Figure 5 shown, in the remaining pad group columns 3 except for the pad group columns 3 located at the edge in the plurality of pad group columns 3, one of the constant voltage signal line VLED and the common voltage signal line GND passes through the projection of the pad group 2 on the substrate 1 in the projection of the substrate 1.

[0085] In the wiring substrate provided by the embodiment of the present application, in the pad group columns other than the edge pad group columns, one of the constant voltage signal line and the common voltage signal line is disposed in the region where the pad group column is located. Thus, the wiring space for one of the constant voltage signal line and the common voltage signal line can be vacated between the adjacent pad group columns, and the line width of the other one of the constant voltage signal line and the common voltage signal line in the region between the adjacent pad group columns can be increased, and the line width of the signal line passing through the first pad group is also increased. Thus, the resistance of the signal line passing through the first pad group and located between the adjacent pad group columns can be reduced, and the voltage drop can be reduced.

[0086] In some embodiments, as Figure 4As shown in the figure, among multiple pad group columns 3, the common voltage signal line GND corresponding to the pad group columns 3 other than the first pad group column 301 passes through the orthographic projection of the first pad group 201 on the substrate 1. Since there is sufficient wiring space in the area corresponding to the first pad group, the width of the common voltage signal line passing through the first pad group in the first direction can be increased. Moreover, the common voltage signal line passing through the first pad group does not need to be arranged in the area between adjacent pad group columns. Thus, in the area between adjacent pad group columns, there is sufficient wiring space for the constant voltage signal line, and the width of the constant voltage signal line in the area between adjacent pad group columns in the first direction can be increased. The resistances of both the common voltage signal line and the constant voltage signal line are reduced, and the voltage drops of the common voltage signal line and the constant voltage signal line can be decreased.

[0087] It should be noted that when both the constant voltage signal line and the common voltage signal line are located in the area between two adjacent pad group columns, the line width of the constant voltage signal line (i.e., the width of the constant voltage signal line in the first direction) is about 1400 microns, and the line width of the common voltage signal line (i.e., the width of the common voltage signal line in the first direction) is about 2000 microns. If the materials of both the common voltage signal line and the constant voltage signal line are copper and the sheet resistance is 0.011 ohm / square, the resistance of the constant voltage signal line located between two adjacent pad group columns is 0.091 ohm, and the resistance of the common voltage signal line located between two adjacent pad group columns is 0.1299 ohm. However, for the wiring substrate provided by the embodiment of the present application, the common voltage signal line passes through the first pad group, and the line width of the common voltage signal line passing through the first pad group can be increased to, for example, 4727 microns, and the resistance can be reduced to 0.0385 ohm, with the resistance reduced by 57.7%. For the area between adjacent pad groups where only the constant voltage signal line is arranged, the line width of the constant voltage signal line arranged in this area (i.e., h1' as shown in the figure) can be increased to 4100 microns, and the resistance can be reduced to 0.0443, with the resistance reduced by 65.9%. It can be seen that compared with the situation where the constant voltage signal line and the common voltage signal line are arranged in the area between adjacent pad groups, the line widths of both the constant voltage signal line and the common voltage signal line can be greatly increased, the resistances of both the constant voltage signal line and the common voltage signal line can be greatly reduced, and the voltage drop can be decreased. Figure 4 As shown in the figure, among multiple pad group columns 3, the constant voltage signal line VLED corresponding to the pad group columns 3 other than the last pad group column 3 passes through the orthographic projection of the pad group 2 on the substrate 1.

[0088] Or, in some embodiments, as shown in the figure Figure 5 As shown in the figure, among multiple pad group columns 3, the constant voltage signal line VLED corresponding to the pad group columns 3 other than the last pad group column 3 passes through the orthographic projection of the pad group 2 on the substrate 1.

[0089] It should be noted that when the common voltage signal line is arranged in the area where the pad group columns are located, the connection lead for the electrical connection between the common voltage signal line and the ground pad needs to pass through the area between the second pad groups, and the wiring space is relatively narrow. Among the pad group columns outside the edge pad group columns, the constant voltage signal line is arranged in the area where the pad group columns are located. Compared with the case where the common voltage signal line is arranged in the area where the pad group columns are located, the wiring difficulty can be simplified.

[0090] For the wiring substrate provided by the embodiment of the present application, the constant voltage signal line passes through the first pad group. The line width of the constant voltage signal line passing through the first pad group can be increased to, for example, 4727 microns, and the resistance can be reduced to 0.0385 ohms, with a 70.4% reduction in resistance. For the area where only the common voltage signal line is arranged between adjacent pad groups, the line width of the common voltage signal line arranged in this area (i.e., h2' as shown) can be increased to 4100 microns, and the resistance can be reduced to 0.0443, with a 51.3% reduction in resistance. Compared with the case where the constant voltage signal line and the common voltage signal line are arranged between adjacent pad groups, the line widths of the constant voltage signal line and the common voltage signal line can be greatly increased, the resistances of the constant voltage signal line and the common voltage signal line can be greatly reduced, and the voltage drop can be reduced. Figure 5 In some embodiments, as shown, among the multiple pad group columns 3, the common voltage signal line GNDn corresponding to the penultimate pad group column 303 is the first type of common voltage signal line, and the common voltage signal lines GND corresponding to the remaining pad group columns 3 except the last pad group column 302 and the penultimate pad group column 303 are the second type of common voltage signal lines;

[0091] In the first direction X, the width h2' of the second type of common voltage signal line GND is greater than the width h2" of the first type of common voltage signal line GND. Figure 5 In the first direction X, the width h2' of the second type of common voltage signal line GND is greater than the width h2" of the first type of common voltage signal line GND.

[0092] In the first direction X, the width h2' of the second type of common voltage signal line GND is greater than the width h2" of the first type of common voltage signal line GND.

[0093] It should be noted that both the first type of common voltage signal lines and the second type of common voltage signal lines are located in the area between adjacent pad groups 3. A constant voltage signal line is also provided in the area between adjacent pad groups where the first type of common voltage signal line is arranged, while a constant voltage signal line does not need to be provided in the area between adjacent pad groups where the second type of common voltage signal line is arranged. Thus, compared with the first type of common voltage signal line, the width of the second type of common voltage signal line in the first direction can be increased to reduce the resistance of the second type of common voltage signal line and reduce the voltage drop. The common voltage signal line passing through the pad group is the third type of common voltage signal line, that is, compared with the first type of common voltage signal line, in the first direction, the widths of the second type of common voltage signal line and the third type of common voltage signal line are both increased. Moreover, in the wiring substrate, only the area between the last pad group column and the penultimate pad group column needs to be provided with both a constant voltage signal line and a common voltage signal line. Therefore, the number of the first type of common voltage signal lines is small, and the widths of the vast majority of the common voltage signal lines in the wiring substrate in the first direction can be increased, that is, the resistance and voltage drop of the vast majority of the common voltage signal lines can be reduced.

[0094] In some embodiments, as Figure 4 、 Figure 5 shown, in the first direction X, the width h1 of the constant voltage signal line VLED passing through the orthographic projection of the pad group 2 on the substrate 1 is greater than the width h1' of the other constant voltage signal lines VLED. Since the wiring space in the area where the pad group, especially the first pad group, is located is sufficient, compared with the other areas, the width of the constant voltage signal line in the first direction can be increased, thereby reducing the resistance of the constant voltage signal line passing through the first pad group and reducing the voltage drop.

[0095] In some embodiments, as Figure 4 、 Figure 5 shown, in the first direction X, the width h2 of the common voltage signal line GND passing through the orthographic projection of the pad group 2 on the substrate 1 is greater than the widths h2' and h2" of the other common voltage signal lines GND. Since the wiring space in the area where the pad group, especially the first pad group, is located is sufficient, compared with the other areas, the width of the common voltage signal line in the first direction can be increased, thereby reducing the resistance of the common voltage signal line passing through the first pad group and reducing the voltage drop.

[0096] In some embodiments, as Figure 1 、 Figure 4 、 Figure 5 shown, in the first direction X, the width h1 of the constant voltage signal line VLED passing through the orthographic projection of the pad group 2 on the substrate 1 is equal to the width h2 of the common voltage signal line GND passing through the orthographic projection of the pad group 2 on the substrate 1.

[0097] In some embodiments, as Figure 1As shown, in the first direction X, the distance between the constant voltage signal line VLED or the common voltage signal line GND passing through the orthographic projection of the pad group 2 on the substrate 1 and the first pad A is greater than or equal to 200 micrometers. Thereby, the risk of short circuit between the constant voltage signal line or the common voltage signal line and the first pad can be reduced. Figure 1 In it, the distances between the constant voltage signal line VLED passing through the orthographic projection of the pad group 2 on the substrate 1 and the first pads A on both sides thereof are equal, and the distance between the constant voltage signal line VLED passing through the orthographic projection of the pad group 2 on the substrate 1 and the first pad A is h3; the distances between the common voltage signal line GND passing through the orthographic projection of the pad group 2 on the substrate 1 and the first pads A on both sides thereof are equal, and the distance between the common voltage signal line GND passing through the orthographic projection of the pad group 2 on the substrate 1 and the first pad A is h4, that is, h3 is greater than or equal to 200 micrometers and h4 is greater than or equal to 200 micrometers. In specific implementation, for example, h3 = h4.

[0098] An electronic device provided by an embodiment of the present application, such as Figure 6 As shown, the electronic device includes: a wiring substrate 20 provided by an embodiment of the present application, and a plurality of electronic components 18 located on one side of the wiring substrate 20; the electronic components 18 are electrically connected to the pad group 2.

[0099] In some embodiments, such as Figure 6 As shown, the pad group 2 includes a first pad group 201 and a second pad group 202; the first pad group 201 includes a plurality of first pads A, and the electronic components 18 are electrically connected to the first pads A in one-to-one correspondence; the electronic device further includes: a driving chip 19 electrically connected to the second pad group 202 in one-to-one correspondence.

[0100] In specific implementation, the electronic component has two pins, and the two pins are electrically connected to the first sub-pad and the second sub-pad of the first pad respectively. The driving chip has 4 pins, and the 4 pins are electrically connected to the ground pad, the output pad, the address pad, and the power supply pad respectively.

[0101] In some embodiments, the electronic component is a micro-sized inorganic light-emitting diode.

[0102] In specific implementation, the micro-sized inorganic light-emitting diodes are, for example, Mini Light Emitting Diodes (Mini-LEDs) or Micro Light Emitting Diodes (Micro-LEDs). Mini-LEDs and Micro-LEDs are small in size and high in brightness, and can be widely applied to display devices or their backlight modules. For example, the typical size (such as length) of Micro-LEDs is less than 100 micrometers, such as 10 micrometers to 80 micrometers; the typical size (such as length) of Mini-LEDs is 80 micrometers to 350 micrometers, such as 80 micrometers to 120 micrometers. The electronic component can be at least one of Micro-LEDs or Mini-LEDs.

[0103] In specific implementation, the electronic device can be applied to the display field. For example, the electronic device can be used as the backlight source of a display panel.

[0104] The electronic device provided by the embodiment of the present application includes the wiring substrate provided by the embodiment of the present application. Therefore, for the implementation of this electronic device, reference can be made to the embodiment of the above-mentioned wiring panel, and the repeated parts will not be elaborated.

[0105] In summary, for the wiring substrate and the electronic device provided by the embodiment of the present application, the orthographic projection of the constant voltage signal line or the common voltage signal line corresponding to the pad group column at the edge on the substrate passes through the orthographic projection of the pad group located at the edge on the substrate, that is, the constant voltage signal line or the common voltage signal line corresponding to the edge pad group column is arranged within the area where the edge pad group column is located. Thus, the constant voltage signal line or the common voltage signal line corresponding to the edge pad group column does not need to be arranged in the border area, which is beneficial to realizing a narrow border. The size of the border area does not affect the line width of the constant voltage signal line or the common voltage signal line, and there is no need to increase the thickness of the constant voltage signal line or the common voltage signal line, let alone adopt double-layer wiring, which can avoid increasing costs. Moreover, since the regional space corresponding to the pad group is sufficient, the line width of the constant voltage signal line or the common voltage signal line arranged within the area where the edge pad group column is located can be increased, thereby reducing the resistance of the constant voltage signal line or the common voltage signal line, reducing the voltage drop of the constant voltage signal line or the common voltage signal line, and improving the performance of the wiring substrate.

[0106] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.

[0107] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application is also intended to include these modifications and variations.

Claims

1. A wiring substrate, characterized in that, The wiring substrate includes: a substrate board, a plurality of pad groups arranged in an array on one side of the substrate board, a plurality of constant voltage signal lines, and a plurality of common voltage signal lines; the plurality of pad groups include a plurality of pad group columns arranged along a first direction and extending along a second direction, the first direction intersecting the second direction; the plurality of constant voltage signal lines and the plurality of common voltage signal lines both extend along the second direction, and each of the plurality of pad group columns corresponds to one of the constant voltage signal lines and one of the common voltage signal lines. In the first direction, the constant voltage signal line or the common voltage signal line corresponding to the pad group column located at the edge among the plurality of pad group columns passes through the orthographic projection of the pad group located at the edge on the substrate board.

2. The wiring substrate according to claim 1, characterized in that, The pad group columns located at the edge among the plurality of pad group columns are respectively the first pad group column and the last pad group column. The orthographic projection of the constant voltage signal line corresponding to the first pad group column on the substrate board passes through the orthographic projection of the pad groups included in the first pad group column on the substrate board, and the common voltage signal line corresponding to the first pad group column is located between the first pad group column and the second pad group column. The orthographic projection of the common voltage signal line corresponding to the last pad group column on the substrate board passes through the orthographic projection of the pad groups included in the last pad group column on the substrate board, and the constant voltage signal line corresponding to the last pad group column is located between the last pad group column and the penultimate pad group column.

3. The wiring substrate according to claim 2, wherein, The pad group includes: a first pad group and a second pad group. The first pad group includes a plurality of first pads connected in series, and the constant voltage signal line is electrically connected to one of the plurality of first pads. The second pad group includes a ground pad, and the ground pad is electrically connected to the common voltage signal line. In the pad group column located at the edge, the constant voltage signal line or the common voltage signal line passes through the orthographic projection of the first pad group on the substrate board.

4. The wiring substrate according to claim 3, wherein The second pad group further includes: an output pad, an address pad, and a power supply pad; the output pad and the ground pad are arranged in a first row of pad rows along the first direction, and the address pad and the power supply pad are arranged in a second row of pad rows along the first direction. The wiring substrate further includes: a plurality of first connection leads; the ground pad and the common voltage signal line are electrically connected through the first connection leads. In the last pad group column, in the first direction, the output pad is located between the common voltage signal line and the address pad, and the orthographic projection of the first connection lead on the substrate board is located in the area between the orthographic projections of the first row of pad rows and the second row of pad rows on the substrate board.

5. The wiring substrate according to claim 3 or 4, characterized in that, The first pad group further includes second connection leads, and the plurality of first pads are electrically connected through the second connection leads. The constant voltage signal line or the common voltage signal line passing through the orthographic projection of the first pad group on the substrate substrate overlaps with the orthographic projection of some of the second connection leads in the first pad group on the substrate substrate; The second connection lead and the constant voltage signal line that overlap in the orthographic projection on the substrate substrate are on different layers; The second connection lead and the common voltage signal line that overlap in the orthographic projection on the substrate substrate are on different layers.

6. The wiring substrate according to claim 3 or 4, characterized in that, Among the remaining pad group columns in the plurality of pad group columns except for the pad group columns located at the edge, the orthographic projection of one of the constant voltage signal line and the common voltage signal line on the substrate substrate passes through the orthographic projection of the first pad group on the substrate substrate.

7. The wiring substrate according to claim 6, wherein Among the plurality of pad group columns, the orthographic projection of the constant voltage signal line corresponding to the remaining pad group columns except for the last pad group column passes through the orthographic projection of the first pad group on the substrate substrate.

8. The wiring substrate according to claim 7, wherein, Among the plurality of pad group columns, the common voltage signal line corresponding to the penultimate pad group column is a first type of common voltage signal line, and the common voltage signal lines corresponding to the remaining pad group columns except for the last pad group column and the penultimate pad group column are second type of common voltage signal lines; In the first direction, the width of the second type of common voltage signal line is greater than the width of the first type of common voltage signal line.

9. The wiring substrate according to any one of claims 1 to 4, 7, and 8, characterized in that, In the first direction, the width of the constant voltage signal line passing through the orthographic projection of the pad group on the substrate substrate is greater than the width of the remaining constant voltage signal lines.

10. The wiring substrate according to any one of claims 1 to 4, 7, and 8, characterized in that, In the first direction, the width of the common voltage signal line passing through the orthographic projection of the pad group on the substrate substrate is greater than the width of the remaining common voltage signal lines.

11. The wiring substrate according to any one of claims 1 to 4, 7, and 8, characterized in that In the first direction, the width of the constant voltage signal line passing through the orthographic projection of the pad group on the substrate substrate is equal to the width of the common voltage signal line passing through the orthographic projection of the pad group on the substrate substrate.

12. The wiring substrate according to any one of claims 3 to 4, 7, and 8, characterized in that, In the first direction, the distance between the constant voltage signal line or the common voltage signal line passing through the orthographic projection of the pad group on the substrate substrate and the first pad is greater than or equal to 200 micrometers.

13. An electronic device, characterized in that, The electronic device includes: a wiring substrate according to any one of claims 1 to 12, and a plurality of electronic components located on one side of the wiring substrate; the electronic components are electrically connected to the pad group.

14. The electronic device according to claim 13, wherein The pad group includes a first pad group and a second pad group; the first pad group includes a plurality of first pads, and the electronic components are electrically connected to the first pads one by one; the electronic device further includes: a driving chip electrically connected to the second pad group one by one.

15. The electronic device according to claim 13 or 14, characterized in that, The electronic component is a micro-sized inorganic light-emitting diode.

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