An interleaved parallel bidirectional DC-DC converter
By designing an interleaved parallel bidirectional DC-DC converter, the problem of insufficient boost and buck capabilities of traditional converters is solved, achieving high-ratio energy transmission and low loss, making it suitable for a variety of applications.
Patent Information
- Application Number
- CN202211118711.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-09-13
- Publication Date
- 2025-10-31
- Estimated Expiration
- 2042-09-13
AI Technical Summary
Existing bidirectional DC-DC converters have limited boost and buck capabilities, and traditional Buck-Boost converters, while simple in structure, lack sufficient boost and buck capabilities, making it difficult to meet the requirements of high voltage ratio and low current ripple.
An interleaved parallel bidirectional DC-DC converter is adopted, including a front-end circuit and a back-end circuit. The front-end circuit consists of a low-voltage side voltage stabilizing filter capacitor and an interleaved parallel bidirectional BUCK-BOOST branch. The back-end circuit consists of a high-voltage side voltage stabilizing filter capacitor and a dual-coupled inductor voltage multiplier circuit with reverse blocking. Energy transfer and conversion are achieved through interleaved control.
It achieves bidirectional energy transmission with high transformation ratio, reduces switching losses, improves power density and reliability, and has strong adaptability, making it suitable for applications such as energy storage systems, uninterruptible power supplies, dynamic voltage restorers and DC microgrids.
Smart Images

Figure CN115473433B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power electronics technology, specifically an interleaved parallel bidirectional DC-DC converter. Background Technology
[0002] With the rapid development of renewable energy, the use of new low-voltage DC sources such as photovoltaic cells, fuel cells, energy storage batteries, and supercapacitors is becoming increasingly widespread, highlighting the growing importance of DC-DC converters with high voltage ratios and low current ripple characteristics. For applications such as energy storage systems, uninterruptible power supplies (UPS), dynamic voltage restorers (DVRs), and DC microgrids, DC-DC converters are required to have bidirectional transmission capabilities.
[0003] Based on whether energy exchange occurs through an isolation transformer, bidirectional DC-DC converters can be categorized into two types: isolated and non-isolated converters. Compared to isolated bidirectional converters, non-isolated converters inherently possess a simpler structure and maintain high efficiency. Fewer components reduce potential failure points and improve reliability.
[0004] Traditional bidirectional Buck-Boost converters have a simple structure, use fewer components, and have relatively mature control schemes, making them widely used in applications requiring bidirectional power transfer with both boost and buck capabilities. However, their boost / buck capabilities are limited. Interleaved Buck-Boost converters, due to their fewer components, low input ripple, and ease of modulation, are well-suited for the aforementioned application environments. Summary of the Invention
[0005] The purpose of this invention is to provide an interleaved parallel bidirectional DC-DC converter to solve the problems mentioned in the background art.
[0006] To achieve the above-mentioned objectives, the present invention adopts the following technical solution:
[0007] An interleaved parallel bidirectional DC-DC converter includes a front-end circuit and a rear-end circuit, which are cascaded together.
[0008] The front-end circuit includes: a low-voltage side voltage regulator and filter capacitor C1, and two bidirectional BUCK-BOOST branches connected in parallel with the low-voltage side voltage regulator and filter capacitor. The voltage across the voltage regulator and filter capacitor C1 is the low-voltage side voltage E1; the first parallel branch is the first low-voltage side winding L. 1a Switch S3 is connected in series with switch S1, and switch S3 is connected in series with energy storage capacitor C. m1 Series connection; the second parallel branch is the second low-voltage side winding L 2a Switch S4 and energy storage capacitor C are connected in series with switch S2. m2It is configured in series. The emitter of switch S3 is connected to the collector of switch S1, and the collector of switch S4 is connected to the emitter of switch S2. The energy storage capacitor C... m1 One end of the capacitor is connected to the collector of switching transistor S3, and the other end is connected to the collector of switching transistor S2. The energy storage capacitor C... m2 One end is connected to the collector of the switching transistor S2, and the other end is connected to the emitter of the switching transistor S4.
[0009] The subsequent circuit includes: a high-voltage side voltage regulator and filter capacitor C2, and a dual-coupled inductor voltage multiplier circuit with reverse blocking. The voltage across the voltage regulator and filter capacitor C2 is the high-voltage side voltage E2; the dual-coupled inductor voltage multiplier circuit with reverse blocking consists of the first high-voltage side winding L. 1b Second high-voltage side winding L 1b Switched capacitor C m3 Composed of switching transistors S5, S7, and S8; the first high-voltage side winding L 1b With the first low-voltage side winding L 1a Both are two windings in a coupled inductor, the second high-voltage side winding L 2b With the second low-voltage side winding L 2a These are two windings in another coupled inductor, with the first low-voltage side winding L... 1a Second low-voltage side winding L 2a The terminal connected to the same pole as the low-voltage side voltage E1 is the reference terminal, and the first low-voltage side winding L... 1a With the first high-voltage side winding L 1b The other end corresponding to the same name terminal and the second low-voltage side winding L 2a With the second high-voltage side winding L 2b The other ends of the corresponding terminals are connected; the emitters of switching transistor S7 and S8 are connected to form reverse blocking; the switched capacitor C m3 The positive terminal of the transistor is connected to the collector of the switching transistor S7; the emitter of the switching transistor S5 is connected to the first low-voltage side winding L. 1a With the first high-voltage side winding L 1b The corresponding terminals are connected, and its collector is connected to the collector of the switching transistor S8; the collector of the switching transistor S6 is connected to the positive terminal of the high-voltage side voltage E2, and its emitter is connected to the collector of the switching transistor S8, thus connecting the high-voltage side voltage regulator and filter capacitor to the voltage multiplier circuit.
[0010] The pre-stage circuit and the post-stage circuit are cascaded, that is, the collector of the switching transistor S3 is connected to the emitter of the switching transistor S5, and the emitter of the switching transistor S4 is connected to the negative terminal of the high-voltage side voltage E2.
[0011] Compared with the prior art, the beneficial effects of the present invention are:
[0012] 1) It overcomes the disadvantage that energy cannot flow bidirectionally in general high-variable-ratio topologies, making its application scenarios more extensive.
[0013] 2) During the voltage reduction process, the extreme duty cycle can be avoided, and a larger voltage reduction ratio can be achieved.
[0014] 3) It combines the advantages of IPOS structure and voltage multiplier module, reduces ripple through interleaved control, and is tightly connected between modules through magnetic coupling, which helps to improve power density.
[0015] 4) The boost ratio can be flexibly changed by adjusting the coupling coefficient and turns ratio, which has strong adaptability to some specific applications.
[0016] 5) The switching transistor has low current and voltage stress, resulting in excellent heat dissipation. Therefore, switching devices with low voltage ratings and low on-resistance can be selected to reduce switching losses and improve efficiency.
[0017] 6) The leakage inductance of the coupled inductor solves the reverse recovery problem of the diode and improves the reliability of the converter. Attached Figure Description
[0018] Figure 1 This is a circuit diagram of an interleaved parallel bidirectional DC-DC converter;
[0019] Figure 2 This is the equivalent circuit diagram of an interleaved parallel bidirectional DC-DC converter;
[0020] Figure 3 This is a basic waveform diagram of the present invention in boost mode;
[0021] Figure 4 This is a modal diagram of the present invention in boost mode;
[0022] Figure 4 In the diagram, af corresponds to the working mode diagrams of modes I to VI corresponding to the boosting process.
[0023] Figure 5 This is a basic waveform diagram of the present invention in the buck mode;
[0024] Figure 6 This is a schematic diagram of the working modes I-IV of the present invention in buck mode.
[0025] Figure 6 In the diagram, a is the working mode diagram corresponding to mode I [t0-t1] and the pressure reduction process, b is the working mode diagram corresponding to mode II: [t1-t2] and the pressure reduction process, and mode IV: [t3-t4] and the pressure reduction process, and c is the working mode diagram corresponding to mode III: [t2-t3] and the pressure reduction process. Detailed Implementation
[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0027] like Figure 1 As shown, an interleaved parallel bidirectional DC-DC converter includes a front-end circuit and a rear-end circuit, which are cascaded together.
[0028] The front-end circuit includes: a low-voltage side voltage regulator and filter capacitor C1, and two bidirectional BUCK-BOOST branches connected in parallel with the low-voltage side voltage regulator and filter capacitor. The voltage across the voltage regulator and filter capacitor C1 is the low-voltage side voltage E1; the first parallel branch is the first low-voltage side winding L. 1a Switch S3 is connected in series with switch S1, and switch S3 is connected in series with energy storage capacitor C. m1 Series connection; the second parallel branch is the second low-voltage side winding L 2a Switch S4 and energy storage capacitor C are connected in series with switch S2. m2 It is configured in series. The emitter of switch S3 is connected to the collector of switch S1, and the collector of switch S4 is connected to the emitter of switch S2. The energy storage capacitor C... m1 One end of the capacitor is connected to the collector of switching transistor S3, and the other end is connected to the collector of switching transistor S2. The energy storage capacitor C... m2 One end is connected to the collector of the switching transistor S2, and the other end is connected to the emitter of the switching transistor S4.
[0029] The subsequent circuit includes: a high-voltage side voltage regulator and filter capacitor C2, and a dual-coupled inductor voltage multiplier circuit with reverse blocking. The voltage across the voltage regulator and filter capacitor C2 is the high-voltage side voltage E2; the dual-coupled inductor voltage multiplier circuit with reverse blocking consists of the first high-voltage side winding L. 1b Second high-voltage side winding L 1b Switched capacitor C m3 Composed of switching transistors S5, S7, and S8; the first high-voltage side winding L 1b With the first low-voltage side winding L 1a Both are two windings in a coupled inductor, the second high-voltage side winding L 2b With the second low-voltage side winding L 2a These are two windings in another coupled inductor, with the first low-voltage side winding L... 1a Second low-voltage side winding L 2a The terminal connected to the same pole as the low-voltage side voltage E1 is the reference terminal, and the first low-voltage side winding L... 1a With the first high-voltage side winding L1b The other end corresponding to the same name terminal and the second low-voltage side winding L 2a With the second high-voltage side winding L 2b The other ends of the corresponding terminals are connected; the emitters of switching transistor S7 and S8 are connected to form reverse blocking; the switched capacitor C m3 The positive terminal of the transistor is connected to the collector of the switching transistor S7; the emitter of the switching transistor S5 is connected to the first low-voltage side winding L. 1a With the first high-voltage side winding L 1b The corresponding terminals are connected, and its collector is connected to the collector of the switching transistor S8; the collector of the switching transistor S6 is connected to the positive terminal of the high-voltage side voltage E2, and its emitter is connected to the collector of the switching transistor S8, thus connecting the high-voltage side voltage regulator and filter capacitor to the voltage multiplier circuit.
[0030] The pre-stage circuit and the post-stage circuit are cascaded, that is, the collector of the switching transistor S3 is connected to the emitter of the switching transistor S5, and the emitter of the switching transistor S4 is connected to the negative terminal of the high-voltage side voltage E2.
[0031] This invention can operate in both boost and buck modes, with voltage turns ratios M and M, respectively. up and M down .
[0032]
[0033] Where k is the coupling coefficient of the two coupled inductors, N is the turns ratio of the primary and secondary sides, D1 is the duty cycle of the main switches S1 and S2 in boost mode, and D2 is the duty cycle of S3 and S4 in buck mode.
[0034] When the converter is in boost mode (S1 and S2 are off), the voltage across it is C. m1 and C m2 The voltage, and the corresponding voltage stress are
[0035]
[0036] During the voltage boost process, when S3 and S4 are turned off, the corresponding voltage stress is:
[0037]
[0038] When the converter is in the step-down process, the voltage stresses of S1, S2, S3, and S4 are:
[0039]
[0040] Example 2: Based on the example, this design also discloses the corresponding equivalent circuit, such as... Figure 2As shown in the diagram. S1 and S3 are complementary to S2 and S4, respectively. S1 and S2 are controlled by phase shift, with their trigger signals differing in phase by π / 2, and each having a duty cycle greater than 0.5. S5 and S6 function as freewheeling diodes in boost mode and are conducting in buck mode. S7 and S8 are simultaneously conducting in boost mode and simultaneously turning off in buck mode, serving as reverse blocking.
[0041] The working principle is as follows:
[0042] In boost mode, energy is transferred from the low-voltage side to the high-voltage side. The low-voltage side voltage regulator capacitor is connected in parallel with the low-voltage side DC power supply, and the high-voltage side voltage regulator capacitor is connected in parallel with the load. When the duty cycle D1 is greater than 0.5, the converter operates in CCM mode. In one switching cycle T... s Internally, based on the switching states of the eight power devices, the converter has six main operating states. The drive signal waveforms, excitation current waveforms, leakage inductance current waveforms, input current waveforms, and voltage multiplier unit current waveforms for S1, S2, S3, and S4 are as follows: Figure 3 As shown, the operating modes corresponding to the boost process are as follows: Figure 4 As shown.
[0043] 1) Mode I: such as Figure 4 As shown in (a), during the period [t0-t1], S1 is on, S2 remains on, S3 begins to turn off, and S4 remains off. Due to the leakage inductance of the coupled inductor, its first low-voltage winding current i Lk1 The second low-voltage winding current i increases rapidly. Lk2 The value decreases rapidly, at which point i S6 Slowly decrease, when i S6 When the value decreases to 0, this mode ends.
[0044] 2) Mode II: such as Figure 4 As shown in (b), the switching state of the power devices remains unchanged at time [t1-t2]. At this time, S1 and S2 remain on, while S3 and S4 remain off. The low-voltage side DC power supply simultaneously charges the leakage inductance and magnetizing of the coupled inductors, storing energy in both sets of low-voltage side windings. Since the high-voltage side windings of the two coupled inductors are in anti-series configuration, the voltage across them is 0 after series connection. At this time, the freewheeling diode D... S5 and D S6 Reverse cutoff, thus the subsequent voltage multiplier unit does not work.
[0045] 3) Module III: such as Figure 4 As shown in (c), during the period [t2-t3], S1 remains on, S2 begins to turn off, S3 remains off, and S4 begins to turn on. The low-voltage side DC power supply and the second low-voltage side winding supply power to capacitor C through S4. m2During charging, the energy stored in the two low-voltage side windings is transferred to the high-voltage side via coupling, making the high-voltage side windings function as a controlled voltage source within the voltage multiplier unit. At this time, the operating voltage is in the negative half-cycle, D... S5 Conduction, D S6 Reverse cutoff. The high-voltage side winding of the coupled inductor is connected via D. S5 To capacitor C m3 Charge.
[0046] 4) Modal IV: such as Figure 4 As shown in (d), during the period [t3-t4], S1 remains on, S2 begins to conduct, S3 remains off, and S4 begins to turn off. Due to the leakage inductance of the coupling inductor, the loop current i of the subsequent voltage multiplier unit... S5 The value gradually decreases until it reaches 0, at which point the mode ends.
[0047] 5) Modal V: such as Figure 4 As shown in (e), S1 and S2 remain on during time [t4-t5], while S3 and S4 remain off. At this time, the downstream stage of the converter fails, and the low-voltage side winding stores energy, with the same state as at time II.
[0048] 6) Modal VI: such as Figure 4 As shown in (f), during the time interval [t5-t6], S1 is turned off, S2 remains on, S3 is on, and S4 remains off. At this time, the low-voltage side DC power supply not only charges the second low-voltage side winding, but also, together with the first low-voltage side winding, charges capacitor C through S3. m1 Charging. At this time, the high-voltage side winding of the coupled inductor is equivalent to a controlled voltage source operating in the positive half-cycle, D S5 Reverse cutoff, D S6 Conduction, with C m1 C m2 and C m3 They supply power to the load together.
[0049] In buck mode, energy is transferred from the high-voltage side of the converter to the low-voltage side. The high-voltage side voltage regulator capacitor is connected in parallel with the high-voltage side DC power supply, and the low-voltage side voltage regulator capacitor is connected in parallel with the load. S5 and S6 remain on, while S7 and S8 remain off, thus removing the voltage multiplier module composed of the coupling inductor and the switched capacitor. S3 and S4 act as the main power devices, controlling their on / off state; D2 is denoted as the duty cycle of S3 and S4. S1 and S2 act as auxiliary on / off devices, complementing S3 and S4. In one cycle T... s Internally, based on the state of the switching transistors and the current flow direction, the converter has three operating states. The waveforms of the drive signals S1, S2, S3, and S4, the current waveforms of the main switches S3 and S4, the leakage inductance current waveform, and the output current waveform within one cycle of the converter are as follows: Figure 5 As shown, the operating mode diagram corresponding to the pressure reduction process is as follows: Figure 6 As shown.
[0050] 1) Mode I: [t0-t1] (e.g.) Figure 6 (a) At time S3, the circuit starts to turn on; S4 remains off; S1 starts to turn off; and S2 remains on. At this time, due to the inductor L1 being blocked by the capacitor C... m1 Magnetization, inductor current i Lk1 The current increases linearly. Simultaneously, inductor L2 transfers energy to capacitor C1, and the inductor current i... Lk2 The speed decreases linearly. This mode ends when switch S3 is turned off.
[0051] 2) Mode II: [t1-t2] (e.g.) Figure 6 (b) At time S3, the circuit begins to turn off; S4 remains off; S1 begins to turn on; and S2 remains on. At this time, inductors L1 and L2 transfer energy to capacitor C. m1 Inductor current i Lk1 and i Lk2 Linear decrease. This mode ends when S4 is activated.
[0052] 3) Modulus III: [t2-t3] (e.g.) Figure 6 (c) At time S4, the circuit starts to turn on; S3 remains off; S2 starts to turn off; and S1 remains on. At this time, due to the inductor L2 being blocked by the capacitor C... m2 Magnetization, inductor current i Lk2 The current increases linearly. Simultaneously, inductor L1 transfers energy to capacitor C1, and the inductor current i... Lk1 Linear decrease. This mode ends when switch S4 is turned off. This mode is the symmetrical operation of mode I.
[0053] 4) Modal IV: [t3-t4] (e.g.) Figure 6 (b) At time S4, the circuit begins to turn off; at time S3, the circuit remains off; at time S2, the circuit begins to turn on; and at time S1, the circuit remains on. This mode is the same as Mode II. This mode ends when S3 begins to turn on.
[0054] This invention, based on the traditional bidirectional Buck-Boost topology, proposes a new approach using an interleaved parallel input stage, a series output capacitor, and a dual-coupled inductor voltage doubler module with reverse blocking in the output stage. A coupling inductor is introduced to connect the front and rear stages. The buck-boost ratio of the topology is adjusted by controlling the duty cycle of the low-voltage power devices in the front stage, and bidirectional power transfer is achieved by changing the switching state of the high-voltage side transistors. For the buck operation mode, four transistors are controlled simultaneously, achieving a high buck gain ratio without reaching the maximum duty cycle. This converter not only reduces input current ripple through the interleaved parallel structure but also achieves high voltage gain by leveraging the coupling between the input inductor and the voltage doubler module inductor.
[0055] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.
[0056] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. An interleaved parallel bidirectional DC-DC converter, comprising a front-end circuit and a rear-end circuit, characterized in that, The front-end circuit is connected to the back-end circuit. The front-end circuit includes a capacitor C1 and two bidirectional BUCK-BOOST branches that are connected in parallel with the capacitor C1. The back-end circuit includes a capacitor C2 and a dual-coupled inductor voltage multiplier circuit with reverse blocking. The voltage across capacitor C1 is the low-voltage side voltage E1, and the first bidirectional BUCK-BOOST branch is the first low-voltage side winding L. 1a Switch S3 is connected in series with switch S1, and switch S3 is connected in series with energy storage capacitor C. m1 The second bidirectional BUCK-BOOST branch is connected in series and is located on the second low-voltage side winding L. 2a Switch S4 and energy storage capacitor C are connected in series with switch S2. m2 Composed of series connection; The emitter of switch S3 is connected to the collector of switch S1, and the collector of switch S4 is connected to the emitter of switch S2. The energy storage capacitor C... m1 One end of the capacitor is connected to the collector of switching transistor S3, and the other end is connected to the collector of switching transistor S2. The energy storage capacitor C... m2 One end is connected to the collector of switch S2, and the other end is connected to the emitter of switch S4; The voltage across capacitor C2 is the high-voltage side voltage E2; the dual-coupled inductor voltage multiplier circuit with reverse blocking consists of the first high-voltage side winding. L 1b Second high-voltage side winding L 2b Switched capacitor C m3 It consists of switching transistors S5, S7 and S8; The first high-voltage side winding L 1b With the first low-voltage side winding L 1a Both are two windings in a coupled inductor, the second high-voltage side winding L 2b With the second low-voltage side winding L 2a They are two windings in another coupled inductor; With the first low-voltage side winding L 1a Second low-voltage side winding L 2a The terminal connected to the low-voltage side voltage E1 is the reference terminal, and the first low-voltage side winding L... 1a With the first high-voltage side winding L 1b The other end corresponding to the same name terminal and the second low-voltage side winding L 2a With the second high-voltage side winding L 2b The other ends of the corresponding terminals are connected; the emitters of switching transistors S7 and S8 are connected, and the switching capacitor C... m3 The positive terminal of the transistor is connected to the collector of the switching transistor S7; the emitter of the switching transistor S5 is connected to the first low-voltage side winding L. 1a With the first high-voltage side winding L 1b The corresponding terminals are connected, and its collector is connected to the collector of switch S8; the collector of switch S6 is connected to the positive terminal of high voltage side voltage E2, and the emitter of switch S6 is connected to the collector of switch S8. The collector of the switching transistor S3 is connected to the emitter of the switching transistor S5, and the emitter of the switching transistor S4 is connected to the negative terminal of the high-voltage side voltage E2, thus cascading the front-end circuit and the back-end circuit.
2. The interleaved parallel bidirectional DC-DC converter according to claim 1, characterized in that, It operates in both boost and buck modes, with voltage turns ratios of M and M respectively. up and M down Where k is the coupling coefficient of the two coupled inductors, N is the turns ratio of the primary and secondary sides, D1 is the duty cycle of the main switches S1 and S2 in boost mode, and D2 is the duty cycle of S3 and S4 in buck mode.
3. The interleaved parallel bidirectional DC-DC converter according to claim 2, characterized in that, When the converter is in boost mode, i.e., when S1 and S2 are off, the voltage across it is C. m1 and C m2 The voltage, and the corresponding voltage stress are: During the voltage boosting process, when S3 and S4 are turned off, the corresponding voltage stresses are: When the converter is in the step-down process, the voltage stresses of S1, S2, S3, and S4 are: