Power detection device and detection power range correction method

Abstract

The present application relates to a power detection device and a method for calibrating a detection power range. The power detection device includes a power detector circuit, a filter circuit, and a calibration circuit system. The power detector circuit detects a first signal to generate a second signal. The filter circuit filters the second signal to generate a third signal. The calibration circuit system calculates first signal strength information in response to the third signal, adjusts a gain of the power detector circuit to obtain second signal strength information, and combines the first and second signal strength information to calibrate the detection power range of the power detector circuit to be linear.

Description

Technical Field

[0001] The present application relates to a power detection device, and more particularly to a power detection device and a detection power range calibration method applied to a transmitter circuit. Background Art

[0002] In practical applications, the output power of a transmitter circuit may fluctuate due to environmental conditions (such as temperature) and variations in antenna impedance, exceeding the permitted range of communication protocol standards. A power detector circuit can be used to detect the transmitter circuit's output power and adjust it in real time. However, existing power detector circuits may become oversaturated at higher output powers or have a narrow detection power range, making them unsuitable for many communication applications. Summary of the Invention

[0003] In some embodiments, a power detection device includes a power detector circuit, a filter circuit, and a calibration circuit system. The power detector circuit is configured to detect a first signal to generate a second signal. The filter circuit is configured to filter the second signal to generate a third signal. The calibration circuit system is configured to calculate first signal strength information in response to the third signal, adjust a gain of the power detector circuit to obtain second signal strength information, and combine the first signal strength information with the second signal strength information to calibrate the detection power range of the power detector circuit to be linear.

[0004] In some embodiments, a detection power range calibration method includes the following operations: detecting a first signal through a power detector circuit to generate a second signal; filtering the second signal to generate a third signal; calculating first signal strength information in response to the third signal; and adjusting a gain of the power detector circuit to obtain second signal strength information, and combining the first signal strength information with the second signal strength information to calibrate the detection power range of the power detector circuit to be linear.

[0005] The features, practices and effects of the present application are described in detail below with reference to preferred embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A schematic diagram of a transmission system according to some embodiments of the present application;

[0007] Figure 2A A schematic diagram of signal strength information drawn according to some embodiments of the present application;

[0008] Figure 2B A schematic diagram of correcting multiple signal strength information according to some embodiments of the present application;

[0009] Figure 2C A schematic diagram of calculating an offset value according to some embodiments of the present application;

[0010] Figure 3A A schematic diagram of signal strength information drawn according to some embodiments of the present application;

[0011] Figure 3B A schematic diagram of correcting the slopes of multiple signal strength information according to some embodiments of the present application; and

[0012] Figure 4 The flowchart is a detection power range correction method according to some embodiments of the present application. DETAILED DESCRIPTION

[0013] All terms used herein have their ordinary meanings. The definitions of the above terms in commonly used dictionaries and any examples of their use in this application are provided for illustrative purposes only and should not limit the scope and meaning of this application. Similarly, this application is not limited to the various embodiments described herein.

[0014] As used herein, the terms "coupled" or "connected" may refer to direct physical or electrical contact between two or more components, or indirect physical or electrical contact between two or more components, or to the mutual operation or action of two or more components. As used herein, the term "circuit" may refer to a device composed of at least one transistor and / or at least one active or passive component connected in a specific manner to process signals.

[0015] As used herein, the term "and / or" includes any combination of one or more of the listed associated items. Terms such as first, second, and third are used herein to describe and identify individual elements. Thus, a first element herein could also be referred to as a second element without departing from the intent of this application. For ease of understanding, similar elements in the drawings will be designated with the same reference numerals.

[0016] Figure 1This is a schematic diagram of a transmission system 100 according to some embodiments of the present application. Transmission system 100 includes a transmitter circuit 110, a power amplifier circuit 120, an antenna 130, a receiver circuit 140, and a signal path 141. Transmitter circuit 110 can transmit a signal S1 via power amplifier circuit 120 and antenna 130. Receiver circuit 140 includes a signal path 142 and a calibration circuit system 143. Signal path 141 operates in conjunction with calibration circuit system 143 as a power detection device, which can be used to calibrate the gain of transmitter circuit 110 (and / or power amplifier circuit 120). Signal path 142 acts as a general receiver path, receiving signals from transmitter circuit 110 via antenna 130 for use by subsequent circuits or devices.

[0017] Specifically, signal path 141 includes a power detector circuit 141A and a filter circuit 141B. In some embodiments, power detector circuit 141A is used to detect signal S1 to generate signal S2. In some embodiments, power detector circuit 141A may be (but not limited to) an envelope detector circuit or a peak detector circuit. In some embodiments, the gain of power detector circuit 141A can be adjusted based on the control of correction circuit system 143. For example, based on the control of correction circuit system 143, the bias setting of power detector circuit 141A can be adjusted to thereby set the gain of power detector circuit 141A. The above-described method for adjusting the gain of power detector circuit 141A is for illustrative purposes only and is not intended to be limiting. Filter circuit 141B is used to filter signal S2 to generate signal S3. In some embodiments, filter circuit 141B may be (but not limited to) a low-pass filter circuit or a band-pass filter circuit. Signal path 142 includes a low-noise amplifier circuit 142A and a down-conversion circuit 142B. Low-noise amplifier circuit 142A processes signal S2 to generate signal S4. Down-conversion circuit 142B modulates signal S4 (e.g., by lowering the frequency of signal S4) to generate signal S5. In some embodiments, down-conversion circuit 142B may be, but is not limited to, a mixing circuit.

[0018] As previously described, calibration circuitry 143 is a circuit component of receiver circuitry 140. When calibration circuitry 143 receives signal S3 from signal path 141, it can be used to adjust the gain of transmitter circuitry 110 (and / or power amplifier circuitry 120). Before transmission begins, calibration circuitry 143 can adjust the gain of power detector circuitry 141A to obtain signals S3 with varying powers. In response to these signals S3, calibration circuitry 143 can obtain multiple pieces of signal strength information to calibrate the detection power range of power detector circuitry 141A to ensure linearity. When calibration circuitry 143 receives signal S5 from signal path 142, calibration circuitry 143 can process signal S5 for subsequent signal processing.

[0019] In some embodiments, the calibration circuitry 143 includes a multiplexer circuit 143A, an analog-to-digital converter circuit 143B, and a baseband circuit 143C. The multiplexer circuit 143A is configured to selectively receive signal S3 from signal path 141 or signal S5 from signal path 142 based on a mode signal SM, and output the received signal as signal S6. For example, when the mode signal SM has a first logic value (e.g., a logic value of 1), the multiplexer circuit 143A outputs signal S3 as signal S6. Under these conditions, the calibration circuitry 140 operates in a calibration mode to adjust the gain of the transmitter circuit 110 (and / or the power amplifier circuit 120). When the mode signal SM has a second logic value (e.g., a logic value of 0), the multiplexer circuit 143A outputs signal S5 as signal S6. Under these conditions, the calibration circuitry 140 operates in a normal mode to process signal S5 transmitted from the signal path 142.

[0020] The analog-to-digital converter circuit 143B converts the signal S6 into a digital signal SD. When the signal S6 is the signal S5 (i.e., operating in the normal mode), the baseband circuit 143C can be used to process the digital signal SD for subsequent signal processing. Alternatively, when the signal S6 is the signal S3 (i.e., operating in the calibration mode), the baseband circuit 143C can be used to analyze the digital signal SD to obtain a plurality of signal strength information (hereinafter referred to as a plurality of signal strength information I1-I2). n ), and combine these signal strength information I1~I n The detection power range of the power detector circuit 141A is corrected to be linear. Figures 2A to 2C In some embodiments, the baseband circuit 143C may include (but is not limited to) a digital signal processor circuit (not shown) and a register circuit (not shown). The digital signal processor circuit may be used to analyze the digital signal SD to obtain a plurality of signal strength information I1-I n The register circuit can store multiple signal strength information I1~In and multiple parameters (such as the preset slope value S mentioned later) ideal , offset value b and offset values K1~K n etc).

[0021] The baseband circuit 143C can control the gain of the transmitter circuit 110 and / or the power amplifier circuit 120 to meet the requirements of different communication protocol standards. In some embodiments, the plurality of signal strength information I1-I n It is a transmitter signal strength indicator (TSSI). Before the transmission starts, the baseband circuit 143C can provide a transmitter signal strength indicator to the subsequent circuit so that the subsequent circuit can know the current transmission signal strength and adjust the circuit setting accordingly. Generally speaking, the larger the detection power range of the power detector circuit 141A, the more acceptable communication applications. If the output power of the transmitter circuit 110 (and / or the power amplifier circuit 120) is greater, the power detector circuit 141A is set to have a higher gain. Otherwise, at a fixed gain, the power detector circuit 141A may be oversaturated due to the signal S1 with too high power, and cannot correctly judge the output power of the transmitter circuit 110. In some embodiments, to avoid the above situation, the baseband circuit 143C may adjust the gain of the power detector circuit 141A when operating in the calibration mode to generate multiple signal strength information I1~I n , and combine these signal strength information I1~I n The detection power range of the power detector circuit 141A is corrected. In this way, the detection power range of the power detector circuit 141A can be linearly increased.

[0022] In some embodiments, the baseband circuit 143C may execute Figures 2A to 2C and / or Figures 3A to 3B Multiple operations in order to correct the detection power range. Figure 2A FIG1 is a schematic diagram of signal strength information I1 according to some embodiments of the present application. When the power detector circuit 141A has a first gain, the baseband circuit 143C can obtain a power value P according to the signal SD converted from the signal S3. out (equivalent to the current output power of the transmitter circuit 110), and can be adjusted according to the power value P out , preset slope value S ideal , offset value b and offset value K1 to obtain signal strength information I1. In this example, the preset slope value S ideal The offset value b is a pre-stored fixed parameter, and the offset value K1 can be used Figure 2C For example, the preset slope value S idealThe offset value b can be estimated by measuring the existing circuit and pre-stored in the baseband circuit 143C. In some embodiments, the preset slope value S ideal It can be (but is not limited to) 8. In some embodiments, the signal strength information I1 is the sum of the first value and the offset value b, where the first value is the power value P out With the initial power value P out0 (which may be zero or the initial power of the transmitter circuit 110) and the preset slope value S ideal In other words, the signal strength information I1 can be expressed as follows:

[0023] I1=S ideal ×(P out -P out0 )+b

[0024] After obtaining the signal strength information I1 corresponding to the first gain, the baseband circuit 143C can adjust the gain of the power detector circuit 141A to the second gain, and obtain the signal strength information I2 corresponding to the second gain through similar operations. Similarly, the baseband circuit 143C can obtain a plurality of signal strength information I1 to I2 corresponding to different gains. n .

[0025] Figure 2B The modified multiple signal strength information I1-I are drawn according to some embodiments of the present application. n Schematic diagram of . Figure 2B As shown, after obtaining multiple signal strength information I1~I n Afterwards, the baseband circuit 143C can use multiple offset values K1 to K n Shift multiple signal strength information I1~I n Thus, multiple signal strength information I1~I n The signal strength information I1 can be aligned with the line segment T. For example, the baseband circuit 143C can add the offset value K1 and the signal strength information I1 to align the signal strength information I1 with the line segment T. The baseband circuit 143C can add the offset value K2 and the signal strength information I2 to align the signal strength information I2 with the line segment T. The baseband circuit 143C can add the offset value K n With signal strength information I n , so that the signal strength information I n Aligned with line segment T. Equivalently, the baseband circuit 143C uses multiple offset values K1-K n Combines multiple signal strength information I1~I n , to expand the detection power range of the power detector circuit 141A and maintain the linearity of the detection power range.

[0026] Figure 2CSchematic diagram of calculating the offset value K1 according to some embodiments of the present application. Due to system errors or variations in actual circuits, multiple offset values K1 to K n In some embodiments, the baseband circuit 143C may utilize Figure 2B Multiple signal strength information I1~I n For example, after the baseband circuit 143C calibrates the transmitter circuit 110 and the power amplifier circuit 120, the baseband circuit 143C can adjust the gain of the transmitter circuit 110 and / or the power amplifier circuit 120 so that the power amplifier circuit 120 sequentially outputs a signal with a power P n-1 The signal S1 and the signal with power P n According to the signal strength information I1, the baseband circuit 143C can obtain the power value P out P n-1 When the corresponding transmitter signal strength index is T n-1 According to the signal strength information I2, the baseband circuit 143C can obtain the power value P out P n When the corresponding transmitter signal strength index is T n In this way, the baseband circuit 143C can be used according to the power value P n-1 , signal strength index T n-1 , power value P n , signal strength index T n And the preset slope value S ideal Get the offset value K1. For example, Figure 2C As shown, the offset value K1 is equivalent to the signal strength index T n With signal strength indicator T n-1 The difference between the two values minus the value L1, where the value L1 can be expressed as the value d and the preset slope value S ideal The product of (that is, d×S ideal ), the value d is the power value P n With power value P n-1 In other words, the offset value K1 can be expressed as follows:

[0027] K1=(T n -T n-1 )-d×S ideal =(T n -T n-1 )-(P n -P n-1 )×S ideal

[0028] Through the above calculation, the baseband circuit 143C can obtain a more accurate offset value K1. Similarly, the baseband circuit 143C can use the multiple signal strength information I2-I n The remaining offset values K2~K are calculated by using two of them. n .

[0029] Figure 3A FIG1 is a schematic diagram of a signal strength information I1 drawn according to some embodiments of the present application. In the previous embodiment, a plurality of signal strength information I1 to I n Preset to have a preset slope value S ideal In some embodiments, according to system errors or actual circuit changes, a plurality of signal strength information I1-I n The slopes of Figure 3B (S310 shown in FIG. 3 ) To more accurately calibrate the detection power range, under the condition that the gain of the power detector circuit 141A is fixed, the baseband circuit 143C can obtain a power value P1 and a signal strength indicator T1 corresponding to the power value P1 based on the signal SD converted from the signal S3. Then, the baseband circuit 143C can control the transmitter circuit 110 (and / or the power amplifier circuit 120) to output a signal S3 having a higher power. The baseband circuit 143C can obtain a power value P2 (which is greater than the power value P1) and a signal strength indicator T2 corresponding to the power value P2 based on the signal SD converted from the signal S3. The baseband circuit 143C can calculate the slope offset value S based on the power value P1, the signal strength indicator T1, the power value P2, and the signal strength indicator T2. offset , and according to the slope offset value S offset Correction preset slope value S ideal To obtain the correction slope value S. Slope offset value S offset is a ratio between the first difference and the second difference, the first difference being the difference between the power value P2 and the power value P1, and the second difference being the difference between the signal strength indicator T2 and the signal strength indicator T1. In other words, the slope offset value S offset It can be expressed as the following formula:

[0030]

[0031] Figure 3B A method of correcting multiple signal strength information I1-I according to some embodiments of the present application is shown. n Schematic diagram of the slope. After obtaining the slope offset value S offset After that, the baseband circuit 143C can be adjusted according to the slope offset value S offset Correction preset slope value S ideal To obtain the corrected slope value S. For example, the slope of the signal strength information I1 can be corrected to the corrected slope value S, which can be a preset slope value Sideal and slope offset value S offset In other words, the correction slope value S can be expressed as follows:

[0032]

[0033] like Figure 3B In operation S320 shown, the slope of the signal strength information I1 after correction may be close to (or the same as) the slope of the line segment T. Then, the baseband circuit 143C may adjust the gain of the power amplifier circuit 120 to obtain a plurality of signal strength information I2 to I3 corresponding to different gains of the power amplifier circuit 120 (or the power detector circuit 141A). n Through similar operations, the baseband circuit 143C can obtain the remaining signal strength information I2~I n The slope offset value S of each offset and the correction slope value S to correct the remaining signal strength information I2 to I n The slope of (operation S320; wherein the dotted line segment is the signal strength information I1 to I n ). In this way, the baseband circuit 143C can continue to execute Figure 2B and Figure 2C Multiple operations to combine multiple signal strength information I1~I n is a line segment T (operation S330).

[0034] Figure 4 The flowchart of a detection power range calibration method 400 according to some embodiments of the present application is shown. In operation S410, a first signal (e.g., signal S1) is detected by a power detector circuit to generate a second signal (e.g., signal S2). In operation S420, the second signal is filtered to generate a third signal (e.g., signal S3). In operation S430, first signal strength information (e.g., signal strength information I1) is calculated in response to the third signal. In operation S440, the gain of the power detector circuit is adjusted to obtain second signal strength information (e.g., signal strength information I2), and the first signal strength information and the second signal strength information are combined to calibrate the detection power range of the power detector circuit to be linear.

[0035] The above-mentioned operations can be referred to in the aforementioned embodiments, and thus will not be repeated here. The above-mentioned operations of the detection power range calibration method 400 are merely examples and are not intended to limit the order in which they must be performed. Without departing from the operational manner and scope of the various embodiments of the present application, the various operations in the detection power range calibration method 400 may be appropriately added, replaced, omitted, or performed in a different order (e.g., they may be performed simultaneously or partially simultaneously).

[0036] In summary, the power detection device and detection power range calibration method in some embodiments of the present application can adjust the gain of the power detector to integrate multiple signal strength information into a single line segment, thereby linearly expanding the detection power range of the power detector circuit.

[0037] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application. Those skilled in the art may modify the technical features of the present application based on the explicit or implicit content of the present application. All such modifications may fall within the scope of the patent protection sought by the present application. In other words, the scope of patent protection of the present application shall be subject to the scope of the patent application defined in this specification.

[0038]

Explanation of symbols

[0039] 100: Transmission System

[0040] 110: Transmitter circuit

[0041] 120: Power amplifier circuit

[0042] 130: Antenna

[0043] 140: Receiver Circuit

[0044] 141, 142: Signal path

[0045] 141A: Power Detector Circuit

[0046] 141B: Filter Circuit

[0047] 142A: Low Noise Amplifier Circuit

[0048] 142B: Frequency reduction circuit

[0049] 143: Correction circuit system

[0050] 143A: Multiplexer Circuit

[0051] 143B: Analog-to-Digital Converter Circuits

[0052] 143C: Baseband Circuit

[0053] 400: Detection power range calibration method

[0054] b: offset value

[0055] d, L1: numerical value

[0056] I1, I2, I n : Signal strength information

[0057] K1, K2, K n : offset value

[0058] T: Line segment

[0059] P1, P2, P n : Power value

[0060] P out : Power value

[0061] P out0 : Initial power value

[0062] S1, S2, S3, S4, S5, S6: Signal

[0063] S310, S320, S330, S410, S420, S430, S440: Operation

[0064] SD: digital signal

[0065] SM: Mode signal

[0066] S ideal : Preset slope value

[0067] S offset : Slope offset value

[0068] T1, T2, T n-1 、T n : Signal strength indicator.

Claims

1. A power detection device, comprising: a power detector circuit for detecting a first signal under a first gain condition to generate a second signal; a filter circuit for filtering the second signal to generate a third signal; and a calibration circuit system for calculating first signal strength information in response to the third signal, adjusting the first gain of the power detector circuit to a second gain to obtain second signal strength information, and combining the first signal strength information with the second signal strength information so that the combined first signal strength information and the second signal strength information are aligned on a line segment, thereby calibrating a detection power range of the power detector circuit to be linear; in, The first signal strength information represents a first variation relationship in which the transmitter signal strength index varies linearly with the power value under the first gain condition, and the second signal strength information represents a second variation relationship in which the transmitter signal strength index varies linearly with the power value under the second gain condition. The combining the first signal strength information and the second signal strength information so that the combined first signal strength information and the second signal strength information are aligned on a line segment includes: The first signal strength information and the second signal strength information are shifted so that the shifted first signal strength information and the shifted second signal strength information are located on the same line segment.

2. The power detection device of claim 1 , wherein the calibration circuit system is a circuit portion of a receiver circuit, and the calibration circuit system comprises: a multiplexer circuit for selectively outputting the third signal or a fourth signal from the receiver circuit as a fifth signal; an analog-to-digital converter circuit for converting the fifth signal into a digital signal; and A baseband circuit is used to analyze the digital signal to obtain the first signal strength information and the second signal strength information, and combine the first signal strength information and the second signal strength information to calibrate the detection power range. 3 . The power detection device as claimed in claim 1 , wherein the calibration circuit system is configured to obtain a first power value according to the third signal, and obtain the first signal strength information according to the first power value, a predetermined slope value, and a first offset value. 4 . The power detection device as claimed in claim 3 , wherein the first signal strength information is a sum of a first value and the first offset value, and the first value is a product of a difference between the first power value and an initial power value and the preset slope value. 5 . The power detection device as claimed in claim 3 , wherein the calibration circuit system is further configured to shift the first signal strength information using a second offset value.

6. The power detection device of claim 5 , wherein the calibration circuit system is configured to obtain a second power value according to the third signal after adjusting the gain, and to obtain the second offset value according to the first power value, a first transmit signal strength indicator corresponding to the first power value, the second power value, and a second transmit signal strength indicator corresponding to the second power value.

7. The power detection device of claim 6 , wherein the correction circuit system is configured to subtract a second value from a difference between the first transmit signal strength indicator and the second transmit signal strength indicator to obtain the second offset value, wherein the second value is a product of the difference between the first power value and the second power value and the predetermined slope value.

8. The power detection device of claim 3 , wherein the correction circuit system is further configured to obtain a second power value greater than the first power value based on the third signal, calculate a slope offset value based on the first power value, a first transmit signal strength indicator corresponding to the first power value, the second power value, and a second transmit signal strength indicator corresponding to the second power value, correct the preset slope value based on the slope offset value to generate a corrected slope value, and use the corrected slope value to correct the first signal strength information.

9. The power detection device of claim 8 , wherein the slope offset value is a ratio between a first difference and a second difference, the first difference being a difference between the second power value and the first power value, and the second difference being a difference between the second transmit signal strength indicator and the first transmit signal strength indicator.

10. A detection power range calibration method, comprising: A power detector circuit detects a first signal under a first gain condition to generate a second signal; filtering the second signal to generate a third signal; Calculating first signal strength information in response to the third signal; and adjusting the first gain of the power detector circuit to a second gain to obtain second signal strength information, and combining the first signal strength information with the second signal strength information so that the combined first signal strength information and the second signal strength information are aligned on a line segment, thereby calibrating a detection power range of the power detector circuit to be linear; in, The first signal strength information represents a first variation relationship in which the transmitter signal strength index varies linearly with the power value under the first gain condition, and the second signal strength information represents a second variation relationship in which the transmitter signal strength index varies linearly with the power value under the second gain condition. The combining the first signal strength information and the second signal strength information so that the combined first signal strength information and the second signal strength information are aligned on a line segment includes: The first signal strength information and the second signal strength information are shifted so that the shifted first signal strength information and the shifted second signal strength information are located on the same line segment.

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