Physically unclonable functional device, semiconductor device and operating method thereof

Abstract

A physically unclonable function (PUF) device includes a first inverter and a second inverter, each of the first inverter and the second inverter including a common gate node and a common drain node. The common drain node of the first inverter is electrically connected to the common gate node of the second inverter. The PUF device also includes: a common output node; a first RMD electrically connected to the common drain node and the common output node of the first inverter; and a second RMD electrically connected to the common drain node and the common output node of the second inverter. Embodiments of the present invention also relate to semiconductor devices and methods of operating the same.

Description

Technical Field

[0001] Embodiments of the present invention relate to a physically unclonable functional device, a semiconductor device, and an operating method thereof. Background Art

[0002] The semiconductor integrated circuit (IC) industry produces a wide variety of analog and digital devices to solve problems in many different fields. Advances in semiconductor process technology nodes have gradually reduced component size and tightened pitch, resulting in increasing transistor density. ICs are becoming smaller.

[0003] A physically unclonable function (PUF) is a physical device that, for a given input and conditions (e.g., a challenge), outputs a physically defined digital fingerprint response, which serves as a unique identifier. PUFs are commonly used in applications with high security requirements, such as cryptography. Summary of the Invention

[0004] An embodiment of the present invention provides a physically unclonable function (PUF) device, comprising: a first inverter and a second inverter, each of the first inverter and the second inverter comprising: a common gate node; and a common drain node, wherein the common drain node of the first inverter is electrically connected to the common gate node of the second inverter; a common output node; a first resistive memory device (RMD) electrically connected to the common drain node and the common output node of the first inverter; and a second resistive memory device electrically connected to the common drain node and the common output node of the second inverter.

[0005] Another embodiment of the present invention provides a semiconductor device comprising: M inverters, M being a positive integer, the M inverters being electrically connected in series; and (M-1) pairs of resistive memory devices (RMD), wherein a first inverter of the M inverters is electrically connected to a first node, the first node is electrically connected to a first resistive memory device of a first pair of resistive memory devices of the (M-1) pairs of resistive memory devices and a second inverter of the M inverters, and each inverter after the first inverter of the M inverters is electrically connected in parallel to a pair of resistive memory devices of the (M-1) pairs of resistive memory devices.

[0006] Another embodiment of the present invention provides a method for operating a semiconductor device, the method comprising: setting a first resistive memory device of a pair of resistive memory devices (RMD) in a first programming operation; setting a second resistive memory device of the pair of resistive memory devices in a second programming operation; randomly resetting one of the first resistive memory device or the second resistive memory device in a third programming operation; and performing a read operation on the pair of resistive memory devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] One or more embodiments are illustrated by way of example and not limitation in the accompanying drawings, in which like reference numerals designate like elements throughout. Unless otherwise disclosed, the accompanying drawings are not drawn to scale.

[0008] Figure 1 is a block diagram of an integrated circuit (IC) according to some embodiments.

[0009] Figure 2A 、 Figure 2B and Figure 2C is a schematic diagram of an IC according to some embodiments.

[0010] Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D is a schematic diagram of an IC according to some embodiments.

[0011] Figure 4A 、 Figure 4B and Figure 4C is a schematic diagram of an IC according to some embodiments.

[0012] Figure 4D is a schematic diagram of an IC according to some embodiments.

[0013] Figure 5 is a flow chart of a method of operating a semiconductor device according to some embodiments.

[0014] Figure 6 is a flow chart of a method of manufacturing a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0015] The following disclosure discloses many different embodiments or examples for implementing the different features of the subject matter. Specific examples of components, materials, values, steps, operations, arrangements, etc. are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc. are contemplated. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the embodiments and / or configurations discussed.

[0016] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. Spatially relative terms are intended to include different orientations of the device in use or during operation in addition to the orientation shown in the figures. The device can be positioned in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. In some embodiments, the term "standard cell structure" refers to a standardized building block included in a library of various standard cell structures. In some embodiments, various standard cell structures are selected from its library and used as components in a layout diagram representing a circuit.

[0017] In various embodiments, a semiconductor device includes a PUF, the PUF including two inverters connected in series, a first resistive memory device (RMD) coupled between an output node and an output of the first inverter, and a second RMD coupled between an output node and an output of the second inverter. A single PUF (also referred to as a PUF cell) or an array including multiple PUF cells can thus be used for both random programming operations and controlled programming operations.

[0018] In a random programming operation, the semiconductor device is configured to set two RMDs to an initial programming state by applying a combination of a first programming voltage and a reference voltage to an output node and an input of a first inverter in a first write operation and a second write operation, and to reset the first RMD or the second RMD in a third write operation, by randomly determining the first RMD or the second RMD by applying a second programming voltage to the input of the first inverter while floating the output node.

[0019] In a controlled programming operation, the semiconductor device is configured to set the first RMD and the second RMD to opposite programming states by applying a reference voltage or a third programming voltage to the input of the first inverter and applying a fourth programming voltage to the output node in a single write operation, wherein the voltage level of the fourth programming voltage is between the voltage levels of the reference voltage and the third programming voltage.

[0020] As discussed below with respect to various embodiments, the semiconductor device thus includes a reconfigurable PUF cell or array capable of providing one or more PUF signatures and / or generating one or more random signals or numbers.

[0021] Figure 1 1 is a block diagram of an IC 100 according to some embodiments. The IC 100 includes a semiconductor device 102 including a PUF 104.

[0022] IC 100 is referred to as a chip or microchip and is a collection of electronic circuits or semiconductor devices on a small flat piece of semiconductor material (e.g., a wafer, die, or substrate), typically silicon or other suitable materials within the contemplation of the present invention. IC 100 supports one or more metal oxide semiconductor field effect transistors (MOSFETs), such as semiconductor device 102, integrated into the chip; however, other suitable transistors and electronic components are within the contemplation of the present invention. IC 100 is electrically connected to, incorporated into, or houses one or more semiconductor devices, such as semiconductor device 102.

[0023] Semiconductor device 102 is an electronic component or group of electronic components configured to exploit the electronic properties of one or more semiconductor materials (e.g., silicon, germanium, or gallium arsenide, as well as organic semiconductors or other suitable materials within the contemplated scope of the present invention) for its function, such as PUF 104.

[0024] The unclonability of a PUF (e.g., PUF 104) means that each IC with a PUF has a unique and unpredictable way of mapping challenges to responses, even when the ICs are identical in design and layout and manufactured using the same process. The applied stimulus is called a challenge, and the response is the PUF's reaction. The challenge and its corresponding response together form a challenge-response pair (CRP). The identity of the PUF is established by the properties of the microstructure itself. Such devices are resistant to spoofing attacks because this structure is not directly revealed by the challenge-response mechanism.

[0025] PUF 104 is an IC device that includes a microstructure that is configured to uniquely and unpredictably map challenges to responses, thereby supporting the randomness and unpredictability of the CRP. In some embodiments, PUF 104 is reconfigurable. In some embodiments, PUF 104 is configured to be reconfigurable to change the challenge or response behavior of PUF 104 without physically replacing the associated PUF. In some embodiments, PUF 104 is unclonable because each IC (such as IC 100 having a PUF (such as PUF 104)) has a unique and unpredictable way of mapping challenges to responses, even when the design and layout between ICs are exactly the same and manufactured using the same process. The challenge / response behavior of PUF 104 is configurable because the challenge / response behavior of PUF 104 is not fixed, but the uniqueness is retained in the manufactured hardware and can be modified without changing the hardware.

[0026] In some embodiments, IC 100 including semiconductor device 102 includes one or more instances of PUF 104, including the following: Figures 2A to 2C In some embodiments, examples of PUF 104 include the following: Figures 3A to 3D PUF 304 discussed below. In some embodiments, as described below with respect to Figures 4A to 4D As discussed, examples of PUF 104 include PUFs 404A-404F configured for random signal generation and time sampling.

[0027] Figure 2A 、 Figure 2B and Figure 2C is a schematic diagram of an IC 200 according to some embodiments. The IC 200 is an example of the IC 100 and includes a semiconductor device 202 as an example of the semiconductor device 102 and includes a PUF 204 as an example of the PUF 104. The semiconductor device 202 is configured to perform Figure 2A and Figure 2B The write operation shown in Figure 2C The read operation shown in .

[0028] PUF 204 includes two inverters 208A and 208B extending on the X-axis. Inverters 208A and 208B are electrically connected at nodes 210A and 210C. Node 210A is a common drain node of a p-type metal oxide semiconductor (PMOS) transistor 212A and an n-type metal oxide semiconductor (NMOS) transistor 214A. PMOS transistor 212A and NMOS transistor 214A also share a common gate node at node 210B that is electrically connected to input 216A. In some embodiments, input 216A is configured to carry a programming voltage (VPP), a power supply at or near ground, a potential below ground, an erase voltage (VEE) for resetting one or more RMDs, or a read voltage (V in ) or more. Other suitable voltages are within the contemplated scope of the present invention. A pair of RMDs 209 includes an RMD 220A electrically connected to node 210A of inverter 208A and an RMD 220B electrically connected to node 210D of inverter 208B. A common output node 210E electrically connects RMDs 220A and 220B.

[0029] Inverters 208A and 208B are electrically connected at a common gate node (node ​​210C) of PMOS transistor 212B and NMOS transistor 214B. PMOS transistor 212B and NMOS transistor 214B also share node 210D, a common drain node. Each of NMOS transistors 214A and 214B is electrically connected to a ground node 218. In some embodiments, each of NMOS transistors 214A and 214B is electrically connected to a power supply (VSS) that is at or near ground, at a potential lower than ground, at a potential lower than the programming voltage (VPP) at input 216A, at zero volts or a negative voltage, or at other suitable voltages within the contemplated scope of the present invention. Each of PMOS transistors 212A and 212B is electrically connected to a power supply node 216B. In some embodiments, power supply node 216B is configured to carry a drain voltage (VDD) ( Figure 2C ), the drain voltage (VDD) is at or near the operating voltage of the PMOS transistors 212A and 212B, a positive voltage, or other suitable voltage within the contemplated scope of the present invention.

[0030] In operation, inverters 208A and 208B generate output voltages at respective nodes 210A and 210D. The output voltages at nodes 210A and 210D are of opposite logic levels to the input voltages at nodes 210B and 210C. For example, when the input voltage at node 210B is high (e.g., 1 bit or VPP), the output voltage at node 210A is low (e.g., 0 bit, 0V, or ground), the input voltage at node 210C is low (e.g., 0 bit, 0V, or ground), and the output voltage at node 210D is high (e.g., 1 bit or VPP).

[0031] Each of inverters 208A and 208B is constructed using a single NMOS transistor 214A, 214B connected to a single PMOS transistor 212A, 212B. In some embodiments, NMOS transistors 214A, 214B are connected via a resistor to implement the inverting function. In some embodiments, the inverters are constructed with bipolar junction transistors (BJTs) in resistor-transistor logic (RTL), transistor-transistor logic (TTL) configurations, or other suitable configurations within the contemplated scope of the present invention. In some embodiments, the inverters are constructed with transistors in RMD-transistor logic.

[0032] In some embodiments, inverters 208A and 208B operate at fixed voltage levels input at nodes 210B and 210C corresponding to a logical 0 or 1 (e.g., binary low and high). In some embodiments, inverters 208A and 208B function as logic gates that switch between two voltage levels. In some embodiments, the actual voltage is determined by the implementation.

[0033] RMD 220A and 220B are electrically connected to nodes 210A and 210D.RMD 220A and 220B are paired, and a pair of RMD 209 is electrically connected in parallel with inverter 208B.In certain embodiments, inverter 208A, the first inverter or the inverter electrically connected to input 216A are inverters that are not connected in parallel with the corresponding pair of RMD 209.That is, the output (such as the output at node 210A) of the first inverter (such as inverter 208A) is the input of the first pair of RMD 209, and the first pair of RMD 209 is connected in parallel with the second inverter (such as inverter 208B).In certain embodiments, the first inverter 208A is connected in parallel with the corresponding pair of RMD 209.A pair of RMD 209 is connected together at node 210E. In some embodiments, node 210E is configured to carry a programming voltage (VPP) to program one or more RMDs, a power supply greater than zero but less than VPP, zero or ground, or a voltage equal to or less than V in or other suitable voltages within the contemplated scope of the present invention.

[0034] An RMD (e.g., RMD 220A or 220B) is a non-volatile memory (NVM) device that includes one or more resistive elements controllable to have a first physical state and a second physical state corresponding to a high resistance value and a low resistance value (or a range of values). High resistance values ​​are those values ​​greater than a first threshold value, while low resistance values ​​are those values ​​less than a second threshold value, which is less than or equal to the first threshold value. In some embodiments, the high resistance value and the low resistance value correspond to corresponding high and low logic states, for example, one and zero. In some embodiments, the high and low resistance values ​​and the low resistance value correspond to corresponding low and high logic states. In some embodiments, the ratio of the high resistance value to the low resistance value is approximately equal to or greater than ten.

[0035] In some embodiments, the RMD (e.g., RMD 220A or 220B) is a unipolar memory device, wherein the RMD can be set (or reset) to each of a first physical state and a second physical state independently of the polarity of an applied voltage. In some embodiments, the RMD (e.g., RMD 220A or 220B) is a bipolar memory device, wherein the RMD is configured to be set to a first physical state based on a first polarity of an applied voltage and to be set to a second physical state based on a second polarity of an applied voltage opposite to the first polarity.

[0036] exist Figures 2A to 2C In the embodiment depicted in FIG, each of RMDs 220A and 220B is a unipolar memristor device, also referred to in some embodiments as a resistive random access memory (RRAM) device. In various embodiments, the memristor includes one or more layers comprising one or more materials, such as titanium dioxide (TiO2), one or more polymers, carbon nanotubes, or other suitable materials, and the memristor is configured to be controllable to have high and low resistance values.

[0037] exist Figures 2A to 2C In the embodiment depicted in FIG, each of the RMDs 220A and 220B is a two-terminal device. In some embodiments, one or both of the RMDs 220A and 220B have more than two terminals, e.g., are three-terminal devices, and the semiconductor device 202 is configured to use one or more additional terminals to control one or both of the RMDs 220A and 220B, e.g., during write operations and / or read operations.

[0038] Figures 2A to 2C The orientations of the RMDs 220A and 220B depicted in FIG are non-limiting examples provided for illustrative purposes. In some embodiments, one or both of the RMDs 220A and 220B have different Figures 2A to 2CIn some embodiments, RMDs 220A and 220B are bipolar RMDs with opposite orientations.

[0039] In some embodiments, one or both of RMDs 220A or 220B is an RRAM other than a unipolar memristor, such as a bipolar RRAM device, a phase change memory (PCM) device, a ferroelectric tunnel junction (FTJ) device, or a magnetic tunnel junction (MTJ) device.

[0040] In some embodiments, an RRAM device is a type of NVM device that is configured to switch between a high resistance value and a low resistance value corresponding to the resistance of a dielectric material. In operation, the RRAM device controls defects in a thin oxide layer, called oxygen vacancies (oxide bond sites from which oxygen has been removed), so that the current level changes under a given electric field strength.

[0041] In some embodiments, a PCM (also referred to in some embodiments as PCME, PRAM, PCRAM, bidirectional unified memory, or chalcogenide RAM) device is an NVM device that includes one or more materials (e.g., chalcogenide glass) configured to respond to heat generated by passing an electric current through a heating element during operation by switching between an amorphous state and a crystalline state.

[0042] A FTJ device is a type of NVM device that includes one or more ferroelectric materials with an electric polarization that is reversible by applying an external electric field. In operation, the polarization of the one or more ferroelectric materials corresponds to a hysteresis effect, thereby achieving high and low resistance values.

[0043] An MTJ device is a type of NVM device that includes two ferromagnetic layers separated by a thin insulator and is configured to switch between states (in which the magnetization directions of the two layers are aligned or perpendicular) using tunnel magnetoresistance (TMR), thereby achieving high and low resistance values ​​in operation.

[0044] In some embodiments, the resistance values ​​of RMDs 220A and 220B are set / reset to Figure 2A ) logical state and "yes" ( Figure 2B ) logical state is written to the PUF. In the NOT logical state, the PUF 204 is configured as a NOT gate or inverter, wherein the input signal is inverted to generate an output signal during operation, as discussed below. In the YES logical state, the PUF 204 is configured as a YES gate or buffer, wherein the input signal is maintained to generate an output signal during operation, as discussed below. In some embodiments, a pair of RMDs 209 comprising opposite states are configured to provide data storage functionality during operation.

[0045] exist Figure 2AIn the write operation shown in FIG, during the set / reset operation of the NOT logic state, the voltage at input 216A and node 216B is set to VPP, and the voltage at node 210E is V x is set to a value between VPP and ground so that the voltage at node 210D is VPP, which is greater than the voltage V at node 210E. x The direction of the electric field strength 222B at the RMD 220B is upward from the node 210D toward the node 210E, the current flows from the node 210D to 210E in the direction of the electric field strength 222B, and the resistance of the RMD 220B is from R L Change to R H (e.g., a reset operation).

[0046] continue Figure 2A In the example shown in FIG. 2 , the voltage at node 210A is 0 V because it is the inverse of the signal applied at node 210B (which is VPP). The direction of the electric field strength 222A at RMD 220A is from node 210E downward to node 210A, the current flows from node 210E to node 210A in the direction of the electric field strength 222A, and the resistance of RMD 220A is from R H Change to R L (e.g., set operations).

[0047] exist Figure 2A In the embodiment shown in FIG. 1 , the voltage V x The RMDs 220A and 220B are set to a level between VPP and ground and are configured to generate electric field strengths 222A and 222B having values ​​corresponding to set and reset operations. In some embodiments, each of the RMDs 220A and 220B is a unipolar RMD, and the electric field strength 222A is greater than (e.g., twice) or less than (e.g., half) the electric field strength 222B. In some embodiments, each of the RMDs 220A and 220B is a bipolar RMD, and the electric field strength 222A is approximately equal to, greater than, or less than the electric field strength 222B, and the set and reset operations correspond to the RMDs 220A and 220B having polarities opposite to the polarities of the electric field strengths 222A and 222B.

[0048] In some embodiments, as Figure 2A The directions and magnitudes of the electric field strengths 222A and 222B shown in FIG are used to program the PUF 204 to a “NOT” logic state. Figure 2C In the read operation shown in FIG, with PUF 204 programmed to the NOT logic state, when the input at input 216A is zero or low, the output voltage V at node 210E is 100V based on the current flowing from node 210A, through RMD 220A, through node 210E, and back to node 210D. YIn some embodiments, the voltage V Y It is expressed by equation (1).

[0049] V Y =V in -(I·R 220A )≈V in (1)

[0050] In some embodiments, since the resistance of RMD 220A is low R L , the voltage drop across RMD 220A is small, and therefore the voltage V at 210E Y Basically close to V in , a voltage greater than zero, or 1 bit. In some embodiments, V in Less than VPP. In some embodiments, V in 10 times smaller than VPP. In some embodiments, V in is less than VPP, so that the electric field strengths 222A and 222B do not change, thus changing the resistance of the RMDs 220A, 220B and changing the PUF 204.

[0051] In some embodiments, when the voltage at input 216A is V in or high, the voltage at node 210A is 0, and the voltage at node 210D is V in In some embodiments, the output voltage V at node 210E is Y is 0V or low because the resistance at RMD 220B is high. In some embodiments, the voltage at node 210E is represented by equation (2).

[0052] V Y =V in -(I·R 220B )≈0 (2)

[0053] In some embodiments, the voltage drop across RMD 220B is close to V in , and therefore, V Y Or node 210E is almost zero.

[0054] exist Figure 2B In the write operation shown in FIG, during the set / reset operation for the “yes” logic state, the voltage at input 216A is set to 0V, the voltage at node 216B is set to VPP, and the voltage at node 210E is V x is set to a value between VPP and ground so that the voltage at node 210A is VPP, which is greater than the voltage V at node 210E. x .

[0055] The electric field strength 222A at RMD 220A is directed from node 210A to node 210E, and current flows from node 210A to node 210E in the direction of electric field strength 222A. The current changes the resistance of RMD 220A from R L Change to R H , because the programming voltage VPP is high enough to change the resistance of RMD 220A. The electric field strength 222B is directed from node 210E to 210D, and the resistance of RMD 220B changes from R H Change to R L .

[0056] like Figure 2B The directions and magnitudes of the electric field strengths 222A and 222B are shown to program the PUF 204 to a "yes" logic state. Figure 2C In the read operation shown in FIG, with PUF 204 programmed to a “yes” logic state, when V in When the voltage at node 210A is zero or low, the voltage at node 210A is V in In some embodiments, the output voltage V at node 210E is Y is 0V or low because the resistance at RMD 220A is high. In some embodiments, the voltage V Y It is expressed by equation (3).

[0057] V Y =V in -(I·R 220A )≈0 (3)

[0058] In some embodiments, the voltage drop across RMD 220A is close to V in , and therefore V Y In some embodiments, when the voltage at input 216A is V in or high, the voltage at node 210A is zero, and the voltage at node 210D is V in Since the resistance at RMD 220B is low, the voltage drop across RMD 220B is small, and node 210E is close to V in So for a YES logic state, in operation, the voltage in corresponds to the voltage out, just with a slight delay in the buffer.

[0059] exist Figure 2B In the embodiment shown in FIG. 1 , the voltage V xThe RMDs 220A and 220B are set to a level between VPP and ground and are configured to generate electric field strengths 222A and 222B having values ​​corresponding to set and reset operations. In some embodiments, each of the RMDs 220A and 220B is a unipolar RMD, and the electric field strength 222A is greater than (e.g., twice) or less than (e.g., half) the electric field strength 222B. In some embodiments, each of the RMDs 220A and 220B is a bipolar RMD, and the electric field strength 222A is approximately equal to, greater than, or less than the electric field strength 222B, and the set and reset operations correspond to the RMDs 220A and 220B having polarities opposite to the polarities of the electric field strengths 222A and 222B.

[0060] In some embodiments, inverters 208A and 208B are located in the transistor level or in the first level. In some embodiments, RMDs 220A and 220B are located in the RMD level or in the second level above the first level. In some embodiments, other suitable configurations are within the contemplation of the present invention, such as RMDs 220A and 220B being located in the first level and inverters 208A and 208B being located in the second level above the first level. In some embodiments, additional inverters (such as inverters 208A and 208B) and additional pairs of RMDs (such as a pair of RMDs 209) are added to the existing inverters 208A and 208B and the existing pair of RMDs 209. Figure 3A In some embodiments, multiple rows of inverters extending on the X-axis are separated by a distance on the Y-axis ( Figure 4A In some embodiments, multiple pairs of RMDs extending from multiple rows of inverters are located in the second level, the third level, the fourth level, and the Nth level (where N is a non-negative integer). Figure 4C In some embodiments, multiple columns of inverters (e.g., in the 1st, 3rd, 5th, and N-1th levels, where N is a non-negative integer) are electrically connected to multiple pairs of RMDs ( Figure 4C In some embodiments, multiple rows of inverters having multiple pairs of RMDs are located below other multiple rows of inverters having multiple pairs of RMDs in a vertically stacked manner (see Figure 4A ).

[0061] With the configuration discussed above, the IC 200 including the semiconductor device 202 includes the PUF 204, which can be controllably programmed to "NOT" and "YES" logic states. Figures 3A to 3D As discussed, PUF 204 (eg, by inclusion in PUF 304) can also be randomly programmed to one of a "not" or "yes" logic state.

[0062] Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D is a schematic diagram of an IC 300 according to some embodiments. IC 300 is an example of IC 100 and includes a semiconductor device 302 as an example of semiconductor device 102 and includes a PUF 304 as an example of PUF 104. Semiconductor device 302 is configured to perform Figures 3A to 3C The write operation shown in Figure 3D The read operation shown in .

[0063] exist Figures 3A to 3D In the embodiment depicted in FIG, PUF 304 includes the following components, which correspond to the components described above: Figures 2A to 2C The discussed inverters 208A and 208B and the array of inverters 308A-308E (the total set of inverters 308) and the paired RMDs 309A-309D of the RMD 209. For clarity, the description of the set of inverters 308 is simplified.

[0064] In some embodiments, PUF 304 is a unipolar 4-bit array. In some embodiments, PUF 304 is an example of PUF 204, except for additional connected inverters 308C, 308D, and 308E, and additional pairs of RMDs 309B, 309C, and 309D connected in parallel with the additional inverters 308C, 308D, and 308E. In some embodiments, the paired RMDs 309A and 309C extend along the Z axis and are located in another layer or level of the set of inverters 308. In some embodiments, PUF 304 includes a set of inverters 308 extending along the X axis and including inverters 308A, 308B, 308C, 308D, and 308E. In some embodiments, RMDs 309B and 309D extend along the Y and Z axes in another layer or level of the set of inverters 308.

[0065] Inverter 308A is electrically connected to write line 316A, which is configured for programming PUF 304, as discussed in detail below. Inverter 308A is also electrically connected to read line 316B, which is configured for reading the state or bit of paired RMDs 309A, 309B, 309C, and 309D (hereinafter referred to as paired RMDs 309), as discussed in detail below. In some embodiments, PUF 304 is a bipolar 4-bit array.

[0066] The set of inverters 308 is electrically connected in series with a pair of RMDs 309 electrically connected in parallel with each of the inverters 308B, 308C, 308D, and 308E. In various embodiments, each RMD in the pair of RMDs 309 is a unipolar or bipolar RMD, as described above with respect to Figures 2A to 2Cdiscussed.

[0067] In some embodiments, as discussed below, the random switching characteristics in each RMD within the pair of RMDs 309 generate randomness for PUF 304. In some embodiments, random refers to a property described by a random probability distribution. In some embodiments, although random and randomness are different because the former generally refers to a modeling method and the latter generally refers to a phenomenon, the two terms can be used interchangeably. In some embodiments, a random process is further referred to as a stochastic process.

[0068] In some embodiments, two write operations or two program operations are performed (with Figure 2A and Figure 2B The single programming operation is opposite to the single programming operation) to set each RMD in the pair of RMDs 309 to a low resistance R L In some embodiments, the first write operation is Figure 3A A programming voltage VPP is applied to the write line 316A and each output node 310 to set the first RMD of the pair of RMDs 309 to a low resistance R L (SET Operation). In some embodiments, a program voltage VPP is applied to the write line 316A to set a single RMD of each pair of RMDs 309 to R L , such as pointing to R H Change to R L The output of each RMD of inverters 308A, 308C, and 308E is 0V or close to zero volts. In some embodiments, each RMD electrically connected to the output of inverters 308A, 308C, and 308E is connected to the output of inverters 308A, 308C, and 308E from R H Set to R L In some embodiments, each RMD electrically connected to the output of inverters 308B and 308D is maintained at R H or a previous state because there is no significant voltage difference between the outputs of inverters 308B and 308D and the voltage at output node 310 (e.g., both are at programming potential VPP). In some embodiments, each of the RMDs in the pair 309 that experiences a voltage difference of VPP or near VPP between the inverter output and output node 310 has a voltage difference from R H Change to R L In some embodiments, each RMD in the pair of RMDs 309 that experiences a zero or near-zero voltage difference between the inverter output and the output node 310 does not have a modified resistance of the RMD.

[0069] In some embodiments, Figure 3BA second write operation is shown in FIG. 1 . Zero volts is applied to write line 316A and a programming voltage VPP is applied to each output node 310 to set a single RMD in each pair of RMDs 309 to a low resistance R L (e.g., a set operation). In some embodiments, Figure 3B The write operation sets the RMD to a low resistance at the reference Figure 3A RMD is not affected during the write operation discussed.

[0070] In some embodiments, 0V is applied to the write line 316A to change (reconfigure) the resistance of one RMD in each pair of RMDs 309 to R L , such as pointing to R H Change to R L The output of each RMD of inverters 308B and 308D is 0V or close to zero volts. In some embodiments, each RMD electrically connected to the output of inverters 308B and 308D is from R H Set to R L In some embodiments, each RMD electrically connected to the output of inverters 308A, 308C, and 308E is maintained at R L or previous state because there is no significant voltage difference between the outputs of inverters 308A, 308C, and 308E and the voltage at output node 310 (e.g., both are at programming potential VPP). In some embodiments, each RMD in a pair of RMDs 309 that experiences a voltage difference of VPP or near VPP between the inverter output and output node 310 has a voltage difference from R H Change to R L In some embodiments, each RMD in a pair of RMDs 309 that experiences a zero or near-zero voltage difference between the inverter output and the output node 310 does not have a modified RMD resistance.

[0071] In some embodiments, after setting each pair of RMDs 309 (eg, resistors from R H Change to R L ), an erase voltage VEE is applied to write line 316A, and each output node 310 is allowed to float. Thus, the voltage output of the consecutive inverters of the set of inverters 308 corresponding to the erase voltage VEE is applied to the series connection of the RMDs in each pair of RMDs 309A-309D. In response to the applied erase voltage VEE, current (represented by the example of arrow 330 around the pair of RMDs 309C) flows through each pair of RMDs 309.

[0072] Because the two RMDs of a given pair of RMDs 309 are not identical based on manufacturing variations, the applied voltage VEE causes the first of the two RMDs to reset to a high resistance R at the second of the two RMDs. H Before reset to high resistance R H In some embodiments, the random nature of the reset operation is due to structural features of the RMDs. For example, each RMD is fabricated with random structural variations, where the first of the two RMDs has a lower threshold voltage than the second of the two RMDs in order to reset (e.g., change to a high resistance R H ).

[0073] Thus, the programmed state of the bits of PUF 304 is based on the uniqueness of the physical microstructure of each RMD. The PUF microstructure is based on random physical factors of the paired RMDs 309 introduced during manufacturing. In some embodiments, these factors are unpredictable and uncontrollable, which makes it almost impossible to copy or clone the structure. In some embodiments, PUF 304 is thus configured so that when a physical stimulus is applied to PUF 304, PUF 304 reacts in an unpredictable (but repeatable) manner due to the complex interaction of the stimulus with the physical microstructure of the paired RMDs 309. In some embodiments, the microstructure of the paired RMDs 309 depends on the physical factors introduced during manufacturing. In some embodiments, PUF 304 thus has an identity established by the properties of the paired RMDs 309. In some embodiments, PUF 304 thus resists spoofing attacks.

[0074] In some embodiments, once a single RMD is reset such that the reset operation stops, the current through a given pair of RMDs 309 is significantly reduced. In some embodiments, the current is configured to reset one RMD in each pair of RMDs 309. In some embodiments, the single RMD in each pair of RMDs 309 is reset by controlling the erase voltage VEE. In some embodiments, the single RMD in each pair of RMDs 309 is reset by controlling the erase voltage VEE and the amount of time that the erase voltage VEE is applied to the write line 316A. In some embodiments, the R H If RL is 1 bit and RL is 0 bit, then a pair of RMDs 309 is configured for a 1-bit representation of (1, 0). In some embodiments, each pair of RMDs 309 is configured to represent a single bit of either 1 or 0.

[0075] exist Figure 3D In the read operation shown in FIG, where the PUF 304 is programmed to a random logic state, a physical stimulus applied to the PUF 304 causes the PUF 304 to be programmed to a random logic state due to the stimulus at the read line 316B (V in) reacts in an unpredictable (but repeatable) manner due to the interaction of the applied stimulus (V in ) is called a challenge, and the response (output at node 310) is the reaction of PUF 304. The challenge and its corresponding response together form a CRP.

[0076] In some embodiments, to read the PUF 304, when a challenge (read voltage, V in ), the response is at output node 310. In some embodiments, a first subset of output nodes 310 is at a challenge voltage (e.g., V in or 1), and a second subset of output nodes 310 are low (eg, at or near 0V or 0).

[0077] In some embodiments, when the challenge voltage is at or near 0V, a first subset of output nodes 310 is at the challenge voltage (e.g., 0V) and a second subset of output nodes 310 is high (e.g., at V in or close to V in ).

[0078] In some embodiments, the output at node 310 provides a random 4-bit response (e.g., 0111, 1011, 1101, 1110, 1000, 0100, 0010, or 0001), where the output is determined by which RMD of each pair of RMDs 309 is selected from R L Reconfigure to R H The number of bits included in PUF 304 is a non-limiting example provided for illustration. In some embodiments, PUF 304 includes fewer or more than four bits.

[0079] In some embodiments, the bits of the PUF 304 of the semiconductor device 302 are independent and thus can be as described above with respect to Figures 2A to 2C Semiconductor device 302 is thus capable of generating an output having a selectable number of randomly programmed bits and / or controllably programmed bits.

[0080] In some embodiments, the semiconductor device 302 is configured to perform a sequential read operation on the PUF 304, wherein the sequentially read bits are used to generate an output signal. Since the bits are random, the output signal is thus configured as a random signal, and the random RMD is reset to R based on each pair of RMDs 309. H , the PUF 304 is thereby configured as a random number generator.

[0081] Figure 4A 、 Figure 4B 、 Figure 4C and Figure 4D 4 is a schematic diagram of an IC 400 according to some embodiments. IC 400 is an example of IC 100 and includes a semiconductor device 402 that includes a random number generator (RNG) 405. In some embodiments, RNG 405 is an example of semiconductor device 102. RNG 405 includes PUF arrays 404A, 404B, 404C, 404D, and 404E. Each of PUF arrays 404A, 404B, 404C, 404D, and 404E is an example of PUF 304.

[0082] RNG 405 includes several PUF arrays 404A, 404B, 404C, 404D, and 404E. In some embodiments, each of PUF arrays 404A, 404B, 404C, 404D, and 404E includes N inverters 408 and (N-1) pairs of RMDs 409, where N is a positive integer. Each pair of RMDs 409 is connected in parallel with the inverters 408 except for the first inverter, which instead begins with the second inverter 408A. In some embodiments, PUF arrays 404A, 404B, 404C, 404D, and 404E include different numbers of inverters and different numbers of pairs of RMDs 409. Other suitable inverter and RMD configurations are within the contemplated scope of the present invention.

[0083] exist Figures 4A to 4D In various embodiments depicted in FIG, prior to applying input 416 as discussed below, some or all of the PUF arrays (e.g., PUF arrays 404A, 404B, 404C, 404D, or 404E) are randomly programmed, e.g., as described above with respect to Figures 3A to 3D discussed.

[0084] In some embodiments, input 416 is a direct current (DC) voltage, such as voltage VPP, voltage VDD, or ground, and IC 400 operates as described above with respect to Figures 3A to 3D The discussed approach is configured as a three-dimensional (3D) random number generator as discussed below.

[0085] In some embodiments, input 416 is from a random signal generator (e.g., Figures 3A to 3DIn some embodiments, the output of the first RMD pair 409_A of the PUF array 404E is routed to the PUF array 404A via conductor 430. In some embodiments, the output of the second RMD pair 409_B of the PUF array 404E is routed to the PUF array 404B via conductor 432. In some embodiments, the output of the third RMD pair 409_C of the PUF array 404E is routed to the PUF array 404C via conductor 434. In some embodiments, the output of the fourth RMD pair 409_D of the PUF array 404E is routed to the PUF array 404D via conductor 436.

[0086] In some embodiments, the random signal 415 at input 416 is considered the first level of randomness (RDG), and the output from PUF array 404E on the X-axis is considered the second level of randomness based on the output through PUF arrays 404A, 404B, 404C, and 404D. In some embodiments, RNG 405 thus includes two levels of random number generation, the first random generation based on the time of the random signal generator, and the second random number generation based on the offset of PUF arrays 404A, 404B, 404C, and 404D from PUF array 404E on the X-axis. In some embodiments, the randomness of RNG 405 generates a second dimension (2D) of randomness (e.g., time, X) on PUF 304.

[0087] Figure 4B 4 is a schematic diagram of an IC 400A according to some embodiments. IC 400A is an example of IC 100 and includes a semiconductor device 402A as an example of RNG 405 and includes RNG 407. RNG 405 includes the components described above with respect to Figure 4A Discussed PUF array 404B and PUF array 404F. PUF array 404F is an example of PUF 304.

[0088] In some embodiments, RNG 407 includes PUF array 404F separated from PUF array 404B on the Z axis. In some embodiments, RNG 407 is RNG 411 ( Figure 4C In some embodiments, PUF array 404B receives input at conductor 432 from paired RMDs 409_B that have passed through two-dimensional randomness.

[0089] In some embodiments, the output of the first RMD pair 409_E of the PUF array 404B is routed to the PUF array 404F via conductor 440. In some embodiments, each of the PUF arrays 404A, 404B, 404C, and 404D of the RNG 405 outputs a signal from its corresponding first RMD pair 409_E to another PUF array (such as PUF array 404F) offset on the Z axis. In some embodiments, the routing of the random signal from the PUF array 404B to the PUF array 404F on the Z axis creates a third dimension (3D) of randomness (e.g., time, X, Z). In some embodiments, the outputs of the RMD pairs 409_F, 409_G, 409_H, and 409_I of the PUF array 404F are routed on the Y axis via conductors 442, 444, 446, and 448. In some embodiments, semiconductor device 402A, including PUF array 404F, is configured to generate a fourth dimension (4D) of randomness (e.g., time, X, Y, Z). In some embodiments, semiconductor device 402A is configured to generate random numbers based on four levels or dimensions of randomness RDG in RNG 407, which corresponds to increased entropy compared to random numbers based on fewer than four levels. In some embodiments, semiconductor device 402A, including a four-dimensional (4D) PUF, is capable of continuously outputting random numbers based on position and time (x, y, z, time).

[0090] Figure 4C 4 is a schematic diagram of IC 400B according to some embodiments. IC 400B is an example of IC 100 and includes semiconductor device 402B, which includes RNG 411 and RNGs 405A, 405B, 405C, 405D, and 405E, which are examples of RNG 405.

[0091] RNGs 405A, 405B, 405C, 405D, and 405E are stacked in the Z direction. RNG 405A includes instances of PUF arrays 404A, 404B, 404C, 404D, and 404E discussed above, and each of RNGs 405B, 405C, 405D, and 405E includes instances of PUF arrays 404A, 404B, 404C, and 404D.

[0092] RNG 411 includes a hierarchy of interlayer dielectrics (ILDs) 450, 452, 454, 456, and 458. Each ILD 450, 452, 454, 456, and 458 includes a corresponding one of RNGs 405A, 405B, 405C, 405D, or 405E. In some embodiments, RNG 409 corresponds to multiple instances of RNG 405, as each of ILDs 450, 452, 454, 456, and 458 includes an RNG corresponding to RNG 405. In some embodiments, RNGs 405B, 405C, 405D, and 405E do not include PUF array 404E. In some embodiments, RNG 411 corresponds to multiple instances of RNG 407 because RNGs 405B, 405C, 405D, and 405E in ILDs 452, 454, 456, and 458 are electrically connected and the outputs from PUF arrays 404A, 404B, 404C, and 404D are input to RNGs 405B, 405C, 405D, and 405E.

[0093] The outputs of the first pair of RMDs 409_E in each of the PUF arrays 404A, 404B, 404C, and 404D are electrically connected to the inputs of the corresponding PUF arrays 404A, 404B, 404C, and 404D in the RNG 405B in the ILD 452 via conductors 440. The outputs of the second pair of RMDs 409_G in each of the PUF arrays 404A, 404B, 404C, and 404D of the RNG 405A are electrically connected to the inputs of the corresponding PUF arrays 404A, 404B, 404C, and 404D of the RNG 405C in the ILD 454 via conductors 470. The outputs of the third pair of RMDs 409_H in each of the PUF arrays 404A, 404B, 404C, and 404D are electrically connected to the inputs of the corresponding PUF arrays 404A, 404B, 404C, and 404D of the RNG 405D in the ILD 456 via conductors 472. The outputs of the fourth pair of RMDs 409_I in each of the PUF arrays 404A, 404B, 404C, and 404D are electrically connected to the inputs of the corresponding PUF arrays 404A, 404B, 404C, and 404D of the RNG 405E in the ILD 458 via conductors 474.

[0094] In some embodiments, each of the outputs 460A, 460B, 460C, and 460D from RNGs 405A, 405B, 405C, 405D, and 405E is a 16-bit random number. In some embodiments, RNG 411 is embedded in a memory array (e.g., RRAM, PCM, etc.). In some embodiments, as described above with respect to Figures 3A to 3DAs discussed, the number of bits of the random number is adjustable. In some embodiments, RNG 411 is a 64-bit RNG comprising four ILD layers 452, 454, 456, and 458, wherein each layer outputs 16 bits in parallel from outputs 460A, 460B, 460C, and 460D. In some embodiments, the number of bits is adjustable.

[0095] In some embodiments, RNG 411 increases entropy, which provides increased randomness and produces a more secure PUF compared to other methods.In some embodiments, RNG 411 is referred to as a random time signal generator.

[0096] Figure 4D is a schematic diagram of IC 400B according to some embodiments. Figure 4D A cross-sectional view of a non-limiting example of an IC 400B is depicted, the IC 400B including N ILDs IL1, IL2, ... IL N , each ILD includes a pair of RMDs 409 .

[0097] exist Figure 4D In the embodiment depicted in FIG, random polarization within the ferromagnetic material of the paired RMDs 409 generates a source of randomness for PUF applications. The RMDs of the paired RMDs 409 include varying polarization intensities, as indicated by polarization arrows 480. Each pair of RMDs 409 has an unbalanced polarization such that one of the two RMDs has a lower switching threshold than the other of the two RMDs. In some embodiments, for example, Figure 3C As shown, the RMD with fewer or more polarization arrows changes from a low resistance R L Switch to a higher resistor R H In some embodiments, polarization is determined during fabrication of the RMD, thereby producing an unclonable PUF or PUF array according to the embodiments discussed above.

[0098] Figure 5 is a flow chart of a method 500 of operating a semiconductor device according to some embodiments. The method 500 may be used with a semiconductor device including a PUF array, such as described above with respect to Figures 1 to 4D One of the semiconductor devices 102 , 202 , 302 , 402 , 402A, or 402B in question.

[0099] Figure 5 The order in which the operations of method 500 are depicted is for illustration only; the operations of method 500 can be performed simultaneously or in different Figure 5 In some embodiments, Figure 5 The depicted operations are performed before, between, during, and / or after Figure 5In some embodiments, the operations of method 500 are a subset of a method of operating a circuit including a semiconductor device. In some embodiments, some or all of the operations of method 500 correspond to CRP.

[0100] At operation 502, a first RMD of a pair of RMDs is set in a first programming operation. Setting the first RMD includes applying a first voltage to serially connected inverters and applying a second voltage to a common node of the pair of RMDs in parallel with the inverters in the serially connected inverters.

[0101] In some embodiments, applying the first voltage and the second voltage includes applying the same voltage as the first voltage and the second voltage. In some embodiments, applying the first voltage to the series-connected inverters and applying the second voltage to the common node of the pair of RMDs includes applying the first voltage to the series-connected inverters and applying the second voltage to the common node of the pair of RMDs as described above with respect to Figure 3A The write line 316A in question and the node 310 have a voltage VPP applied thereto.

[0102] In some embodiments, setting the first RMD in the first programming operation includes setting the first RMD to the value described above. Figures 2A to 4D The low resistance R L .

[0103] In some embodiments, setting the first RMD of the pair of RMDs includes setting the above Figures 2A to 4D The pair of RMDs discussed are 209, 309A-309D, or 409 RMDs.

[0104] In some embodiments, the pair of RMDs is a pair of RMDs in a plurality of pairs of RMDs, and setting the first RMD in the pair of RMDs includes setting the first RMD of each pair of RMDs in the plurality of pairs of RMDs, e.g., Figures 3A to 3D The paired RMD309A-309D discussed above or Figures 4A to 4D Paired RMD 409 discussed.

[0105] At operation 504, a second RMD of the pair of RMDs is set in a second programming operation. Setting the second RMD includes applying a third voltage to the series-connected inverters and applying a second voltage to a common node of the pair of RMDs. In some embodiments, applying the third voltage to the series-connected inverters and applying the second voltage to the common node of the pair of RMDs includes applying a ground or 0V voltage at write line 316A and applying a voltage VPP at node 310, as described above with respect to Figure 3A discussed.

[0106] In some embodiments, setting the second RMD in the second programming operation includes setting the second RMD to the value described above. Figures 2A to 4D The low resistance RL .

[0107] In some embodiments, setting the second RMD of the pair of RMDs includes setting the above Figures 2A to 4D The pair of RMDs discussed is RMD 209, 309A-309D, or 409.

[0108] In some embodiments, the pair of RMDs is a pair of RMDs in a plurality of pairs of RMDs, and setting the second RMD in the pair of RMDs includes setting the second RMD of each pair of RMDs in the plurality of pairs of RMDs. Figures 3A to 3D The paired RMD309A-309D discussed above or Figures 4A to 4D Paired RMD 409 discussed.

[0109] In some embodiments, one or both of operations 502 or 504 further includes programming the two RMDs of another pair of RMDs to opposite settings, e.g., as described above with respect to a pair of RMDs 209 and 208. Figures 2A to 2C discussed.

[0110] At operation 506, a first RMD or a second RMD of a pair of RMDs is randomly reset in a third programming operation. Randomly resetting the first RMD or the second RMD includes applying a fourth voltage to the series-connected inverters and floating a common node of the pair of RMDs. In some embodiments, applying the fourth voltage to the series-connected inverters and floating the common node of the pair of RMDs includes applying an erase voltage VEE to the write line 316A and the floating node 310, as described above with respect to Figure 3A discussed.

[0111] In some embodiments, randomly resetting the first RMD or the second RMD in the third program operation includes resetting the first RMD or the second RMD to the value set forth above with respect to Figures 2A to 4D The high resistance R H .

[0112] In some embodiments, randomly resetting the first RMD or the second RMD includes resetting the above Figures 2A to 4D The pair of RMDs discussed are 209, 309A-309D, or 409 RMDs.

[0113] In some embodiments, the pair of RMDs is a pair of RMDs in a plurality of pairs of RMDs, and randomly resetting the first RMD or the second RMD includes resetting the first RMD or the second RMD of each pair of RMDs in the plurality of pairs of RMDs, for example, as described above with respect to Figures 3A to 3D Paired RMDs 309A-309D discussed above or regarding Figures 4A to 4D Paired RMD 409 discussed.

[0114] At operation 508, a read operation is performed on the pair of RMDs. Performing the read operation includes applying a fifth voltage to the serially connected inverters and measuring a voltage at a common node of the pair of RMDs. In some embodiments, applying the fifth voltage to the serially connected inverters and measuring a voltage at a common node of the pair of RMDs includes as described above with respect to Figures 2A to 2C The voltage V is applied to the input 216A. in and measuring the voltage at node 210E, or as described above with respect to Figure 3A The voltage V is applied to the write line 316A. in and measuring the voltage V at one of the nodes 310 Y .

[0115] In some embodiments, measuring the voltage at the common node of the pair of RMDs includes measuring the voltage at the common node of the pair of RMDs. Figures 2A to 4D The voltage at node 210E of the pair of RMDs 209 , node 310 of the pair of RMDs 309A- 309D, or the common node of the pair of RMDs 409 in question.

[0116] In some embodiments, the pair of RMDs is a pair of RMDs in a plurality of pairs of RMDs, and measuring the voltage at the common node of the pair of RMDs includes measuring the voltage at the common node of each pair of RMDs in the plurality of pairs of RMDs, such as described above with respect to Figures 3A to 3D Paired RMDs 309A-309D discussed above or regarding Figures 4A to 4D Paired RMD 409 discussed.

[0117] At operation 510, in some embodiments, a random number is output. Outputting the random number includes outputting the random number based on the read operation. In some embodiments, outputting the random number includes outputting the random number from the PUF array. In some embodiments, outputting the random number from the PUF array includes outputting the random number from the PUF array described above. Figures 3A to 3D PUF 304 discussed above or Figures 4A to 4D The RNG 405, 407 and / or 411 in question outputs random numbers.

[0118] At operation 512, in some embodiments, a random signal is output. Outputting the random signal includes outputting the random signal based on sequentially performing read operations. In some embodiments, outputting the random signal includes outputting the random signal from the PUF array. In some embodiments, outputting the random signal from the PUF array includes outputting the random signal from the PUF array described above. Figures 3A to 3D PUF 304 discussed above or Figures 4A to 4D The RNGs 405, 407 and / or 411 in question output a random signal.

[0119] By performing some or all of the operations of method 500, RMDs in a pair of RMDs are randomly programmed and read, thereby achieving the benefits discussed above with respect to ICs 100-400.

[0120] Figure 6 is a flow chart of a method 600 for fabricating a semiconductor device according to some embodiments. The method 600 is operable to form a semiconductor device including a PUF array, such as described above with respect to Figures 1 to 4D One of the semiconductor devices 102, 202, 302, 402, 402A, or 402B discussed. In some embodiments, the operations of method 600 are a subset of the operations of a method of forming a semiconductor wafer or die.

[0121] In some embodiments, the operations of method 600 are performed by Figure 6 In some embodiments, the operations of method 600 are performed in the order described in Figure 6 In some embodiments, one or more additional operations are performed before, during, between, and / or after the operations of method 600.

[0122] At operation 602, in some embodiments, a partially processed semiconductor wafer is received. Receiving the partially processed semiconductor wafer includes receiving a substrate including silicon and / or one or more other suitable semiconductor materials.

[0123] At operation 604, a first PUF array is constructed in a first ILD. Constructing the first PUF array includes constructing the first PUF array in the first ILD, which is an ILD (eg, a first or higher ILD) of a partially processed semiconductor wafer.

[0124] Constructing a first PUF array in a first ILD of a partially processed semiconductor wafer includes constructing a first plurality of inverters and a first plurality of pairs of RMDs, for example, configured as described above with respect to Figures 1 to 4D Inverters 208, 308A-308E or 408 and pairs of RMDs 209, 309A-309D or 409 operating as discussed.

[0125] In some embodiments, constructing the first PUF array in the first ILD includes the following steps: Figures 4A to 4D The first PUF array is constructed in the ILD IL1 discussed.

[0126] Building the first PUF array includes performing a first plurality of fabrication operations, such as one or more of lithography, diffusion, deposition, etching, planarization, or other operations suitable for building a first plurality of inverters and a first plurality of pairs of RMDs in the first ILD.

[0127] At operation 606, in some embodiments, a second PUF array is constructed in a second ILD above the first ILD. Constructing the second PUF array in the second ILD of the partially processed semiconductor wafer includes constructing a second plurality of inverters and a second plurality of pairs of RMDs, for example, configured as described above with respect to Figures 1 to 4D Inverters 208, 308A-308E or 408 and pairs of RMDs 209, 309A-309D or 409 operating as discussed.

[0128] In some embodiments, constructing the second PUF array in the second ILD includes the following steps: Figures 4A to 4D In some embodiments, constructing the second PUF array in the second ILD includes constructing one or more additional PUF arrays in one or more ILDs above the second ILD, such as those described above with respect to Figures 4A to 4D Discussion of ILDs IL3-IL5.

[0129] Constructing the second PUF array includes performing a second plurality of fabrication operations, such as one or more of lithography, diffusion, deposition, etching, planarization, or other operations suitable for constructing a second plurality of inverters and a second plurality of pairs of RMDs in the second ILD.

[0130] At operation 608, in some embodiments, one or more additive manufacturing operations are performed. In some embodiments, performing the one or more additive manufacturing operations includes performing one or more IC packaging operations, such as bonding, encapsulation, or implantation operations. In some embodiments, performing the one or more additive manufacturing operations includes performing one or more semiconductor wafer processing operations, such as deposition, etching, or planarization operations.

[0131] By performing some or all of the operations of method 600 , a semiconductor device including a PUF array located in a first ILD is fabricated, thereby achieving the benefits discussed above with respect to ICs 100 - 400 .

[0132] In some embodiments, a PUF device includes: a first inverter and a second inverter, each of the first inverter and the second inverter including a common gate node and a common drain node, wherein the common drain node of the first inverter is electrically connected to the common gate node of the second inverter; a common output node; a first RMD electrically connected to the common drain node and the common output node of the first inverter; and a second RMD electrically connected to the common drain node and the common output node of the second inverter. In some embodiments, each of the first and second RMDs includes a memristor, an RRAM device, a PCM device, an FTJ device, or an MTJ device. In some embodiments, each of the first and second RMDs includes a unipolar RMD. In some embodiments, each of the first and second RMDs includes a bipolar RMD. In some embodiments, the first inverter and the common output node are configured to receive the same programming voltage in a first programming operation and different programming voltages in a second programming operation. In some embodiments, the first inverter is configured to receive the programming voltage, and the common output node is configured to float during a random programming operation. In some embodiments, the first inverter is configured to receive an input voltage, and the common output node is configured to output a measurement voltage during a read operation.

[0133] In some embodiments, the semiconductor device includes: M inverters, M is a positive integer, the M inverters are electrically connected in series; and (M-1) pairs of RMDs, wherein the first inverter of the M inverters is electrically connected to a first node, the first node is electrically connected to the first RMD of the first pair of RMDs in the (M-1) pairs of RMDs and the second inverter of the M inverters, and each inverter after the first inverter of the M inverters is electrically connected in parallel with a pair of RMDs in the (M-1) pairs of RMDs. In some embodiments, the semiconductor device includes a write line configured to program one or more RMDs in the (M-1) pairs of RMDs, the write line being electrically connected to the input of the first inverter of the M inverters. In some embodiments, the semiconductor device includes a plurality of output nodes, wherein each output node electrically connects the RMDs of a corresponding pair of the (M-1) pairs of RMDs to each other. In some embodiments, the first RMD of the corresponding pair of RMDs is electrically connected to the first inverter output, the second inverter input, and the first output node of the plurality of output nodes. In some embodiments, a second RMD of a corresponding pair of RMDs is electrically connected to a second inverter output, a third inverter input, and a first output node of a plurality of output nodes. In some embodiments, a semiconductor device includes: a first level of a semiconductor device, the first level of the semiconductor device including M inverters and (M-1) pairs of RMDs, the M inverters being first M inverters of a plurality of M inverters, the (M-1) pair of RMDs being first (M-1) pairs of RMDs of a plurality of (M-1) pairs of RMDs; and a second level of the semiconductor device, located above the first level of the semiconductor device, the second level of the semiconductor device including: second M inverters of the plurality of M inverters, the second M inverters being electrically connected in series; a second (M-1) pair of RMDs of the plurality of (M-1) pairs of RMDs, the second (M-1) pair of RMDs being electrically connected in parallel with the second M inverters other than the first inverter of the second M inverters, wherein the input of the first inverter of the second M inverters is electrically connected to the output node of the corresponding pair of RMDs of the first (M-1) pairs of RMDs. In some embodiments, the M inverters are the first M inverters among a plurality of M inverters, the (M-1) pair of RMDs are the first (M-1) pair of RMDs among the plurality of (M-1) pairs of RMDs, and the semiconductor device includes: a second M inverter among the plurality of M inverters, the second M inverters being connected in parallel with the first M inverters; and a second (M-1) pair of RMDs among the plurality of (M-1) pairs of RMDs, the second (M-1) pair of RMDs being electrically connected in parallel with the second M inverters other than the first inverter of the second M inverters, wherein the input of the first inverter of the second M inverters is electrically connected to the output nodes of a pair of RMDs among the first (M-1) pairs of RMDs.

[0134] In some embodiments, a method of operating a semiconductor device includes: setting a first RMD of a pair of RMDs in a first programming operation, setting a second RMD of the pair of RMDs in a second programming operation, randomly resetting one of the first RMD or the second RMD in a third programming operation, and performing a read operation on the pair of RMDs. In some embodiments, setting the first RMD in the first programming operation includes applying a first voltage to a common node of the pair of RMDs arranged in parallel with an inverter in the series connection, and setting the second RMD in the second programming operation includes applying a second voltage to the inverters connected in series and applying the first voltage to the common node of the pair of RMDs. In some embodiments, randomly resetting the first RMD or the second RMD includes applying a third voltage to the inverters connected in series and floating the common node of the pair of RMDs. In some embodiments, performing a read operation on the pair of RMDs includes applying a fourth voltage to the inverters connected in series and measuring the voltage at the common node of the pair of RMDs. In some embodiments, the method includes outputting a random number based on the read operation. In some embodiments, the method includes outputting a random signal based on sequentially performing a read operation.

[0135] It will be readily apparent to one skilled in the art that one or more of the disclosed embodiments achieve one or more of the advantages described above. After reading the foregoing description, one skilled in the art will be able to effect various changes, substitutions of equivalents, and various other embodiments broadly disclosed herein. Accordingly, the protection granted herein is intended to be limited only by the definitions contained in the appended claims and their equivalents.

Claims

1. A physically unclonable function (PUF) device, comprising: A first inverter and a second inverter, each of the first inverter and the second inverter comprising: a common gate node; and a common drain node, wherein the common drain node of the first inverter is electrically connected to the common gate node of the second inverter, the first inverter and the second inverter are connected in series between the common gate node of the first inverter and the common drain node of the second inverter, and are configured to cause a voltage change at the common drain node of the second inverter through a voltage change at the common gate node of the first inverter and, in turn, through a voltage change at the common drain node of the first inverter; Public output node; a first resistive memory device RMD electrically connected to the common drain node and the common output node of the first inverter; and a second resistive memory device electrically connected to the common drain node and the common output node of the second inverter, The first inverter is configured to receive a programming voltage, and the common output node is configured to float in a random programming operation.

2. The physically unclonable functional device according to claim 1, wherein: Each of the first resistive memory device and the second resistive memory device includes a memristor, a resistive random access memory (RRAM) device, a phase change memory (PCM) device, a ferroelectric tunnel junction (FTJ) device, or a magnetic tunnel junction (MTJ) device.

3. The physically unclonable functional device according to claim 1, wherein: Each of the first resistive memory device and the second resistive memory device includes a unipolar resistive memory device.

4. The physically unclonable functional device according to claim 1, wherein: Each of the first resistive memory device and the second resistive memory device includes a bipolar resistive memory device.

5. The physically unclonable functional device according to claim 1, wherein: The first inverter and the common output node are configured to receive the same program voltage in a first program operation and to receive different program voltages in a second program operation.

6. The physically unclonable functional device according to claim 1 , wherein each of the first resistive memory device and the second resistive memory device is configured to be controllable to have a high resistance value and a low resistance value, wherein: A ratio of the high resistance value to the low resistance value is equal to or greater than 10.

7. The physically unclonable functional device according to claim 6, wherein: The first inverter is configured to receive an input voltage, and the common output node is configured to output a measurement voltage in a read operation.

8. A semiconductor device comprising: M inverters, where M is a positive integer, and the M inverters are electrically connected in series; as well as (M-1) for the resistive memory device RMD, in, Each of the M inverters includes: a common gate node serving as an input to the corresponding inverter; and a common drain node serving as an output of a corresponding inverter, wherein the common drain nodes of the first inverter to the (M-1)th inverter among the M inverters are electrically connected to the common gate nodes of the second inverter to the Mth inverter among the corresponding M inverters; A common drain node of the first inverter of the M inverters is electrically connected to a first resistive memory device of a first pair of the (M-1) pairs of resistive memory devices and an input of the second inverter of the M inverters, and an output of the second inverter of the M inverters is connected to a second resistive memory device of the first pair of resistive memory devices, and Each inverter subsequent to the first inverter of the M inverters is electrically connected in parallel to a pair of resistive memory devices of the (M−1) pairs of resistive memory devices.

9. The semiconductor device according to claim 8, further comprising: A write line is configured to program one or more resistive memory devices of the (M-1) pairs of resistive memory devices, the write line being electrically connected to an input of the first inverter of the M inverters.

10. The semiconductor device according to claim 8, further comprising: A plurality of output nodes, wherein each output node electrically connects the resistive memory devices of a corresponding pair of the (M-1) pairs of resistive memory devices to each other.

11. The semiconductor device according to claim 10, wherein The first resistive memory device of the first pair of the (M-1) pairs of resistive memory devices is also electrically connected to a first output node of the plurality of output nodes.

12. The semiconductor device according to claim 11, wherein The second resistive memory device of the first pair of the (M−1) pairs of resistive memory devices is also electrically connected to an input of a third inverter of the M inverters and the first output node of the plurality of output nodes.

13. The semiconductor device according to claim 8, further comprising: The first level of the semiconductor device includes the M inverters and the (M-1) pair of resistive memory devices, wherein the M inverters are first M inverters of a plurality of M inverters, and the (M-1) pair of resistive memory devices is a first (M-1) pair of resistive memory devices of a plurality of (M-1) pairs of resistive memory devices; as well as The second level of the semiconductor device is located above the first level of the semiconductor device, and the second level of the semiconductor device includes: second M inverters of the plurality of M inverters, the second M inverters being electrically connected in series; and a second (M-1) pair of resistive memory devices of the plurality (M-1) pairs of resistive memory devices, the second (M-1) pair of resistive memory devices being electrically connected in parallel to the second M inverters excluding a first inverter of the second M inverters, The inputs of the first inverters of the second M inverters are electrically connected to output nodes of corresponding pairs of resistive memory devices of the first (M−1) pairs of resistive memory devices.

14. The semiconductor device according to claim 8, wherein The M inverters are first M inverters of a plurality of M inverters, The (M-1) pair of resistive memory devices is a first (M-1) pair of resistive memory devices of a plurality of (M-1) pairs of resistive memory devices, and The semiconductor device further includes: second M inverters of the plurality of M inverters, the second M inverters being connected in parallel with the first M inverters; and a second (M-1) pair of resistive memory devices of the plurality of (M-1) pairs of resistive memory devices, the second (M-1) pair of resistive memory devices being electrically connected in parallel to the second M inverters excluding a first inverter of the second M inverters, The inputs of the first inverters of the second M inverters are electrically connected to output nodes of a pair of resistive memory devices of the first (M−1) pairs of resistive memory devices.

15. A method of operating a semiconductor device, the method comprising: setting a first resistive memory device of a pair of resistive memory devices RMD in a first programming operation; setting a second resistive memory device of the pair of resistive memory devices in a second programming operation; randomly resetting one of the first resistive memory device or the second resistive memory device in a third programming operation; as well as performing a read operation on the pair of resistive memory devices, in, Setting the first resistive memory device in the first programming operation includes applying a first voltage to a common node of a pair of resistive memory devices arranged in parallel with inverters connected in series and inverters of the series connected inverters, and Setting the second resistive memory device in the second programming operation includes applying a second voltage to the serially connected inverters and applying the first voltage to the common node of the pair of resistive memory devices.

16. The method according to claim 15, wherein Each of the first resistive memory device and the second resistive memory device includes a memristor, a resistive random access memory (RRAM) device, a phase change memory (PCM) device, a ferroelectric tunnel junction (FTJ) device, or a magnetic tunnel junction (MTJ) device.

17. The method according to claim 15, wherein: Randomly resetting the first resistive memory device or the second resistive memory device includes applying a third voltage to the serially connected inverters and floating the common node of the pair of resistive memory devices.

18. The method according to claim 17, wherein Performing the read operation on the pair of resistive memory devices includes applying a fourth voltage to the serially connected inverters and measuring a voltage at the common node of the pair of resistive memory devices. The method of claim 15 , further comprising outputting a random number based on the read operation.

20. The method of claim 15, further comprising outputting a random signal based on sequentially performing the read operations.

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