Data processing method, device and readable storage medium

Abstract

The present application provides a data processing method, device, and readable storage medium. The method includes: loading N groups of data into multiple first vector registers respectively; determining first boundary values of data elements in the multiple first vector registers in parallel; writing the first boundary values of the data elements in the multiple first vector registers sequentially into a second vector register; and executing the following loop process until a preset loop condition is satisfied: determining second boundary values of multiple first boundary values in the second vector register; writing the second boundary values into a storage unit; setting target data elements corresponding to the first boundary values of the data elements in the target first vector register to zero to update the target first vector register; determining third boundary values of the data elements in the updated target first vector register; updating the target first boundary values to the third boundary values to update the second vector register; the preset loop condition is writing M second boundary values into the storage unit, where M is a positive integer greater than 1.

Description

Technical Field

[0001] The present application relates to the field of processor technology, and more specifically, to a data processing method, device, and readable storage medium. Background Art

[0002] Currently, finding multiple boundary values in a dataset is primarily accomplished by traversing the data elements within the dataset multiple times. Specifically, a single data element in the dataset is used as the initial boundary value. For each traversed data element, the boundary value is compared with the initial boundary value to update the boundary value. After all data elements have been traversed, the updated boundary value becomes the global boundary value for the dataset. This process must be repeated to determine multiple boundaries.

[0003] This approach can only compare two pieces of data at a time, preventing parallel comparisons, resulting in slower processing speeds. Furthermore, each comparison requires reading the data from memory into the processor cache, comparing it to the current boundary, and updating the current boundary value based on the comparison results. When the data volume is large, the processor needs to frequently exchange data with memory, increasing its power consumption. Summary of the Invention

[0004] The present application provides a data processing method, device, and readable storage medium. The following introduces various aspects of the embodiments of the present application.

[0005] In a first aspect, a data processing method is provided, comprising: calling a load data instruction to load N groups of data in a data set into a plurality of first vector registers of a processor respectively; calling a determine maximum value instruction to determine first boundary values of data elements in the plurality of first vector registers in parallel; calling a set instruction to sequentially write the plurality of first boundary values into a second vector register of the processor; executing a loop process until a preset loop condition is satisfied, the loop process comprising: calling the determine maximum value instruction to determine a second boundary value of the plurality of first boundary values in the second vector register; calling the set instruction to write the second boundary value into the storage unit; calling the set instruction to sequentially write the plurality of first boundary values into the storage unit; A set instruction is provided to set the target data element corresponding to the first boundary value of the data element in the target first vector register to zero, so as to update the target first vector register; wherein the target first vector register is the first vector register to which the target first boundary value corresponding to the second boundary value belongs; the determine maximum value instruction is called to determine the third boundary value of the data element in the updated target first vector register; the set instruction is called to update the target first boundary value shown to the third boundary value, so as to update the second vector register; the preset loop condition is that M second boundary values are written in the storage unit, wherein M is an integer greater than 1.

[0006] In a second aspect, a device for processing data is provided, comprising: a loading unit for calling a load data instruction to load N groups of data in the data set into multiple first vector registers of a processor respectively; a first calculation unit for calling a determine maximum value instruction to determine the first boundary values of the data elements in the multiple first vector registers in parallel; a writing unit for calling a set instruction to write multiple first boundary values into the second vector register of the processor in sequence; a second calculation unit for executing a loop process until a preset loop condition is met, the loop process comprising: calling the determine maximum value instruction to determine the second boundary value of the multiple first boundary values in the second vector register; calling the set instruction to set the second The boundary value is written into the storage unit; the set instruction is called to set the target data element corresponding to the first boundary value of the data element in the target first vector register to zero, so as to update the target first vector register; wherein the target first vector register is the first vector register to which the target first boundary value corresponding to the second boundary value belongs; the determine maximum value instruction is called to determine the third boundary value of the data element in the updated target first vector register; the set instruction is called to update the shown target first boundary value to the third boundary value, so as to update the second vector register; the preset loop condition is that M second boundary values are written into the storage unit, wherein M is a positive integer greater than 1.

[0007] In a third aspect, a device for processing data is provided, comprising: a memory for storing instructions; and a processor for executing the instructions stored in the memory to perform the method as described in the first aspect.

[0008] In a fourth aspect, a readable storage medium is provided, on which instructions for executing the method described in the first aspect are stored.

[0009] According to a fifth aspect, a program product is provided, comprising instructions for executing the method according to the first aspect.

[0010] The method provided by this application, through vector instructions, can reduce the computational complexity and processing latency when determining multiple boundary values of a data set, thereby improving processing speed. Furthermore, according to the method provided by this application, data only needs to be loaded from memory into vector registers at the beginning of processing. All intermediate calculations are performed between vector processors, reducing the interaction between the processor and memory, thereby significantly reducing system power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a schematic flow chart of the data processing method provided in the embodiment of the present application.

[0012] Figure 2 This is a schematic diagram of the state of each vector register when the method provided in an embodiment of the present application is used to determine the largest first 4 values from 32 data.

[0013] Figure 3 It is a schematic structural diagram of a data processing device provided in one embodiment of the present application.

[0014] Figure 4 It is a schematic structural diagram of a data processing device provided in another embodiment of the present application. DETAILED DESCRIPTION

[0015] The following will provide a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0016] The method of the embodiment of the present application is used to find multiple boundary values in a data set, for example, to find multiple maximum values or minimum values in a data set.

[0017] Currently, finding the boundary value of a dataset is primarily accomplished by traversing the data within the dataset. This involves first determining an initial boundary value, then comparing each data element in the dataset against this boundary value. For each traversed data element, the value is compared to the initial boundary value to determine whether the boundary value needs to be updated. After all data elements in the dataset have been traversed, the updated boundary value becomes the boundary value of the dataset.

[0018] In addition, since the data in the array is traversed and compared sequentially, after obtaining the boundary value of the data set, the index corresponding to the boundary value can also be obtained. The index of the boundary value of the data set can be understood as the position of the boundary value of the data set in the data set, and the number of data elements in the data set that the boundary value of the data set is.

[0019] The method described above can determine a boundary value in the array by traversing all data elements in the array and comparing them one by one.

[0020] In some scenarios of this application, it is necessary to determine multiple boundary values for all elements in an array, for example, to determine the two largest values among multiple data points. In this case, after obtaining the first maximum value, it is necessary to set the first maximum value to null, update the elements in the array, and perform the above steps again on the updated array to determine the second maximum value and its index.

[0021] The above method is described in detail below with reference to a specific example, which is to find the first four largest values from a first array, where the first array includes 32 data as shown in Table 1 below.

[0022] Table 1

[0023] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

[0024] Step 1: Use the first value 0 in the array as the initial maximum value. Compare it to the other elements in the array one by one and update the maximum value. After traversing all elements in the array, determine that the first maximum value of the first array is 17. Save this value and update the first array, clearing the maximum value 17 to NULL. The process of determining the first maximum value requires 31 comparisons and 1 assignment. The updated first array is shown in Table 2 below.

[0025] Table 2

[0026] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Null

[0027] In step 2, using the first value 0 in the array as the initial maximum value, the same operation as in step 1 is performed to obtain the second maximum value, 16. This value is saved and the array is updated, that is, the value is set to null in the array shown in Table 2. In step 2, 31 comparisons and 1 assignment are required. The updated array in step 2 is shown in Table 3.

[0028] Table 3

[0029] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Null Null

[0030] Step 3, traverse the data shown in Table 3 again, determine the third maximum value 15, save the value, and update the first array. The updated first array is shown in Table 4. In this step, 31 comparisons and 1 assignment are performed.

[0031] Table 3

[0032] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Null 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Null Null

[0033] In step 4, the data in the array shown in Table 4 are compared in a loop, and the fourth maximum value is determined to be 15. This data is recorded. 31 comparisons and 1 assignment are performed in step 4. Thus, the four largest values in the first array are obtained: 17, 15, 15, and 15.

[0034] In the example above, to find the four largest values from 32 data, a total of 31*4=124 comparisons and 4 assignments are required.

[0035] As can be seen from the above process, determining the top M largest or smallest values from an array of N data requires (N-1)*M comparisons and M assignments. This means that the larger the total amount of data, the greater the number of boundary values that need to be determined, and the higher the algorithmic complexity of the process. Due to the limited power of the processor, these calculations can cause significant system latency. For example, determining the top 10 largest values from 1 million data points requires approximately 10 million comparisons.

[0036] Furthermore, currently widely used scalar processors must read the data to be compared from the memory unit into the processor's cache for each data comparison, compare it with the current maximum value, and update the current maximum value based on the comparison result. When the data group contains a large amount of data, the processor needs to frequently exchange data with the memory unit, which increases the processor's power consumption.

[0037] In view of the above problems, an embodiment of the present application proposes a data processing method.

[0038] In the method provided in the embodiment of the present application, data loading instructions such as VLD can be used to record the data in the data set into multiple first vector registers in the processor; then, using the determine maximum value instruction, the first boundary values of the data elements in the multiple first vector registers can be directly determined, and the first boundary values of the multiple first vector registers can be written into the second vector register. The determine maximum value instruction is executed in the second vector register to obtain the second boundary value of the second vector register, and the second boundary value is a global boundary value of all the data in the data set.

[0039] Based on the second boundary value corresponding to the global boundary value, the value in the first vector register to which it belongs is invalidated, and the data elements in the first vector register are updated. The boundary values of the data elements in the updated first vector register are re-determined, and the data elements in the second vector register are updated, and the second boundary value of the second vector register is re-determined. This second boundary value becomes the second global boundary value for all data in the data set. Repeating these steps multiple times can determine multiple boundary values of the data set.

[0040] The method of the embodiment of the present application can be applied to technical fields such as machine learning, artificial intelligence, and image processing. The method of the embodiment of the present application can be executed by a processor, which may include multiple first vector registers and second vector registers to respectively store grouped data and boundary value data of each group of data.

[0041] In the embodiment of the present application, the length of the first vector register is related to the parallel processing capability (also known as the degree of parallelism) of the processor. For example, if the parallel processing capability of the processor is X, then when the processor executes the determine maximum value instruction, it can find a maximum value from the X numbers.

[0042] In the embodiment of the present application, the second vector register is used to store the first boundary values of multiple first vector registers. Therefore, the length of the second vector register should be set to be greater than or equal to the number of the first vector registers.

[0043] The data processing method provided in the embodiment of the present application is described in detail below with reference to the accompanying drawings.

[0044] See also Figure 1 In step S110 , a load data instruction is called to load N groups of data in the data set into a plurality of first vector registers of the processor respectively.

[0045] In some embodiments, the load instruction may be a VLD instruction. When executed by a processor, multiple groups of data elements may be read from a data set and loaded into multiple vector registers. For example, when a processor executes a VLD(VR0-VR3, DATA) instruction, DATA data may be loaded from memory into four vector registers VR0-VR3.

[0046] The embodiments of the present application do not limit the data types in the data set. For example, the data types may include one or more of the following: floating point type and integer type. Floating point types may include single-precision floating point type (float) and double-precision floating point type (double). Integer types may include signed integer type, unsigned integer type, long integer type, short integer type, etc.

[0047] The number of data contained in each of the N groups of data in the data set can be the same or different, and this embodiment of the present application does not limit this. As a preferred embodiment, the number of data contained in the N groups can be set to be the same and the same as the length of multiple first vector registers in the processor, so that register resources can be maximized.

[0048] In some embodiments, the number of data groups in the data set is equal to or less than the number of first vector registers in the processor, so that all data in the data set can be added to the processor at the same time.

[0049] For example, Figure 2 FIG2 is a schematic diagram showing the state of each register when the method provided by this application is applied to determine the largest first four data from 32 data. The original data set in this example can be found in Table 1 above.

[0050] like Figure 2 As shown, the data in Table 1 are divided into 4 groups and written into four vector registers VR0, VR1, VR2 and VR3 respectively, where each register includes 8 data elements.

[0051] In step S120 , a determine maximum value instruction is called to determine first boundary values of data elements in a plurality of first vector registers in parallel.

[0052] In an embodiment of the present application, the maximum value determination instruction may be, for example, a VMAX or VMIN instruction, which is used to find a maximum or minimum value and its index from a first vector register. After determining a maximum value and index of the first vector register, the instruction is further used to write the maximum value and index to a scalar register. For example, when the processor executes the instruction VMAX(SR0,SR1,VR0), the maximum value of the data elements in vector register VR0 and the index of the maximum value can be stored in scalar registers SR0 and SR1, respectively.

[0053] Therefore, in some embodiments, the above step S120 further includes storing the first boundary value and the index of the first boundary value into multiple scalar registers.

[0054] Continue reading Figure 2 In this example, it can be determined that the maximum values of the eight data elements in the four vector registers VR0, VR1, VR2, and VR3 are 7, 15, 9, and 17, respectively, and the corresponding indexes are all 0.

[0055] Furthermore, the above four maximum values and their corresponding indexes are written into scalar registers SR0-SR7, wherein scalar registers SR0, SR2, SR4 and SR6 are respectively used to store the first boundary values of the above four vector registers, and SR1, SR3, SR5 and SR7 are used to store the indexes of the above four first boundary values.

[0056] In step S130, a set instruction is called to sequentially write the first boundary value into the second vector register of the processor.

[0057] In an embodiment of the present application, the set instruction may be, for example, a VSET instruction, which is used to place the value in a scalar register into a position in a specified vector register, where the position may be specified by another scalar register. For example, when the processor executes the instruction VSET(VR0,SR0,SR1), the value in the scalar register SR0 may be placed into the SR1th position of the vector register VR0.

[0058] By executing a set instruction in the scalar register storing the plurality of first boundary values, the plurality of first boundary values can be sequentially written into the second vector register.

[0059] It can be understood that, in order to be able to store the first boundary value in each first vector register, the length of the second vector register is configured to be greater than or equal to the number of the first vector registers.

[0060] Combine Figure 2 By running the VSET instruction on the scalar registers SR0, SR2, SR4 and SR6 storing the above four maximum values, the above four maximum values 7, 15, 9 and 17 are written into the 0th to 3rd bits of the second vector register VR4 in sequence.

[0061] In step S140, a determine maximum value instruction is called to determine a second boundary value of the plurality of first boundary values in the second vector register.

[0062] The method of determining the second boundary value of multiple first boundary values using the determine maximum value instruction is similar to step S120 in the previous text and will not be repeated here.

[0063] Combine Figure 2 For example, it is determined that the second boundary value (ie, the maximum value) among the four maximum values 7, 15, 9, and 17 in the second vector register VR4 is 17, and the corresponding index is 3.

[0064] In step S150, a set instruction is called to write the second boundary value into the storage unit.

[0065] It is understood that the second boundary value determined in step S140 is the first boundary value of the data set in the embodiment of the present application. Therefore, after the second boundary is determined, it can be output to the storage unit (or result vector register).

[0066] exist Figure 2 In the example, after determining that the second boundary value in the second vector register VR4 is 17 in the aforementioned step, the VSET instruction can be called to write the second boundary value into the storage unit VR5.

[0067] In step S160 , a set instruction is called to set the target data element corresponding to the first boundary value of the data element in the target first vector register to zero, so as to update the target first vector register.

[0068] The target first vector register is the first vector register to which the target first boundary value corresponding to the second boundary value belongs.

[0069] Continue reading Figure 2 In this example, the second boundary value is 17, and the vector register to which the target first boundary value corresponding to the threshold belongs is register VR3, that is, the target first vector register is VR3.

[0070] By calling the set instruction, the target data element 17 in the vector register VR3 is set to 0, thereby obtaining the updated vector register VR3 (ie, the target first vector register).

[0071] In step S170 , a determine maximum value instruction is called to determine a third boundary value of the data element in the updated target first vector register.

[0072] like Figure 2 As shown, the VMAX instruction is run on the vector register VR3 to determine that the current maximum value (the third boundary value) is 16, and the corresponding index is 2. The third boundary value is written into the scalar register SR6, and the index of the third boundary value is written into the scalar register SR5.

[0073] In step S180, a set instruction is called to update the target first boundary value to the third boundary value to update the second vector register.

[0074] The target first boundary value is the second boundary value determined in step S140 above, which is a global boundary value of the array. After determining the third boundary of the updated target first vector register, the second vector register needs to be updated, that is, the first boundary value is updated to the third boundary value, thereby obtaining an updated second vector register.

[0075] like Figure 2 As shown, the VSET instruction is run on the second vector register VR4 to update the third bit of the second vector register to the third boundary value 16 stored in the scalar register SR6, and the 0th to 3rd bits in the updated second vector register VR4 are 7, 15, 9 and 16 respectively.

[0076] After updating the second vector register, the method of the embodiment of the present application further includes repeatedly executing steps S140-180 until a preset amount of data is written into the storage unit, where the preset amount is the number of boundary values that need to be determined from the data set.

[0077] For example, in Figure 2 In the example of FIG, the second boundary value of the updated second vector memory VR4 is determined to be 16, and is written into the storage unit VR5.

[0078] According to the second boundary value 16 in the corresponding target first vector memory and the position of the second boundary value in the vector memory, the target first vector memory is updated to obtain an updated vector memory VR3, in which the data elements are 10, 11, 12, 13, 14, 15, 0, 0.

[0079] The first boundary value of the updated vector register VR3 is determined to be 15 again, and is written into the first bit of the second vector register VR4 to obtain the updated second vector register VR4.

[0080] The updated second boundary value of register VR4 is determined to be 15, and is written into storage unit VR5.

[0081] According to the second boundary value 15 and index of the updated second vector register VR4, the first vector register VR1 is updated, and the element 15 therein is set to 0, thereby obtaining the updated first vector register VR1, in which the data elements are 8, 9, 10, 11, 12, 13, 14, and 0.

[0082] The first boundary value of the updated first vector register VR1 is determined to be 14, which is written to bit 1 of the second vector register VR4. This results in an updated second vector register VR4 with data elements 7, 14, 9, and 15.

[0083] The updated second boundary value 15 of second vector register VR4 is determined and written to memory cell VR5. At this point, four data elements have been written to memory cell VR5, satisfying the pre-set condition of determining four boundary values from 32 data elements. The above loop ends at this point. Data elements 17, 16, 15, and 15 in memory cell VR5 are the first four largest values of the 32 data elements shown in Table 1.

[0084] The following is a summary of the processor instructions in the specific processing process. Figure 2 The method shown in is further described.

[0085] In step S210, the 32 numbers in the data set are written to vector registers VR0-VR3. The VMAXA instruction is called to determine the maximum value and index of each vector register and place them in scalar registers SR0-SR7. SR0, SR2, SR4, and SR6 store the maximum value, while SR1, SR3, SR5, and SR7 store the corresponding index. The VSET instruction is called to sequentially store the maximum values stored in scalar registers SR0, SR2, SR4, and SR6 into vector register VR4. The VMAX instruction is called in vector register VR4 to determine the maximum value, 17. The index corresponding to this maximum value is recorded and assigned to k, i.e., k = 3. The maximum value, 17, is then stored in result register VR5.

[0086] The corresponding processor pseudo-instructions are as follows:

[0087]

[0088]

[0089] In step S220, the index position of the SR7 record corresponding to the previous maximum value 17 in the vector register VR3 with index number k=3 is cleared, VR3 is updated, and the new maximum value 16 is found. 16 is placed in the kth (k=3) position of VR4. Then, the maximum value 16 is found in the updated VR4 and stored in the final result register VR5, whose corresponding index number is K=3. The index number k is updated, that is, k=3.

[0090] The corresponding processor pseudo-instructions are as follows:

[0091]

[0092] In step S230, the index position of the SR3 record corresponding to the previous maximum value 16 in VR3 with index number k=3 is cleared, VR3 is updated, and the new maximum value 15 is found. 15 is placed in the kth (k=3) position of VR4. Then, the maximum value 15 is found in the updated VR4 and stored in the final result register VR5, whose corresponding index number is k=2. The index number k is updated, that is, k=2.

[0093] The corresponding processor pseudo-instructions are as follows:

[0094]

[0095]

[0096] In step S240, the index position of the SR3 record corresponding to the previous maximum value 15 in VR1 with index number k=1 is cleared, VR3 is updated, the new maximum value 14 is found, and 14 is placed in the kth (k=1) position of VR4. Then, the maximum value 15 is found in the updated VR4 and stored in the final result register VR5, whose corresponding index number is k=3. The index number k is updated, that is, k=3.

[0097] The corresponding processor pseudo-instructions are as follows:

[0098]

[0099] Through the above steps, the first four maximum values of the 32 data in the data set are found and stored in the result register.

[0100] As can be seen from the above process, in the solution of the present application, finding the first four maximum values from 32 data requires a total of 29 instructions. Ignoring processing delays, it only takes 29 clock cycles to complete. In contrast, in the prior art, finding the first four maximum values from 32 data requires 31*4=124 comparisons and 4 assignments, requiring a total of 128 instructions, that is, 128 clock cycles. For another example, when determining the 32 maximum values from 1024 numbers, the computational complexity of the prior art one-by-one comparison solution is 32*1024=32768, while the complexity of the above solution of the present application is: to determine the first maximum value, it is necessary to run 32 VLD instructions, 32 VMAX instructions, and 64 VSET instructions, and the core loop is repeated 5*32 times, for a total of 288 times. Compared with the prior art solution, the computational complexity of the method of the present application is reduced by 32768 / 288=113 times.

[0101] In other words, the method provided by this application, through vector instructions, can reduce the computational complexity and processing latency when determining multiple boundary values of a data set, thereby improving processing speed. Furthermore, according to the method provided by this application, data only needs to be loaded from memory into vector registers at the beginning of processing; all intermediate operations are performed between vector processors, reducing the interaction between the processor and memory, thereby significantly reducing system power consumption.

[0102] Combined with the above Figure 1 and Figure 2 , describes the method embodiment of the present application in detail, and the following is combined with Figure 3 and Figure 4 , the device embodiment of the present application is described in detail. It should be understood that the description of the method embodiment corresponds to the description of the device embodiment, so for parts not described in detail, reference can be made to the previous method embodiment.

[0103] Figure 3 It is a structural diagram of a data processing device provided in an embodiment of the present application. Figure 3 The device 300 shown may include a loading unit 310, a first calculation unit 320, a writing unit 330, and a second calculation unit 340. These units are described in detail below.

[0104] A loading unit 310 is configured to call a load data instruction to load N groups of data in the data set into a plurality of first vector registers of the processor respectively;

[0105] A first calculation unit 320 is configured to call a determine maximum value instruction to determine first boundary values of the data elements in the plurality of first vector registers in parallel;

[0106] A writing unit 330 is configured to call a set instruction to sequentially write the first boundary values into a second vector register of the processor;

[0107] The second calculation unit 340 is configured to execute a loop process until a preset loop condition is satisfied. The loop process includes:

[0108] Calling the determination method to determine a second boundary value of the plurality of first boundary values in the second vector register;

[0109] Calling the set instruction to write the second boundary value into the storage unit;

[0110] Invoking the set instruction to set a target data element corresponding to a first boundary value of a data element in a target first vector register to zero, thereby updating the target first vector register; wherein the target first vector register is the first vector register to which the target first boundary value corresponding to the second boundary value belongs;

[0111] Calling the determination method to determine a third boundary value of the data element in the updated target first vector register;

[0112] Calling the set instruction to update the target first boundary value to the third boundary value to update the second vector register;

[0113] The preset loop condition is to write M second boundary values into the storage unit, where M is a positive integer greater than 1.

[0114] Optionally, the device further comprises:

[0115] a third determining unit, configured to determine a first index of each of the first boundary values and a second index of each of the second boundary values;

[0116] The second calculation unit is further configured to: determine, according to a second index of the second boundary value, that the target first vector register is the Ith first vector register among the plurality of first vector registers;

[0117] determining, according to a first index of a first boundary value of a data element in the target first vector register, that the target data element is a K-th data element in the I-th first vector register;

[0118] The Kth data element in the Ith first register is set to zero.

[0119] Optionally, the lengths of the plurality of first vector registers are all less than or equal to the parallelism of the processor, and the length of the second vector register is greater than or equal to the number of the plurality of first vector registers.

[0120] Optionally, the load data instruction is a VLD instruction.

[0121] Optionally, the maximum value determination instruction is a VMAX and / or VMIN instruction.

[0122] Optionally, the set instruction is a VLD instruction.

[0123] Figure 4 4 is a schematic diagram of another data processing device provided in an embodiment of the present application. The device 400 can be used to implement the method described in the above method embodiment. The device 400 can be a computer or any type of electronic device.

[0124] The apparatus 400 may include a storage unit 410 and a processor 420. The storage unit 410 may be configured to store instructions. The processor 420 may be configured to execute the method described in any of the above embodiments according to the instructions stored in the storage unit 410.

[0125] The processor 420 may be a general-purpose processor or a special-purpose processor. For example, the processor may be a central processing unit (CPU). Alternatively, the processor may be another general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0126] The present application also provides a computer-readable storage medium for storing a program. The computer-readable storage medium can be applied to a terminal device or network device provided in the present application, and the program enables a computer to execute the method performed by the terminal device or network device in each embodiment of the present application.

[0127] The present application also provides a computer program product. The computer program product includes a program. The computer program product can be applied to a terminal device or network device provided in the present application, and the program causes a computer to execute the method performed by the terminal device or network device in each embodiment of the present application.

[0128] The present application also provides a computer program that can be applied to a terminal device or network device provided in the present application, and enables a computer to execute the method performed by the terminal device or network device in each embodiment of the present application.

[0129] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present disclosure is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a digital video disc (DVD)), or a semiconductor medium (eg, a solid state disk (SSD)).

[0130] Those skilled in the art will appreciate that the units and algorithm steps of the various examples described in conjunction with the embodiments of the present disclosure can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0131] In the several embodiments provided in the present disclosure, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0132] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0133] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0134] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A data processing method, characterized in that: include: Calling a load data instruction to load N groups of data in the data set into a plurality of first vector registers of the processor respectively; Calling a determine maximum value instruction to determine first boundary values of the data elements in the plurality of first vector registers in parallel; Calling a set instruction to sequentially write the plurality of first boundary values into a second vector register of the processor; The cycle process is executed until a preset cycle condition is met, and the cycle process includes: Calling the determine maximum value instruction to determine a second boundary value of the plurality of first boundary values in the second vector register; Calling the set instruction to write the second boundary value into the storage unit; Invoking the set instruction to set a target data element corresponding to a first boundary value of a data element in a target first vector register to zero, thereby updating the target first vector register; wherein the target first vector register is the first vector register to which the target first boundary value corresponding to the second boundary value belongs; Calling the determine maximum value instruction to determine a third boundary value of the data element in the updated target first vector register; Calling the set instruction to update the target first boundary value to the third boundary value to update the second vector register; The preset loop condition is that M second boundary values are written into the storage unit, where M is an integer greater than 1.

2. The method according to claim 1, characterized in that The method further comprises: Determine a first index for each of the first boundary values and a second index for each of the second boundary values; The calling of the set instruction to set the data element corresponding to the first boundary value of the data element in the target first vector register to zero to update the target first vector register includes: determining, according to a second index of the second boundary value, that the target first vector register is an I-th first vector register among the plurality of first vector registers; determining, according to a first index of a first boundary value of a data element in the target first vector register, that the target data element is a K-th data element in the I-th first vector register; The Kth data element in the Ith first register is set to zero.

3. The method according to claim 1, characterized in that The lengths of the plurality of first vector registers are less than or equal to the parallelism of the processor, and the length of the second vector register is greater than or equal to the number of the plurality of first vector registers.

4. The method according to claim 1, wherein The load data instruction is a VLD instruction.

5. The method according to claim 1, wherein The maximum value determination instruction is a VMAX and / or VMIN instruction.

6. The method according to claim 1, characterized in that The setting instruction is a VLD instruction.

7. A device for processing data, characterized in that: The device comprises: A loading unit, configured to call a load data instruction to load N groups of data in the data set into a plurality of first vector registers of the processor respectively; a first calculation unit, configured to call a determine maximum value instruction to determine first boundary values of the data elements in the plurality of first vector registers in parallel; a writing unit, configured to call a set instruction to sequentially write the plurality of first boundary values into a second vector register of the processor; The second computing unit is configured to execute a loop process until a preset loop condition is satisfied, wherein the loop process includes: Calling the determination method to determine a second boundary value of the plurality of first boundary values in the second vector register; Calling the set instruction to write the second boundary value into the storage unit; Invoking the set instruction to set a target data element corresponding to a first boundary value of a data element in a target first vector register to zero, thereby updating the target first vector register; wherein the target first vector register is the first vector register to which the target first boundary value corresponding to the second boundary value belongs; Calling the determine maximum value instruction to determine a third boundary value of the data element in the updated target first vector register; Calling the set instruction to update the target first boundary value to the third boundary value, so as to update the second vector register; The preset loop condition is that M second boundary values are written into the storage unit, where M is an integer greater than 1.

8. The device according to claim 7, characterized in that The device further comprises: a third determining unit, configured to determine a first index of each of the first boundary values and a second index of each of the second boundary values; The second computing unit is further configured to: determining, according to a second index of the second boundary value, that the target first vector register is an I-th first vector register among the plurality of first vector registers; determining, according to a first index of a first boundary value of a data element in the target first vector register, that the target data element is a K-th data element in the I-th first vector register; The Kth data element in the Ith first register is set to zero.

9. The device according to claim 7, characterized in that The lengths of the plurality of first vector registers are all less than or equal to the parallelism of the processor, and the length of the second vector register is greater than or equal to the number of the plurality of first vector registers.

10. The device according to claim 7, characterized in that The load data instruction is a VLD instruction.

11. The device according to claim 7, characterized in that The maximum value determination instruction is a VMAX and / or VMIN instruction.

12. The device according to claim 7, characterized in that The setting instruction is a VLD instruction.

13. A device for processing data, characterized in that: include: a memory for storing instructions; A processor, configured to execute instructions stored in the memory to perform the method according to any one of claims 1 to 6.

14. A readable storage medium, characterized in that Instructions for executing the method according to any one of claims 1 to 6 are stored thereon.

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