A processor-safe lockstep method based on low-bit computation

Abstract

A processor-safe lockstep method based on low-bit-precision computing includes: in the convolutional neural network computation of an artificial intelligence processor, inputting feature maps and weight data, and performing parallel computation using a low-bit-precision computing unit array and a high-bit-precision computing unit array to obtain low-bit-precision computation results and high-bit-precision computation results respectively, wherein the number of bits in the low-bit-precision computing unit array is lower than the number of bits in the high-bit-precision computing unit array; verifying the high-bit-precision computation result based on the low-bit-precision computation result and outputting it. This application employs parallel low-bit-precision and high-bit-precision computation, compares the error of the low-bit-precision computation result with the error of the high-bit-precision computation result, and if the error is controlled within a certain range, the high-bit-precision computation result is considered correct. This verification of the computation result constitutes a safe lockstep mechanism, thereby reducing the area overhead and energy consumption of the artificial intelligence processor core.

Description

Technical Field

[0001] This application relates to the field of artificial intelligence data processing technology, and in particular to a processor-safe lockstep method based on low-bit computation. Background Technology

[0002] With the development of intelligent, connected, and electrified vehicles, automobiles are placing higher demands on automotive-grade chips for computing power, as well as on data accuracy and reliability. Currently, AI (artificial intelligence) processors in automotive-grade computing chips require large amounts of data and significant computing power when performing related calculations. Traditional security AI processors employ a dual-core synchronous computing mechanism, where two identical high-performance computing cores perform the same calculations, and the results are compared. Because these high-performance AI computing cores occupy a large area, the area utilization rate of such security AI processors is relatively low.

[0003] Currently, when performing CNN (Convolutional Neural Network) calculations, most AI processors use a cross-verification mechanism between a dual-core CPU and the AI ​​processor. However, this design comes at the cost of additional core area and power consumption. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this application aims to provide a processor-safe lockstep method based on low-bit computation. When an artificial intelligence processor performs convolutional neural network computation, it employs parallel computation of low-bit computation unit arrays and high-bit precision computation unit arrays, and verifies the high-bit precision computation results based on the low-bit computation results to form a secure lockstep mechanism.

[0005] To achieve the above objectives, this application provides a processor security lockstep method based on low-bit computation, comprising:

[0006] In the convolutional neural network computation of an artificial intelligence processor, the input feature map and weight data are used to perform parallel computation using a low-bit precision computation unit array and a high-bit precision computation unit array, respectively obtaining low-bit precision computation results and high-bit precision computation results. The number of bits in the low-bit precision computation unit array is lower than the number of bits in the high-bit precision computation unit array.

[0007] The high-bit-precision calculation result is verified and output based on the low-bit-precision calculation result.

[0008] Furthermore, the step of verifying and outputting the high-bit-precision calculation result based on the low-bit-precision calculation result further includes: comparing the error of the high-bit-precision convolution calculation result with the low-bit-precision convolution calculation result and outputting the error.

[0009] Furthermore, the step of verifying and outputting the high-bit-precision calculation result based on the low-bit-precision calculation result further includes: comparing the error of the high-bit-precision activation calculation result with the low-bit-precision activation calculation result and outputting the error.

[0010] Furthermore, the step of verifying and outputting the high-bit-precision calculation result based on the low-bit-precision calculation result further includes: comparing the error of the high-bit-precision pooling result with the low-bit-precision pooling result and outputting the error.

[0011] To achieve the above objectives, this application also provides a processor security lockstep system based on low-bit computation, comprising:

[0012] The feature map input module and the weight input module provide feature map and weight data, respectively.

[0013] The high-bit precision calculation module takes the feature map and the weight data as input, calculates the high-bit precision convolution calculation result, the high-bit precision activation calculation result, and the high-bit precision pooling result, and outputs them to the calculation result verification module respectively.

[0014] The low-bit precision calculation module takes the feature map and the weight data as input, and performs parallel calculations with the high-bit precision calculation module to obtain low-bit precision convolution calculation results, low-bit precision activation calculation results, and low-bit precision pooling results, and outputs them to the calculation result verification module.

[0015] The calculation result verification module compares the errors of the high-bit-precision convolution calculation result, high-bit-precision activation calculation result, and high-bit-precision pooling result based on the low-bit-precision convolution calculation result, the low-bit-precision activation calculation result, and the low-bit-precision pooling result, respectively.

[0016] Furthermore, the number of bits in the high-bit-precision calculation block is higher than the number of bits in the low-bit-precision calculation module.

[0017] Furthermore, the high-bit-precision calculation module includes:

[0018] A high-bit precision computing unit array is input with the feature map and the weight data respectively, calculates the convolution, obtains the high-bit precision convolution calculation result, and outputs it to the first normalization and activation module and the calculation result verification module respectively.

[0019] The first normalization and activation module normalizes and calculates activation functions on the high-bit-precision convolution calculation result to obtain the high-bit-precision activation calculation result, and outputs it to the first pooling module and the calculation result verification module respectively.

[0020] The first pooling module performs a pooling operation on the high-bit-precision activation calculation result to obtain a high-bit-precision pooling result, and outputs it to the calculation result verification module.

[0021] Furthermore, the low-bit computing module includes:

[0022] The low-bit precision computing unit array is input with the feature map and the weight data respectively, calculates the convolution, obtains the low-bit precision convolution calculation results respectively, and outputs them to the second normalization and activation module and the calculation result verification module respectively.

[0023] The second normalization and activation module performs normalization and activation function calculation on the low-bit precision convolution calculation result to obtain the low-bit precision activation calculation result, and outputs it to the second pooling module and the calculation result verification module respectively.

[0024] The second pooling module performs a pooling operation on the low-bit precision activation calculation result to obtain a low-bit precision pooling result, and outputs it to the calculation result verification module.

[0025] To achieve the above objectives, this application also provides a processor security lockstep chip, including the processor security lockstep system based on low-bit computing as described above.

[0026] To achieve the above objectives, this application also provides an electronic device, including a processor, a memory, and a computer program stored in the memory and executable on the processor. The processor is configured to execute the computer program stored in the memory to implement the processor-secure lockstep method based on low-bit computation as described above.

[0027] To achieve the above objectives, this application also provides a computer-readable storage medium storing at least one instruction that is loaded and executed by a processor to implement the processor-safe lockstep method based on low-bit computation as described above.

[0028] The processor secure lockstep method based on low-bit computation provided in this application uses a low-bit precision computing unit array with a lower bit count than the high-bit precision computing unit array to perform parallel computation when the artificial intelligence processor performs convolutional neural network computation. The error of the low-bit precision computation result is compared with the error of the high-bit precision computation result. The error comparison is used to determine whether the high-bit precision computation data is correct, thereby verifying the computation result and forming a secure lockstep mechanism, thereby reducing the area and power consumption of the processor core.

[0029] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing this application. Attached Figure Description

[0030] The accompanying drawings are provided to further illustrate the present application and form part of the specification. Together with the embodiments of the present application, they serve to explain the present application but do not constitute a limitation thereof. In the drawings:

[0031] Figure 1 The flowchart below illustrates the processor security lockstep method based on low-bit computation according to this application.

[0032] Figure 2 This is a schematic diagram of a processor-secure lockstep system architecture based on low-bit computation according to this application;

[0033] Figure 3 This is a schematic diagram of an electronic device structure according to an embodiment of this application. Detailed Implementation

[0034] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.

[0035] It should be understood that the implementation of the method of this application may include additional steps and / or omit the steps shown. The scope of this application is not limited in this respect.

[0036] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0037] In the accompanying drawings, certain structural or methodological features are shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be necessary. In some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features may be omitted or may be combined with other features.

[0038] It should be understood that although the terms "first," "second," etc., may be used in this application to describe various modules / units or data, these modules / units or data should not be limited by these terms. The use of these terms is merely for distinguishing different modules / units or data, and is not intended to limit the order of functions performed by these modules / units or data, or their interdependencies. For example, without departing from the scope of the exemplary embodiments, a first feature may be referred to as a second feature, and similarly, a second feature may be referred to as a first feature.

[0039] It should be noted that the terms "one" and "multiple" used in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless explicitly stated otherwise in the context, they should be understood as "one or more". "Multiple" should be understood as two or more.

[0040] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0041] When a typical AI (Artificial Intelligence) processor performs CNN (Convolutional Neural Network) calculations, including PE array convolution, activation function calculations, and pooling operations, its technical precision is achieved using int or floating-point types. It has high security and reliability requirements and needs to be designed with secure lockstep mechanisms such as numerical verification.

[0042] Lockstepping is an error detection mechanism. Taking a dual-core lockstep mechanism as an example, it involves running the same application simultaneously on two identical processors. A checker module compares the execution output of the application on the two CPUs. If the outputs match, the checker module generates an interrupt, saving the current states of both CPUs to memory as checkpoint files. If the outputs do not match, the checker module generates an interrupt, and both CPUs retrieve the most recently saved checkpoint file to roll back and restore the system. Therefore, after a soft error occurs, the dual-core lockstep mechanism can be used for error correction, restoring the system to a safe state.

[0043] In convolutional neural networks (CNNs), convolution operations are used for feature extraction. A convolutional layer extracts a filtered version of an input image, representing a feature of the input image. A convolutional layer consists of multiple convolutional kernels, each acting as a different feature extractor. In each convolutional layer, data exists in a three-dimensional form, which can be viewed as many two-dimensional images stacked together, each called a feature map. Information is passed between different convolutional layers, and the kernels are activated to transmit information only when the activation function reaches a certain value. Furthermore, information with higher weights is more likely to activate the kernel, while information with lower weights is less likely to activate it. Generally, in a CNN, all pixels within the same channel of a feature map share a set of kernel weights; this property is called weight sharing.

[0044] Pooling layers, also known as subsampling layers, in convolutional neural networks perform feature selection, reducing the number of features and thus the number of parameters, preventing overfitting. Furthermore, pooling layers do not involve weights.

[0045] In convolutional neural network computation, weight data can be stored with different precisions. The more bits in a storage unit, the higher the precision of the stored data; conversely, the fewer bits in a storage unit, the lower the precision. Data representations with a higher bit count than low bit counts are called high bit counts. For example, `int8` or `int16` is relative to `int4` or `int2`, where `int4` or `int2` represents low bit count precision, and `int8` or `int16` represents high bit count precision. Similarly, `float point16` is relative to `float point8`. However, while high-precision weight data is beneficial for obtaining more accurate computational results, it consumes more area and storage resources. Low-precision weight data is beneficial for reducing computational and storage resources, but the accuracy of the neural network's computational results is lower.

[0046] In this embodiment, a processor-safe lockstep method based on low-bit computation is provided. During the computation of a convolutional neural network in an artificial intelligence processor, the input feature map and weight data are computed in parallel with a low-bit precision computation unit (PE) array, which has a lower number of bits than the high-bit precision computation unit (PE) array. Low-bit precision computation results and high-bit precision computation results are obtained respectively. Then, the high-bit precision computation results are verified based on the low-bit precision computation results and output. That is, the error of the high-bit precision computation results is compared with the low-bit precision computation results. If the error of the computation results is within a preset error range, the high-bit precision computation results are considered to be correct. This verification of computation results forms a safe lockstep mechanism.

[0047] Example 1

[0048] Figure 1 To illustrate the processor security lockstep method flowchart based on low-bit computation of this application, the following will refer to... Figure 1 This paper provides a detailed description of the processor-safe lockstep method based on low-bit computation proposed in this application.

[0049] In step 101, during the convolutional neural network computation of the artificial intelligence processor, feature maps and weight data are input, and low-bit precision computation unit arrays and high-bit precision computation unit arrays are used for parallel computation to obtain low-bit precision computation results and high-bit precision computation results, respectively. The number of bits in the low-bit precision computation unit array is lower than the number of bits in the high-bit precision computation unit array.

[0050] A bit (or binary digit) is a unit of measurement for information, referring to a single digit in a binary number. It is the smallest unit of data representation. Data represented using four bits per group has four bits. The higher the number of bits, the more precise the data representation. For example, `int8` or `int16` are relative to `int4` or `int2`; `int4` or `int2` represents low bit precision, while `int8` or `int16` represents high bit precision. Similarly, `float point16` represents high bit precision compared to `float point8`.

[0051] In this embodiment, the computational unit array is composed of multiple identical, simple computational units (Processing Elements, PEs) connected in a grid-like manner. It exhibits parallelism, regularity, and local communication characteristics, and is used to implement convolution computation. Each computational unit is a multiplier and accumulator (MAC).

[0052] A high-bit-precision computing unit array has a higher number of bits than the low-bit-precision computing unit array. For example, when the high-bit-precision computing unit array uses high-bit quantization such as int8, int16, or floatpoint16 for calculation, the low-bit-precision computing unit array can use low-bit quantization such as int2 or int4 for parallel calculation.

[0053] In this embodiment, when the AI ​​processor performs CNN calculations, it employs parallel computation using low-bit-precision PE arrays and high-bit-precision PE arrays. Convolution calculations are first performed on the weight and feature map (fmap) data, followed by activation function calculations on both the low-bit and high-bit-precision convolution results. Pooling operations are then performed on both activation calculation results. Compared to the dual-core synchronous computation mechanism used in traditional secure AI processors, this reduces the use of high-performance AI computing cores and decreases the area occupied by these cores, thereby improving the computational efficiency of the secure AI processor.

[0054] In step 102, the high-bit-precision calculation result is verified based on the low-bit-precision calculation result and then output.

[0055] In this embodiment, after performing convolution, activation function calculation, and pooling operations on the feature map and weight data in parallel with low-bit precision calculation and high-bit precision calculation, the error of the high-bit precision calculation result is compared based on the low-bit precision calculation result, including: comparing the error of the high-bit precision convolution calculation result based on the low-bit convolution calculation result, comparing the error of the high-bit precision activation calculation result based on the low-bit activation calculation result, and comparing the error of the high-bit precision pooling result based on the low-bit pooling result.

[0056] Within a certain range of the calculation results, the error between the low-bit precision calculation result and the high-bit precision calculation result is compared. For example, if the error of the calculation result is controlled within 20% (including 20%), the high-bit precision calculation data is considered to be correct. The calculation result is then verified, forming a secure lockstep mechanism.

[0057] In this embodiment of the application, the comparison error includes numerical statistical characteristic error, such as mean, variance, distribution, etc.

[0058] In this embodiment, during low-bit-precision calculations, the weights can be retrained and do not share weight and feature map data with high-bit-precision calculations. In some implementations, the weights are not retrained during low-bit-precision calculations; in this case, the high-bit data needs to be truncated to low-bit data, and the calculation results are compared between the low-bit-precision and high-bit-precision calculation results at each step of the algorithm to implement a lockstep verification mechanism. If the weights are trained, the low-bit calculation data of each layer of the convolutional neural network will differ from the high-bit calculation data. In this case, only the final calculation result needs to be compared, but the error at this point needs to consider the differences brought about by training at different precision levels.

[0059] The processor-safe lockstep method based on low-bit computation provided in this application employs parallel computation using low-bit precision computation unit arrays and high-bit precision computation unit arrays, and verifies the high-bit precision computation results based on the low-bit precision computation results. If the verification results conform to the safe range, a safe lockstep mechanism is formed. Compared with the mutual verification mechanism using the same dual-core CPU / AI processor, this method can reduce the processor core area overhead and also reduce power consumption.

[0060] Example 2

[0061] Figure 2 The schematic diagram of the processor-secure lockstep system architecture based on low-bit computation according to this application will be referenced below. Figure 2 This paper provides a detailed description of the secure lockstep system based on low-bit computation in this application.

[0062] refer to Figure 2 The processor-safe lockstep system based on low-bit computing of this application includes:

[0063] The feature map input module 201 and the weight input module 202 are used to provide feature map and weight data, respectively.

[0064] High-bit precision computation module: High-bit precision computation unit (Processing Element, PE) array 203, normalization and activation computation (BN&Activation) module 205, and pooling module 207, among which,

[0065] The high-bit precision PE array 203 takes the input feature map and weight data, performs convolution calculation using high-bit quantization such as int16 or floatpoint16, and obtains the high-bit precision convolution calculation result, which is then output to the normalization and activation calculation module 205 and the calculation verification module 209 respectively.

[0066] The normalization and activation calculation module 205 normalizes and calculates the activation function on the high bit precision convolution calculation result to obtain the high bit precision activation calculation result, and outputs it to the pooling module 207 and the calculation verification module 209 respectively.

[0067] Pooling module 207 performs a pooling operation on the high-bit precision activation result to obtain a high-bit precision pooling result, and outputs it to calculation and verification module 209.

[0068] Low-bit computation module: low-bit precision computation unit array 204, normalization and activation computation module 206, and pooling module 208, wherein,

[0069] The low-bit precision computation unit array 204 takes the feature map and weight data as input, performs convolution calculation using low-bit quantization such as int4 or int8, obtains the low-bit precision convolution calculation result, and outputs it to the normalization and activation calculation module 206 and the calculation verification module 209 respectively.

[0070] The normalization and activation calculation module 206 normalizes and calculates activation functions on the low-bit precision convolution result to obtain the low-bit precision activation calculation result, and outputs it to the pooling module 208 and the calculation and verification module 209 respectively.

[0071] Pooling module 208 performs a pooling operation on the low-bit precision activation calculation result to obtain a low-bit precision pooling result, and outputs it to calculation and verification module 209.

[0072] The calculation result verification module 209 takes into account the low-bit precision convolution calculation result, low-bit precision activation calculation result, low-bit precision pooling result, high-bit precision convolution calculation result, high-bit precision activation calculation result, and high-bit precision pooling result, and compares the error between the low-bit precision calculation result and the high-bit precision calculation result.

[0073] In this embodiment, the low-bit-precision PE array 204 and the high-bit-precision PE array 203 are computed in parallel. During the low-bit-precision computation, the weights can be retrained and do not share weight and feature map data with the high-bit-precision computation. In this case, only the final computation result needs to be compared.

[0074] In the embodiments of this application, the low-bit precision PE array can be calculated using one of the low-bit quantization methods such as int4 and int2, while the high-bit precision PE array can be calculated using high-bit quantization methods such as int16, int8, and floatpoint16. The characteristics of the low-bit precision PE array are: simple logic of the computational unit (PE), small physical area, and inaccurate calculation.

[0075] In this embodiment of the application, the calculation result verification module verifies the calculation result of each step of the high-bit-precision calculation module based on the calculation result of each step of the low-bit-precision calculation module, that is, compares the error of the high-bit-precision calculation result, thereby verifying the settlement result.

[0076] The processor-safe lockstep system based on low-bit-precision computing provided in this application performs parallel computations by a low-bit-precision computation module and a high-bit-precision computation module. These modules perform PE array convolution, normalization, activation function calculations, and pooling operations on feature maps and weight data, respectively. A computation verification module compares the computational results of each step in the two modules to determine the accuracy of the high-bit-precision computation result. This process verifies the computational result and constitutes a secure lockstep mechanism. Because the low-bit AI computing core requires a smaller silicon area and consumes less power, it significantly reduces the area overhead of the secure AI processor core and lowers energy consumption.

[0077] Example 3

[0078] In embodiments of this application, an electronic device is also provided. Figure 3 This is a schematic diagram of the electronic device structure according to an embodiment of this application, such as... Figure 3 As shown, the electronic device of this application includes a processor 301 and a memory 302, wherein,

[0079] The memory 302 stores a computer program, which, when read and executed by the processor 301, performs the steps described above in the embodiment of the processor-safe lockstep method based on low-bit computation.

[0080] Example 4

[0081] In embodiments of this application, a computer-readable storage medium is also provided, which stores a computer program configured to execute the steps described above in the embodiments of the processor security lockstep method based on low-bit computation.

[0082] In this embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0083] This application employs a high-bit precision / high-bit AI computing core and a low-bit AI computing core for computation, and then verifies the results through numerical comparison and statistical characteristics to achieve secure lockstepping, thereby reducing the use of high-performance computing cores and minimizing processor core area and power consumption.

[0084] It will be understood by those skilled in the art that the above descriptions are merely preferred embodiments of this application and are not intended to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A processor-safe lockstep method based on low-bit computation, comprising: In the convolutional neural network computation of an artificial intelligence processor, the input feature map and weight data are used to perform parallel computation using a low-bit precision computation unit array and a high-bit precision computation unit array, respectively obtaining low-bit precision computation results and high-bit precision computation results. The number of bits in the low-bit precision computation unit array is lower than the number of bits in the high-bit precision computation unit array. Verifying and outputting the high-bit-precision calculation result based on the low-bit-precision calculation result includes: comparing the error between the low-bit-precision calculation result and the high-bit-precision calculation result, wherein the error includes numerical statistical characteristic error.

2. The processor-safe lockstep method based on low-bit computation according to claim 1, characterized in that, The step of verifying and outputting the high-bit-precision calculation result based on the low-bit-precision calculation result further includes: comparing the error of the high-bit-precision convolution calculation result with the low-bit-precision convolution calculation result and outputting the error.

3. The processor-secure lockstep method based on low-bit computation according to claim 1, characterized in that, The step of verifying and outputting the high-bit-precision calculation result based on the low-bit-precision calculation result further includes: comparing the error of the high-bit-precision activation calculation result with the low-bit-precision activation calculation result and outputting the error.

4. The processor-safe lockstep method based on low-bit computation according to claim 1, characterized in that, The step of verifying and outputting the high-bit-precision calculation result based on the low-bit-precision calculation result further includes: comparing the error of the high-bit-precision pooling result with the low-bit-precision pooling result and outputting the error.

5. A processor-safe lockstep system based on low-bit computation, comprising: The feature map input module and the weight input module provide feature map and weight data, respectively. The high-bit precision calculation module takes the feature map and the weight data as input, calculates the high-bit precision convolution calculation result, the high-bit precision activation calculation result, and the high-bit precision pooling result, and outputs them to the calculation result verification module respectively. The low-bit precision calculation module takes the feature map and the weight data as input, and performs parallel calculations with the high-bit precision calculation module to obtain low-bit precision convolution calculation results, low-bit precision activation calculation results, and low-bit precision pooling results, and outputs them to the calculation result verification module. The calculation result verification module compares the errors of the high-bit-precision convolution calculation result, high-bit-precision activation calculation result, and high-bit-precision pooling result based on the low-bit-precision convolution calculation result, the low-bit-precision activation calculation result, and the low-bit-precision pooling result, respectively. The errors include numerical statistical characteristic errors.

6. The processor-secure lockstep system based on low-bit computation according to claim 5, characterized in that, The number of bits in the high-bit-precision calculation module is higher than the number of bits in the low-bit-precision calculation module.

7. The processor-secure lockstep system based on low-bit computation according to claim 6, characterized in that, The high-bit-precision calculation module includes: A high-bit precision computing unit array is input with the feature map and the weight data respectively, calculates the convolution, obtains the high-bit precision convolution calculation result, and outputs it to the first normalization and activation module and the calculation result verification module respectively. The first normalization and activation module normalizes and calculates activation functions on the high-bit-precision convolution calculation result to obtain the high-bit-precision activation calculation result, and outputs it to the first pooling module and the calculation result verification module respectively. The first pooling module performs a pooling operation on the high-bit-precision activation calculation result to obtain a high-bit-precision pooling result, and outputs it to the calculation result verification module.

8. The processor-secure lockstep system based on low-bit computing according to claim 6, characterized in that, The low-bit precision calculation module includes: The low-bit precision computing unit array is input with the feature map and the weight data respectively, calculates the convolution, obtains the low-bit precision convolution calculation results respectively, and outputs them to the second normalization and activation module and the calculation result verification module respectively. The second normalization and activation module performs normalization and activation function calculation on the low-bit precision convolution calculation result to obtain the low-bit precision activation calculation result, and outputs it to the second pooling module and the calculation result verification module respectively. The second pooling module performs a pooling operation on the low-bit precision activation calculation result to obtain a low-bit precision pooling result, and outputs it to the calculation result verification module.

9. A processor security lockstep chip, comprising the processor security lockstep system based on low-bit computing as described in any one of claims 5-8.

10. An electronic device comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, the processor being configured to execute the computer program stored in the memory to implement the processor-secure lockstep method based on low-bit computation as described in any one of claims 1-4.

11. This application also provides a computer-readable storage medium storing at least one instruction that is loaded and executed by a processor to implement the processor-safe lockstep method based on low-bit computation as described in any one of claims 1-4.

Images