Pixel circuit, display panel, and display device

Abstract

The present application provides a pixel circuit, a display panel, and a display device, wherein the pixel circuit includes: a driving module, a second light-emitting control module, and a light-emitting element. The second light-emitting control module is configured to apply a driving current from a first terminal to the light-emitting element through a second terminal under the control of a second light-emitting control signal received at a control terminal, and to delay the on-time of the second light-emitting control module during a data hold period in a hold frame phase. The pixel circuit provided in the present application delays the on-time of the second light-emitting control module to prevent the second light-emitting control module from prematurely applying the driving current to the light-emitting element, thereby reducing the difference in current applied to the light-emitting element between the refresh frame phase and the hold frame phase, thereby reducing the difference in screen brightness between the refresh frame phase and the hold frame phase, and improving optical defects of the circuit.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel circuit, a display panel, and a display device. Background Art

[0002] With the rapid development of OLED (Organic Light Emitting Diode) technology, low-power circuits such as LTPO (Low Temperature Polycrystalline Oxide) have gradually begun to highlight and amplify the advantages of OLED.

[0003] In the prior art, during non-refresh periods, also known as hold frames, some OLED driver units are put into hibernation to reduce the overall power consumption of the panel. However, due to internal compensation within the pixel circuit (e.g., a 7T1C circuit) and limitations of current driver integrated circuits, the potentials of various points within the pixel circuit differ between the refresh and hold frames, ultimately manifesting as differences in screen brightness. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a pixel circuit, a display panel, and a display device to solve or partially solve the above problems.

[0005] Based on the above purpose, the present application provides a pixel circuit, comprising: a driving module, a data writing module, a compensation storage module, a first reset module, a second reset module, a first light-emitting control module, a second light-emitting control module and a light-emitting element, wherein: the driving module is configured to control a driving current flowing through the light-emitting element for driving the light-emitting element to emit light; the data writing module is connected to the driving module and is configured to write a data signal to the driving module under the control of a write control signal; the compensation storage module is connected to the driving module and is configured to store the data signal written by the data writing module and compensate the driving module under the control of a compensation control signal; the first reset module is connected to the driving module and is configured to write a data signal to the driving module under the control of a first reset signal A first reset voltage is provided; the second reset module is connected to the light-emitting element and is configured to provide a second reset voltage to the light-emitting element under the control of a second reset signal; the first light-emitting control module is connected to the driving module and is configured to apply a first power supply voltage to the driving module under the control of the first light-emitting control signal; the second light-emitting control module includes a first terminal, a second terminal and a control terminal, the first terminal is connected to the driving module, and the second terminal is connected to the light-emitting element, the second light-emitting control module is configured to apply the driving current from the first terminal to the light-emitting element through the second terminal under the control of the second light-emitting control signal received by the control terminal, and delay the turn-on time of the second light-emitting control module during the data holding period of the holding frame stage.

[0006] Optionally, the second light-emitting control module includes a sixth transistor, a first electrode of the sixth transistor is connected to the driving module, a second electrode of the sixth transistor is connected to the light-emitting element, a control electrode of the sixth transistor is configured to receive the second light-emitting control signal, and the sixth transistor is an N-type transistor.

[0007] Optionally, the first light emitting control module includes a fifth transistor, and the fifth transistor is an N-type transistor.

[0008] Optionally, the driving module includes a driving transistor, the gate of the driving transistor is connected to the compensation storage module, the first electrode of the driving transistor is connected to the first light-emitting control module, and the second electrode of the driving transistor is connected to the compensation storage module and the second light-emitting control module.

[0009] Optionally, the data writing module includes a fourth transistor, a gate of the fourth transistor is used to receive the writing control signal, a first electrode of the fourth transistor is used to receive the data signal, and a second electrode of the fourth transistor is connected to the driving module.

[0010] Optionally, the compensation storage module includes a second transistor and a storage capacitor, the gate of the second transistor is used to receive the compensation control signal, the first electrode of the second transistor, the second electrode of the second transistor and the first electrode of the storage capacitor are all connected to the driving module, and the second electrode of the storage capacitor is used to receive the first power supply voltage.

[0011] Optionally, the first reset module includes a first transistor, a gate of the first transistor is used to receive the first reset signal, a first electrode of the first transistor is connected to the driving module, and a second electrode of the first transistor is used to receive the first reset voltage.

[0012] Optionally, the second reset module includes a seventh transistor, a gate of the seventh transistor is used to receive the second reset signal, a first electrode of the seventh transistor is connected to the light emitting element, and a second electrode of the seventh transistor is used to receive the second reset voltage.

[0013] Based on the same inventive concept, the present application also provides a display panel, comprising: a plurality of pixel circuits arranged in an array, wherein the pixel circuit is any one of the pixel circuits described above.

[0014] Based on the same inventive concept, the present application also provides a display device, including the display panel. As can be seen from the above description, the pixel circuit, display panel, and display device provided by the present application delay the on-time of the second light-emitting control module to prevent the second light-emitting control module from prematurely applying a driving current to the light-emitting element, thereby reducing the difference in current applied to the light-emitting element between the refresh frame stage and the hold frame stage, thereby reducing the difference in screen brightness between the refresh frame stage and the hold frame stage, and improving the optical defects of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in this application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are merely embodiments of this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0016] Figure 1 This is a schematic diagram of the pixel circuit module structure of an embodiment of the present application;

[0017] Figure 2 This is a timing diagram of the potentials at various points in the pixel circuit according to an embodiment of the present application;

[0018] Figure 3 A schematic diagram of a pixel circuit according to an embodiment of the present application;

[0019] Figure 4 This is a timing diagram of pixel circuit control signals in the related art;

[0020] Figure 5 This is a timing diagram of the pixel circuit control signals according to an embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to make the objectives, technical solutions and advantages of this application more clear, this application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0022] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should have the usual meanings understood by people with ordinary skills in the field to which this application belongs. The "first", "second" and similar words used in the embodiments of the present application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0023] An embodiment of the present application provides a pixel circuit, such as Figure 1 As shown, it includes: a driving module 10, a data writing module 20, a compensation storage module 30, a first reset module 40, a second reset module 50, a first light control module 60, a second light control module 70 and a light emitting element 80, wherein:

[0024] The driving module is configured to control a driving current flowing through the light emitting element for driving the light emitting element to emit light.

[0025] The data writing module is connected to the driving module and is configured to write the data signal Vdata into the driving module under the control of a write control signal Gate2. The write control signal Gate2 can be generated by a GOA (Gate Driven on Array) circuit and applied to the plurality of pixel circuits on each row in a row-shifted manner to control the data writing module to write data.

[0026] The compensation storage module is connected to the driving module and is configured to store the data signal written by the data writing module and compensate the driving module under the control of the compensation control signal Gate1.

[0027] The first reset module is connected to the driving module and is configured to provide a first reset voltage Vint1 to the driving module under the control of a first reset signal Reset1.

[0028] The second reset module is connected to the light emitting element and is configured to provide a second reset voltage Vint2 to the light emitting element under the control of a second reset signal Reset2.

[0029] In one specific embodiment, the second reset signal is the write control signal or is synchronized with the write control signal. This means that while data is being written, the voltage at the first electrode of the light-emitting element is also reset. This allows for the discharge of any charge on the parasitic capacitance of the light-emitting element to ensure normal light emission. In other embodiments, the second reset signal may also be synchronized with the first reset signal, as long as the voltage at the first electrode of the light-emitting element is reset before the first and second light-emitting control signals of the frame become valid.

[0030] The first light emitting control module is connected to the driving module and is configured to apply a first power supply voltage ELVDD to the driving module under the control of a first light emitting control signal EM1 .

[0031] The second light-emitting control module includes a first end, a second end, and a control end, the first end is connected to the driving module, and the second end is connected to the light-emitting element. The second light-emitting control module is configured to apply the driving current from the first end to the light-emitting element through the second end under the control of the second light-emitting control signal EM2 received by the control end, and delay the turn-on time of the second light-emitting control module during the data holding period in the holding frame stage.

[0032] The pixel circuit provided in the present application delays the turn-on time of the second light-emitting control module to prevent the second light-emitting control module from applying the driving current to the light-emitting element in advance, thereby reducing the difference in the current applied to the light-emitting element in the refresh frame stage and the hold frame stage, and further reducing the brightness difference of the screen in the refresh frame stage and the hold frame stage, thereby improving the optical defects of the circuit.

[0033] The pixel circuit sequentially includes a refresh frame phase and at least one hold frame phase during each display cycle. The refresh frame phase includes: a drive reset period Phase 1, a data write period Phase 2, a light-emitting element reset period Phase 3, and a display period Phase 4. The hold frame phase includes: a potential hold period Phase 5, a data hold period Phase 6, a light-emitting element reset period Phase 7, and a display period Phase 8. The second light-emitting control module is configured to apply the drive current from the first terminal to the light-emitting element via the second terminal during display periods Phase 4 / Phase 8.

[0034] This application is for Figure 1 The potential of each point in the pixel circuit shown is monitored at each stage / period, such as Figure 2 As shown, by overlapping and comparing the data in the refresh frame stage with the data in the hold frame stage, it can be found that the potential of N3 in the data hold period Phase6 of the hold frame stage is higher than the potential of N3 in the data write period Phase2 of the refresh frame stage.

[0035] Since in the related art, the second light-emitting control module is a P-type transistor, according to the principle that the P-type transistor is turned on when Vgs is less than Vth, at this time, Vgs of the P-type transistor of the second light-emitting control module is V(EM2)-V(N3), then once the potential of N3 rises, it will cause Vgs to drop, and then cause Vgs<Vth, that is, the P-type transistor of the second light-emitting control module is turned on in advance in Phase 6 of the frame holding stage, and the driving current is applied to the light-emitting element in advance to pre-charge the light-emitting element, which ultimately causes the screen brightness in the frame holding stage to be higher than that in the frame refresh stage.

[0036] In view of this, the pixel circuit provided in the above embodiment of the present application delays the conduction time of the second light-emitting control module to avoid the second light-emitting control module applying the driving current to the light-emitting element in advance, thereby reducing the difference in the current applied to the light-emitting element in the refresh frame stage and the hold frame stage, and further reducing the brightness difference of the screen in the refresh frame stage and the hold frame stage, thereby improving the optical defects of the circuit.

[0037] Figure 3 A circuit diagram showing an example circuit structure of the pixel circuit is shown. It should be noted that the various example pixel circuits shown herein are for Figure 1 The circuit configuration of each circuit module in the embodiment is described as an example, but this does not limit each circuit module to adopt the same Figure 3 The same structure as described in the , for example, the driver module uses Figure 3 The circuit structure shown in the figure can be used in different Figure 3The circuit structure shown in the figure may include more transistors, etc., as long as the data voltage can be applied to the second node (N2) under the control of the write control signal. This understanding also applies to other exemplary circuit structures of the present disclosure. Figure 3 Briefly describe the working principle of the pixel circuit provided in this application in each stage / time period.

[0038] This application provides two specific embodiments to delay the on-time of the second light emitting control module. In some embodiments A, Figure 3 As shown, the second light-emitting control module includes a sixth transistor T6, the first electrode of the sixth transistor is connected to the driving module, the second electrode of the sixth transistor is connected to the light-emitting element, the control electrode of the sixth transistor is configured to receive the second light-emitting control signal, and the sixth transistor is an N-type transistor.

[0039] Because N-type transistors turn on when Vgs > Vth, when the potential of N3 rises and Vgs drops, T6 is further turned off, preventing T6 from turning on prematurely during Phase 6, which is the hold frame. By replacing the P-type transistors in the second light-emission control module in the related art with N-type transistors, the turn-on time of the second light-emission control module can be delayed.

[0040] The timing of the second light emitting control signal EM2 received by T6 can be adjusted accordingly based on the timing of the second light emitting control signal EM2 received by the P-type transistor T6 in the related art, and the timing of the control signals received by other modules of the circuit can remain unchanged. Figure 4 and Figure 5 As shown, Figure 4 is a timing diagram of various control signals received by the pixel circuit described in the related art, Figure 5 is a timing diagram of various control signals received by the pixel circuit of an embodiment of the present application, Figure 4 and Figure 5 The numbers 1 to 8 in the table represent Phase 1 to Phase 8.

[0041] In a specific embodiment A, EM2 inputs a low level to turn off T6 during Phase 1 to Phase 3 and Phase 5 to Phase 7; and inputs a high level to turn on T6 during Phase 4 and Phase 8, so that T6 applies the driving current to the light-emitting element.

[0042] In some embodiments, as Figure 3 As shown, the first light emitting control module includes a fifth transistor T5, and the fifth transistor is an N-type transistor.

[0043] In the related art, the transistors of the first and second light-emitting control modules are of the same type, so that they can be controlled by the same light-emitting control signal. In embodiment A, since the transistors of the second light-emitting control module are N-type transistors, in order to use the same light-emitting control signal, the transistors of the first light-emitting control module can be replaced with N-type transistors. In this embodiment, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 can be the same signal EM, thereby reducing wiring and saving wiring resources. The EM timing reference Figure 5 EM2 in.

[0044] In a specific embodiment A, EM1 inputs a low level to turn off T5 during Phase 1 to Phase 3 and Phase 5 to Phase 7; and inputs a high level to turn on T5 during Phase 4 and Phase 8, so that T5 applies ELVDD to the driving module.

[0045] In other embodiments, the first end of the second light-emitting control module and the driving module are both connected to a third node N3, the voltage at the third node is a first voltage during a data writing period in a refresh frame stage, and is a second voltage during a data holding period in a holding frame stage; the second light-emitting control signal includes a high-level signal and a low-level signal, the sixth transistor is turned off in response to the high-level signal, and the sixth transistor is turned on in response to the low-level signal, and the driving current from the first electrode is applied to the light-emitting element through the second electrode.

[0046] The second light-emitting control module includes a sixth transistor, a first electrode of the sixth transistor is connected to the driving module and the third node, a second electrode of the sixth transistor is connected to the light-emitting element, and a control electrode of the sixth transistor is configured to receive the second light-emitting control signal. The sixth transistor is a P-type device, wherein:

[0047] The voltage of the high-level signal minus the second voltage is greater than the threshold voltage of the control transistor, and the voltage of the low-level signal minus the first voltage is less than the threshold voltage of the control transistor.

[0048] The above embodiment retains the P-type transistor in the related art as the second light emitting control module, and instead delays the on-time of the second light emitting control module by controlling the second light emitting control signal or the threshold voltage of the transistor.

[0049] The above embodiment also includes two specific embodiments. The second light-emitting control signal controls the second light-emitting control module through the timing interaction of a high-level signal and a low-level signal. In one specific embodiment, the voltage in the second light-emitting control signal that turns off the transistor can be increased accordingly, thereby increasing Vgs = V(EM2) - V(N3) when the transistor is turned off, thereby further turning off the transistor and preventing the transistor of the second light-emitting control module from turning on prematurely.

[0050] If the turn-off voltage of the second light-emitting control signal is not changed, the on-time of the second light-emitting control module can be delayed by reducing the threshold voltage of the transistor of the second light-emitting control module. In another specific embodiment, the P-type transistor in the related art can be replaced with a P-type transistor with a lower threshold voltage. Figure 2 As shown, V(N3) in Phase 6 is approximately 5V higher than V(N3) in Phase 2. Those skilled in the art can determine the threshold voltage and corresponding model of the transistor in Example D of the present application based on the actual threshold voltage of the transistor of the second light-emitting control module in the pixel circuit in the related art, and no further limitations are given here.

[0051] In some embodiments, as Figure 3 As shown, the driving module includes a driving transistor T3, the gate of the driving transistor is connected to the compensation storage module, the first electrode of the driving transistor is connected to the first light-emitting control module, and the second electrode of the driving transistor is connected to the compensation storage module and the second light-emitting control module.

[0052] In a specific embodiment, for T3 in the refresh frame stage, during Phase 1, Reset 1 inputs a high level, turns on the N-type T1, and the Vinit 1 signal is input to the T3 gate (N1). The voltage maintained on the T3 gate in the previous frame is reset; during Phase 2, Reset 1 switches to a low level, T1 is closed, Gate 1 inputs a high level, turns on the N-type T2, and at this time the T3 gate voltage is Vdata+Vth; Gate 2 inputs a low level, turns on the P-type T4, and the Vdata voltage is written to the first pole (N2) of T3; during Phase 3, Gate 1 switches to a low level first, T2 Close, and at the same time, Gate2 switches to a high level, T4 is closed, Reset2 inputs a low level, P-type T7 is turned on, the Vinit2 signal is written to the anode of the light-emitting element, the light-emitting element is turned off, and waits for the light-emitting control signal to be input before normal light emission; in Phase 4, according to the T5 and T6 models in the above-mentioned different embodiments, T5 and T6 tubes are turned on respectively, the first pole voltage of T3 rises to ELVDD, and the gate potential of T3 is still Vdata+Vth. At this time, VGS-Vth of T3 = (Vdata+Vth-ELVDD)-Vth = Vdata-ELVDD, and normal light emission is displayed after pixel compensation Vth.

[0053] For T3 in the frame maintenance stage, in Phase 5, Reset1 remains at a low level, T1 remains closed, and the gate potential of T3 in the previous frame is maintained at Vdata+Vth; in Phase 6, Gate1 remains at a low level, T2 remains closed, Gate2 inputs a low level, T4 is turned on, and the Vdata' voltage is written to the first electrode of T3. At this time, VGS' of T3 = Vdata+Vth-Vdata'; Phase 7 is the same as Phase 3, Gate2 switches to a high level, T4 is turned off; Reset2 inputs a low level, T7 is turned on, the Vinit2 signal is written to the anode of the light-emitting element, the light-emitting element is turned off, and it waits for the light-emitting control signal to be input before it emits light normally; Phase 8 is the same as Phase 4, according to the T5 and T6 models in the above different embodiments, T5 and T6 tubes are turned on respectively, and the potential of the first electrode of T3 rises to ELVDD. At this time, VGS'-Vth of T3 = (Vdata+Vth-Vdata'-ELVDD)-Vth, and it emits light normally.

[0054] Currently in the display field, the use of LTPO TFTs has lower driving power than the use of LTPS TFTs. For example, LTPS transistors have a larger leakage current, but a faster driving speed and a larger on-state current. LTPO transistors can refer to oxide transistors, which have a smaller leakage current. To further avoid leakage in the pixel circuit, transistors outside the drive current flow path (such as T1, T2, T4, and T7 in the embodiment of the present application) can be selected as transistors with better leakage current characteristics, that is, the leakage current characteristics are better than those of the transistors in the drive current flow path, while the transistors in the drive current flow path (such as T3, T5, and T6 in the embodiment of the present application) use LTPS to ensure a fast driving speed.

[0055] In some embodiments, as Figure 3 As shown, the data writing module includes a fourth transistor T4, a gate of the fourth transistor is used to receive the writing control signal Gate2, a first electrode of the fourth transistor is used to receive the data signal Vdata, and a second electrode of the fourth transistor is connected to the driving module.

[0056] In a specific embodiment, during Phase 2 and Phase 6, Gate 2 inputs a valid level to turn on T4 and write the Vdata voltage into the driver module; during other periods, Gate 2 inputs an invalid level to turn off T4.

[0057] In a more specific embodiment, T4 is a P-type transistor. During Phase 2 and Phase 6, Gate 2 inputs a low level to turn on T4 and write the Vdata voltage into the driver module; during other periods, Gate 2 inputs a high level to turn off T4.

[0058] In some embodiments, as Figure 3 As shown, the compensation storage module includes a second transistor T2 and a storage capacitor Cst, the gate of the second transistor is used to receive the compensation control signal Gate1, the first electrode of the second transistor, the second electrode of the second transistor and the first electrode of the storage capacitor are all connected to the driving module, and the second electrode of the storage capacitor is used to receive the first power supply voltage.

[0059] In a specific embodiment, during Phase 1, Phase 2, Phase 5, and Phase 6, Gate 1 inputs a valid level to turn on T2; during Phase 3, Phase 4, Phase 7, and Phase 8, Gate 1 inputs an invalid level to turn off T2. The storage capacitor is configured to store the threshold voltage Vth of T3 during Phase 2 and Phase 6, and to maintain the gate potential of T3 at Vdata+Vth during Phase 4 and Phase 8.

[0060] In a more specific embodiment, T2 is an N-type transistor. During Phase 1, Phase 2, Phase 5, and Phase 6, Gate 1 inputs a high level to turn on T2; during Phase 3, Phase 4, Phase 7, and Phase 8, Gate 1 inputs a low level to turn off T2.

[0061] In some embodiments, as Figure 3 As shown, the first reset module includes a first transistor T1, a gate of the first transistor is used to receive the first reset signal Reset1, a first electrode of the first transistor is connected to the driving module, and a second electrode of the first transistor is used to receive the first reset voltage Vint1.

[0062] In a specific embodiment, during Phase 1, Reset 1 inputs a valid level to turn on T1, and T1 inputs Vinit 1 to the gate of T3, so that the voltage maintained on the gate of T3 in the previous frame is reset; during other periods, Reset 1 inputs an invalid level to turn off T1.

[0063] In a more specific embodiment, T1 is an N-type transistor. During Phase 1, Reset1 inputs a high level to turn on T1, and T1 inputs Vinit1 to the gate of T3, so that the voltage maintained on the gate of T3 in the previous frame is reset; during other periods, Reset1 inputs a low level to turn off T1.

[0064] In some embodiments, as Figure 3 As shown, the second reset module includes a seventh transistor T7, a gate of the seventh transistor is used to receive the second reset signal Reset2, a first electrode of the seventh transistor is connected to the light emitting element, and a second electrode of the seventh transistor is used to receive the second reset voltage Vint2.

[0065] In a specific embodiment, during Phase 3 and Phase 7, Reset2 inputs a valid level to turn on T7, and T7 writes Vinit2 into the light-emitting element; during other periods, Reset2 inputs an invalid level to turn off T7.

[0066] In a more specific embodiment, T7 is a P-type transistor. During Phase 3 and Phase 7, Reset2 inputs a low level to turn on T7, and T7 writes Vinit2 into the light-emitting element. During other periods, Reset2 inputs a high level to turn off T7.

[0067] exist Figure 3The transistors in the described pixel circuit use oxide transistors, which can reduce leakage in the circuit. Since a light-emitting control signal is used to control the resetting of the voltage on the first electrode of the light-emitting element, the resetting time of the second reset voltage on the light-emitting element is greatly lengthened, ensuring the complete release of the voltage on the light-emitting element and saving signal overhead. When the fourth transistor of the data writing module and the second transistor of the compensation storage module are both oxide transistors of the same type, they can be driven by the same signal (i.e., a scan signal), so two separate signals are not required, and signal overhead can also be saved, which is conducive to the design of narrow borders and the reduction of overall power consumption of signal generation circuits (e.g., GOA circuits) that generate various signals.

[0068] In the embodiment of the present application, the first power supply voltage ELVDD can be a DC voltage greater than 0, such as 5V, 4.6V, etc. The second power supply voltage ELVSS can be a DC voltage less than or equal to 0, such as 0V, 2V, etc. The first reset voltage and the second reset voltage can be the same, for example, both are the second power supply voltage ELVSS, but they can also take different values ​​less than or equal to 0.

[0069] The width-to-length ratio of the N-type transistor in each of the above embodiments can be 2.5 / 3.5, for example, its width ranges from 1.5 to 4 μm (micrometers), for example, it can be 1.5, 2, 2.5, 3, 3.5, 4, etc., and its length ranges from 3 to 5 μm, for example, it can be 3, 3.5, 4, 4.5, 5, etc.; the width-to-length ratio of the P-type transistor can be 2.2 / 3.0 (excluding the driving transistor), for example, its width ranges from 1.5 to 4 μm, for example, it can be 1.5, 2, 2.5, 3, 3.5, 4, etc., and its length ranges from 2 to 6 μm, for example, it can be 2, 3, 4, 5, 6, etc., and the embodiments of the present disclosure are not limited to this.

[0070] The pixel circuit needs to turn on the driving transistor T3 during the data writing and compensation phases. Therefore, the voltage difference Vint1-ELVDD between the reset voltage Vint1 and the first power supply terminal ELVDD needs to be less than the threshold voltage Vth of the driving transistor T3. Vint1 can be 2 to 6V, for example, 2V, 3V, 4V, 5V, 6V, etc. Vint1-ELVDD can be less than a*Vth, where a can be 2 to 7, for example, a can be 2, 4, 6, or 7; and Vth can be 2 to 5V, for example, 2V, 3V, 5V, etc. ELVDD can be greater than 1.5 times Vth, for example, ELVDD can be 1.6 times, 1.8 times, or 2 times Vth, etc.

[0071] It should be noted that in the description of the embodiments of the present disclosure, the first node N1, the second node N2, and the third node N3 do not represent actual components, but represent the junction points of related circuit connections in the circuit diagram.

[0072] It should be noted that in the description of the embodiments of the present disclosure, Vdata can represent both a data signal terminal and a data signal level. Similarly, Vint1 and Vint2 can represent both an initial voltage terminal and a reset voltage. ELVDD can represent both a first power line and a first voltage, and ELVSS can represent both a second power line and a second voltage. The following embodiments are the same and will not be described in detail.

[0073] In at least one embodiment of the present disclosure, the threshold voltage Vth of the driving transistor in the driving module can be greater than or equal to -5V and less than or equal to -2V. For example, Vth can be greater than or equal to -4V and less than or equal to -2.5V. For example, Vth can be -4V, -3.5V, -3V or -2.5V, but is not limited thereto.

[0074] Based on the same inventive concept, corresponding to the pixel circuit of any of the above embodiments, the present application also provides a display panel, which includes a plurality of pixel units arranged in an array, and each pixel unit includes the pixel circuit provided by any embodiment of the present disclosure.

[0075] The display panel provided by the present application has a pixel circuit therein which delays the turn-on time of the second light-emitting control module to prevent the second light-emitting control module from applying the driving current to the light-emitting element in advance, thereby reducing the difference in the current applied to the light-emitting element in the refresh frame stage and the hold frame stage, and further reducing the brightness difference of the screen in the refresh frame stage and the hold frame stage, thereby improving the optical defects of the circuit.

[0076] The plurality of pixel units are arranged in multiple rows, and the same signal line of each pixel circuit in each row of pixel units is connected and provides the same signal, which is not limited in the embodiments of the present disclosure. In addition, in the same pixel row, two pixel circuits in adjacent columns can be mirrored to facilitate wiring.

[0077] Based on the same inventive concept, corresponding to the pixel circuit of any of the above embodiments, the present application also provides a display device, including the display panel provided by the above embodiments of the present disclosure.

[0078] The display device provided by the present application has a pixel circuit therein which delays the conduction time of the second light-emitting control module to prevent the second light-emitting control module from applying the driving current to the light-emitting element in advance, thereby reducing the difference in the current applied to the light-emitting element in the refresh frame stage and the hold frame stage, thereby reducing the brightness difference of the screen in the refresh frame stage and the hold frame stage, and improving the optical defects of the circuit.

[0079] The display device provided in this embodiment can be applied to any product or component with a display function, such as electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, and navigators.

[0080] The display device of the above embodiment includes the corresponding pixel circuit in any of the above embodiments and has the beneficial effects of the corresponding embodiment, which will not be described in detail here.

[0081] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. Within the scope of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0082] In addition, for simplicity of description and discussion, and in order not to make the embodiment of the application difficult to understand, the known power supply / ground connection with integrated circuit (IC) chip and other components may or may not be shown in the accompanying drawings provided. In addition, the device can be shown in the form of a block diagram to avoid making the embodiment of the application difficult to understand, and this also takes into account the following fact, that is, the details of the embodiment of these block diagram devices are highly dependent on the platform to be implemented in the embodiment of the application (that is, these details should be fully within the scope of understanding of those skilled in the art). When specific details (for example, circuit) are set forth to describe exemplary embodiments of the application, it will be apparent to those skilled in the art that the embodiment of the application can be implemented without these specific details or when these specific details are changed. Therefore, these descriptions should be considered to be illustrative rather than restrictive.

[0083] Although the present invention has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those skilled in the art based on the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may utilize the embodiments discussed.

[0084] The embodiments of the present application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of this application.

Claims

1. A pixel circuit comprising: A driving module, a data writing module, a compensation storage module, a first reset module, a second reset module, a first light-emitting control module, a second light-emitting control module, and a light-emitting element, wherein: The driving module is configured to control a driving current flowing through the light emitting element for driving the light emitting element to emit light; The data writing module is connected to the driving module and is configured to write a data signal into the driving module under the control of a write control signal; The compensation storage module is connected to the driving module and is configured to store the data signal written by the data writing module and compensate the driving module under the control of a compensation control signal; The first reset module is connected to the driving module and is configured to provide a first reset voltage to the driving module under the control of a first reset signal; The second reset module is connected to the light emitting element and is configured to provide a second reset voltage to the light emitting element under the control of a second reset signal; The first light emitting control module is connected to the driving module and is configured to apply a first power supply voltage to the driving module under the control of a first light emitting control signal; The second light-emitting control module includes a first end, a second end and a control end, the first end is connected to the driving module, and the second end is connected to the light-emitting element. The second light-emitting control module is configured to apply the driving current from the first end to the light-emitting element through the second end under the control of the second light-emitting control signal received by the control end, and delay the turn-on time of the second light-emitting control module during the data holding period of the frame holding stage.

2. The pixel circuit according to claim 1, wherein: The second light-emitting control module includes a sixth transistor, a first electrode of the sixth transistor is connected to the driving module, a second electrode of the sixth transistor is connected to the light-emitting element, a control electrode of the sixth transistor is configured to receive the second light-emitting control signal, and the sixth transistor is an N-type transistor.

3. The pixel circuit according to claim 2, wherein: The first light emitting control module includes a fifth transistor, and the fifth transistor is an N-type transistor.

4. The pixel circuit according to claim 1, wherein: The driving module includes a driving transistor, a gate of the driving transistor is connected to the compensation storage module, a first electrode of the driving transistor is connected to the first light emitting control module, and a second electrode of the driving transistor is connected to the compensation storage module and the second light emitting control module.

5. The pixel circuit according to claim 1, wherein: The data writing module includes a fourth transistor, a gate of the fourth transistor is used to receive the writing control signal, a first electrode of the fourth transistor is used to receive the data signal, and a second electrode of the fourth transistor is connected to the driving module. The pixel circuit according to claim 1 , wherein: The compensation storage module includes a second transistor and a storage capacitor, the gate of the second transistor is used to receive the compensation control signal, the first electrode of the second transistor, the second electrode of the second transistor and the first electrode of the storage capacitor are all connected to the driving module, and the second electrode of the storage capacitor is used to receive the first power supply voltage.

7. The pixel circuit according to claim 1, wherein: The first reset module includes a first transistor, a gate of the first transistor is used to receive the first reset signal, a first electrode of the first transistor is connected to the driving module, and a second electrode of the first transistor is used to receive the first reset voltage.

8. The pixel circuit according to claim 1, wherein: The second reset module includes a seventh transistor, a gate of the seventh transistor is used to receive the second reset signal, a first electrode of the seventh transistor is connected to the light emitting element, and a second electrode of the seventh transistor is used to receive the second reset voltage.

9. A display panel comprising: A plurality of pixel circuits arranged in an array, wherein the pixel circuit is the pixel circuit according to any one of claims 1 to 8. 10 . A display device comprising the display panel according to claim 9 .

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