A 10T1C SRAM cell structure capable of performing in-situ storage logic operations

Abstract

The present invention discloses a 10T1C SRAM cell structure capable of performing in-situ storage logic operations. The structure comprises 10 MOS transistors; a transfer storage capacitor, wherein M1 to M6 constitute the storage portion, and M7 to M10 constitute the calculation portion; a PMOS transistor M1 and an NMOS transistor M2, as well as a PMOS transistor M3 and an NMOS transistor M4, forming two cross-coupled inverters; a CVDP terminal and a VDD terminal connected or disconnected under the control of a switch SW1, and a CVSP terminal and a VSS terminal connected or disconnected under the control of a switch SW2. Based on the structure of the 10T1C SRAM cell, a single 10T1C SRAM cell can perform an in-situ storage logic "AND" operation. The 10T1C SRAM cell can efficiently and quickly perform an in-situ storage logic "AND" operation, with the operation result being stored in-situ overwritten in the 10T1C SRAM cell where the operand is located.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a 10T1C SRAM (Static Random Access Memory) cell structure capable of performing in-situ storage logic operations. Background Art

[0002] Because storage and computation are separated in the von Neumann architecture, performing intensive data operations within the artificial intelligence (AI) paradigm requires extensive data movement, resulting in significant power consumption and time overhead. In-memory computing technology, an effective strategy to overcome this dilemma, eliminates the need to fetch data from the processor and instead integrates computation into memory. This significantly reduces data movement, thereby effectively lowering the corresponding power consumption and time overhead. It is important to note that research on in-memory computing should not be limited to computational functions but should also serve the needs of data analysis. While neural networks currently achieve excellent performance, a deeper understanding of their principles is needed, particularly the establishment of an interpretable analytical framework. Convolution is a fundamental operation in neural networks, and convolution is composed of multiplications. Therefore, multiplications account for a significant portion of the overall operation of neural networks. Multiplication data is crucial for in-depth analysis of neural network operation.

[0003] The output results of current multiplication circuits are mainly in the form of multiplication and accumulation. Therefore, the results of each specific multiplication operation have black box characteristics, and the results of the specific multiplication are not clear. When analyzing the operation data of the neural network, it is not enough to only analyze the multiplication and accumulation data. According to the existing technology, multi-bit multiplication can be decomposed into a series of "AND" logical operations. If these "AND" logical operation results can be effectively stored and output, then the operation results of each multiplication can be analyzed, and the operation of the neural network can be analyzed at a deeper level. Summary of the Invention

[0004] The present invention aims to provide a 10T1C SRAM cell structure capable of performing in-situ storage logic operations. The 10T1C SRAM cell can efficiently and quickly perform in-situ storage logic "AND" operations. The operation results are stored in-situ overwritten in the 10T1C SRAM cell where the operands are located. Therefore, the operation results can be stored and obtained without requiring additional storage space. This is suitable for scenarios such as artificial intelligence paradigm data analysis.

[0005] The purpose of the present invention is achieved through the following technical solutions:

[0006] A 10T1C SRAM cell structure capable of performing in-situ storage logic operations, wherein the 10T1C SRAM cell includes 10 MOS transistors, denoted as M1 to M10, and a transfer storage capacitor, denoted as C1, wherein:

[0007] M1 to M6 constitute the storage part, and M7 to M10 constitute the calculation part;

[0008] The PMOS transistor M1 and the NMOS transistor M2, as well as the PMOS transistor M3 and the NMOS transistor M4 form two cross-coupled inverters;

[0009] The source end of the PMOS transistor M1 is connected to the controllable VDD port, namely CVDP, and the drain end is connected to the storage point Q; the source end of the NMOS transistor M2 is connected to the controllable VSS port, namely CVSP, and the drain end is connected to the storage point Q; CVDP is controlled by the switch SW1, and CVSP is controlled by the switch SW2. When the switch SW1 is closed, CVDP is connected to VDD, and when the switch SW1 is open, CVDP is unconnected; when the switch SW2 is closed, CVSP is connected to VSS, and when the switch SW2 is open, CVSP is unconnected;

[0010] The source terminal of the PMOS tube M3 is connected to VDD, and the drain terminal is connected to the storage point QB; the source terminal of the NMOS tube M4 is connected to VSS, and the drain terminal is connected to the storage point QB;

[0011] The gate ends of the PMOS tube M1 and the NMOS tube M2 are controlled by the storage point QB, and the gate ends of the PMOS tube M3 and the NMOS tube M4 are controlled by the storage point Q;

[0012] The drain end of the NMOS transistor M5 is connected to the storage point Q, the gate end is connected to the word line WL, and the source end is connected to the left bit line BL;

[0013] The drain end of the NMOS transistor M6 is connected to the storage point QB, the gate end is connected to the word line WL, and the source end is connected to the right bit line BLB;

[0014] The drain end of the NMOS transistor M9 is connected to the storage point QB, the gate end is connected to the control signal EN1, and the source end is connected to the transfer storage capacitor C1;

[0015] The transfer storage capacitor C1 is used to store the voltage of the transfer storage point QC. The upper end of the transfer storage capacitor C1 is connected to the drain end of the PMOS transistor M10 and the gate end of the NMOS transistor M8, and the lower end is connected to VSS.

[0016] The gate terminal of the PMOS transistor M10 is connected to the control signal WL_VICE, and the source terminal is connected to the bit line RBL;

[0017] The drain terminal of the NMOS transistor M7 is connected to the storage point Q, the source terminal is connected to the drain terminal of the NMOS transistor M8, and the gate terminal is connected to the control signal EN2;

[0018] The source end of the NMOS tube M8 is connected to VSS, and the gate end is connected to the transfer storage node QC;

[0019] A parasitic capacitor C2 is formed between the PMOS transistor M1, the NMOS transistor M2, the NMOS transistor M5, and the NMOS transistor M7. When CVDP and CVSP are unconnected, the parasitic capacitor C2 formed between the PMOS transistor M1, the NMOS transistor M2, the NMOS transistor M5, and the NMOS transistor M7 stores the voltage of the storage point Q.

[0020] Based on the structure of the 10T1C SRAM cell, a single 10T1C SRAM cell can perform an in-situ storage logical AND operation. At the same time, since a multi-bit multiplication operation can be decomposed into a series of logical AND operations, a group of 10T1C SRAM cells can perform a multi-bit multiplication operation.

[0021] It can be seen from the technical solution provided by the present invention that the above-mentioned 10T1C SRAM unit can efficiently and quickly perform in-situ storage logical "AND" operations, and the operation results are stored in-situ overwritten in the unit where the operands are located. Therefore, no additional storage space is required to store and obtain the operation results, which is suitable for scenarios such as artificial intelligence paradigm data analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 A schematic diagram of the structure of a 10T1C SRAM cell capable of performing in-situ storage logic operations provided by an embodiment of the present invention;

[0024] Figure 2 Schematic diagram of the process of performing an in-situ storage logic “AND” operation on a single 10T1C SRAM cell according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments, and do not constitute a limitation of the present invention. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0026] like Figure 1FIG. 1 is a schematic diagram of the structure of a 10T1C SRAM cell capable of performing in-situ storage logic operations according to an embodiment of the present invention. The 10T1C SRAM cell includes 10 MOS transistors, denoted as M1 to M10, and one intermediate storage capacitor, denoted as C1.

[0027] M1 to M6 constitute the storage part, and M7 to M10 constitute the calculation part;

[0028] The PMOS transistor M1 and the NMOS transistor M2, as well as the PMOS transistor M3 and the NMOS transistor M4 form two cross-coupled inverters;

[0029] The source end of the PMOS transistor M1 is connected to the controllable VDD port, namely CVDP (Controllable VDD Port), and the drain end is connected to the storage point Q. The source end of the NMOS transistor M2 is connected to the controllable VSS port, namely CVSP (Controllable VSS Port), and the drain end is connected to the storage point Q. CVDP is controlled by the switch SW1, and CVSP is controlled by the switch SW2. When the switch SW1 is closed, CVDP is connected to VDD. When the switch SW1 is open, CVDP is disconnected. When the switch SW2 is closed, CVSP is connected to VSS. When the switch SW2 is open, CVSP is disconnected.

[0030] The source terminal of the PMOS tube M3 is connected to VDD, and the drain terminal is connected to the storage point QB; the source terminal of the NMOS tube M4 is connected to VSS, and the drain terminal is connected to the storage point QB;

[0031] The gate ends of the PMOS tube M1 and the NMOS tube M2 are controlled by the storage point QB, and the gate ends of the PMOS tube M3 and the NMOS tube M4 are controlled by the storage point Q;

[0032] The drain end of the NMOS transistor M5 is connected to the storage point Q, the gate end is connected to the word line WL, and the source end is connected to the left bit line BL;

[0033] The drain end of the NMOS transistor M6 is connected to the storage point QB, the gate end is connected to the word line WL, and the source end is connected to the right bit line BLB;

[0034] The drain end of the NMOS transistor M9 is connected to the storage point QB, the gate end is connected to the control signal EN1, and the source end is connected to the transfer storage capacitor C1;

[0035] The transfer storage capacitor C1 is used to store the voltage of the transfer storage point QC. The upper end of the transfer storage capacitor C1 is connected to the drain end of the PMOS transistor M10 and the gate end of the NMOS transistor M8, and the lower end is connected to VSS.

[0036] The gate terminal of the PMOS transistor M10 is connected to the control signal WL_VICE, and the source terminal is connected to the bit line RBL;

[0037] The drain terminal of the NMOS transistor M7 is connected to the storage point Q, the source terminal is connected to the drain terminal of the NMOS transistor M8, and the gate terminal is connected to the control signal EN2;

[0038] The source end of the NMOS tube M8 is connected to VSS, and the gate end is connected to the transfer storage node QC;

[0039] A parasitic capacitor C2 is formed between the PMOS transistor M1, NMOS transistor M2, NMOS transistor M5, and NMOS transistor M7. When CVDP and CVSP are unconnected, the parasitic capacitor C2 formed between the PMOS transistor M1, NMOS transistor M2, NMOS transistor M5, and NMOS transistor M7 stores the voltage of the storage point Q. It is worth noting that C2 is not set in the unit structure, but is a parasitic capacitor formed between M1-M2 and M5, M7.

[0040] Based on the structure of the 10T1C SRAM cell, a single 10T1C SRAM cell can perform an in-situ storage logical AND operation; a multi-bit multiplication operation can be decomposed into a series of logical AND operations, and a group of 10T1C SRAM cells performs the multi-bit multiplication operation.

[0041] In specific implementation, such as Figure 2 FIG. 1 is a schematic diagram showing a process of performing an in-situ storage logic AND operation on a single 10T1C SRAM cell according to an embodiment of the present invention, wherein: Figure 2 There are four cases: a, b, c, and d. Operand A is stored in the 10T1C SRAM cell, and operand B is reflected on the control signal EN1. The logical "AND" operation is performed in three steps. Before the operation is performed, the transfer storage node QC is precharged to a high voltage, and operand A is written into the 10T1C SRAM cell. If A=0, then the storage point Q=0 and the storage point QB=1 (such as Figure 2 c and d in ); if A=1, then store point Q=1 and store point QB=0 (as Figure 2 a) and b) in the above code, the specific steps are:

[0042] Step 1: Control signal EN1 is enabled. If operand B=1, control signal EN1 generates a high voltage pulse. NMOS transistor M9 is turned on during the pulse. At this time, if the storage point QB is at a low voltage, that is, QB=0, the transit storage node QC is discharged to the storage point QB through NMOS transistor M9, and the transit storage node QC is discharged to a low voltage. If the storage point QB is at a high voltage, that is, QB=1, no discharge is formed between the transit storage node QC and the storage point QB, and the transit storage node QC maintains a high voltage.

[0043] If operand B=0, the control signal EN1 maintains a low voltage, the NMOS transistor M9 is turned off, no discharge channel is formed between the transit storage node QC and the storage point QB, and the transit storage node QC maintains a high voltage;

[0044] Step 2: Switches SW1 and SW2 are disconnected, control signal EN2 is enabled, NMOS transistor M7 is turned on, and if the intermediate storage node QC is at a high voltage, NMOS transistor M8 is turned on, forming a discharge path from the storage point Q at the upper end of the parasitic capacitor C2 through the NMOS transistors M7 and M8 to VSS. If the intermediate storage node QC is at a low voltage, NMOS transistor M8 is turned off, and a discharge path from the storage point Q at the upper end of the parasitic capacitor C2 through the NMOS transistors M7 and M8 to VSS is not formed, and the storage point Q maintains its original voltage.

[0045] After this step, the operation result is overwritten and stored in the 10T1 C SRAM unit where the operand A is located;

[0046] Step 3: Switches SW1 and SW2 are closed again, the logical AND operation is completed, and the operation data is stably stored in the 10T1C SRAM unit.

[0047] In addition, multi-bit multiplication operations can be decomposed into a series of logical "AND" operations, and multi-bit multiplication operations are performed by a group of 10T1C SRAM units. The in-situ storage of multi-bit multiplication operations is suitable for artificial intelligence paradigm data analysis. When performing artificial intelligence paradigm calculations, multi-row word line activation multiplication operations are applicable.

[0048] In order to more clearly demonstrate the technical solution and technical effects provided by the present invention, the logical "AND" operation process is described in detail using (A=1)&(B=1) and (A=1)&(B=0) as examples:

[0049] like Figure 2 As shown, when operands A = 1 and B = 1, before the operation begins, node QC is precharged to VDD, completing the set of nodes Q = 1 and QB = 0, representing operand A = 1, within the 10T1C SRAM cell. After the precharge completes, the operation begins. In step 1, since B = 1, a high voltage pulse is generated on EN1, causing node QC to discharge to node QB via M9, ​​discharging node QC to a low voltage. In step 2, SW1 and SW2 are disconnected, EN2 is enabled, and M7 is turned on. Since QC is at a low voltage, M8 is also turned off, preventing a discharge path from node Q through M7 and M8 to VSS, maintaining node Q at its original voltage. After this step, the operation result is overwritten and stored in the 10T1C SRAM cell where operand A resides, i.e., Q = 1, QB = 0. In step 3, SW1 and SW2 are closed again, completing the logical AND operation. The operation data, Q = 1, QB = 0, is stably stored within the 10T1C SRAM cell. At the same time, the result of the operation of (A=1) & (B=1) is also 1, so the operation is correct;

[0050] When operands A = 1 and B = 0, node QC is precharged to VDD before the operation begins. This sets nodes Q = 1 and QB = 0, representing operand A = 1, within the 10T1C SRAM cell. In step 1, since B = 0, EN1 remains low, M9 is off, and no discharge path is formed between nodes QC and QB, maintaining a high voltage at node QC. In step 2, SW1 and SW2 are disconnected, EN2 is enabled, and M7 is turned on. Since QC is high, M8 is also turned on, creating a discharge path from node Q at the upper end of parasitic capacitance C2 through M7 and M8 to VSS, discharging node Q to a low voltage. Simultaneously, since M3 and M4 are controlled by Q, M3 turns on and M4 turns off, charging node QB to a high voltage. After this step, the result of the operation is overwritten and stored in the 10T1 C SRAM cell where operand A resides, i.e., Q = 0, QB = 1. In step three, SW1 and SW2 are closed again, completing the logical AND operation. This means that the operation data, Q = 0, QB = 1, is stably stored in the 10T1 C SRAM cell. At the same time, the result of the operation (A = 1) & (B = 0) is also 0, indicating that the operation is correct.

[0051] It should be noted that the contents not described in detail in the embodiments of the present invention belong to the prior art known to those skilled in the art.

[0052] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims. The information disclosed in the background technology section of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art.

Claims

1. A 10T1C SRAM cell structure capable of performing in-situ storage logic operations, characterized in that: The 10T1CSRAM cell includes 10 MOS transistors, denoted as M1 to M10, and a transfer storage capacitor, denoted as C1, wherein: M1 to M6 constitute the storage part, and M7 to M10 constitute the calculation part; The PMOS transistor M1 and the NMOS transistor M2, as well as the PMOS transistor M3 and the NMOS transistor M4 form two cross-coupled inverters; The source end of the PMOS transistor M1 is connected to the controllable VDD port, namely CVDP, and the drain end is connected to the storage point Q; the source end of the NMOS transistor M2 is connected to the controllable VSS port, namely CVSP, and the drain end is connected to the storage point Q; CVDP is controlled by the switch SW1, and CVSP is controlled by the switch SW2. When the switch SW1 is closed, CVDP is connected to VDD, and when the switch SW1 is open, CVDP is unconnected; when the switch SW2 is closed, CVSP is connected to VSS, and when the switch SW2 is open, CVSP is unconnected; The source terminal of the PMOS tube M3 is connected to VDD, and the drain terminal is connected to the storage point QB; the source terminal of the NMOS tube M4 is connected to VSS, and the drain terminal is connected to the storage point QB; The gate ends of the PMOS tube M1 and the NMOS tube M2 are controlled by the storage point QB, and the gate ends of the PMOS tube M3 and the NMOS tube M4 are controlled by the storage point Q; The drain end of the NMOS transistor M5 is connected to the storage point Q, the gate end is connected to the word line WL, and the source end is connected to the left bit line BL; The drain end of the NMOS transistor M6 is connected to the storage point QB, the gate end is connected to the word line WL, and the source end is connected to the right bit line BLB; The drain end of the NMOS transistor M9 is connected to the storage point QB, the gate end is connected to the control signal EN1, and the source end is connected to the transfer storage capacitor C1; The transfer storage capacitor C1 is used to store the voltage of the transfer storage point QC. The upper end of the transfer storage capacitor C1 is connected to the drain end of the PMOS transistor M10 and the gate end of the NMOS transistor M8, and the lower end is connected to VSS. The gate terminal of the PMOS transistor M10 is connected to the control signal WL_VICE, and the source terminal is connected to the bit line RBL; The drain terminal of the NMOS transistor M7 is connected to the storage point Q, the source terminal is connected to the drain terminal of the NMOS transistor M8, and the gate terminal is connected to the control signal EN2; The source end of the NMOS tube M8 is connected to VSS, and the gate end is connected to the transfer storage node QC; A parasitic capacitor C2 is formed between the PMOS transistor M1, the NMOS transistor M2, the NMOS transistor M5, and the NMOS transistor M7. When CVDP and CVSP are unconnected, the parasitic capacitor C2 formed between the PMOS transistor M1, the NMOS transistor M2, the NMOS transistor M5, and the NMOS transistor M7 stores the voltage of the storage point Q. Based on the structure of the 10T1C SRAM cell, a single 10T1C SRAM cell can perform an in-situ storage logical AND operation. At the same time, since a multi-bit multiplication operation can be decomposed into a series of logical AND operations, a group of 10T1C SRAM cells can perform a multi-bit multiplication operation.

2. The 10T1C SRAM cell structure capable of performing in-situ storage logic operations according to claim 1, characterized in that: The specific process of performing the in-situ storage logic "AND" operation of the single 10T1C SRAM unit is as follows: Operand A is stored in the 10T1C SRAM cell, and operand B is reflected on the control signal EN1. The logical "AND" operation is performed in three steps. Before the operation is performed, the intermediate storage node QC is precharged to a high voltage, and operand A is written to the 10T1C SRAM cell. If A=0, then the storage point Q=0 and the storage point QB=1; if A=1, then the storage point Q=1 and the storage point QB=0. The specific steps are: Step 1: Control signal EN1 is enabled. If operand B=1, control signal EN1 generates a high voltage pulse. NMOS transistor M9 is turned on during the pulse. At this time, if the storage point QB is at a low voltage, that is, QB=0, the transit storage node QC is discharged to the storage point QB through NMOS transistor M9, and the transit storage node QC is discharged to a low voltage. If the storage point QB is at a high voltage, that is, QB=1, no discharge is formed between the transit storage node QC and the storage point QB, and the transit storage node QC maintains a high voltage. If operand B=0, the control signal EN1 maintains a low voltage, the NMOS transistor M9 is turned off, no discharge channel is formed between the transit storage node QC and the storage point QB, and the transit storage node QC maintains a high voltage; Step 2: Switches SW1 and SW2 are disconnected, control signal EN2 is enabled, NMOS transistor M7 is turned on, and if the intermediate storage node QC is at a high voltage, NMOS transistor M8 is turned on, forming a discharge path from the storage point Q at the upper end of the intermediate storage capacitor C2 through NMOS transistors M7 and M8 to VSS. If the intermediate storage node QC is at a low voltage, NMOS transistor M8 is turned off, and a discharge path from the storage point Q at the upper end of the intermediate storage capacitor C2 through NMOS transistors M7 and M8 to VSS is not formed, and the storage point Q maintains its original voltage. After this step, the operation result is overwritten and stored in the 10T1C SRAM unit where the operand A is located; Step 3: Switches SW1 and SW2 are closed again, the logical AND operation is completed, and the operation data is stably stored in the 10T1CSRAM unit.

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