Bit logic operator and electronic device

Abstract

The application discloses a bit logic operator and electronic equipment. The trigger comprises a plurality of first data modules, the first data module comprises a pair of state-complementary first magnetic tunnel junction groups; the logic gate comprises a plurality of second data modules, the second data module comprises a pair of state-complementary second magnetic tunnel junction groups; the logic gate is used for obtaining a logic operation result according to a plurality of first operation data provided by the trigger and a plurality of second operation data output by the plurality of second data modules; and the control module is connected with the trigger and the logic gate respectively, and is used for selecting and controlling a first target data module to output one bit of first operation data to the logic gate and reading one bit of second operation data from the selected second target data module according to a preset output control signal. In the embodiment of the application, full non-volatility of data storage and multi-bit expansion logic operation on the logic gate can be realized, which is beneficial to improving the logic operation efficiency and optimizing the device integration.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a bit logic arithmetic unit and electronic device. Background Technology

[0002] In today's era, the integration density of modules within chips is increasing rapidly. With this ever-growing integration density, there is an urgent need for new theoretical methods to break through the limits of Moore's Law in the field of integrated modules. In recent years, spintronics has developed extremely rapidly, and one important research achievement in this field is the magnetic tunnel junction (MTJ). The MTJ is a novel spintronic device, essentially a magnetoresistive structure, a three-layer structure formed by two ferromagnetic layers sandwiching an insulating layer. The MTJ has two resistance states, high and low, corresponding to data "1" and "0". Its most significant characteristic is that it can maintain its state value even when power is off. Incorporating this device into module design can reduce the module's static power consumption. However, current application circuits using MTJs can only store partial data in the MTJ, meaning only a portion of the data is non-volatile, not all data. Furthermore, only one-bit logic operations can be performed, resulting in reduced logic operation efficiency and low device integration density. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art, and to provide a bit logic arithmetic unit and electronic device that can realize the complete non-volatileness of data storage and provide the function of multi-bit logic operation.

[0004] In a first aspect, the present invention provides a bit logic arithmetic unit, comprising:

[0005] The trigger includes multiple first data modules, each first data module including a pair of state-complementary first magnetic tunnel junctions, and the first data module is used to write and store one bit of first operational data.

[0006] A logic gate, connected to the flip-flop, includes multiple second data modules. Each second data module includes a pair of complementary second magnetic tunnel junctions. The second data module is used to write and store one bit of second operational data.

[0007] The logic gate is used to obtain a logic operation result based on the multiple bits of the first operation data provided by the flip-flop and the multiple bits of the second operation data output by the multiple second data modules;

[0008] The control module is connected to the trigger and the logic gate respectively, and is used to select and control the first target data module to output one bit of the first operation data to the logic gate according to the preset output control signal, and to read one bit of the second operation data from the selected second target data module, wherein the first target data module is one of the first data modules matched with the preset output control signal, and the second target data module is one of the second data modules matched with the preset output control signal.

[0009] The aforementioned bit logic arithmetic unit has at least the following beneficial effects: Since the flip-flops and logic gates are respectively equipped with multiple first data modules and multiple second data modules, and each first data module includes a pair of complementary first magnetic tunnel junctions for writing and storing one bit of first operational data, and each second data module includes a pair of complementary second magnetic tunnel junctions for writing and storing one bit of second operational data, any bit of data can be stored accordingly in the data modules of the flip-flops and logic gates. This achieves fully non-volatile data storage, improves data storage stability, and, under the overall management of the control module, can select the first target data module to output first operational data to the logic gate and read second operational data from the selected second target data module according to the preset output control signal. Since the preset output control signal can be extended, corresponding bit data can be read for different first and second target data modules, thereby realizing multi-bit extended logic operations on the logic gates, providing complete multi-bit logic operation functions, which is beneficial for improving logic operation efficiency and optimizing device integration, thus filling the technical gaps in related methods.

[0010] According to some embodiments of the present invention, the trigger further includes a first write module and a first output module. The plurality of first data modules are connected between the first write module and the first output module. The output terminal of the first output module is connected to the logic gate. The first write module is used to write multiple bits of the first operation data to the plurality of first data modules respectively. The first output module is used to output multiple bits of the first operation data to the logic gate, thereby ensuring that the corresponding bits of the first operation data can be accurately and reliably written to each first data module, and that each first operation data stored in each first data module can be reliably output to the logic gate.

[0011] According to some embodiments of the present invention, the logic gate further includes a second writing module and a logic calculation module. The plurality of second data modules are connected between the second writing module and the logic calculation module. The input terminal of the logic calculation module is connected to the output terminal of the first output module. The second writing module is used to write multiple bits of second operation data to the plurality of second data modules respectively. The logic calculation module is used to calculate the logic operation result based on the multiple bits of first operation data and the multiple bits of second operation data, thereby providing complete multi-bit logic operation function, which is beneficial to improving logic operation efficiency and optimizing device integration.

[0012] According to some embodiments of the present invention, the control module is further configured to control the first writing module to write the first operation data to the first target data module according to a preset write control signal, and to control the second writing module to write the second operation data to the second target data module. The preset write control signal can reliably realize the data writing of the first target data module and the data writing of the second target data module, so as to further utilize the data written by each first target data module and each second target data module for logical operations in subsequent steps.

[0013] According to some embodiments of the present invention, the logic gate further includes a second output module, the input terminal of the second output module is connected to the output terminal of the logic calculation module, the second output module is used to obtain the logic operation result from the logic calculation module and output the logic operation result, the logic operation result can be stably output through the second output module, so as to facilitate further related processing of the logic operation result.

[0014] According to some embodiments of the present invention, the control module includes a plurality of output control interfaces, each of which is used to connect a pair of state-complementary first magnetic tunnel junctions and a pair of state-complementary second magnetic tunnel junctions, so as to control the pair of state-complementary first magnetic tunnel junctions and the pair of state-complementary second magnetic tunnel junctions to output relevant bit data through each output control interface, thereby realizing the function of bitwise logic operation.

[0015] According to some embodiments of the present invention, each of the first magnetic tunnel junction groups includes a first magnetic tunnel junction and a first conducting element connected in series, and each of the second magnetic tunnel junction groups includes a second magnetic tunnel junction and a second conducting element connected in series. One of the output control interfaces of the control module is respectively connected to the first conducting element and the second conducting element to enable selection of each magnetic tunnel junction through the first conducting element and the second conducting element.

[0016] According to some embodiments of the present invention, the control module includes a decoder and a peripheral control circuit. The output terminal of the peripheral control circuit is connected to the decoder. The peripheral control circuit is used to provide a preset control signal to the enable signal terminal of the decoder, so that the decoder can control the magnetic tunnel junctions in each data module accordingly according to the preset control signal.

[0017] According to some embodiments of the present invention, both the first conducting element and the second conducting element are MOS transistors, which have good on and off functions and can work with each magnetic tunnel junction to achieve stable and reliable data writing control, storage control and output control functions.

[0018] Secondly, embodiments of the present invention provide an electronic device including a bit logic arithmetic unit as described in the first aspect, which is capable of achieving fully non-volatile data storage and providing multi-bit logic operation functionality.

[0019] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description and the drawings. Attached Figure Description

[0020] The accompanying drawings are provided to further understand the technical methods of this application and form part of the specification. They are used together with the embodiments of this application to explain the technical methods of this application and do not constitute a limitation on the technical methods of this application.

[0021] Figure 1 This is a schematic diagram of the structure of a bit logic arithmetic unit provided in one embodiment of this application;

[0022] Figure 2 This is a schematic diagram of the structure of a magnetic tunnel junction provided in one embodiment of this application;

[0023] Figure 3(a) is a circuit schematic diagram of a logic calculation module provided in an embodiment of this application;

[0024] Figure 3(b) is a circuit schematic diagram of a logic calculation module provided in another embodiment of this application;

[0025] Figure 4 This is a circuit schematic diagram of a bit logic arithmetic unit provided in one embodiment of this application;

[0026] Figure 5(a) is a circuit schematic diagram of a first write module provided in an embodiment of this application;

[0027] Figure 5(b) is a circuit schematic diagram of the second write module provided in one embodiment of this application;

[0028] Figure 6 This is a simulation waveform diagram of a bit logic arithmetic unit provided in one embodiment of this application;

[0029] Figure 7 This is a schematic diagram of an electronic device provided in one embodiment of this application. Detailed Implementation

[0030] To make the objectives, technical methods, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0031] It should be noted that although the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than that shown in the flowchart.

[0032] This application provides a bit logic arithmetic unit and an electronic device. One embodiment of the bit logic arithmetic unit includes: a flip-flop, comprising a plurality of first data modules, each first data module including a pair of complementary first magnetic tunnel junctions, the first data modules being used to write and store one bit of first operational data; a logic gate, connected to the flip-flop, comprising a plurality of second data modules, each second data module including a pair of complementary second magnetic tunnel junctions, the second data modules being used to write and store one bit of second operational data; a logic gate, used to obtain a logical operation result based on the multiple bits of first operational data provided by the flip-flop and the multiple bits of second operational data output by the multiple second data modules; and a control module, connected to both the flip-flop and the logic gate, used to select and control a first target data module to output one bit of first operational data to the logic gate according to a preset output control signal, and to read one bit of second operational data from the selected second target data module, wherein the first target data module is one of the first data modules matched with the preset output control signal, and the second target data module is one of the second data modules matched with the preset output control signal. In this embodiment, since the flip-flops and logic gates are respectively equipped with multiple first data modules and multiple second data modules, and each first data module includes a pair of complementary first magnetic tunnel junctions for writing and storing one bit of first operational data, and each second data module includes a pair of complementary second magnetic tunnel junctions for writing and storing one bit of second operational data, any bit of data can be stored in the data modules of the flip-flops and logic gates accordingly. This achieves complete non-volatility of data storage, improves the stability of data storage, and under the overall management of the control module, the first target data module can be selected to output first operational data to the logic gate according to the preset output control signal, and the second operational data can be read from the selected second target data module. Since the preset output control signal can be extended, corresponding bit data can be read for different first target data modules and second target data modules, thereby realizing multi-bit extended logic operations on the logic gate, providing complete multi-bit logic operation functions, which is beneficial to improving logic operation efficiency and optimizing device integration, thus filling the technical gaps in related methods.

[0033] like Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of a bit logic arithmetic unit provided in one embodiment of this application.

[0034] Reference Figure 1 This bit logic unit includes:

[0035] The trigger includes multiple first data modules, each first data module including a pair of state-complementary first magnetic tunnel junctions, and the first data module is used to write and store one bit of first operational data.

[0036] A logic gate, connected to a flip-flop, includes multiple second data modules. Each second data module includes a pair of complementary second magnetic tunnel junctions. The second data module is used to write and store one bit of second operation data.

[0037] Logic gates are used to obtain the result of a logic operation based on multiple bits of first operation data provided by flip-flops and multiple bits of second operation data output by multiple second data modules.

[0038] The control module is connected to the flip-flop and the logic gate respectively. It is used to select and control the first target data module to output one bit of first operation data to the logic gate according to the preset output control signal, and to read one bit of second operation data from the selected second target data module. The first target data module is one of the first data modules matched with the preset output control signal, and the second target data module is one of the second data modules matched with the preset output control signal.

[0039] In one embodiment, since the flip-flops and logic gates are respectively provided with multiple first data modules and multiple second data modules, and each first data module includes a pair of complementary first magnetic tunnel junctions for writing and storing one bit of first operational data, and each second data module includes a pair of complementary second magnetic tunnel junctions for writing and storing one bit of second operational data, any bit of data can be stored in the data modules of the flip-flops and logic gates accordingly. This achieves complete non-volatility of data storage, improves the stability of data storage, and under the overall management of the control module, the first target data module can be selected to output first operational data to the logic gate according to the preset output control signal, and the second operational data can be read from the selected second target data module. Since the preset output control signal can be extended, corresponding bit data can be read for different first target data modules and second target data modules, thereby realizing multi-bit extended logic operations on the logic gate, providing complete multi-bit logic operation functions, which is beneficial to improving logic operation efficiency and optimizing device integration, thus filling the technical gaps in related methods.

[0040] In one embodiment, the number of first data modules and second data modules can be the same, and the number of first target data modules and second target data modules can also be the same. That is, the number of bits of binary data output by the flip-flop and the number of bits of binary data output by the logic gate can be the same. The first target data module includes a pair of complementary first magnetic tunnel junctions for matching a preset output control signal of the control module. When the preset output control signal changes, the changed preset output control signal corresponds to another first target data module, thereby enabling the selection of another binary data. Therefore, it is possible to select and output all bits of the first operational data for multi-bit logic operations. Since the working principle of the second target data module is similar to that of the first target data module, it will not be described in detail here.

[0041] In one embodiment, the control module is further configured to control the first writing module to write the first operation data to the first target data module according to a preset write control signal, and to control the second writing module to write the second operation data to the second target data module. The preset write control signal can reliably realize the data writing of the first target data module and the data writing of the second target data module, so as to further utilize the data written by each first target data module and each second target data module for logical operations.

[0042] In one embodiment, both the first and second magnetic tunnel junction groups include a pair of magnetic tunnel junctions. Their specific form and configuration parameters are not limited and can be selected and set according to the actual application scenario. For example, refer to... Figure 2 It can be seen that each magnetic tunnel junction includes a free layer, an insulating layer, and a fixed layer. Depending on the form of the write current, there are two resistance states: high and low, which correspond to parallel and antiparallel states, respectively, to the data "1" and "0". If a pair of magnetic tunnel junctions are complementary, it means that the corresponding data are opposite (i.e., "1" to "0", or "0" to "1"). Based on this, other specific forms of magnetic tunnel junctions can be set according to the actual application.

[0043] In one embodiment, the specific number of bits of data corresponding to the multi-bit bitwise logical operation is not limited. For example, it can be 4 bits, 8 bits, or 16 bits. For data of different bits, corresponding control modules can be used to perform multi-bit expansion. The principle is similar. To avoid redundancy, the principle will be explained mainly with 8-bit data in the following embodiments, but it should not be construed as a limitation of this embodiment.

[0044] In one embodiment, the preset output control signal and the preset write control signal can be configured according to the specific scenario, which is not limited here. The principle will be explained in detail in subsequent embodiments, and will not be repeated here.

[0045] Reference Figure 1 The trigger also includes a first write module and a first output module. Multiple first data modules are connected between the first write module and the first output module. The output terminal of the first output module is connected to a logic gate. The first write module is used to write multiple bits of first operation data to the multiple first data modules respectively. The first output module is used to output multiple bits of first operation data to the logic gate, thereby ensuring that the corresponding bits of first operation data can be accurately and reliably written to each first data module, and that each first operation data stored in each first data module can be reliably output to the logic gate.

[0046] In one embodiment, the specific forms of the first writing module and the first output module can be set according to the specific application scenario, and are not limited here.

[0047] Reference Figure 1 The logic gate also includes a second write module and a logic calculation module. Multiple second data modules are connected between the second write module and the logic calculation module. The input terminal of the logic calculation module is connected to the output terminal of the first output module. The second write module is used to write multiple bits of second operation data to the multiple second data modules respectively. The logic calculation module is used to calculate the logic operation result based on the multiple bits of first operation data and the multiple bits of second operation data, thereby providing complete multi-bit logic operation function, which is beneficial to improving logic operation efficiency and optimizing device integration.

[0048] In one embodiment, the specific forms of the second writing module and the logic calculation module can be set according to the specific application scenario, and are not limited here. For example, referring to FIG3(a), a specific circuit diagram of the logic calculation module is shown. Under this XOR gate circuit, the logic calculation module is used to implement the XOR operation. Referring to FIG3(a), another specific circuit diagram of the logic calculation module is shown. Under this OR gate circuit, the logic calculation module is used to implement the OR operation.

[0049] Reference Figure 1 The logic gate also includes a second output module. The input of the second output module is connected to the output of the logic calculation module. The second output module is used to obtain the logic operation result from the logic calculation module and output the logic operation result. The logic operation result can be stably output through the second output module so that the logic operation result can be further processed.

[0050] In one embodiment, the first output module and the second output module can be, but are not limited to, various types of amplifier circuits. The amplifier circuit amplifies and outputs the acquired data parameters, which is beneficial for outputting the data parameters more stably. For example, the first output module and the second output module can both be sensor amplifier circuits or other types of amplifier circuits, etc., which are not limited here.

[0051] In one embodiment, the control module includes a decoder and a peripheral control circuit. The output of the peripheral control circuit is connected to the decoder. The peripheral control circuit is used to provide a preset control signal to the enable signal terminal of the decoder, so that the decoder can control the magnetic tunnel junctions in each data module accordingly according to the preset control signal. Since the peripheral control circuit is well known to those skilled in the art, it will not be described in detail here.

[0052] Reference Figure 4 The control module includes a decoder, which has multiple output control interfaces. Each output control interface is used to connect to a pair of complementary first magnetic tunnel junctions and a pair of complementary second magnetic tunnel junctions, so that the output control interfaces can control the pair of complementary first magnetic tunnel junctions and the pair of complementary second magnetic tunnel junctions to output relevant bit data, thereby realizing the function of bitwise logic operation; for example, Figure 4 The decoder Y0 interface is an output control interface used to select a pair of complementary first magnetic tunnel junctions, namely N28-M16 and N36-M24, and to select a pair of complementary second magnetic tunnel junctions, namely N7-M0 and N15-M8. This circuit design can be fixed, and the decoder can only have one interface enabled at a time. Therefore, the decoder output will not simultaneously select multiple other first magnetic tunnel junctions or / and second magnetic tunnel junctions, which can ensure that the corresponding magnetic tunnel junctions are selected bit by bit for logical operations.

[0053] like Figure 4 As shown, each first magnetic tunnel junction group includes a first magnetic tunnel junction and a first conducting element connected in series, and each second magnetic tunnel junction group includes a second magnetic tunnel junction and a second conducting element connected in series. An output control interface of the control module is connected to the first conducting element and the second conducting element respectively, so as to realize the selection of each magnetic tunnel junction through the first conducting element and the second conducting element.

[0054] In one embodiment, since the conducting element has a good turn-on or turn-off function, a stable and reliable magnetic tunnel junction group can be obtained by combining the first magnetic tunnel junction and the first conducting element (the second magnetic tunnel junction and the second conducting element), which is more conducive to the control module to select the corresponding magnetic tunnel junction group; wherein, the first conducting element and the second conducting element are MOS transistors, which have good turn-on and turn-off functions and can work with the magnetic tunnel junction to realize stable and reliable data writing control, storage control and output control functions.

[0055] To better illustrate the working principle of the above embodiments, several specific examples are given below for detailed explanation.

[0056] Example 1:

[0057] Reference Figure 4 Using 8-bit binary data as an example, this bit logic unit consists of 8-bit non-volatile logic gates and 8-bit non-volatile flip-flops. The 8-bit non-volatile flip-flops consist of a first output module, a first write module, and eight first data modules. Each first data module includes a pair of complementary first magnetic tunnel junctions, and each first magnetic tunnel junction includes one magnetic tunnel junction. The 8-bit non-volatile flip-flops are used to store and output a set of 8-bit binary data. The 8-bit non-volatile logic gate consists of a second output module, a second write module, eight second data modules, and a MOS logic module for logic calculation. Each second data module includes a pair of complementary second magnetic tunnel junctions, and each second magnetic tunnel junction includes one magnetic tunnel junction. The 8-bit non-volatile logic gate is used to store and output a set of 8-bit binary data. Figure 4 The left side shows the circuit of an 8-bit non-volatile logic gate, and the right side shows the circuit of an 8-bit non-volatile flip-flop. The two circuits together have a total of 16 pairs of magnetic tunnel junctions, which are controlled by a 38 decoder.

[0058] exist Figure 4 In the circuit of the non-volatile trigger, P3, P4 and P5 (all PMOS transistors), N24, N25 and N44 (all NMOS transistors), and capacitors C3 and C4 constitute the first output module, which is used to output a set of 8-bit data stored for bit operations. NMOS transistors N26 and N27 are used for read-write isolation to prevent read-write interference. NMOS transistors N28-N35 and magnetic tunnel junctions M16-M23 together form one group of NMOS transistors and magnetic tunnel junctions, i.e., eight first magnetic tunnel junction groups. NMOS transistors N36-N43 and magnetic tunnel junctions M24-M31 together form another group of NMOS transistors and magnetic tunnel junctions, i.e., another eight first magnetic tunnel junction groups. These two groups of NMOS transistors and magnetic tunnel junctions together form eight pairs of complementary first magnetic tunnel junction groups. The NMOS transistors are selected by a 38 decoder. At the same time, one first magnetic tunnel junction in each group is selected and connected to the circuit. The states of the two first magnetic tunnel junctions selected and connected to the circuit are complementary, and they jointly store one bit of binary data, thus enabling the storage and output of 8 bits of binary data.

[0059] exist Figure 4In the non-volatile logic gate circuit, P0, P1, and P2 (all PMOS transistors), along with N0, N1, and N23 (all NMOS transistors) and capacitors C1 and C2, constitute the second output module. This module is used to output a stored set of 8-bit data for bit operations. NMOS transistors N2 and N3 are used for read / write isolation to prevent read / write interference. NMOS transistors N7 to N14, together with magnetic tunnel junctions M0 to M7, form a combination of NMOS transistors and magnetic tunnel junctions (for redundancy avoidance). Figure 4 (Not all NMOS transistors and magnetic tunnel junction combinations are shown in the text; they are replaced with "...", the same below.) This forms eight second magnetic tunnel junction groups. NMOS transistors N15-N22 and magnetic tunnel junctions M8-M15 form another set of NMOS transistor and magnetic tunnel junction combinations, forming another eight second magnetic tunnel junction groups. These two sets of NMOS transistor and magnetic tunnel junction combinations together form eight pairs of complementary second magnetic tunnel junction groups. A 38 decoder selects the NMOS transistors, and at the same time, one second magnetic tunnel junction from each group is selected and connected to the circuit. The states of the two selected second magnetic tunnel junctions are complementary, and they jointly store one bit of binary data. N4, N5, and N6 form a MOS logic module, used to perform corresponding logical operations on the data stored in this part and the data output by the non-volatile flip-flops, enabling the second output module to output the corresponding logical result value.

[0060] The circuit of a first writing module is shown in Figure 5(a), and the circuit of a second writing module is shown in Figure 5(b). Referring to Figure 5(a), the first write module consists of three PMOS transistors P9, P10, and P11 and three NMOS transistors N48, N49, and N50. The connection points "E", "F", and "G" of this part of the circuit are respectively connected to the connection points "E", "F", and "G" of the non-volatile flip-flop circuit in Figure 3, realizing the writing of data to the corresponding first magnetic tunnel junction. Due to the characteristics of the write circuit structure, in order to realize its function, the connection method of the first magnetic tunnel junction and NMOS in the 8-bit non-volatile flip-flop circuit can also be different, which will not be elaborated here. Referring to Figure 5(b), the second write module consists of three PMOS transistors P6, P7, and P8 and three NMOS transistors N45, N46, and N47. The connection points "B", "C", and "D" of this part of the circuit are respectively connected to the connection points "B", "C", and "D" of the non-volatile logic gate circuit in Figure 3, realizing the writing of data to the corresponding second magnetic tunnel junction.

[0061] The MOS logic module in Figure 3 enables it to perform logical operations. Changing the structure of the MOS logic module can enable the circuit to perform different logical operations.

[0062] It can be seen that by combining multi-bit non-volatile flip-flops and multi-bit non-volatile logic gates, all data is stored in the corresponding magnetic tunnel junction, which has the characteristics of being fully non-volatile; using 6 transistors as part of the write circuit reduces the number of transistors and reduces the area overhead of the entire device.

[0063] Example 2:

[0064] Reference Figure 4 The operation of this arithmetic unit is divided into two stages: the input stage and the output stage. The input stage involves storing the data to be calculated into the magnetic tunnel junction of the data module. The output stage involves the circuit reading the data from the magnetic tunnel junction of the data module, performing logical operations, and outputting the result.

[0065] During the input phase, the enable control signals A0-A2 of the 38 decoder are first set to "000". At this time, the outputs Y0-Y7 of the 38 decoder are "10000000". One pair of magnetic tunnel junctions in each of the 8-bit non-volatile logic gates and 8-bit non-volatile flip-flops are selected, that is, one pair of first magnetic tunnel junctions in one pair of first magnetic tunnel junction groups and one pair of second magnetic tunnel junctions in one pair of second magnetic tunnel junction groups are selected. Each pair of magnetic tunnel junctions is fixed and their states are complementary, and they are used to store one bit of binary data. The write control signals V0-V7 are used to write these two pairs of magnetic tunnel junctions. Each pair of magnetic tunnel junctions stores one bit of binary data. After the writing is completed, the 8-bit non-volatile logic gates and 8-bit non-volatile flip-flops each write one bit of binary data. In this way, different values ​​can be output by the 38 decoder to select different pairs of magnetic tunnel junctions, thereby storing all 8-bit binary data in the arithmetic unit and completing the data writing operation.

[0066] In the output stage, the control signals A0-A2 of the 38 decoder are again set to "000". At this time, the 38 decoder outputs Y0-Y7 as "10000000". One pair of magnetic tunnel junctions in each of the 8-bit non-volatile logic gates and 8-bit non-volatile flip-flops is selected. The non-volatile flip-flops read one bit of stored binary data and input it into the MOS logic module of the non-volatile logic gate. A logical operation is performed between this input and the one bit of binary data stored in the non-volatile logic gate. Finally, the result is output through the OUT port of the non-volatile logic gate, completing the logical operation between the two binary data. Similarly, by outputting different values ​​from the 38 decoder, different pairs of magnetic tunnel junctions are selected, and bitwise logical operations are performed on all 8 sets of binary data. Finally, the 8-bit non-volatile logic gate outputs the result of the 8-bit bitwise logical operation sequentially, completing the output stage.

[0067] The specific working waveform diagram of the 8-bit AND logic unit in Figure 3 is as follows: Figure 6As shown, the 8-bit binary data written by the 8-bit non-volatile logic gate is "11111111", and the 8-bit binary data written by the 8-bit non-volatile flip-flop is "10110010". The two sets of binary numbers are synchronously selected bit-by-bit by the 38 decoder control signals A0-A2. The non-volatile logic gate performs bit-by-bit logic operations. After 8 CLK cycles, the result of the bitwise AND operation on the two sets of data is "10110010", thus realizing the bitwise AND operation function.

[0068] It can be seen that using a 38 decoder to extend non-volatile logic gates by multiple bits enables them to store data with high integration and perform multi-bit logic operations; combining multi-bit non-volatile flip-flops and multi-bit non-volatile logic gates in the design allows all data to be stored in the magnetic tunnel junction, exhibiting the characteristic of being fully non-volatile.

[0069] In addition, such as Figure 7 As shown, one embodiment of this application also discloses an electronic device, including: a bit logic arithmetic unit as described in the previous embodiments.

[0070] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0071] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

[0072] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

[0073] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A bit logic arithmetic unit, characterized in that, include: The trigger includes multiple first data modules, each first data module including a pair of state-complementary first magnetic tunnel junctions, and the first data module is used to write and store one bit of first operational data. A logic gate, connected to the flip-flop, includes multiple second data modules. Each second data module includes a pair of complementary second magnetic tunnel junctions. The second data module is used to write and store one bit of second operational data. The logic gate is used to obtain a logic operation result based on the multiple bits of the first operation data provided by the flip-flop and the multiple bits of the second operation data output by the multiple second data modules; A control module, connected to the trigger and the logic gate respectively, is used to select and control the first target data module to output one bit of the first operation data to the logic gate according to the preset output control signal, and to read one bit of the second operation data from the selected second target data module, wherein the first target data module is one of the first data modules matched with the preset output control signal, and the second target data module is one of the second data modules matched with the preset output control signal; The control module includes multiple output control interfaces, each of which is used to connect a pair of state-complementary first magnetic tunnel junctions and a pair of state-complementary second magnetic tunnel junctions. Each of the first magnetic tunnel junction groups includes a first magnetic tunnel junction and a first conducting element connected in series, and each of the second magnetic tunnel junction groups includes a second magnetic tunnel junction and a second conducting element connected in series, and one of the output control interfaces of the control module is respectively connected to the first conducting element and the second conducting element.

2. The bit logic arithmetic unit according to claim 1, characterized in that, The trigger further includes a first write module and a first output module. The plurality of first data modules are connected between the first write module and the first output module. The output terminal of the first output module is connected to the logic gate. The first write module is used to write multiple bits of the first operation data to the plurality of first data modules respectively. The first output module is used to output multiple bits of the first operation data to the logic gate.

3. A bit logic arithmetic unit according to claim 2, characterized in that, The logic gate further includes a second writing module and a logic calculation module. The plurality of second data modules are connected between the second writing module and the logic calculation module. The input terminal of the logic calculation module is connected to the output terminal of the first output module. The second writing module is used to write multiple bits of second operation data to the plurality of second data modules respectively. The logic calculation module is used to calculate the logic operation result based on the multiple bits of first operation data and the multiple bits of second operation data.

4. A bit logic arithmetic unit according to claim 3, characterized in that, The control module is further configured to control the first writing module to write the first computational data to the first target data module according to a preset write control signal, and to control the second writing module to write the second computational data to the second target data module.

5. A bit logic arithmetic unit according to claim 3, characterized in that, The logic gate further includes a second output module, the input of which is connected to the output of the logic calculation module. The second output module is used to obtain the logic operation result from the logic calculation module and output the logic operation result.

6. A bit logic arithmetic unit according to any one of claims 1 to 5, characterized in that, The control module includes a decoder and a peripheral control circuit. The output terminal of the peripheral control circuit is connected to the decoder, and the peripheral control circuit is used to provide a preset control signal to the enable signal terminal of the decoder.

7. A bit logic arithmetic unit according to claim 1, characterized in that, Both the first conducting element and the second conducting element are MOSFETs.

8. An electronic device, characterized in that, It includes a bit logic arithmetic unit as described in any one of claims 1 to 7.

Images