Memory device with leakage current verification circuit for minimizing leakage current
By introducing a leakage current verification circuit into the memory device, high leakage current cells are detected and repaired or the negative voltage of unselected WL is adjusted, thus solving the leakage current problem caused by the reduction of die size, improving write efficiency and reliability, and reducing power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WINBOND ELECTRONICS CORP
- Filing Date
- 2022-04-12
- Publication Date
- 2026-06-02
AI Technical Summary
In existing technologies, as die size decreases, leakage current problems worsen, leading to poor write efficiency, and there is a lack of effective solutions to minimize leakage current, especially during write operations and verification processes.
A leakage current verification circuit is used to perform an erase operation on the memory cell column through the controller configuration, set leakage current threshold conditions, and compare them through the leakage current verification circuit. Cells with leakage current exceeding the threshold are detected and repaired, or the negative voltage of the unselected WL is adjusted before the write operation until the leakage current passes the threshold.
It effectively reduces leakage current, improves the write efficiency and reliability of memory devices, reduces power consumption, and adapts to the effects of factors such as temperature changes.
Smart Images
Figure CN115482867B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to a memory device having a leakage current verification circuit for minimizing leakage current. Background Technology
[0002] To obtain the binary contents of a cell, a read operation can be performed to determine the cell's state, such as write or erase. This is accomplished by applying a reference threshold voltage (e.g., VTref) to the gate of a transistor (e.g., a MOSFET). If the gate of the cell's transistor conducts current, the cell can be considered to be in an erase state. Conversely, if the gate of the cell's transistor does not conduct current, the cell can be considered to be in a write state. A write operation involves injecting electrons into the transistor's gate, causing an increase in the threshold voltage. If a cell has been written to, it may be necessary to maintain a sufficient reference threshold voltage level. An erase operation may involve retrieving the injected electrons from the transistor's gate, causing a decrease in the reference threshold voltage.
[0003] During an erase operation, as the entire block is erased, the change in threshold voltage can cause some cells to have a low threshold voltage that would lead to leakage current.
[0004] The leakage current problem worsens as die size decreases. Reduced die size subsequently leads to increased program current, resulting in poor write efficiency for memory devices. Currently, efforts are focused on addressing the leakage current issue during post-write and verification processes, specifically for read operations but not write operations. However, a reliable solution to minimize leakage current exists for both write operations. Summary of the Invention
[0005] Therefore, this disclosure relates to a memory device having a leakage current verification circuit for minimizing leakage current.
[0006] In one aspect, this disclosure relates to a memory device comprising, but not limited to: a memory array having a group of memory cells comprising M memory cells (WLs) and N memory blocks (BLs), where M and N are integers greater than 1; a leakage current verification circuit for verifying leakage current of the memory array; and a controller coupled to the memory array and the leakage current verification circuit. The controller is configured at least to: perform an erase operation on a first column of memory cells, the first column of memory cells belonging to the group of memory cells and connected to a first WL among the M WLs; set verification conditions including a leakage current threshold during the leakage current verification operation; perform a leakage current verification operation on the first column of memory cells connected to the first WL among the M WLs by comparing the leakage current of cells in the first column of memory cells with the leakage current threshold via the leakage current verification circuit; detect a fault in the first column of memory cells via the leakage current verification circuit and respond to a cell in the first column of memory cells having a leakage current higher than the leakage current threshold; and perform a post-write operation to repair the fault in the first column of memory cells.
[0007] In another aspect, this disclosure relates to a memory device comprising, but not limited to: a memory array having a group of memory cells comprising M WLs and N BLs, where M and N are integers greater than 1; a leakage current verification circuit for verifying leakage current of the memory array; and a controller coupled to the memory array and the leakage current verification circuit. The controller is configured at least to: initiate a write operation for a first column of memory cells, the first column of memory cells belonging to the group of memory cells and connected to a first WL among the M WLs; set verification conditions including a leakage current threshold during the leakage current verification operation; perform the leakage current verification operation for the first column of memory cells via the leakage current verification circuit by applying a negative voltage scan to each of the first remaining M-1 unselected WLs among the M WLs until a first negative voltage is found such that the first column of memory cells has passed the leakage current threshold; and apply a write operation to the first column of memory cells by applying the first negative voltage to each of the first remaining M-1 unselected WLs among the M WLs and applying a positive BL voltage to the N BLs.
[0008] To facilitate understanding of the foregoing features and advantages of this disclosure, exemplary embodiments with accompanying drawings are described in detail below. It should be understood that the foregoing general description and the following detailed description are exemplary and intended to provide further explanation of the disclosure as claimed.
[0009] However, it should be understood that this overview may not contain all aspects and embodiments of this disclosure, and therefore is not intended to be limiting or restrictive in any way. Furthermore, this disclosure will include improvements and modifications that will be apparent to those skilled in the art. Attached Figure Description
[0010] Figure 1 and Figure 2 Block diagrams of memory devices having leakage current verification circuitry for minimizing leakage current are shown respectively according to a first exemplary embodiment and a second exemplary embodiment of the present disclosure.
[0011] Figure 3 and Figure 4 Flowcharts of methods for minimizing leakage current according to a first exemplary embodiment and a second exemplary embodiment of the present disclosure are shown respectively;
[0012] Figure 5 A negative voltage scan is shown according to an exemplary embodiment of the present disclosure;
[0013] Figure 6 A leakage current verification circuit according to an exemplary embodiment of the present disclosure is shown;
[0014] Figure 7 A leakage current verification circuit for a column of memory cells according to an exemplary embodiment of the present disclosure is shown.
[0015] Figure 8 A leakage current verification circuit connected to a memory cell is shown according to an exemplary embodiment of the present disclosure;
[0016] Figure 9 A word line voltage regulator for a post-write verification operation of a first exemplary embodiment is shown according to an exemplary embodiment of the present disclosure;
[0017] Figure 10 and Figure 11 Word line voltage regulators for write operations of a first exemplary embodiment and a second exemplary embodiment according to exemplary embodiments of the present disclosure are shown respectively.
[0018] Explanation of icon numbers
[0019] 100, 200: Memory devices;
[0020] 101, 201: Memory array;
[0021] 102, 202: Controller;
[0022] 103, 203, 600, 801: Leakage current verification circuit;
[0023] 104, 204, 900, 1000, 1100: WL voltage regulation circuit;
[0024] 600a, 600b, 600c: Leakage current verification circuit for a single unit;
[0025] 601: Sensing amplifier circuit;
[0026] 701: OR gate;
[0027] 802: Y decoder;
[0028] A1: First buffer amplifier;
[0029] A3: Voltage follower amplifier;
[0030] A4: Comparator amplifier;
[0031] C1: Constant reference current source;
[0032] N1, N2: Channel bandwidth;
[0033] Q1, Q2, Q3: Transistors;
[0034] Q4: NMOS transistor;
[0035] R1: First resistor;
[0036] R2: Second resistor;
[0037] R3: Third resistor;
[0038] S101, S102, S103, S104, S201, S202, S203, S204, S301, S302, S303, S304, S305, S401, S402, S403, S404, S405, S406, S407, S501, S502, S503: Steps;
[0039] Vth: Threshold voltage;
[0040] WL <0> WL <l>、WL 、WL <m>: Word line. Detailed Implementation
[0041] This disclosure provides a memory device having a leakage current verification circuit for minimizing leakage current. This disclosure provides a technique that not only reduces leakage current during write operations by utilizing a negative voltage on an unselected word line WL, but also provides a target for the leakage current level during write operations, given the current lack of a verification process for leakage current levels under write conditions. One objective of this disclosure is to provide a leakage current verification circuit that verifies the leakage current level and also ensures that the leakage current level is below an acceptable threshold.
[0042] This disclosure provides two exemplary embodiments of a leakage current verification circuit for minimizing leakage current. A first exemplary embodiment will involve performing a post-write verification process not only for read operations but also for write operations. The post-write process may also be included as part of an erase operation.
[0043] The second exemplary embodiment will involve adjusting a negative voltage for an unselected WL, and the level of the applied negative voltage will depend on the leakage current measured during the write operation. The techniques of the second exemplary embodiment during the write operation will be implemented immediately prior to the actual writing to a cell or group of cells, and will be repeated again for writing to the next data address.
[0044] The process of the first exemplary embodiment can be performed during both a post-verification operation and a post-write operation. The process may involve setting a post-verification target for a negative voltage level for an unselected WL during a write operation. If a cell's leakage current is found to be higher than a leakage current threshold, the previously described post-write operation can be repeated until the cell's leakage current is lower than the leakage current threshold. The process of the first exemplary embodiment can be fully performed during an erase operation, and therefore will not affect the timing of the write operation.
[0045] The process of the second exemplary embodiment involves verifying the column leakage current of the cell prior to a write operation. Dynamic adjustment of the negative voltage level of the unselected WL can be performed until the column leakage current of the cell exceeds a leakage current threshold. Dynamic adjustment of the negative voltage level of the unselected WL may involve applying an optimal negative voltage level to a voltage scan of the unselected WL during the write operation. It should be noted that if the negative voltage level is too low, it can cause more drain interference on unselected cells sharing the same BL.
[0046] Regarding the first exemplary embodiment, in Figure 1 The diagram shows a block diagram of a memory device with leakage current verification circuitry for minimizing leakage current. See also... Figure 1 The memory device 100 includes, but is not limited to, a memory array 101 having memory cell groups (the memory cell groups include M WLs and N BLs when M and N are integers greater than 1), a leakage current verification circuit 103 for verifying the leakage current of the memory array, and a controller 102 coupled to the memory array 101 and the leakage current verification circuit 103. The controller 102 can be configured to perform an erase operation (S101) on a first column of memory cells connected to a first WL of the M WLs. Next, the controller can be configured to set verification conditions including a leakage current threshold during the leakage current verification operation (S102). Additionally, the controller can perform a leakage current verification operation on the first column of memory cells via the leakage current verification circuit 103 by comparing the leakage current of cells in the first column of memory cells connected to the first WL with a leakage current threshold (S103). Subsequently, the controller can detect the success or failure of the first column of memory cells via the leakage current verification circuit 103 in response to any cell in the first column of memory cells having a leakage current higher than the leakage current threshold. Furthermore, the controller can be configured to perform a post-write operation to repair a fault in the first column of memory cells (S104). Depending on the situation, the memory array 101 may include a WL voltage regulation circuit 104 connected to the leakage current verification circuit 103 for adjusting the negative voltage of an unselected WL in the event of voltage fluctuations due to temperature changes or other reasons.
[0047] Regarding the second exemplary embodiment, in Figure 2 The diagram shows a block diagram of a memory device with leakage current verification circuitry for minimizing leakage current. See also... Figure 2 The memory device 200 includes, but is not limited to, a memory array 201 having memory cell groups (the memory cell groups contain M WLs and N BLs when M and N are integers greater than 1), a leakage current verification circuit 203 for verifying the leakage current of the memory array, and a controller 202 connected to the memory array 201 and the leakage current verification circuit 203. First, the controller 202 can be configured to initiate a write operation for the first column of memory cells connected to the first WL of the M WLs (S201). The controller can also set verification conditions including a leakage current threshold during the leakage current verification operation. Next, the controller 202 can perform a leakage current verification operation for the first column of the memory cells via the leakage current verification circuit 203 by applying a negative voltage scan to each of the first remaining M-1 unselected WLs of the M WLs (S202) until a first negative voltage is found such that the first column of the memory cells has passed the leakage current threshold (S203). Subsequently, the controller 202 can be configured to perform a write operation on the first column of the memory cell by applying a first negative voltage to each of the first remaining M-1 unselected WLs out of the M WLs and applying a positive BL voltage to the N BLs (S204). Depending on the situation, the memory array 201 may include a WL voltage regulation circuit 204 connected to the leakage current verification circuit 203 for adjusting the negative voltage of the unselected WLs in the event of voltage fluctuations due to temperature changes or other reasons.
[0048] exist Figure 3 The flowchart shows the target for by Figure 1 The memory device 100 uses a first exemplary embodiment to perform a process for minimizing leakage current. In step S301, a block of memory cells is erased, and the first memory device 100 performs an erase operation on a first memory location associated with a first address of the block of memory cells. The first memory location may be, but is not limited to, a column of cells, such that the erase operation can be performed on a column of cells, which may be controlled by the same WL and thus selected by activating the WL. In step S302, the memory device 100 may perform a leakage current verification operation on the first memory location associated with the first address. The leakage current verification operation may be performed on a column of cells, which has been selected for the erase operation and controlled by the same WL (i.e., the selected WL).
[0049] During the leakage current verification operation, the first memory device 100 may implement verification conditions, which include a leakage current threshold, a negative voltage of each of the remaining M-1 unselected WLs (assuming the cell block to be erased is controlled by a total of M WLs), and positive bit line (BL) voltages of N BLs. The leakage current threshold may be, for example, 10 microamps (μA). The negative voltage of each of the remaining M-1 unselected WLs may be, for example, -1 volt (V). The BL voltage may be, for example, 4 volts.
[0050] The first memory device 100 may detect whether a memory cell group has passed a leakage current verification operation via a leakage current verification circuit (e.g., 103) by comparing the leakage current of cells in the memory cell group associated with the first address with a leakage current threshold. In response to each cell in the memory cell group having a leakage current below the leakage current threshold, the memory cell group is considered to have passed the leakage current verification operation, and the process performed for the first exemplary embodiment continues from step S303. In response to any cell in the memory cell group having a leakage current above the leakage current threshold, the memory cell group is considered to have failed the leakage current verification operation, and the process performed for the first exemplary embodiment continues from step S305.
[0051] In step S303, the memory device 100 determines whether the first address is the final address. If the first address is the final address, the process performed for the first exemplary embodiment ends. If the first address is not the final address, it is incremented to the next address in step S304. Step S302 is then repeated for the next address. Primarily, step S302 is repeated until an erase operation is performed on the entire memory cell block controlled by M WLs. In step S305, a post-write operation is performed to repair the memory cell group that failed the leakage current verification operation. The post-write operation is currently well known and primarily involves increasing the threshold voltage of each cell within the memory cell group until the entire memory cell group passes the leakage current verification operation.
[0052] exist Figure 4 The flowchart shows the target for by Figure 2 The memory device 200 uses a second exemplary embodiment to perform a process for minimizing leakage current. In step S401, the memory device 200 receives a first address of a group of memory cells to be written and begins a write operation to be performed at a first memory location corresponding to the first address of the group of memory cells. The first memory location may be, but is not limited to, the first column of cells, such that a write operation can be performed on the first column of cells, which may be controlled by the same WL and thus selected by activating the WL. In step S402, the memory device 200 may perform a leakage current verification operation on the first column of cells corresponding to the first memory location of the first address. The leakage current verification operation may be performed column by column on a column-by-column basis, and the selected column may be controlled by the same WL (i.e., the selected WL).
[0053] During the leakage current verification operation, the first memory device 200 may implement verification conditions, which include a leakage current threshold, a first negative voltage of each of the remaining M-1 unselected WLs (assuming the cell block to be erased is controlled by a total of M WLs), and the positive bit line (BL) voltages of N BLs. If all cells in the first column have a leakage current below the leakage current threshold (i.e., pass the leakage current verification operation), then step S404 is executed next. If at least one cell in the first column has a leakage current greater than the leakage current threshold (i.e., fail the leakage current verification operation), then step S403 is executed next. The initial negative voltage of each of the remaining M-1 unselected WLs can be any negative voltage, such as -1 volt (V). The BL voltage is, for example, 4 volts.
[0054] Assuming the first column described above fails the leakage current verification operation, then in step S403, a negative voltage scan will be performed on the unselected WLs (WLs in the memory cell group to be written, excluding the WL controlling the first column). Later, regarding... Figure 5 The negative voltage scanning is described in further detail in the written description. Assuming that a first negative voltage has been determined during the negative voltage scanning in step S403, causing all cells in the first column to pass the leakage current verification operation, then in step S404, the first negative voltage is selected for the write operation in step S404. In step S405, the first column is written by applying the first negative voltage to the unselected WL. In step S406, the memory device 200 determines whether the first address is the final address. If the first address is the final address, then the process performed for the first exemplary embodiment ends. If the first address is not the final address, then in step S407, the address of the next column is incremented from the first address to the next address. Step S402 is then repeated for the next address. Mainly, step S402 is repeated until a write operation is performed for the entire group of memory cells that have already been written.
[0055] Regarding the concept of negative voltage scanning described above, Figure 5 This is used to illustrate the concept. The purpose of negative voltage scanning is to adjust the negative voltage applied to the unselected WL over time until an adjusted negative voltage is found that will cause the selected column of the memory cell to be controlled by the selected WL through leakage current verification operation. See also Figure 5 The negative voltage level of the unselected WL is reduced (S503) until an adjusted negative voltage is found that causes the column of the memory cell to be controlled by the selected WL, which has already passed the leakage current verification operation (S501). Next, the adjusted negative voltage will be used to write to the selected column of the memory cell. Step S502 is for the unselected WL voltage for writing.
[0056] Figure 6 A (partial) leakage current verification circuit 600 for verifying the leakage current of a single memory cell is shown. The leakage current verification circuit 600 for a single memory cell includes, but is not limited to, a sense amplifier circuit 601 and a current mirror circuit including transistors Q1, Q2, and Q3. The channel width N2 of transistor Q2 may be greater than the channel width N1 of transistor Q1 to reduce the BL bias current during write operations. A previously described positive BL voltage (e.g., 4 volts) may be applied to the source terminal of each of transistors Q1, Q2, and Q3 in the current mirror circuit. The drain terminal of transistor Q2 is connected to a selected column of the memory array (e.g., memory array 101, memory array 201), and the drain terminal of transistor Q1 is connected to a constant reference current source C1 having a reference current of N2 / N1. The reference current is used as a leakage current threshold, and the sense amplifier 601 circuit acts as a comparator to compare the leakage current of the memory cell with the reference current (i.e., the leakage current threshold). The sense amplifier 601 circuit outputs the result of the comparison as a comparison signal to a first buffer amplifier A1. If the leakage current of the memory cell is lower than the reference current, the comparison signal output from the first buffer amplifier A1 indicates a low voltage. If the leakage current of the memory cell is higher than the reference current, the comparison signal output from the first buffer amplifier A1 indicates a high voltage.
[0057] Figure 7 An array of single-cell leakage current verification circuits (e.g., single-cell leakage current verification circuit 600) is shown, the array forming a plurality of single-cell leakage current verification circuits (e.g., single-cell leakage current verification circuit 600a, single-cell leakage current verification circuit 600b, single-cell leakage current verification circuit 600c) to verify the leakage current of columns of memory cells. Each of the plurality of single-cell leakage current verification circuits (e.g., single-cell leakage current verification circuit 600a, single-cell leakage current verification circuit 600b, single-cell leakage current verification circuit 600c) outputs a comparison signal to an OR gate 701 that performs a logical OR operation. If any of the plurality of single-cell leakage current verification circuits (e.g., single-cell leakage current verification circuit 600a, single-cell leakage current verification circuit 600b, single-cell leakage current verification circuit 600c) outputs a high signal, then the OR gate 701 outputs a high signal indicating that the selected column of the memory cell has failed the leakage current verification operation. If all of the multiple single-cell leakage current verification circuits (e.g., single-cell leakage current verification circuit 600a, single-cell leakage current verification circuit 600b, single-cell leakage current verification circuit 600c) output low signals, then OR gate 701 will output a low signal indicating that the selected column of the memory cell has passed the leakage current verification operation.
[0058] exist Figure 8 The diagram illustrates a leakage current verification circuit 801 connected to memory cells in a memory device 800. The leakage current verification circuit 801 can be connected to a memory array (e.g., memory array 101, memory array 201) via a Y decoder 802. The Y decoder 802 is connected to the BL of the memory array (e.g., memory array 101, memory array 201), and therefore the BL of the memory array (e.g., memory array 101, memory array 201) can be selected via the Y decoder 802. Furthermore, each column of the memory array can be composed of different WL (e.g., WL...). <0> WL <l> WL< / l> < / m> 、WL <m>The controller (e.g., controller 102, controller 202) is controlled by a shared SL, and the memory array is coupled to the shared SL. Therefore, the controller (e.g., controller 102, controller 202) will be able to facilitate the leakage current verification circuit 801 to access a specific memory cell location by activating a specific WL for selecting a column and by inputting a selection signal into the Y decoder 802 for selecting a BL.
[0059] This disclosure also provides a WL voltage regulation circuit for an unselected WL for a memory device 100 of a first exemplary embodiment and a memory device 200 of a second exemplary embodiment. It has been observed that leakage current can increase with temperature, and therefore the WL voltage regulation circuit will assist in regulating the negative voltage of the unselected WL. Figure 9 This illustrates a WL voltage regulation circuit 900 for a write-after-verification operation of a memory device 100 according to a first exemplary embodiment. The voltage regulation circuit 900 includes, but is not limited to, a first resistor R1 (Poly resistor), a second resistor R2 (Poly resistor), a third resistor R3 (NLDD resistor), a voltage follower amplifier A3, a comparator amplifier A4, a negative voltage charge pump, and an NMOS transistor Q4. A first terminal of the first resistor R1 is connected to the voltage follower amplifier A3, and a second terminal of the first resistor R1 is connected to the comparator amplifier A4, the NMOS transistor Q4, and the third resistor R3. A first terminal of the second resistor R2 is connected to the negative voltage charge pump, and a second terminal of the second resistor R2 is connected to the NMOS transistor Q4 and the third resistor R3. The third resistor R3 is connected in parallel with the NMOS transistor Q4, and a first terminal and a second terminal of the third resistor R3 are respectively connected to the second terminal of the first resistor R1 and the first terminal of the second resistor R2.
[0060] The second terminal of the second resistor R2 is connected to the column WL of the memory cell, and therefore an regulated negative voltage can be output to an unselected WL during a post-write verification operation. Figure 9 The circuit configuration adjusts the negative voltage at the second terminal of the second resistor R2 according to -(R2 / R1 + Vth) (where Vth is the threshold voltage of the NMOS transistor Q4). As the temperature increases, the threshold voltage Vth of the NMOS transistor Q4 becomes smaller to compensate for the increased temperature, resulting in a less negative voltage at the second terminal of the second resistor R2. Furthermore, as the temperature increases, less current flows through the NMOS transistor Q4, leading to a smaller negative voltage at the second terminal of the second resistor R2. Generally, for post-write verification operations, the absolute value of the negative voltage at the second terminal of the second resistor R2 at a warmer temperature will be less than the absolute value of the negative voltage at a cooler temperature.
[0061] Figure 10 This illustrates a WL voltage regulation circuit 1000 for a write operation of a memory device 100 according to a first exemplary embodiment. The circuit components of the WL voltage regulation circuit 1000 are... Figure 9 The WL voltage regulation circuit 900 is similar. However, the negative voltage at the second terminal of the second resistor R2 is adjusted according to -((R2 / R1) + (R3 / R1)) (where the first resistor R1 and the second resistor R2 have highly doped resistance and therefore their resistances are less affected by temperature changes, while the third resistor R3 has lightly doped resistance and therefore its resistance is higher at higher temperatures). Therefore, as the temperature increases, less current will flow through the third resistor R3, resulting in a larger negative voltage at the second terminal of the second resistor R2. Thus, for post-write operations, the absolute value of the negative voltage at the second terminal of the second resistor R2 at a warmer temperature will be greater than the absolute value of the negative voltage at a cooler temperature.
[0062] exist Figure 11 The diagram illustrates a WL voltage regulation circuit 1100 for a write operation of a memory device 200 according to a second exemplary embodiment. Except for the absence of the NMOS transistor Q4 and the third resistor R3, the WL voltage regulation circuit 1100 is similar to the WL voltage regulation circuits 900 and 1000 of the first exemplary embodiments. The difference lies in the fact that, for a write operation, the effect of temperature on leakage current need not be considered. However, the negative voltage at the second terminal of the second resistor R2 is adjusted according to -(R2 / R1) (where the first resistor R4 receives a constant voltage from the non-inverting input of the buffer amplifier, the inverting input of the buffer amplifier receives ground voltage GND, and the second resistor R5 is an adjustable resistor used to adjust the negative voltage for the negative voltage scan in step S403).
[0063] In view of the foregoing description, this disclosure provides a memory device having a mechanism for minimizing leakage current of the memory device. This disclosure is suitable for use by flash memory devices and the like to improve the overall performance of the memory device and reduce the power consumption of the memory device.
[0064] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the disclosed embodiments without departing from the scope or spirit of this disclosure. In view of the foregoing, it is intended that this disclosure cover modifications and variations thereof, provided that such modifications and variations fall within the scope of the appended claims and their equivalents.< / m> < / l>
Claims
1. A memory device, comprising: A memory array includes memory cell groups, each memory cell group comprising M word lines and N bit lines, wherein M and N are integers greater than 1; A leakage current verification circuit is used to verify the leakage current of the memory array; as well as The controller is connected to the memory array and the leakage current verification circuit and is configured to at least: An erase operation is performed on the first column of a memory cell, the first column of which belongs to the memory cell group and is connected to the first word line of the M word lines; Set verification conditions that include a leakage current threshold during the leakage current verification operation. The leakage current verification operation is performed on the first column of the memory cells connected to the first word line of the M word lines by comparing the leakage current of the cells in the first column of the memory cells with the leakage current threshold via the leakage current verification circuit. The leakage current verification circuit detects a fault in the first column of the memory cell and responds to a cell in the first column of the memory cell that has a leakage current higher than the leakage current threshold. as well as Perform a post-write operation to repair the fault in the first column of the memory cell, wherein the verification conditions further include a negative voltage of each of the remaining M-1 unselected word lines and a positive bit line voltage of the N bit lines implemented during the leakage current verification operation.
2. The memory device of claim 1, wherein the controller is further configured to: The passage of the first column of the memory cells is detected via the leakage current verification circuit in response to all cells in the first column of the memory cells having a leakage current lower than the leakage current threshold; and The leakage current verification operation continues for the second column of the memory cell connected to the second word line of the M word lines, based on the same verification conditions.
3. The memory device of claim 2, wherein the controller is configured to perform a post-write operation to repair the fault in the column of the cell, comprising: Increase the threshold voltage of the cell in the first column of the memory cell until the leakage current of the cell in the first column of the memory cell is higher than the leakage current threshold.
4. The memory device of claim 2, wherein the leakage current verification circuit comprises: A sensing amplifier circuit is configured to compare the leakage current of the cell in the first column of the memory cell with a reference current source used as the leakage current threshold. A buffer amplifier configured to transmit a binary signal indicating either a pass or a fault in the first column of the memory cell; as well as An OR gate is connected to each cell in the first column of the memory cell to indicate whether any cell in the first column of the memory cell has failed the leakage current verification operation.
5. The memory device of claim 1, wherein the leakage current verification circuit further comprises a word line voltage regulation circuit for regulating the negative voltage of each of the remaining M-1 unselected word lines.
6. The memory device of claim 5, wherein the word line voltage regulation circuit comprises: The first resistor receives a constant voltage from the buffer amplifier; The second resistor is connected to one of the M word lines; as well as A third resistor is connected in parallel with an NMOS transistor having a threshold voltage, wherein the first resistor is connected in series with the NMOS transistor and the third resistor is connected in series with the second resistor.
7. The memory device of claim 5, wherein during the leakage current verification operation, the negative voltage of each of the remaining M-1 unselected word lines is adjusted by the word line voltage adjustment circuit according to -((R2 / R1) + Vth).