A lateral homojunction heterostructure memory device and method of fabrication

Abstract

This invention relates to a lateral homo-heterojunction memory device and its fabrication method. The memory device includes a substrate gate layer, a first dielectric layer, a second dielectric layer, a two-dimensional semiconductor channel layer, and ohmic electrodes. The first and second dielectric layers are both located on the substrate gate layer and are in contact with each other. The two-dimensional semiconductor channel layer is located on the first and second dielectric layers. The ohmic electrodes are located at both ends of the two-dimensional semiconductor channel layer. This memory device uses a composite dielectric layer to perform dielectric modulation and electrostatic gate modulation on the two-dimensional semiconductor channel layer, thereby forming a lateral heterojunction in a homogeneous material. The cross-section of the formed lateral heterojunction is located at the junction of the first and second dielectric layers, and the interface of the formed lateral heterojunction consists of only one line, reducing defects at the interface. Furthermore, since the heterojunction is formed using the same material, there is no lattice mismatch problem between different materials, thus improving the electrical performance of the memory.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, specifically relating to a lateral homo-heterojunction memory device and its fabrication method. Background Technology

[0002] Two-dimensional materials, such as graphene and transition metal dichalcogenides (TMDs), possess atomic-level thickness, excellent physicochemical properties, and ultra-large specific surface area, making them widely applicable as conductive channels in semiconductor electronic devices. In memory devices, the unique atomic-level thickness of two-dimensional materials can effectively reduce device size, avoiding short-channel effects caused by size reduction. Furthermore, the low current required for two-dimensional devices to operate results in low power consumption, thus making them a next-generation semiconductor memory device.

[0003] Traditional heterojunctions formed by vertically stacking two-dimensional materials have large interface contact areas and numerous interface traps. In contrast, lateral heterojunctions formed by two-dimensional materials have smaller contact interfaces, thereby reducing the impact of interface defects on the device and improving its electrical performance. Therefore, fabricating a small-sized, low-power memory device has become a key issue in memory device research.

[0004] Existing research discloses a two-dimensional material heterojunction floating gate memory, comprising: a gate layer, multiple floating gate layers, a barrier layer, a channel layer, and an electrode layer. However, the fabrication method of this memory requires a series of process steps such as multiple stacking, photolithography, and etching of the two-dimensional material. These processes can cause varying degrees of damage to the interface and quality of the two-dimensional material, thereby further affecting the electrical performance of the memory. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a lateral homo-heterojunction memory device and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] This invention provides a lateral homo-heterojunction memory device, comprising: a substrate gate layer, a first dielectric layer, a second dielectric layer, a two-dimensional semiconductor channel layer, and an ohmic electrode, wherein...

[0007] Both the first dielectric layer and the second dielectric layer are located on the substrate gate layer, and the first dielectric layer and the second dielectric layer are in contact with each other;

[0008] The two-dimensional semiconductor channel layer is located on the first dielectric layer and the second dielectric layer;

[0009] The ohmic electrodes are located at both ends of the two-dimensional semiconductor channel layer.

[0010] In one embodiment of the present invention, the material of the substrate gate layer comprises heavily doped silicon, wherein the doping concentration of the heavily doped silicon is 1×10⁻⁶. 17 -1×10 19 cm -3 .

[0011] In one embodiment of the present invention, the thickness of the first dielectric layer and the thickness of the second dielectric layer are both 10-100 nm.

[0012] In one embodiment of the present invention, at least one of the first dielectric layer and the second dielectric layer is made of a ferroelectric material.

[0013] In one embodiment of the present invention, the ferroelectric dielectric material includes one or more of hafnium zirconium oxide, barium titanate, and α-phase indium triselenide.

[0014] In one embodiment of the present invention, the material of the two-dimensional semiconductor channel layer includes several layers of two-dimensional semiconductor material, wherein the number of the several layers of two-dimensional semiconductor material is less than or equal to 10 layers.

[0015] In one embodiment of the present invention, the thickness of the two-dimensional semiconductor channel layer is 0.35-10 nm.

[0016] In one embodiment of the present invention, the material of the ohmic electrode includes one or more of metal X and metal Au, wherein metal X includes any one of Ti, Cr, Pt, and Pd, and the thickness of metal X is 5-10 nm, and the thickness of metal Au is 30-80 nm.

[0017] Another embodiment of the present invention provides a method for fabricating a lateral homo-heterojunction memory device, comprising the steps of:

[0018] S1. A first dielectric layer and a second dielectric layer are fabricated on the substrate gate layer, such that the first dielectric layer and the second dielectric layer are in contact;

[0019] S2. Transfer the two-dimensional semiconductor channel layer onto the first dielectric layer and the second dielectric layer;

[0020] S3. Ohmic electrodes are prepared at both ends of the two-dimensional semiconductor channel layer.

[0021] In one embodiment of the present invention, step S1 includes:

[0022] S11. A first dielectric material is grown on the substrate gate layer;

[0023] S12. Perform photolithography and patterning etching on the first dielectric material to expose part of the surface of the substrate gate layer, thereby obtaining the first dielectric layer;

[0024] S13. Grow a second dielectric material on the exposed surface of the substrate gate layer and on the first dielectric layer;

[0025] S14. The second dielectric material on the first dielectric layer is patterned and etched to obtain the second dielectric layer.

[0026] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0027] The lateral homo-heterojunction memory device of the present invention forms a composite dielectric layer through a first dielectric layer and a second dielectric layer. The composite dielectric layer modulates the dielectric and electrostatic gate of the two-dimensional semiconductor channel layer stacked on it, so that a lateral heterojunction is formed in the homogeneous material of the two-dimensional semiconductor channel layer. The cross section of the formed lateral heterojunction is located at the junction of the first dielectric layer and the second dielectric layer, and the interface of the formed lateral heterojunction has only one line, which reduces defects at the interface. Furthermore, since the heterojunction is formed using the same material, there is no lattice mismatch problem between different materials, thus improving the electrical performance of the memory. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the structure of a lateral homo-heterojunction memory device provided in an embodiment of the present invention;

[0029] Figure 2 This is a schematic flowchart illustrating a method for fabricating a lateral homo-heterojunction memory device according to an embodiment of the present invention.

[0030] Figures 3a-3g This is a schematic diagram illustrating the process of fabricating a lateral homo-heterojunction memory device according to an embodiment of the present invention. Detailed Implementation

[0031] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0032] Example 1

[0033] Please see Figure 1 , Figure 1 This is a schematic diagram of a lateral homojunction-heterojunction memory device provided in an embodiment of the present invention.

[0034] The lateral homojunction memory device includes: a substrate gate layer 1, a first dielectric layer 2, a second dielectric layer 3, a two-dimensional semiconductor channel layer 4, and ohmic electrodes 5. The first dielectric layer 2 and the second dielectric layer 3 are both located on the substrate gate layer 1 and are in contact with each other; the two-dimensional semiconductor channel layer 4 is located on the first dielectric layer 2 and the second dielectric layer 3; and the ohmic electrodes 5 are located at both ends of the two-dimensional semiconductor channel layer 4.

[0035] Substrate gate layer 1 serves as both the substrate and the gate, acting as a gate control layer. The material of substrate gate layer 1 includes heavily doped silicon, with a doping concentration of 1 × 10⁻⁶. 17 -1×10 19 cm -3 .

[0036] The first dielectric layer 2 and the second dielectric layer 3 together form a composite dielectric layer. The thicknesses of the first dielectric layer 2 and the second dielectric layer 3 can be equal or unequal at the nanometer level; preferably, the thicknesses of the first dielectric layer 2 and the second dielectric layer 3 are equal. The thickness of both the first dielectric layer 2 and the second dielectric layer 3 is 10-100 nm.

[0037] In the first dielectric layer 2 and the second dielectric layer 3, at least one dielectric layer is made of a ferroelectric material. That is, the materials of the first dielectric layer 2 and the second dielectric layer 3 can both be ferroelectric materials, or the material of the first dielectric layer 2 can be a ferroelectric material while the material of the second dielectric layer 3 is not a ferroelectric material, or the material of the first dielectric layer 2 can be not a ferroelectric material while the material of the second dielectric layer 3 is a ferroelectric material. Specifically, the ferroelectric material includes one or more of hafnium zirconium oxide, barium titanate, and α-phase indium triselenide (α-In2Se3).

[0038] This invention avoids the lattice mismatch problem caused by heterojunction material contact by preparing a composite dielectric layer, reduces interface defects, and thus improves the electrical performance of the storage.

[0039] The two-dimensional semiconductor channel layer 4 is located above the composite dielectric layer, covering the contact area between the first dielectric layer 2 and the second dielectric layer 3. The material of the two-dimensional semiconductor channel layer 4 comprises several layers of two-dimensional semiconductor material, including any one of molybdenum disulfide, tungsten disulfide, and tungsten diselenide; the number of these layers is less than or equal to 10, meaning the material of the two-dimensional semiconductor channel layer 4 is a single-layer or few-layer two-dimensional semiconductor material, where "few-layer" refers to a number of layers less than or equal to 10. The thickness of the two-dimensional semiconductor channel layer 4 is 0.35-10 nm.

[0040] The material of the ohmic electrode 5 includes one or more of metal X and metal Au. Metal X includes any one of Ti, Cr, Pt, and Pd, and the thickness of metal X is 5-10 nm, while the thickness of metal Au is 30-80 nm.

[0041] In this embodiment, the lateral homogeneous heterojunction memory device forms a composite dielectric layer through a first dielectric layer and a second dielectric layer. At least one dielectric layer in the composite dielectric layer is made of a ferroelectric material. This composite dielectric layer modulates the dielectric and electrostatic gate of the two-dimensional semiconductor channel layer stacked above it, resulting in the formation of a lateral heterojunction within the homogeneous material of the two-dimensional semiconductor channel layer. The cross-section of the formed lateral heterojunction is located at the interface between the first and second dielectric layers, and the interface consists of only one line corresponding to the interface between the first and second dielectric layers. This reduces defects at the interface. Furthermore, since the heterojunction is formed using the same material, there is no lattice mismatch problem between different materials, improving the electrical performance of the memory. In summary, this embodiment uses a homogeneous lateral heterojunction, which avoids the impact of lattice mismatch and interface defects on the electrical performance of the memory, thereby improving its electrical performance.

[0042] Example 2

[0043] Based on Example 1, this example provides a method for fabricating a lateral homo-heterojunction memory device. Please refer to [link to example]. Figure 2 and Figures 3a-3g , Figure 2 This is a schematic flowchart illustrating a method for fabricating a lateral homo-heterojunction memory device according to an embodiment of the present invention. Figures 3a-3g This is a schematic diagram illustrating the process of fabricating a lateral homo-heterojunction memory device according to an embodiment of the present invention.

[0044] The preparation method includes the following steps:

[0045] S1. A first dielectric layer 2 and a second dielectric layer 3 are fabricated on the substrate gate layer 1, such that the first dielectric layer 2 and the second dielectric layer 3 are in contact. Specifically, this includes the following steps:

[0046] S11. Grow a first dielectric material on the substrate gate layer 1. (See below) Figure 3a and Figure 3b .

[0047] Specifically, the substrate gate layer 1 is first cleaned, and then a first dielectric material is grown on the substrate gate layer 1.

[0048] S12. Perform photolithography and patterning etching on the first dielectric material to expose part of the surface of the substrate gate layer 1, thus obtaining the first dielectric layer 2. Please refer to [link to relevant documentation]. Figure 3c .

[0049] Specifically, the first dielectric material is photolithographically and patterned to expose part of the surface of the substrate gate layer 1. It is then ultrasonically cleaned with acetone, alcohol, and deionized water for 5 minutes each, and dried with nitrogen to form the patterned first dielectric layer 2.

[0050] S13. A second dielectric material is grown on the surface of the exposed substrate gate layer 1 and the first dielectric layer 2. Please refer to [link to documentation]. Figure 3d .

[0051] Specifically, a second dielectric material is grown on the surface of the exposed substrate gate layer 1 and the first dielectric layer 2 using atomic layer deposition.

[0052] S14. Pattern the second dielectric material on the first dielectric layer 2 to obtain the second dielectric layer 3. Please refer to [link to relevant documentation]. Figure 3e .

[0053] Specifically, the second dielectric material above the first dielectric layer 2 is patterned and etched, ultrasonically cleaned with acetone, alcohol and deionized water for 5 minutes respectively, and dried with nitrogen to form the second dielectric layer, thereby bringing the first dielectric layer 2 and the second dielectric layer 3 into contact and forming a composite dielectric layer together.

[0054] S2. Transfer the two-dimensional semiconductor channel layer 4 onto the first dielectric layer 2 and the second dielectric layer 3. Please refer to [link / reference]. Figure 3f .

[0055] Specifically, the two-dimensional semiconductor channel layer 4 is transferred onto the first dielectric layer 2 and the second dielectric layer 3, so that the two-dimensional semiconductor channel layer 4 is in contact with both the first dielectric layer 2 and the second dielectric layer 3.

[0056] S3. Ohmic electrodes 5 are fabricated at both ends of the two-dimensional semiconductor channel layer 4. Please refer to [link to relevant documentation]. Figure 3g .

[0057] Specifically, metal evaporation is performed on the two-dimensional semiconductor channel layer 4 to form an ohmic contact, and the metal layer is annealed and alloyed to form an ohmic electrode 5, thus completing the device fabrication.

[0058] The fabrication method in this embodiment has simple process steps, reduces the processing of two-dimensional materials, and provides convenience for subsequent device fabrication.

[0059] Example 3

[0060] Based on Example 2, this example illustrates a lateral homo-heterojunction memory device in which the first dielectric layer 2 is made of silicon dioxide, the second dielectric layer 3 is made of hafnium zirconium oxide, the composite dielectric layer has a thickness of 10 nm, and the two-dimensional semiconductor layer 4 is made of monolayer molybdenum disulfide.

[0061] S1. A first dielectric layer 2 and a second dielectric layer 3 are prepared on the substrate gate layer 1, such that the first dielectric layer 2 and the second dielectric layer 3 are in contact.

[0062] First, clean the substrate gate layer 1, please refer to [link / reference]. Figure 3aSpecifically, the substrate gate layer 1 was ultrasonically cleaned for 5 minutes each with acetone, alcohol, and deionized water, and then dried with nitrogen gas.

[0063] Then, a composite dielectric layer is fabricated on the substrate gate layer 1. Specifically, a 10 nm layer of the first dielectric material, silicon dioxide, is grown on the substrate gate layer 1 using atomic deposition. Please refer to [link to relevant documentation]. Figure 3b The first dielectric material, silicon dioxide layer, is photolithographically patterned and etched to a depth of 10 nm. It is then ultrasonically cleaned for 5 minutes each with acetone, alcohol, and deionized water, and dried with nitrogen to form the patterned silicon dioxide dielectric layer, thus obtaining the second dielectric layer 2. (See [link to relevant documentation]). Figure 3c Then, a second dielectric layer material, hafnium zirconium oxide, is grown on the device surface at a thickness of 10 nm using atomic layer deposition. Please refer to [link to relevant documentation]. Figure 3d The hafnium zirconium oxide layer, the second dielectric layer material above silicon dioxide, was patterned and etched to a depth of 10 nm. It was then ultrasonically cleaned for 5 minutes each with acetone, alcohol, and deionized water, and dried with nitrogen to form the second dielectric layer 3, thus obtaining the composite dielectric layer. (See [link to documentation]). Figure 3e .

[0064] S2. Transfer the two-dimensional semiconductor channel layer 4 onto the first dielectric layer 2 and the second dielectric layer 3. Please refer to [link / reference]. Figure 3f .

[0065] Specifically, the mechanically exfoliated monolayer molybdenum disulfide nanosheets are transferred to the composite dielectric layer using a dry transfer method, so that the monolayer molybdenum disulfide nanosheets are in contact with both the first dielectric layer 2 and the second dielectric layer 3.

[0066] S3. Ohmic electrodes 5 are fabricated at both ends of the two-dimensional semiconductor channel layer 4. Please refer to [link to relevant documentation]. Figure 3g .

[0067] Specifically, photolithography, metal evaporation, and annealing alloying were performed on a monolayer molybdenum disulfide to form ohmic contact electrodes. The metal used was Ti / Au, with a growth thickness of 5 nm for Ti and 30 nm for Au, thus completing the fabrication of a lateral homo-heterojunction memory device based on a monolayer molybdenum disulfide.

[0068] Example 4

[0069] Based on Example 2, this example illustrates a lateral homo-heterojunction memory device with hafnium dioxide as the material for the first dielectric layer 2, hafnium zirconium oxide as the material for the second dielectric layer 3, a composite dielectric layer thickness of 50 nm, and few-layer tungsten diselenide as the two-dimensional material semiconductor layer 4.

[0070] S1. A first dielectric layer 2 and a second dielectric layer 3 are prepared on the substrate gate layer 1, such that the first dielectric layer 2 and the second dielectric layer 3 are in contact.

[0071] First, clean the substrate gate layer 1, please refer to [link / reference]. Figure 3aSpecifically, the substrate gate layer 1 was ultrasonically cleaned for 5 minutes each with acetone, alcohol, and deionized water, and then dried with nitrogen gas.

[0072] Then, a composite dielectric layer is fabricated on the substrate gate layer 1. Specifically, 50 nm of the first dielectric material, hafnium dioxide, is grown on the substrate gate layer 1 using atomic deposition. Please refer to [link to relevant documentation]. Figure 3b The first dielectric material, hafnium dioxide, was photolithographically patterned and etched to a pattern of 50 nm. It was then ultrasonically cleaned for 5 minutes each with acetone, alcohol, and deionized water, and dried with nitrogen to form a patterned hafnium dioxide dielectric layer, thus obtaining the second dielectric layer 2. (See [link to relevant documentation]). Figure 3c Then, a second dielectric layer material, hafnium zirconium oxide, is grown on the device surface at a thickness of 50 nm using atomic layer deposition. Please refer to [link to documentation]. Figure 3d The hafnium zirconium oxide layer, the second dielectric layer material above the silicon dioxide, was patterned and etched at 50 nm. It was then ultrasonically cleaned for 5 minutes each with acetone, alcohol, and deionized water, and dried with nitrogen to form the second dielectric layer 3, thus obtaining the composite dielectric layer. (See [link to documentation]). Figure 3e .

[0073] S2. Transfer the two-dimensional semiconductor channel layer 4 onto the first dielectric layer 2 and the second dielectric layer 3. Please refer to [link / reference]. Figure 3f .

[0074] Specifically, the mechanically exfoliated few-layer tungsten diselenide nanosheets are transferred to the composite dielectric layer using a dry transfer method, so that the few-layer tungsten diselenide nanosheets are in contact with both the first dielectric layer 2 and the second dielectric layer 3.

[0075] S3. Ohmic electrodes 5 are fabricated at both ends of the two-dimensional semiconductor channel layer 4. Please refer to [link to relevant documentation]. Figure 3g .

[0076] Specifically, photolithography, metal evaporation, and annealing alloying are performed on a few-layer tungsten diselenide to form ohmic contact electrodes. The metal used is Cr / Au, with a Cr growth thickness of 10 nm and an Au growth thickness of 60 nm, thus completing the fabrication of a few-layer tungsten diselenide lateral homo-heterojunction memory device.

[0077] Example 5

[0078] Based on Example 2, this example illustrates a lateral homo-heterojunction memory device in which the first dielectric layer 2 is made of hafnium dioxide, the second dielectric layer 3 is made of hafnium zirconium oxide, the composite dielectric layer thickness is 100 nm, and the two-dimensional material semiconductor layer 4 is a single-layer molybdenum disulfide thin film.

[0079] S1. A first dielectric layer 2 and a second dielectric layer 3 are prepared on the substrate gate layer 1, such that the first dielectric layer 2 and the second dielectric layer 3 are in contact.

[0080] First, clean the substrate gate layer 1, please refer to [link / reference]. Figure 3a Specifically, the substrate gate layer 1 was ultrasonically cleaned for 5 minutes each with acetone, alcohol, and deionized water, and then dried with nitrogen gas.

[0081] Then, a composite dielectric layer is fabricated on the substrate gate layer 1. Specifically, 100 nm of the first dielectric material, hafnium dioxide, is grown on the substrate gate layer 1 using atomic deposition. Please refer to [link to relevant documentation]. Figure 3b The first dielectric material, hafnium dioxide, was photolithographically patterned and etched to a depth of 100 nm. It was then ultrasonically cleaned for 5 minutes each with acetone, alcohol, and deionized water, and dried with nitrogen to form a patterned hafnium dioxide dielectric layer, thus obtaining the second dielectric layer 2. (See [link to relevant documentation]). Figure 3c Then, a second dielectric layer material, hafnium zirconium oxide, is grown on the device surface at a thickness of 100 nm using atomic layer deposition. Please refer to [link to relevant documentation]. Figure 3d The hafnium zirconium oxide layer, the second dielectric layer material above silicon dioxide, was patterned and etched to a depth of 100 nm. It was then ultrasonically cleaned for 5 minutes each with acetone, alcohol, and deionized water, and dried with nitrogen to form the second dielectric layer 3, thus obtaining the composite dielectric layer. (See [link to documentation]). Figure 3e .

[0082] S2. Transfer the two-dimensional semiconductor channel layer 4 onto the first dielectric layer 2 and the second dielectric layer 3. Please refer to [link / reference]. Figure 3f .

[0083] Specifically, the mechanically peeled monolayer molybdenum disulfide film is transferred to the composite dielectric layer using a dry transfer method, so that the monolayer molybdenum disulfide film is in contact with both the first dielectric layer 2 and the second dielectric layer 3.

[0084] S3. Ohmic electrodes 5 are fabricated at both ends of the two-dimensional semiconductor channel layer 4. Please refer to [link to relevant documentation]. Figure 3g .

[0085] Specifically, photolithography, metal evaporation, and annealing alloying were performed on a monolayer molybdenum disulfide thin film to form ohmic contact electrodes. The metals used were Pd / Au, with a growth thickness of 10 nm for Pd and 80 nm for Au, thus completing the fabrication of a lateral homo-heterojunction memory device of monolayer molybdenum disulfide.

[0086] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A lateral homo-heterojunction memory device, characterized in that, include: The substrate gate layer (1), the first dielectric layer (2), the second dielectric layer (3), the two-dimensional semiconductor channel layer (4), and the ohmic electrode (5) are provided. The first dielectric layer (2) and the second dielectric layer (3) are both located on the substrate gate layer (1), and the first dielectric layer (2) and the second dielectric layer (3) are in contact with each other; the materials of the first dielectric layer (2) and the second dielectric layer (3) are both ferroelectric materials; The two-dimensional semiconductor channel layer (4) is located on the first dielectric layer (2) and the second dielectric layer (3); The ohmic electrode (5) is located at both ends of the two-dimensional semiconductor channel layer (4).

2. The lateral homo-heterojunction memory device according to claim 1, characterized in that, The material of the substrate gate layer (1) comprises heavily doped silicon, the doping concentration of the heavily doped silicon being 1 x 10 17 -1 x 10 19 cm -3 .

3. The lateral homo-heterojunction memory device according to claim 1, characterized in that, The thickness of the first dielectric layer (2) and the thickness of the second dielectric layer (3) are both 10-100 nm.

4. The lateral homo-heterojunction memory device according to claim 1, characterized in that, The ferroelectric dielectric material includes one or more of hafnium zirconium oxide, barium titanate, and α-phase indium triselenide.

5. The lateral homo-heterojunction memory device according to claim 1, characterized in that, The material of the two-dimensional semiconductor channel layer (4) includes several layers of two-dimensional semiconductor material, and the number of layers of the several layers of two-dimensional semiconductor material is less than or equal to 10.

6. The lateral homo-heterojunction memory device according to claim 1, characterized in that, The thickness of the two-dimensional semiconductor channel layer (4) is 0.35-10 nm.

7. The lateral homo-heterojunction memory device according to claim 1, characterized in that, The material of the ohmic electrode (5) includes one or more of metal X and metal Au. Metal X includes any one of Ti, Cr, Pt, and Pd, and the thickness of metal X is 5-10 nm, while the thickness of metal Au is 30-80 nm.

8. A method for fabricating a lateral homo-heterojunction memory device, characterized in that, Including the following steps: S1. A first dielectric layer (2) and a second dielectric layer (3) are prepared on a substrate gate layer (1) such that the first dielectric layer (2) and the second dielectric layer (3) are in contact; the materials of the first dielectric layer (2) and the second dielectric layer (3) are both ferroelectric materials; S2. Transfer the two-dimensional semiconductor channel layer (4) onto the first dielectric layer (2) and the second dielectric layer (3); S3. Ohmic electrodes (5) are prepared at both ends of the two-dimensional semiconductor channel layer (4).

9. The method for fabricating a lateral homo-heterojunction memory device according to claim 8, characterized in that, Step S1 includes: S11. A first dielectric material is grown on the substrate gate layer (1); S12. Photolithography and patterning etching are performed on the first dielectric material to expose part of the surface of the substrate gate layer (1) and obtain the first dielectric layer (2); S13. A second dielectric material is grown on the exposed surface of the substrate gate layer (1) and the first dielectric layer (2); S14. The second dielectric material on the first dielectric layer (2) is patterned and etched to obtain the second dielectric layer (3).

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