Switched capacitor amplifier device and method for improving level boosting

Abstract

A switched capacitor amplifier device and method for improving level boosting. The amplifier includes two input terminals and two output terminals. Two capacitor circuits correspond to the two signal input terminals and the two signal output terminals, and respectively include a sampling capacitor circuit, a load capacitor, and a level boosting capacitor. During a sampling period, the sampling capacitor circuit samples an input signal from the signal input terminal and outputs it to the input terminal. A charge neutralization capacitor is connected across the two output terminals. During an estimation period, the load capacitor and the level boosting capacitor are charged according to the output of the output terminal. During a level boosting period, the level boosting capacitor charges the load capacitor to achieve level boosting, and an output signal is generated through the signal output terminal. The charge neutralization capacitor receives charge according to the output terminal during the estimation period and provides charge to the level boosting capacitor during the level boosting period.

Description

Technical Field

[0001] The present invention relates to signal amplification technology, and more particularly to a switched capacitor amplification device and method for improving level boosting. Background Art

[0002] In analog signal processing circuits, a gain stage circuit is often required to amplify the input analog signal. In some technologies, a switched capacitor amplifier circuit is often used to implement the gain stage circuit.

[0003] A switched capacitor amplifier circuit requires an operational amplifier (OPA) and a set of capacitors to amplify the input signal. However, when the connected capacitor circuit switches, the output of the OPA may not be able to provide sufficient current, resulting in unstable output voltage. Summary of the Invention

[0004] In view of the problems in the prior art, an object of the present invention is to provide a switched capacitor amplifier device and method for improving level boosting, so as to improve the prior art.

[0005] The present invention includes a switched capacitor amplifier device for improving level boosting, comprising: an amplifier, two capacitor circuits, and a charge neutralization capacitor. The amplifier includes two input terminals and two output terminals. The two capacitor circuits correspond to one of the two signal input terminals and one of the two signal output terminals, respectively, and each include a sampling capacitor circuit, a load capacitor, and a level boosting capacitor. The sampling capacitor circuit is configured to receive one of two input signals from one of the two signal input terminals during a sampling cycle, sample the sample, and output the sample to one of the two input terminals of the amplifier. The charge neutralization capacitor is connected across the two output terminals of the amplifier. The load capacitor and the level boosting capacitor are connected to one of the two output terminals of the amplifier in multiple connections. During an estimation cycle, the load capacitor is first charged according to the output of the amplifier at one of the two output terminals. Then, during a level boosting cycle, the load capacitor is charged by the level boosting capacitor to achieve level boosting, so that the load capacitor generates one of the two output signals through one of the two signal output terminals. The charge neutralizing capacitor is configured to receive charges from the two output terminals of the amplifier during the estimation period and to provide charges to the level boosting capacitors of the two capacitor circuits during the level boosting period.

[0006] The present invention also includes a switched capacitor amplification method for improving level boosting, which is applied to a switched capacitor amplifier device and includes: causing a sampling capacitor circuit of one of the two capacitor circuits to receive one of two input signals from one of the two signal input terminals during a sampling period and sample the sample for output to one of the two input terminals of an amplifier; establishing multiple connection relationships between a load capacitor and a level-boosting capacitor of one of the two capacitor circuits and one of the two output terminals of the amplifier, so that during an estimation period, the load capacitor is first charged according to the output of the amplifier at one of the two output terminals, and then during a level-boosting period, the load capacitor is charged by the level-boosting capacitor to achieve level boosting, so that the load capacitor generates one of the two output signals through one of the two signal output terminals; and causing a charge neutralization capacitor connected across the two output terminals of the amplifier to receive charge according to the two output terminals of the amplifier during an estimation period and provide charge to the level-boosting capacitor of the two capacitor circuits during a level-boosting period.

[0007] The features, implementation and technical effects of the present disclosure are described in detail below with reference to the accompanying drawings as preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A block diagram showing a switched capacitor amplifier device for improving level boosting according to an embodiment of the present invention;

[0009] Figures 2A to 2C A more detailed circuit diagram showing a switched capacitor amplifier device in different operating cycles according to an embodiment of the present invention;

[0010] Figure 3A A simplified circuit diagram showing an amplifier, a load capacitor, a level-boosting capacitor, and a charge-neutralizing capacitor in an estimation cycle according to an embodiment of the present invention;

[0011] Figure 3B A simplified circuit diagram showing an amplifier, a load capacitor, a level-boosting capacitor, and a charge-neutralizing capacitor during an initial stage of a level-boosting cycle in one embodiment of the present invention;

[0012] Figure 3C A simplified circuit diagram showing an amplifier, a load capacitor, a level-boosting capacitor, and a charge-neutralizing capacitor after an initial section of a level-boosting cycle according to an embodiment of the present invention;

[0013] Figure 4 A voltage waveform diagram showing the output terminal of the amplifier during a level-raising period in one embodiment of the present invention; and

[0014] Figure 5 A flow chart showing a method for improving level-boosting switched capacitor amplification according to an embodiment of the present invention is shown.

[0015] Explanation of symbols

[0016] 100: Switched capacitor amplifier

[0017] 110: Amplifier

[0018] 120A, 120B: Capacitor circuit

[0019] 130A, 130B: Sampling capacitor circuit

[0020] 500: Switched Capacitor Amplification Method

[0021] S510~S530: Steps

[0022] CLD1, CLD2: load capacitance

[0023] CLS1, CLS2: Level-lifting capacitors

[0024] CS1: First sampling capacitor

[0025] CS2: Second sampling capacitor

[0026] CT: Charge Neutralization Capacitor

[0027] GND: Ground

[0028] IN1, IN2: input terminals

[0029] NA1, NB1: First connection end

[0030] NA2, NB2: Second connection end

[0031] OUT1, OUT2: output terminals

[0032] S1, S2: sampling input terminals

[0033] S3: sampling output terminal

[0034] SIN1, SIN2: signal input terminals

[0035] SOUT1, SOUT2: signal output terminals

[0036] SW1: First switching unit

[0037] SW2: Second switching unit

[0038] SW3: The third switching unit

[0039] SW4: Fourth switching unit

[0040] SW5: Fifth switching unit

[0041] T1, T2: time interval

[0042] Vin1, Vin2: input signal

[0043] Vout1, Vout2: output signal DETAILED DESCRIPTION

[0044] An object of the present invention is to provide a switched capacitor amplifier device and method for improving level boosting. By disposing a charge neutralizing capacitor, the current supply capability of the amplifier is compensated during the level boosting cycle, so that the voltage of the level boosting capacitor quickly stabilizes, thereby improving the speed of level boosting.

[0045] Please refer to Figure 1 . Figure 1 A block diagram of a switched capacitor amplifier 100 for improving level boosting according to an embodiment of the present invention is shown. The switched capacitor amplifier 100 includes an amplifier 110, a capacitor circuit 120A, a capacitor circuit 120B, and a charge neutralization capacitor CT.

[0046] In one embodiment, amplifier 110 is an operational amplifier and includes input terminals IN1 and IN2, and output terminals OUT1 and OUT2. In one embodiment, input terminal IN1 is an inverting input terminal, denoted by the symbol "-", and input terminal IN2 is a non-inverting input terminal, denoted by the symbol "+". Output terminal OUT1 is a non-inverting output terminal, denoted by the symbol "+". Output terminal OUT2 is an inverting output terminal, denoted by the symbol "-".

[0047] The capacitor circuits 120A and 120B correspond to one of the signal input terminals SIN1 and SIN2 and one of the signal output terminals SOUT1 and SOUT2 , respectively.

[0048] The capacitor circuit 120A is configured to receive an input signal Vin1 from a signal input terminal SIN1, amplify the signal, and generate an output signal Vout1 through a signal output terminal SOUT1. The capacitor circuit 120A includes a sampling capacitor circuit 130A, a load capacitor CLD1, and a level-boosting capacitor CLS1.

[0049] The sampling capacitor circuit 130A of the capacitor circuit 120A is configured to receive an input signal Vin1 from the signal input terminal SIN1 for sampling during a sampling period, and output the sampled signal to the input terminal IN1 of the amplifier 110 through the sampling output terminal S3 .

[0050] The load capacitor CLD1 and the level-boosting capacitor CLS1 form multiple connections with the output terminal OUT1 of the amplifier 110. Figure 1The three components can be connected to each other in various ways, as shown by dashed lines, without actually showing the connections. Depending on the connection relationships, load capacitor CLD1 and level-boosting capacitor CLS1 are first charged by the output of amplifier 110 at output terminal OUT1 during the estimation period. Then, during the level-boosting period, level-boosting capacitor CLS1 charges load capacitor CLD1, thereby boosting its level. This allows load capacitor CLD1 to generate output signal Vout1 through signal output terminal SOUT1.

[0051] Capacitor circuit 120B includes a sampling capacitor circuit 130B, a load capacitor CLD2, and a level-boosting capacitor CLS2. The operation and structure of capacitor circuit 120B are identical to those of capacitor circuit 120A. The only difference is that capacitor circuit 120B samples input signal Vin2 at signal input terminal SIN2 and interacts with input terminal IN2 and output terminal OUT2 of amplifier 110 to generate output signal Vout2 at signal output terminal SOUT2. Therefore, further description is omitted.

[0052] It should be noted that the input signals Vin1 and Vin2 respectively received by the capacitor circuits 120A and 120B are differential signals, and the output signals Vout1 and Vout2 generated therefrom are also differential signals.

[0053] The charge neutralizing capacitor CT is connected across the two output terminals OUT1 and OUT2 of the amplifier 110 and is configured to receive charge from the two output terminals OUT1 and OUT2 of the amplifier 110 during the estimation period and provide charge to the level-boosting capacitors CLS1 and CLS2 of the two capacitor circuits 120A and 120B during the level-boosting period.

[0054] Please also refer to Figures 2A to 2C . Figures 2A to 2C A more detailed circuit diagram of the switched capacitor amplifier device 100 in different operating cycles is shown in one embodiment of the present invention. Figures 2A to 2C , a more detailed structure and operation of the switched capacitor amplifier device 100 are described.

[0055] like Figure 2A As shown, in one embodiment, the sampling capacitor circuit 130A in the capacitor circuit 120A actually includes a first sampling capacitor CS1 and a second sampling capacitor CS2. The first sampling capacitor CS1 is electrically coupled between the sampling input terminal S1 and the sampling output terminal S3. The second sampling capacitor CS2 is electrically coupled between the sampling input terminal S2 and the sampling output terminal S3.

[0056] The load capacitor CLD1 is electrically coupled between the first connection terminal NA1 and the ground terminal GND. The first connection terminal NA1 is also electrically coupled to the signal output terminal SOUT1. The level-boosting capacitor CLS1 is electrically coupled between the first connection terminal NA1 and the second connection terminal NA2.

[0057] Similarly, the sampling capacitor circuit 130B, the load capacitor CLD2, and the level-boosting capacitor CLS2 in the capacitor circuit 120B have the same structure as those of the capacitor circuit 120A, and thus are not described again.

[0058] In this embodiment, the switched capacitor amplifier device 100 includes a first switching unit SW1, a second switching unit SW2, a third switching unit SW3, a fourth switching unit SW4, and a fifth switching unit SW5 corresponding to the capacitor circuit 120A. The switched capacitor amplifier device 100 can switch the first through fifth switching units SW1 through SW5 in different operating cycles, thereby achieving the technical effect of enabling the capacitor circuit 120A to receive the input signal Vin1 and generate an amplified output signal Vout1. In one embodiment, the switched capacitor amplifier device 100 sequentially operates through a sampling cycle, an estimation cycle, and a level-boosting cycle.

[0059] like Figure 2A As shown, during the sampling period, the first switching unit SW1 electrically couples the sampling input terminal S1 to the signal input terminal SIN1, and the second switching unit SW2 also electrically couples the sampling input terminal S2 to the signal input terminal SIN1. The third switching unit SW3 electrically couples the sampling output terminal S1 and the input terminal IN1 of the amplifier 110 to the ground terminal GND. The fourth switching unit SW4 electrically couples the first connection terminal NA1 to the output terminal OUT1 of the amplifier 110. The fifth switching unit SW5 electrically couples the second connection terminal NA2 to the output terminal OUT2.

[0060] Similarly, capacitor circuit 120B can also perform the same operation corresponding to signal input terminal SIN2, signal output terminal SOUT2, input terminal IN2, and output terminal OUT2 of amplifier 110. In capacitor circuit 120B, the second connection terminal NB2 corresponding to level-boosting capacitor CLS2 is electrically coupled to output terminal OUT1. Other structural and operational details are not further described here.

[0061] Therefore, during the sampling period, the sampling capacitor circuits 130A and 130B respectively receive the input signals Vin1 and Vin2 through the corresponding sampling input terminals S1 and S2 and sample the input signals Vin1 and Vin2.

[0062] like Figure 2BAs shown, during the estimation period, for the capacitor circuit 120A, the first switching unit SW1 electrically couples the sampling input terminal S1 to the ground terminal GND, and the second switching unit SW2 electrically couples the sampling input terminal S2 to the first connection terminal NA1. The third switching unit SW3 electrically isolates the sampling output terminal S1 and the input terminal IN1 of the amplifier 110 from the ground terminal GND. The fourth switching unit SW4 electrically couples the first connection terminal NA1 to the output terminal OUT1 of the amplifier 110. The fifth switching unit SW5 electrically couples the second connection terminal NA2 to the output terminal OUT2.

[0063] Similarly, capacitor circuit 120B can also perform the same operation corresponding to signal input terminal SIN2, signal output terminal SOUT2, input terminal IN2, and output terminal OUT2 of amplifier 110. In capacitor circuit 120B, the second connection terminal NB2 corresponding to level-boosting capacitor CLS2 is electrically coupled to output terminal OUT1. Other structural and operational details are not further described here.

[0064] Therefore, during the estimation period, sampling capacitor circuits 130A and 130B output the sampled input signals Vin1 and Vin2, respectively, to input terminals IN1 and IN2 of amplifier 110 via sampling output terminal S1. Furthermore, load capacitors CLD1 and CLD2 and level-boosting capacitors CLS1 and CLS2 are charged based on the outputs of amplifier 110 at output terminals OUT1 and OUT2, respectively. At this time, load capacitors CLD1 and CLD2 cause the voltages at signal output terminals SOUT1 and SOUT2 to rise.

[0065] At this time, the charge neutralization capacitor CT is connected across the two output terminals OUT1 and OUT2 of the amplifier 110 , and receives charges according to the output of the amplifier 110 at the output terminal OUT1 .

[0066] like Figure 2C As shown, during the level-raising period, for the capacitor circuit 120A, the first switch unit SW1 electrically couples the sampling input terminal S1 to the ground terminal GND, and the second switch unit SW2 electrically couples the sampling input terminal S2 to the first connection terminal NA1. The third switch unit SW3 electrically isolates the sampling output terminal S1 and the input terminal IN1 of the amplifier 110 from the ground terminal GND. The fourth switch unit SW4 electrically isolates the first connection terminal NA1 from the output terminal OUT1 of the amplifier 110. The fifth switch unit SW5 electrically couples the second connection terminal NA2 to the output terminal OUT1 of the amplifier 110.

[0067] Similarly, the capacitor circuit 120B can also perform the same operation corresponding to the signal input terminal SIN2, the signal output terminal SOUT2, the input terminal IN2, and the output terminal OUT2 of the amplifier 110. For the capacitor circuit 120B, the second connection terminal NB2 corresponding to the level-boosting capacitor CLS2 is electrically coupled to the output terminal OUT2. This will not be further described here.

[0068] Therefore, during the level-boosting cycle, the level-boosting capacitors CLS1 and CLS2 charge the load capacitors CLD1 and CLD2. At this point, the load capacitors CLD1 and CLD2 cause the voltages at the signal output terminals SOUT1 and SOUT2 to rise again, achieving the level-boosting effect and generating output signals Vout1 and Vout2 at the signal output terminals SOUT1 and SOUT2.

[0069] Please also refer to Figures 3A to 3C . Figure 3A A simplified circuit diagram of the amplifier 110 , load capacitors CLD1 and CLD2 , level-boosting capacitors CLS1 and CLS2 , and charge neutralization capacitor CT in an estimation cycle is shown in one embodiment of the present invention. Figure 3B A simplified circuit diagram is shown of the amplifier 110 , the load capacitors CLD1 and CLD2 , the level-boosting capacitors CLS1 and CLS2 , and the charge neutralization capacitor CT during an initial section of a level-boosting cycle in one embodiment of the present invention. Figure 3C A simplified circuit diagram of the amplifier 110 , load capacitors CLD1 and CLD2 , level-boosting capacitors CLS1 and CLS2 , and charge neutralization capacitor CT after an initial section of a level-boosting cycle is shown in one embodiment of the present invention.

[0070] like Figure 3A As shown, during the estimation period, since the output terminal OUT1 is a non-inverting output terminal, the output terminal OUT1 outputs a positive voltage relative to a reference voltage level to one end of the charge neutralization capacitor CT connected thereto, the corresponding load capacitor CLD1, the first connection terminal NA1 of the level-boosting capacitor CLS1, and the second connection terminal NB2 of the level-boosting capacitor CLS2, and outputs a positive voltage to the output terminal OUT1. Figure 3A The symbol "+" is used to indicate these endpoints.

[0071] Since the output terminal OUT2 is an inverting output terminal, the output terminal OUT2 outputs a negative voltage relative to a reference voltage level to the other end of the charge neutralization capacitor CT connected thereto, the corresponding load capacitor CLD2, the second connection terminal NA2 of the corresponding level-lifting capacitor CLS1, and the first connection terminal NB1 of the corresponding level-lifting capacitor CLS2, and Figure 3A The symbol “-” is used to indicate these endpoints.

[0072] On the other hand, Figure 3B As shown, during the level-raising period, due to the above-mentioned charging behavior, the level-raising capacitor CLS1 corresponding to the non-inverting output terminal OUT1 will output a positive voltage, and in the initial section of the level-raising period, the voltage of the first connection terminal NA1 corresponding to the level-raising capacitor CLS1 will increase, and the voltage of the second connection terminal NA2 will decrease. Figure 3B The symbols "+" and "-" are used to represent these endpoints respectively.

[0073] The level-lifting capacitor CLS2 corresponding to the inverting output terminal OUT2 will output a negative voltage, and in the initial section of the level-lifting cycle, the voltage of the first connection terminal NB1 corresponding to the level-lifting capacitor CLS2 will drop (negative rise), and the voltage of the second connection terminal NB2 will rise (negative fall), and Figure 3B The symbols “-” and “+” are used to represent these endpoints respectively.

[0074] At this time, the charge neutralization capacitor CT connected across the two output terminals OUT1 and OUT2 of the amplifier 110 will provide charge. More specifically, the charge neutralization capacitor CT will provide positive charge to the second connection terminal NA2 of the capacitor circuit 120A for neutralization, and provide negative charge to the second connection terminal NB2 of the capacitor circuit 120B for neutralization. Figure 3C As shown, after the initial section of the level-boosting cycle, the output terminals OUT1, OUT2 and the second connection terminals NA2, NB2 corresponding to the level-boosting capacitors CLS1, CLS2 will reach a stable voltage due to charge neutralization, and Figure 3C The symbol "0" is used to represent these endpoints.

[0075] During the level-boosting cycle, the level-boosting capacitors CLS1 and CLS2 must charge not only the load capacitors CLD1 and CLD2 but also the sampling capacitor circuits 130A and 130B electrically coupled to the first connection terminals NA1 and NB1. Therefore, the current input and output capabilities of the amplifier 110 at the two output terminals OUT1 and OUT2 will affect the charging capabilities of the level-boosting capacitors CLS1 and CLS2. However, if the amplifier 110's response capability is poor, the charging capabilities of the level-boosting capacitors CLS1 and CLS2 will be reduced.

[0076] Therefore, by configuring the charge neutralization capacitor CT, the amplifier 110 can first store charge in the charge neutralization capacitor CT during the estimation period, so that the charge neutralization capacitor CT provides charge during the level boost period to compensate for the insufficient current supply capability of the amplifier 110.

[0077] In one embodiment, taking capacitor circuit 120A as an example, the charge neutralization capacitor CT has a first voltage V1 at its corresponding second connection terminal NA2 after receiving charge. The second connection terminal NA2 has a second voltage V2 during the initial portion of the level-boosting cycle. The load capacitor CLD1 and the level-boosting capacitor CLS1 have equivalent capacitances Ce. The target voltage of the second connection terminal NA2 is Vt. The third capacitance of the charge neutralization capacitor CT is Ct for charge neutralization. Based on the formula for multiplying voltage and capacitance to obtain charge, the following relationship can be obtained:

[0078] 2Ct×V1+Ce×V2=Vt×(2Ct+Ce) (Formula 1).

[0079] Therefore, Ct will be:

[0080] Ct=(Ce×(Vt-V2)) / (2×(V1-Vt)) (Formula 2).

[0081] In a numerical example, the first voltage V1 is 0.6, the second voltage V2 is 0.4, the equivalent capacitance Ce is C, and the target voltage Vt is 0.5. According to (Equation 2), the third capacitance Ct of the charge neutralization capacitor CT is 0.5C.

[0082] In one embodiment, the level-boosting capacitors CLS1 , CLS2 and the charge neutralization capacitor Ct are variable capacitors, and the capacitances of the level-boosting capacitors CLS1 , CLS2 and the charge neutralization capacitor Ct are adjusted according to the change of the DC gain of the amplifier 110 .

[0083] More specifically, in some applications, the DC gain of amplifier 110 may vary by tens of decibels (dB) due to temperature, pressure, or process changes. Therefore, the level-boosting capacitors CLS1 and CLS2, as well as the charge-neutralizing capacitor Ct, can be configured as variable capacitors. Under the control of other circuitry (not shown), the capacitance values ​​are determined based on the DC gain of amplifier 110 to maintain the loop gain between output signal Vout and input signal Vin.

[0084] Please refer to Figure 4 . Figure 4 The voltage waveform of the output terminal OUT1 of the amplifier 110 during the level raising period is shown in one embodiment of the present invention. Figure 4 In the figure, the horizontal axis represents time, and the vertical axis represents voltage. Time interval T1 represents the estimation period, and time interval T2 represents the level-raising period. Furthermore, the dashed line segment represents condition 1, where no charge neutralization capacitor CT is provided between the output terminals OUT1 and OUT2 of amplifier 110. The solid line segment represents condition 2, where a charge neutralization capacitor CT is provided between the output terminals OUT1 and OUT2 of amplifier 110.

[0085] like Figure 4 As shown, compared with the first case, although the voltage rises more slowly in the second case during the estimation period because of the need to provide additional charge to the charge neutralization capacitor CT, the surge is smaller and the voltage stabilizes faster during the level increase period due to the setting of the charge neutralization capacitor CT.

[0086] Therefore, the switched capacitor amplifier device 100 for improving level boosting in the present invention can compensate the current supply capability of the amplifier 110 during the level boosting period by disposing the charge neutralizing capacitor CT, so that the voltages of the level boosting capacitors CLS1 and CLS2 tend to stabilize quickly, thereby improving the speed of level boosting.

[0087] It should be noted that the above Figures 2A to 2C The structure of the switched capacitor amplifier device 100 is only an example. In different application scenarios, the detailed structure of the switched capacitor amplifier device 100 can be implemented in other different ways instead of Figures 2A to 2C Limited by the architecture shown.

[0088] Please refer to Figure 5 . Figure 5 A flow chart of a method 500 for improving level-boosting switched capacitor amplification according to an embodiment of the present invention is shown.

[0089] In addition to the aforementioned devices, the present invention further discloses a method 500 for improving level boosting of switched capacitor amplification, which is applied to, for example, but not limited to, Figure 1 An embodiment of a method 500 for improving a switched capacitor amplification of a level boosting circuit is as follows: Figure 5 As shown, it includes the following steps.

[0090] In step S510 , the sampling capacitor circuits 130A and 130B of the two capacitor circuits 120A and 120B receive one of the two input signals Vin1 and Vin2 from one of the two signal input terminals SIN1 and SIN2 during a sampling period for sampling and output to one of the two input terminals IN1 and IN2 of the amplifier 110 .

[0091] In step S520, multiple connections are established between the load capacitors CLD1 and CLD2 and the level-boosting capacitors CLS1 and CLS2 of the two capacitor circuits 120A and 120B and one of the output terminals OUT1 and OUT2 of the amplifier 110. During an estimation cycle, the load capacitors CLD1 and CLD2 are first charged according to the output of the amplifier 110 at one of the output terminals OUT1 and OUT2. Then, the level-boosting capacitors CLS1 and CLS2 charge the load capacitors CLD1 and CLD2 to achieve level boosting, so that the load capacitors CLD1 and CLD2 generate one of the output signals Vout1 and Vout2 through one of the signal output terminals SOUT1 and SOUT2.

[0092] In step S530, the charge neutralizing capacitor CT connected across the two output terminals OUT1 and OUT2 of the amplifier 110 receives charges from the two output terminals OUT1 and OUT2 of the amplifier 110 during the estimation period, and provides charges to the level-boosting capacitors CLS1 and CLS2 of the two capacitor circuits 120A and 120B during the level-boosting period.

[0093] It should be noted that the above-mentioned implementation is only an example. In other embodiments, those skilled in the art may make changes without departing from the spirit of the present invention.

[0094] In summary, the switched capacitor amplifier device and method for improving level boosting in the present invention can compensate for the current supply capability of the amplifier during the level boosting cycle by disposing a charge neutralizing capacitor, allowing the voltage of the level boosting capacitor to quickly stabilize, thereby improving the speed of level boosting.

[0095] Although the embodiments of the present disclosure are described above, these embodiments are not intended to limit the present disclosure. Persons skilled in the art may make changes to the technical features of the present disclosure based on the explicit or implicit content of the present disclosure. All such changes may fall within the scope of patent protection sought by the present disclosure. In other words, the scope of patent protection of the present disclosure shall be determined by the claims of this specification.

Claims

1. A switched capacitor amplifier device for improving level boosting, comprising: an amplifier comprising two input terminals and two output terminals; Two capacitor circuits, corresponding to one of the two signal input terminals and one of the two signal output terminals, respectively, and each comprising a sampling capacitor circuit, a load capacitor, and a level-boosting capacitor, wherein the sampling capacitor circuit is configured to receive one of the two input signals from one of the two signal input terminals during a sampling period, sample the received one of the two input signals, and output the sample to one of the two input terminals of the amplifier; as well as a charge neutralization capacitor connected across the two output terminals of the amplifier; wherein the load capacitor and the level-boosting capacitor are connected to one of the two output terminals of the amplifier in a plurality of ways, such that the load capacitor is first charged according to the output of the amplifier at one of the two output terminals in an estimation cycle, and then the load capacitor is charged by the level-boosting capacitor to achieve level boosting in a level-boosting cycle, so that the load capacitor generates one of the two output signals through one of the two signal output terminals; The charge neutralizing capacitor is configured to receive charges from the two output terminals of the amplifier during the estimation period and provide charges to the level-boosting capacitors of the two capacitor circuits during the level-boosting period.

2. The switched capacitor amplifier device of claim 1 , wherein the load capacitor is electrically coupled between a first connection terminal and a ground terminal, the level-boosting capacitor is electrically coupled between the first connection terminal and a second connection terminal, and the first connection terminal is further electrically coupled to the signal output terminal; During the sampling period, the first connection terminal is electrically coupled to one of the two output terminals of the amplifier, the second connection terminal is grounded, the two sampling input terminals of the sampling capacitor circuit are electrically coupled to only one of the two signal input terminals to receive the input signal for sampling, and a sampling output terminal of the sampling capacitor circuit is electrically coupled to one of the two input terminals of the amplifier and is also grounded; During the estimation period, the first connection terminal and the second connection terminal are respectively electrically coupled to one of the two output terminals of the amplifier, a first of the two sampling input terminals of the sampling capacitor circuit is grounded and a second of the two sampling input terminals is electrically coupled to the first connection terminal, and the sampling output terminal is electrically coupled to one of the two input terminals of the amplifier and is not grounded, so that after the sampled input signal is fed into one of the two input terminals, the amplifier charges the load capacitor and the level-boosting capacitor through one of the two output terminals and the first connection terminal; and During the level-boosting period, the first of the two sampling input terminals of the sampling capacitor circuit is grounded and the second is electrically coupled to the first connection terminal. The sampling output terminal is electrically coupled to one of the two input terminals of the amplifier and is not grounded. The first connection terminal is not electrically coupled to one of the two output terminals of the amplifier, and the second connection terminal is electrically coupled to one of the two output terminals of the amplifier, so that the level-boosting capacitor charges the load capacitor.

3. The switched capacitor amplifier device as claimed in claim 2, wherein the charge neutralization capacitor is configured to provide charge during the level boosting period to neutralize the charge of the level boosting capacitors of the two capacitor circuits at the second connection terminal.

4. The switched capacitor amplifier device of claim 3 , wherein the charge neutralization capacitor has a first voltage of V1 corresponding to the second connection terminal after receiving charge, the second connection terminal has a second voltage of V2 in an initial section of the level boosting cycle, the load capacitor and the level boosting capacitor have an equivalent capacitance of Ce, a target voltage of the second connection terminal is Vt, and a third capacitance of the charge neutralization capacitor is Ct for charge neutralization. Where 2Ct×V1+Ce×V2=Vt×(2Ct+Ce).

5. The switched capacitor amplifier device as claimed in claim 1 , wherein the level-boosting capacitor and the charge-neutralizing capacitor are each a variable capacitor, and each of the level-boosting capacitor and the charge-neutralizing capacitor has a capacitance value that is adjusted according to a change in a DC gain of the amplifier.

6. A method for improving level boosting in a switched capacitor amplifier, applied to a switched capacitor amplifier device, comprising: A sampling capacitor circuit of each of the two capacitor circuits receives one of the two input signals from one of the two signal input terminals in a sampling period, samples the received signal, and outputs the sample to one of the two input terminals of an amplifier; establishing a plurality of connections between a load capacitor and a level-boosting capacitor of one of the two capacitor circuits and one of the two output terminals of the amplifier, so that the load capacitor is first charged according to the output of the amplifier at one of the two output terminals in an estimation cycle, and then the load capacitor is charged by the level-boosting capacitor to achieve level boosting in a level-boosting cycle, so that the load capacitor generates one of the two output signals through one of the two signal output terminals; and A charge neutralizing capacitor connected across the two output terminals of the amplifier receives charges according to the two output terminals of the amplifier during the estimation period, and provides charges to the level-boosting capacitors of the two capacitor circuits during the level-boosting period.

7. The switched capacitor amplification method of claim 6 , wherein the load capacitor is electrically coupled between a first connection terminal and a ground terminal, the level boosting capacitor is electrically coupled between the first connection terminal and a second connection terminal, and the first connection terminal is further electrically coupled to the signal output terminal; During the sampling period, the first connection terminal is electrically coupled to one of the two output terminals of the amplifier, the second connection terminal is grounded, the two sampling input terminals of the sampling capacitor circuit are electrically coupled to only one of the two signal input terminals to receive the input signal for sampling, and a sampling output terminal of the sampling capacitor circuit is electrically coupled to one of the two input terminals of the amplifier and grounded. During the estimation period, the first connection terminal and the second connection terminal are respectively electrically coupled to one of the two output terminals of the amplifier, a first of the two sampling input terminals of the sampling capacitor circuit is grounded and a second is electrically coupled to the first connection terminal, and the sampling output terminal is electrically coupled to one of the two input terminals of the amplifier and is not grounded, so that after the sampled input signal is fed into one of the two input terminals, the amplifier charges the load capacitor and the level-boosting capacitor through one of the two output terminals and the first connection terminal; and During the level-boosting period, the first of the two sampling input terminals of the sampling capacitor circuit is grounded and the second is electrically coupled to the first connection terminal. The sampling output terminal is electrically coupled to one of the two input terminals of the amplifier and is not grounded. The first connection terminal is not electrically coupled to one of the two output terminals of the amplifier, and the second connection terminal is electrically coupled to one of the two output terminals of the amplifier, so that the level-boosting capacitor charges the load capacitor.

8. The switched capacitor amplification method according to claim 7, further comprising: The charge neutralization capacitor is configured to provide charge during the level raising period to neutralize the charge of the level raising capacitors of the two capacitor circuits at the second connection end.

9. The switched capacitor amplification method of claim 8 , wherein the charge neutralization capacitor has a first voltage of V1 corresponding to the second connection terminal after receiving charge, the second connection terminal has a second voltage of V2 in an initial section of the level boosting cycle, the load capacitor and the level boosting capacitor have an equivalent capacitance of Ce, a target voltage of the second connection terminal is Vt, and a third capacitance of the charge neutralization capacitor is Ct for charge neutralization. Where 2Ct×V1+Ce×V2=Vt×(2Ct+Ce).

10. The switched capacitor amplification method according to claim 6, wherein the level-boosting capacitor and the charge-neutralizing capacitor are each a variable capacitor, and each of the level-boosting capacitor and the charge-neutralizing capacitor has a capacitance value that is adjusted according to a change in a DC gain of the amplifier.

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