Vector data processing method, apparatus and device

Abstract

The application provides a vector data processing method, device and equipment, and relates to compiler optimization technology. The method comprises the following steps: obtaining at least two to-be-processed vectors and a preset vector in a selector; wherein, the to-be-processed vectors and the preset vector each comprise a plurality of element values and an index corresponding to each element value; determining a matching relationship between the preset vector and preset fixed feature information; the fixed feature information represents order rule information of the plurality of element values; performing transformation processing on the preset vector according to the at least two to-be-processed vectors and the matching relationship, to obtain a transformed selector; the transformed selector comprises a transformed vector corresponding to the preset vector; generating a vector shuffle instruction according to the transformed selector and the at least two to-be-processed vectors, and sending the vector shuffle instruction to a target processor. The application solves the technical problem of low program execution efficiency.

Description

Technical Field

[0001] This application relates to compiler optimization techniques, and more particularly to a vector data processing method, apparatus, and device. Background Technology

[0002] Currently, in modern computer processors, vector shuffling instructions need to be generated and executed in order to improve program execution speed.

[0003] In the prior art, when generating vector shuffling instructions, the compiler usually performs vector shuffling operations on multiple vectors to be processed and the vectors in the selector to obtain vector shuffling instructions, and then passes the vector shuffling instructions to the processor. The processor executes the target program in the processor according to the received vector shuffling instructions.

[0004] However, in the existing technology, due to hardware complexity, hardware design costs and other reasons, the parameters provided by the processor, the concatenation method of the vector to be processed, the selector content format, etc., are very different from the vector shuffling operation of the compiler front end. This causes the processor to be unable to accurately identify the vector shuffling instructions provided by the compiler, resulting in errors in the execution of the program in the processor, and thus the low execution efficiency of the program in the processor. Summary of the Invention

[0005] This application provides a vector data processing method, apparatus, and device to solve the technical problem of low program execution efficiency.

[0006] In a first aspect, this application provides a vector data processing method applied to an electronic device; the method includes:

[0007] Obtain at least two vectors to be processed and obtain a preset vector in the selector; wherein, both the vector to be processed and the preset vector include multiple element values ​​and an index corresponding to each element value, each element value corresponds to an element, and the selector is used to indicate the position information of the element pointed to by each element value in the preset vector;

[0008] Determine the matching relationship between the preset vector and preset fixed feature information; wherein, the fixed feature information represents the order rule information of multiple element values;

[0009] Based on at least two vectors to be processed and the matching relationship, the preset vector is transformed to obtain a transformed selector; wherein, the transformed selector includes a transformed vector corresponding to the preset vector;

[0010] Based on the transformed selector and at least two vectors to be processed, a vector shuffling instruction is generated and sent to the target processor; wherein, the vector shuffling instruction is used by the target processor to execute the target program within the target processor.

[0011] Further, the vector shuffling instruction includes operation instructions for the transformed selector and at least two vectors to be processed. The vector shuffling instruction is used by the target processor to split the at least two vectors to be processed to obtain two sub-vectors corresponding to each vector to be processed, and to split the transformed vector in the transformed selector corresponding to the preset vector to obtain two sub-selectors; to concatenate the two sub-vectors corresponding to each vector to be processed to obtain multiple first temporary vectors; wherein each first temporary vector corresponds to a sub-selector; to shuffle the first temporary vectors corresponding to the sub-selectors through each sub-selector to obtain multiple first vectors; to concatenate the multiple first vectors to obtain a target vector; and to execute the target program in the target processor according to the target vector.

[0012] Further, determining the matching relationship between the preset vector and preset fixed feature information includes:

[0013] Determine the order information of multiple element values ​​in the preset vector;

[0014] Based on the order information of multiple element values, a matching relationship is determined between the preset vector and preset fixed feature information; wherein, the order rule information represented by the fixed feature information includes first order rule information and second order rule information, the first order rule information indicates grouping according to preset grouping rules, and the second order rule information indicates that the element values ​​in the preset vector cover any vector to be processed; the matching relationship includes a first matching relationship corresponding to the first order rule information and a second matching relationship corresponding to the second order rule information.

[0015] Further, based on at least two vectors to be processed and the matching relationship, the preset vector is transformed to obtain a transformed selector, including:

[0016] If the matching relationship is determined to be a first matching relationship or a second matching relationship, then the first transformation strategy information corresponding to both the first matching relationship and the second matching relationship is determined;

[0017] Based on at least two vectors to be processed and the first transformation strategy information, the preset vector is transformed to obtain the transformed selector.

[0018] Further, based on at least two vectors to be processed and the first transformation strategy information, the preset vector is transformed to obtain a transformed selector, including:

[0019] At least two vectors to be processed are concatenated to generate a second temporary vector;

[0020] Each element value in the preset vector is used as the first index in the second temporary vector, and the first element value corresponding to each first index is determined sequentially in the second temporary vector;

[0021] Replace each element value in the preset vector with the first element value corresponding to each first index to obtain the transformed vector in the transformed selector that corresponds to the preset vector.

[0022] Further, based on at least two vectors to be processed and the matching relationship, the preset vector is transformed to obtain a transformed selector, including:

[0023] If the matching relationship is determined to be a matching relationship other than the first matching relationship and the second matching relationship, then the other matching relationship is determined to correspond to the second transformation strategy information;

[0024] Based on at least two vectors to be processed and the second transformation strategy information, the preset vector is transformed to obtain the transformed selector.

[0025] Further, based on at least two vectors to be processed and the second transformation strategy information, the preset vector is transformed to obtain a transformed selector, including:

[0026] Based on the second transformation strategy information, multiple element values ​​within the preset vector are read and processed sequentially;

[0027] If it is determined that the element value being read is within the preset first interval, then skip the element values ​​within the first interval and perform interval judgment on the next element value to be read.

[0028] If it is determined that the next element value to be read is located within the preset second interval, an offset value is generated based on the number of element values ​​in the preset vector and the number of element values ​​in at least two vectors to be processed. The element value located within the second interval is then transformed based on the offset value to obtain the transformed second element value.

[0029] Based on the skipped element values ​​located in the first interval and the second element value, a transformed selector is obtained; wherein, the transformed selector includes a second transformation vector corresponding to the preset vector, and the second transformation vector includes the skipped element values ​​located in the first interval and the second element value.

[0030] Furthermore, the method also includes:

[0031] If any element value read is determined to be within the preset third interval, a transformation failure signal is generated, and the reading process of the preset vector is stopped.

[0032] Furthermore, the method also includes:

[0033] If the first position information of the element value in the preset vector in the selector is different from the second position information of the element value in the first vector, a shuffling auxiliary instruction is generated.

[0034] Secondly, this application provides a vector data processing apparatus for use in electronic devices; the apparatus includes:

[0035] An acquisition unit is used to acquire at least two vectors to be processed and to acquire a preset vector in a selector; wherein, both the vectors to be processed and the preset vector include multiple element values ​​and an index corresponding to each element value, each element value corresponds to an element, and the selector is used to indicate the position information of the element pointed to by each element value in the preset vector;

[0036] A determining unit is used to determine the matching relationship between the preset vector and preset fixed feature information; wherein, the fixed feature information represents the order rule information of multiple element values;

[0037] A transformation unit is configured to transform the preset vector based on at least two vectors to be processed and the matching relationship to obtain a transformed selector; wherein the transformed selector includes a transformation vector corresponding to the preset vector;

[0038] The first generation unit is configured to generate a vector shuffling instruction based on the transformed selector and at least two vectors to be processed, and send the vector shuffling instruction to the target processor; wherein the vector shuffling instruction is used by the target processor to execute the target program within the target processor.

[0039] Further, the vector shuffling instruction includes operation instructions for the transformed selector and at least two vectors to be processed. The vector shuffling instruction is used by the target processor to split the at least two vectors to be processed to obtain two sub-vectors corresponding to each vector to be processed, and to split the transformed vector in the transformed selector corresponding to the preset vector to obtain two sub-selectors; to concatenate the two sub-vectors corresponding to each vector to be processed to obtain multiple first temporary vectors; wherein each first temporary vector corresponds to a sub-selector; to shuffle the first temporary vectors corresponding to the sub-selectors through each sub-selector to obtain multiple first vectors; to concatenate the multiple first vectors to obtain a target vector; and to execute the target program in the target processor according to the target vector.

[0040] Further, the determining unit includes:

[0041] The first determining module is used to determine the order information of multiple element values ​​in the preset vector;

[0042] The second determining module is used to determine the matching relationship between the preset vector and preset fixed feature information based on the order information of multiple element values; wherein, the order rule information represented by the fixed feature information includes first order rule information and second order rule information, the first order rule information indicates grouping according to preset grouping rules, and the second order rule information indicates that the element values ​​in the preset vector cover any vector to be processed; the matching relationship includes a first matching relationship corresponding to the first order rule information and a second matching relationship corresponding to the second order rule information.

[0043] Further, the transformation unit includes:

[0044] The third determining module is used to determine the first transformation strategy information corresponding to either the first matching relationship or the second matching relationship if the matching relationship is determined to be a first matching relationship or a second matching relationship.

[0045] The first transformation module is used to transform a preset vector based on at least two vectors to be processed and the first transformation strategy information to obtain a transformed selector.

[0046] Further, the first transformation module includes:

[0047] The first generation submodule is used to concatenate at least two vectors to be processed to generate a second temporary vector;

[0048] The determination submodule is used to determine the first element value corresponding to each first index in the second temporary vector, using each element value in the preset vector as the first index;

[0049] The first transformation submodule is used to replace each element value in the preset vector with the first element value corresponding to each first index, so as to obtain the transformation vector in the transformed selector that corresponds to the preset vector.

[0050] Further, the transformation unit includes:

[0051] The fourth determining module is used to determine the second transformation strategy information corresponding to the other matching relationship if the matching relationship is determined to be a matching relationship other than the first matching relationship and the second matching relationship.

[0052] The second transformation module is used to transform the preset vector according to at least two vectors to be processed and the second transformation strategy information to obtain the transformed selector.

[0053] Furthermore, the second transformation module includes:

[0054] The reading submodule is used to read and process multiple element values ​​in the preset vector sequentially according to the second transformation strategy information;

[0055] The skip submodule is used to skip element values ​​within the first preset interval if the element value being read is determined to be within the first interval, and then perform interval judgment on the next element value to be read.

[0056] The second transformation submodule is used to generate an offset value based on the number of element values ​​in the preset vector and the number of element values ​​in at least two vectors to be processed if it is determined that the next element value to be read is located in the preset second interval, and then transform the element value located in the second interval according to the offset value to obtain the transformed second element value.

[0057] The second generation submodule is used to obtain a transformed selector based on the skipped element values ​​located in the first interval and the second element value; wherein the transformed selector includes a second transformation vector corresponding to the preset vector, and the second transformation vector includes the skipped element values ​​located in the first interval and the second element value.

[0058] Furthermore, the device also includes:

[0059] The third generation submodule is used to generate a transformation failure signal and stop reading the preset vector if it is determined that any element value read is within the preset third interval.

[0060] Furthermore, the device also includes:

[0061] The second generation unit is used to generate a shuffling auxiliary instruction if it is determined that the first position information of the element value in the preset vector in the selector is different from the second position information of the element value in the preset vector in the first vector.

[0062] Thirdly, this application provides an electronic device, including a memory and a processor, wherein the memory stores a computer program that can run on the processor, and the processor executes the computer program to implement the method described in the first aspect.

[0063] Fourthly, this application provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the method described in the first aspect.

[0064] Fifthly, this application provides a computer program product, including a computer program that, when executed by a processor, implements the method described in the first aspect.

[0065] This application provides a vector data processing method, apparatus, and device, which acquires at least two vectors to be processed and a preset vector in a selector; wherein both the vectors to be processed and the preset vector include multiple element values ​​and an index corresponding to each element value, each element value corresponds to an element, and the selector is used to indicate the position information of the element pointed to by each element value in the preset vector. A matching relationship between the preset vector and preset fixed feature information is determined; wherein the fixed feature information represents the order rule information of multiple element values. Based on the at least two vectors to be processed and the matching relationship, the preset vector is transformed to obtain a transformed selector; wherein the transformed selector includes a transformed vector corresponding to the preset vector. Based on the transformed selector and the at least two vectors to be processed, a vector shuffling instruction is generated and sent to a target processor; wherein the vector shuffling instruction is used by the target processor to execute a target program within the target processor. In this solution, without altering the hardware design, the preset vectors in the selector are judged based on the fixed characteristic information of the selector provided by the compiler front-end. The selectors that conform to the fixed characteristic information are then transformed to obtain the transformed selector. Subsequently, vector shuffling instructions are generated based on the transformed selector and the vector to be processed, enabling the compiler to successfully complete vectorization optimization. This allows the compiler to generate vector shuffling instruction code that is more efficient than scalar instruction code with the same behavior, and ensures that the behavior of the generated program in vector shuffling operations is consistent with that of the compiler front-end. Thus, the program's running efficiency is improved without compromising program correctness, solving the technical problem of low program execution efficiency. Attached Figure Description

[0066] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0067] Figure 1 A flowchart illustrating a vector data processing method provided in an embodiment of this application;

[0068] Figure 2 A flowchart illustrating another vector data processing method provided in an embodiment of this application;

[0069] Figure 3 A flowchart illustrating yet another vector data processing method provided in an embodiment of this application;

[0070] Figure 4 This is a schematic diagram of the structure of a vector data processing device provided in an embodiment of this application;

[0071] Figure 5 This is a schematic diagram of another vector data processing device provided in an embodiment of this application;

[0072] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0073] Figure 7 This is a block diagram of an electronic device provided in an embodiment of this application.

[0074] The accompanying drawings have illustrated specific embodiments of this disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0075] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure.

[0076] In one example, in modern computer processors, vector shuffling instructions need to be generated and executed to improve program execution speed. In existing technologies, generating vector shuffling instructions typically involves the compiler performing a vector shuffling operation on multiple vectors to be processed and the vectors within a selector to obtain the vector shuffling instructions, which are then passed to the processor. The processor executes the target program based on the received vector shuffling instructions. However, due to hardware complexity and design costs, the parameters provided by the processor, the concatenation method of the vectors to be processed, and the format of the selector content often differ significantly from the vector shuffling operation performed by the compiler. This can lead to the processor being unable to accurately recognize the vector shuffling instructions provided by the compiler, resulting in errors in the execution of the program within the processor and consequently, lower execution efficiency.

[0077] This application provides a vector data processing method, apparatus, and device, which aims to solve the above-mentioned technical problems in the prior art.

[0078] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0079] Figure 1 This is a flowchart illustrating a vector data processing method provided in an embodiment of this application, as shown below. Figure 1 As shown, the method includes:

[0080] 101. Obtain at least two vectors to be processed and obtain a preset vector in the selector; wherein, both the vectors to be processed and the preset vector include multiple element values ​​and an index corresponding to each element value, each element value corresponds to an element, and the selector is used to indicate the position information of the element pointed to by each element value in the preset vector.

[0081] For example, the executing entity of this embodiment can be an electronic device, a terminal device, a vector data processing device or apparatus, or other apparatus or apparatus capable of executing this embodiment, and there is no limitation thereto. In this embodiment, the executing entity is described as an electronic device.

[0082] First, the electronic device is equipped with a compiler. The electronic device needs to acquire at least two vectors to be processed and a preset vector from a selector, where each element in the vector represents a binary number. For example, two vectors to be processed, v1 and v2, can be acquired, along with a preset vector v3 from the selector. Each vector (v1, v2, and v3) includes multiple element values ​​and an index corresponding to each element value. The selector indicates the position information of the element pointed to by each element value in the preset vector. The number of indices in a vector represents the number of elements in the vector; that is, the number of indices equals the length of the vector. The number of indices in vector v1 is equal to the number of indices in vector v2, and the number of indices in vector v2 is equal to the number of indices in the preset vector v3 from the selector. In other words, the length of vector v1 = the length of vector v2 = the length of the preset vector v3 = the number of indices in vector v1.

[0083] 102. Determine the matching relationship between the preset vector and the preset fixed feature information; wherein, the fixed feature information represents the order rule information of multiple element values.

[0084] For example, the fixed feature information is information pre-set by the electronic device. The fixed feature information includes multiple order rule information about element values, namely, first order rule information and second order rule information. The first order rule information indicates that the vector is divided into multiple groups based on at least two identical and adjacent element values, and the difference between the element values ​​of any two adjacent groups is equal. The second order rule information indicates that the element values ​​in the preset vector cover any vector to be processed.

[0085] The electronic device first determines the order information of multiple element values ​​in a preset vector. Then, it compares the order information of multiple element values ​​in the preset vector with first order rule information and second order rule information in sequence. If multiple element values ​​in the preset vector satisfy the first order rule information, a matching relationship between the preset vector and preset fixed feature information is determined, which is the first matching relationship corresponding to the first order rule information. If multiple element values ​​in the preset vector do not satisfy the first order rule information, the order information of multiple element values ​​in the preset vector is further compared with the second order rule information. If multiple element values ​​in the preset vector satisfy the second order rule information, a matching relationship between the preset vector and preset fixed feature information is determined, which is the second matching relationship corresponding to the second order rule information.

[0086] 103. Based on at least two vectors to be processed and the matching relationship, transform the preset vector to obtain the transformed selector; wherein the transformed selector includes the transformed vector corresponding to the preset vector.

[0087] For example, the electronic device can first determine the transformation strategy information corresponding to the matching relationship, and then perform transformation processing on the preset vector according to the transformation strategy information and at least two vectors to be processed to obtain the transformed vector. Since the preset vector is located in the selector, the transformed vector is still located in the selector, that is, the transformed selector can be obtained.

[0088] For example, if the electronic device determines that the matching relationship is either a first matching relationship or a second matching relationship, it determines the first transformation strategy information corresponding to either the first or second matching relationship. Then, based on the first transformation strategy information, it concatenates the ends of the two vectors v1 and the beginning and end of v2 to generate a temporary vector v4, where the length of the temporary vector v4 equals the length of vector v1 plus the length of vector v2. Each element value in the preset vector v3 is used as the first index in the temporary vector v4. The first element value corresponding to each first index is determined sequentially in the temporary vector, and each element value in the preset vector v3 is replaced with the first element value corresponding to each first index, resulting in a transformed selector. The transformed selector includes the first transformation vector corresponding to the preset vector.

[0089] Alternatively, if the electronic device determines that the matching relationship is other than the first and second matching relationships, it determines the second transformation strategy information corresponding to the other matching relationship. Then, based on the second transformation strategy information, it sequentially reads and processes multiple element values ​​within a preset vector, comparing each element value with multiple preset intervals. These preset intervals are pre-defined numerical ranges, which can be customized or automatically generated, and are not limited in this regard. If it is determined that the read element value is within a preset first interval, then the element values ​​within the first interval are skipped; that is, no processing is performed on the element values ​​within the first interval, and the interval judgment is performed on the next read element value. If the read element value is determined to be within a preset second interval, the number of element values ​​in the preset vector and the number of element values ​​in the two vectors to be processed, v1 and v2, are determined. Since the number of element values ​​in the preset vector = the number of element values ​​in vector v1 = the number of element values ​​in vector v2 = 8, 8 is divided by 2 = 4. Taking the negative value of 4, we get an offset value of -4. Based on the offset value -4, the element values ​​located in the second interval are transformed to obtain the transformed second element value. Finally, based on the skipped element values ​​located in the first interval and the transformed second element value, a transformed selector is obtained. The transformed selector includes the second transformation vector corresponding to the preset vector. The second transformation vector includes the skipped element values ​​located in the first interval and the transformed second element value. If any read element value is determined to be within a preset third interval, a transformation failure signal is generated, and the reading and processing of the preset vector is stopped, thus ending the process of this embodiment.

[0090] 104. Based on the transformed selector and at least two vectors to be processed, generate a vector shuffle instruction and send the vector shuffle instruction to the target processor; wherein, the vector shuffle instruction is used by the target processor to execute the target program within the target processor.

[0091] For example, the compiler includes a list of instruction definitions for the target processors it supports. This list contains the instruction header and parameter definitions for each instruction. The parameter definitions describe the number of parameters, parameter requirements, and other information. Vector shuffling instructions are included in the compiler's instruction definition list. When generating vector shuffling instructions, the compiler in the electronic device selects the corresponding instruction header and parameter definitions from this list based on the instructions to be generated. Then, based on the parameter definitions, it concatenates the instruction header with the aforementioned selector and the vector to be processed, thus obtaining the final vector shuffling instruction. Finally, the vector shuffling instruction is sent to the target processor. Upon receiving the vector shuffling instruction, the target processor executes it, thereby enabling the execution of the target program within the target processor.

[0092] In this embodiment, at least two vectors to be processed are obtained, and a preset vector in a selector is also obtained. Both the vectors to be processed and the preset vector include multiple element values ​​and an index corresponding to each element value. Each element value corresponds to an element, and the selector is used to indicate the position information of the element pointed to by each element value in the preset vector. A matching relationship between the preset vector and preset fixed feature information is determined; wherein the fixed feature information represents the order rule information of multiple element values. Based on the at least two vectors to be processed and the matching relationship, the preset vector is transformed to obtain a transformed selector; wherein the transformed selector includes a transformed vector corresponding to the preset vector. Based on the transformed selector and the at least two vectors to be processed, a vector shuffling instruction is generated and sent to the target processor; wherein the vector shuffling instruction is used by the target processor to execute the target program within the target processor. In this solution, without altering the hardware design, the preset vectors in the selector are judged based on the fixed characteristic information of the selector provided by the compiler front-end. The selectors that conform to the fixed characteristic information are then transformed to obtain the transformed selector. Subsequently, vector shuffling instructions are generated based on the transformed selector and the vector to be processed, enabling the compiler to successfully complete vectorization optimization. This allows the compiler to generate vector shuffling instruction code that is more efficient than scalar instruction code with the same behavior, and ensures that the behavior of the generated program in vector shuffling operations is consistent with that of the compiler front-end. Thus, the program's running efficiency is improved without compromising program correctness, solving the technical problem of low program execution efficiency.

[0093] Figure 2A flowchart illustrating another vector data processing method provided in this application embodiment is shown below. Figure 2 As shown, the method includes:

[0094] 201. Obtain at least two vectors to be processed, and obtain a preset vector in the selector; wherein, the vector includes multiple element values ​​and an index corresponding to each element value, and the selector represents the position information of each element value in the preset vector.

[0095] For example, this step can be referred to Figure 1 Step 101 in the text will not be repeated here.

[0096] 202. Determine the order information of multiple element values ​​in a preset vector.

[0097] For example, the electronic device determines the order information of multiple element values ​​in a preset vector. The order information includes: whether there are at least two identical and adjacent element values; whether the multiple element values ​​in the preset vector can be divided into multiple groups, with the element values ​​in each group being identical and consecutive in position within the selector; or whether the element values ​​within the selector cover one and only one vector to be processed, etc.

[0098] 203. Based on the order information of multiple element values, determine the matching relationship between the preset vector and the preset fixed feature information; wherein, the order rule information represented by the fixed feature information includes first order rule information and second order rule information, the first order rule information indicates that the vector is grouped according to the preset grouping rule, and the second order rule information indicates that the element values ​​in the preset vector cover any vector to be processed; the matching relationship includes a first matching relationship corresponding to the first order rule information and a second matching relationship corresponding to the second order rule information.

[0099] For example, the fixed feature information includes various order rule information regarding element values, namely, first order rule information and second order rule information. The first order rule information indicates that the vector is divided into multiple groups based on at least two identical and adjacent element values, and the difference between the element values ​​of any two adjacent groups is equal. The second order rule information indicates that the element values ​​in the preset vector cover any vector to be processed. The matching relationship includes a first matching relationship corresponding to the first order rule information and a second matching relationship corresponding to the second order rule information.

[0100] The electronic device compares the order information of multiple element values ​​in a preset vector with first order rule information and second order rule information in sequence. If the multiple element values ​​in the preset vector satisfy the first order rule information, a matching relationship is determined between the preset vector and preset fixed feature information, which is the first matching relationship corresponding to the first order rule information. If the multiple element values ​​in the preset vector do not satisfy the first order rule information, the order information of multiple element values ​​in the preset vector is further compared with the second order rule information. If the multiple element values ​​in the preset vector satisfy the second order rule information, a matching relationship is determined between the preset vector and preset fixed feature information, which is the second matching relationship corresponding to the second order rule information. For example, the first order rule information includes dividing the vector into multiple groups based on at least two identical element values ​​and the adjacent positions of the identical element values, and the difference between the element values ​​of any two adjacent groups is equal and fixed. As shown in Table 1 below, assuming the temporary vector is w, the values ​​contained in this selector can be divided into 4 groups, the element values ​​within the group are the same and consecutive in position within the selector, and the difference between the elements in the groups is 2.

[0101] Table 1

[0102] index 0 1 2 3 4 5 6 7 Element value w[1] w[1] w[3] w[3] w[5] w[5] w[7] w[7]

[0103] As shown in Table 2 below, the elements within the selector are divided into 3 groups, with the difference in element count between each group being 3. It is worth noting that the number of elements in each group can be unequal.

[0104] Table 2

[0105] index 0 1 2 3 4 5 6 7 Element value w[0] w[0] w[0] w[3] w[3] w[3] w[6] w[6]

[0106] As shown in Table 3 below, the element values ​​within the selector cover one and only one vector to be processed. For example, in the case where a single vector has 8 elements, the index in the example below will cover the vector to be processed that is the first one in the concatenation order:

[0107] Table 3

[0108] index 0 1 2 3 4 5 6 7 Element value w[0] w[1] w[2] w[3] w[4] w[5] w[6] w[7]

[0109] It is important to note that there are no restrictions on the number or content of the fixed feature information defined in the selector parameters. The selector is only considered "not conforming to the fixed feature information" if none of the fixed feature information is matched during execution.

[0110] 204. Based on at least two vectors to be processed and the matching relationship, transform the preset vector to obtain the transformed selector.

[0111] Step 204 can be implemented in the following ways:

[0112] The first implementation of step 204: If the matching relationship is determined to be a first matching relationship or a second matching relationship, then determine the first transformation strategy information corresponding to both the first matching relationship and the second matching relationship; based on at least two vectors to be processed and the first transformation strategy information, perform transformation processing on the preset vector to obtain the transformed selector.

[0113] In one example, "based on at least two vectors to be processed and the first transformation strategy information, the preset vector is transformed to obtain the transformed selector" specifically includes: concatenating at least two vectors to be processed to generate a second temporary vector; using each element value in the preset vector as the first index in the second temporary vector, and sequentially determining the first element value corresponding to each first index in the second temporary vector; replacing each element value in the preset vector with the first element value corresponding to each first index to obtain the transformed vector in the transformed selector that corresponds to the preset vector.

[0114] The second implementation of step 204: If the matching relationship is determined to be other than the first matching relationship and the second matching relationship, then the second transformation strategy information corresponding to the other matching relationship is determined; based on at least two vectors to be processed and the second transformation strategy information, the preset vector is transformed to obtain the transformed selector.

[0115] In one example, "transforming a preset vector based on at least two vectors to be processed and second transformation strategy information to obtain a transformed selector" specifically includes: sequentially reading and processing multiple element values ​​within the preset vector according to the second transformation strategy information; if it is determined that the read element value is within a preset first interval, skipping the element values ​​within the first interval and performing interval judgment on the next read element value; if it is determined that the next read element value is within a preset second interval, generating an offset value based on the number of element values ​​in the preset vector and the number of element values ​​in at least two vectors to be processed, and transforming the element values ​​within the second interval based on the offset value to obtain transformed second element values; obtaining the transformed selector based on the skipped element values ​​within the first interval and the second element value; wherein, the transformed selector includes a second transformation vector corresponding to the preset vector, and the second transformation vector includes the skipped element values ​​within the first interval and the second element value.

[0116] In one example, if it is determined that any element value read is within a preset third interval, a transformation failure signal is generated, and the reading process of the preset vector is stopped.

[0117] For example, the electronic device can first determine the transformation strategy information corresponding to the matching relationship, and then transform the preset vector according to the transformation strategy information and at least two vectors to be processed to obtain the transformed selector, which includes the transformed vector.

[0118] For example, in the first implementation of step 204, if the electronic device determines that the matching relationship is a first matching relationship or a second matching relationship, then it determines the first transformation strategy information corresponding to both the first and second matching relationships. Then, based on the first transformation strategy information, the two vectors v1 and v2 to be processed are concatenated to generate a temporary vector v4, where the length of the temporary vector v4 is equal to the length of v1 plus the length of v2. Each element value in the preset vector v3 is used as the first index in the temporary vector v4. The first element value corresponding to each first index is determined sequentially in the temporary vector, and each element value in the preset vector v3 is replaced with the first element value corresponding to each first index, resulting in a transformed selector. The transformed selector includes the first transformation vector corresponding to the preset vector.

[0119] Alternatively, if the electronic device determines that the matching relationship is other than the first matching relationship and the second matching relationship, it determines the second transformation strategy information corresponding to the other matching relationship. Then, based on the second transformation strategy information, it sequentially reads and processes multiple element values ​​within the preset vector, comparing each element value with multiple preset intervals. If it is determined that the read element value is within the preset first interval, it skips the element values ​​within the first interval, that is, it does not perform any processing on the element values ​​within the first interval, and performs interval judgment on the next read element value. If the read element value is determined to be within a preset second interval, the number of element values ​​in the preset vector and the number of element values ​​in the two vectors to be processed, v1 and v2, are determined. Since the number of element values ​​in the preset vector = the number of element values ​​in vector v1 = the number of element values ​​in vector v2 = 8, 8 is divided by 2 = 4. Taking the negative value of 4, we get an offset value of -4. Based on the offset value -4, the element values ​​located in the second interval are transformed to obtain the transformed second element value. Finally, based on the skipped element values ​​located in the first interval and the second element value, the transformed selector is obtained. The transformed selector includes the second transformation vector corresponding to the preset vector. The second transformation vector includes the skipped element values ​​located in the first interval and the second element value. If any read element value is determined to be within a preset third interval, a transformation failure signal is generated, and the reading and processing of the preset vector is stopped. That is, if more than one failure signal is generated in the above process, the generation operation of the vector shuffling instruction is abandoned, and the process ends.

[0120] For example, selectors can be shown in Table 4 below:

[0121] Table 4

[0122] index 0 1 2 3 4 5 6 7 Element value w0[0] w0[1] w0[8] w0[9] w0[4] w0[5] w0

[12] w0

[13]

[0123] The selector does not match any of the agreed fixed feature information during execution, so it jumps to the process of reading and attempting to convert each element one by one. During the reading process, it is found that the elements at indexes 2 and 3 are located in the lower 128 bits of the selector, and the values ​​w0[8] and w0[9] are from the lower 128 elements of vector v2; the elements at indexes 4 and 5 are located in the higher 128 bits of the selector, and the values ​​w0[2] and w0[3] are from the higher 128 bits of vector v1; therefore, the offset value -4 is obtained by combining the current vector length and the number of elements. After substituting the above four elements, the selector is shown in Table 5 below:

[0124] Table 5

[0125] index 0 1 2 3 4 5 6 7 Element value w1[0] w1[1] w1[4] w1[5] w2[0] w2[1] w2[4] w2[5]

[0126] Alternatively, the selector may match a second matching relationship in the agreed-upon fixed feature information during execution, as shown in Table 6 below:

[0127] Table 6

[0128] index 0 1 2 3 4 5 6 7 Element value w0[0] w0[1] w0[2] w0[3] w0[4] w0[5] w0[6] w0[7]

[0129] The compiler passes two vectors, v1 and v2, to the backend for shuffling. Each vector has 8 elements and a length of 256 bits. During the compiler's vector shuffling operation, the two vectors v1 and v2 are concatenated into a temporary vector w0. The indices and elements of this temporary vector w0 are shown in Table 7 below.

[0130] Table 7

[0131] index 0 1 2 3 4 5 6 7 Element value v1[0] v1[1] v1[2] v1[3] v1[4] v1[5] v1[6] v1[7] index 8 9 10 11 12 13 14 15 Element value v2[0] v2[1] v2[2] v2[3] v2[4] v2[5] v2[6] v2[7]

[0132] As shown in Tables 6 and 7, the element values ​​in this selector cover the elements of vector v1 but do not include the elements of vector v2, which conforms to the definition of fixed characteristic information of selector parameters. Therefore, based on the indexing behavior of the vector to be processed by the processor's vector shuffling instruction, a new selector as shown in Table 8 is generated for the vector shuffling instruction:

[0133] Table 8

[0134] index 0 1 2 3 4 5 6 7 Element value w1[0] w1[1] w1[2] w1[3] w2[0] w2[1] w2[2] w2[3]

[0135] 205. If the first position information of the element value in the preset vector in the selector is different from the second position information of the element value in the preset vector in the first vector, generate a shuffling auxiliary instruction.

[0136] For example, this example uses the same definition of compiler shuffling operations, vectors to be processed, instruction processing parameters, and instruction behavior as the above embodiments.

[0137] The selectors are shown in Table 9 below:

[0138] Table 9

[0139] index 0 1 2 3 4 5 6 7 Element value w0[0] w0[0] w0[0] w0[3] w0[3] w0[3] w0[6] w0[6]

[0140] As shown in Table 9, the selector elements can be divided into three groups based on identical element values ​​and consecutive positions. The difference between two adjacent groups is fixed at 3 (3-0=3, 6-3=3), conforming to the aforementioned definition of fixed characteristic information for selector content. Furthermore, in this selector, the elements at indices 4 and 5 are located in the high 128 bits of the selector, and the specified elements come from the low 128 bits of v1. This falls under the category of requiring additional instructions, thus necessitating multiple instructions, including shuffling auxiliary instructions, to jointly complete the shuffling operation.

[0141] Therefore, in this example, multiple instructions are generated to complete the mixed washing operation according to the following steps:

[0142] 1. Generate a vector shuffling instruction using the modified selector and the vectors to be processed, v1 and v2, with u0 as the target vector. Append an offset value of -3 to the elements at indices 6 and 7 in the modified selector. The resulting elements are shown in Table 10 below:

[0143] Table 10

[0144] index 0 1 2 3 4 5 6 7 Element value w1[0] w1[0] w1[0] w1[3] w2[3] w2[3] w2[3] w2[3]

[0145] 2. Using v1 and v2 as source vectors, generate two vectors using a cyclic left shift (or right shift) instruction, each with a shift amount of 128 bits; the target vectors are vs1 and vs2, respectively. The content layout of these two vectors relative to v1 is shown in Table 11 below, and the content layout relative to v2 is shown in Table 12 below:

[0146] Table 11 (vs1 vector)

[0147] index 0 1 2 3 4 5 6 7 Element value v1[4] v1[5] v1[6] v1[7] v1[0] v1[1] v1[2] v1[3]

[0148] Table 12 (vs2 vectors:)

[0149] index 0 1 2 3 4 5 6 7 Element value v2[4] v2[5] v2[6] v2[7] v2[0] v2[1] v2[2] v2[3]

[0150] 3. Using vs1 and vs2 as vectors to be processed, generate vector shuffling instructions using the same selector as in step 1, with the target vector being u1.

[0151] 4. Generate a 256-bit mask vector m, and set the elements generated by the additional instruction to all 1s in binary at indices 4 and 5, and set all other elements to all 0s in binary.

[0152] 5. Using m as the mask parameter, u0 and u1 as source vectors, and d as the destination vector (in this example, d is set to u0), generate a vector bit-by-bit selection instruction. This instruction will iterate through m bit by bit and set each bit of the target vector: when the i-th bit of m is 0, the i-th bit of the target vector is set to the i-th bit of u0; conversely, when the i-th bit of m is 1, the i-th bit of the target vector is set to the i-th bit of u1.

[0153] The multiple instructions generated through the above steps can correspond to the vector shuffling behavior of the compiler front-end in the final output.

[0154] 206. Based on the transformed selector and at least two vectors to be processed, generate a vector shuffle instruction and send the vector shuffle instruction to the target processor; wherein, the vector shuffle instruction is used by the target processor to execute the target program within the target processor.

[0155] In one example, the vector shuffling instruction includes operation instructions for a transformed selector and at least two vectors to be processed. The vector shuffling instruction is used by the target processor to split the at least two vectors to be processed to obtain two sub-vectors corresponding to each vector to be processed, and to split the transformed vector in the transformed selector corresponding to a preset vector to obtain two sub-selectors; to concatenate the two sub-vectors corresponding to each vector to be processed to obtain multiple first temporary vectors; wherein each first temporary vector corresponds to a sub-selector; to shuffle the first temporary vectors corresponding to each sub-selector through each sub-selector to obtain multiple first vectors; to concatenate the multiple first vectors to obtain a target vector; and to execute the target program in the target processor according to the target vector.

[0156] For example, the shuffling operation passed by the compiler to the backend has two vectors v1 and v2 to be processed. Both vectors v1 and v2 have 8 elements and a length of 256 bits. In the compiler's vector shuffling operation, the two vectors v1 and v2 are concatenated into a temporary vector w0. The indices and elements in the temporary vector w0 are shown in Table 13 below:

[0157] Table 13

[0158] index 0 1 2 3 4 5 6 7 Element value v1[0] v1[1] v1[2] v1[3] v1[4] v1[5] v1[6] v1[7] index 8 9 10 11 12 13 14 15 Element value v2[0] v2[1] v2[2] v2[3] v2[4] v2[5] v2[6] v2[7]

[0159] The selector is a 256-bit vector with 8 elements. The target vector it indicates is derived from the elements of w0, as shown in Table 14 below:

[0160] Table 14

[0161] index 0 1 2 3 4 5 6 7 Element value w0[0] w0[0] w0[0] w0[0] w0[4] w0[4] w0[4] w0[4]

[0162] The selector elements can be divided into two groups based on the same value and consecutive position, and the difference between two adjacent groups is fixed at 4 (4-0=4), which conforms to the aforementioned definition of fixed feature information of selector content.

[0163] The target processor's 256-bit vector shuffle instruction accepts two vectors to be processed, v1 and v2, and a selector as parameters. For example... Figure 3 As shown, Figure 3 This is a flowchart illustrating another vector data processing method provided in an embodiment of this application. Figure 3 It can be seen that when the target processor receives the vector shuffling instruction sent by the electronic device, the target processor first identifies the transformed vector corresponding to the preset vector in the transformed selector, as well as at least two vectors to be processed. Since the transformed vector corresponding to the preset vector in the transformed selector and at least two vectors to be processed all include high and low bits, in order to speed up the processing efficiency, the high and low bits need to be split. Therefore, the two vectors to be processed, v1 and v2, are split and processed respectively to obtain the first sub-vector v1(a) of the lower 128 bits and the second sub-vector v1(b) of the higher 128 bits corresponding to the vector v1 to be processed, and the first sub-vector v2(c) of the lower 128 bits and the second sub-vector v2(d) of the higher 128 bits corresponding to the vector v2 to be processed. The transformed vector corresponding to the preset vector in the transformed selector is split into a lower 128-bit sub-selector and a higher 128-bit sub-selector. The lower 128 bits of the sub-selector indicate which element of w1 the lower 128 bits of the target vector should come from, and the higher 128 bits of the sub-selector indicate which element of w2 the higher 128 bits of the target vector should come from. Then, the lower 128 bits of the first sub-vector v1(a) of the vector v1 to be processed are concatenated with the lower 128 bits of the first sub-vector v2(c) of v2 to form the first temporary vector w1. The higher 128 bits of the second sub-vector v1(b) of the vector v1 to be processed are concatenated with the higher 128 bits of the second sub-vector v2(d) of the vector v2 to be processed to form the first temporary vector w2. Both w1 and w2 are 256 bits and contain 8 elements. The first temporary vector w1 corresponds to the lower 128 bits of the sub-selector, and the first temporary vector w2 corresponds to the higher 128 bits of the sub-selector.

[0164] The table below shows the content layout of w1 and w2:

[0165] As shown in Table 15 below, the temporary vector w1 is:

[0166] Table 15

[0167] index 0 1 2 3 4 5 6 7 Element value v1[0] v1[1] v1[2] v1[3] v2[0] v2[1] v2[2] v2[3]

[0168] As shown in Table 16 below, the temporary vector w2 is:

[0169] Table 16

[0170]

[0171]

[0172] The target processor shuffles the first temporary vector w1 corresponding to the lower 128-bit sub-selector to obtain the lower 128-bit first vector, which is the lower 128-bit target vector. Then, based on the higher 128-bit sub-selector, it shuffles the first temporary vector w2 corresponding to the higher 128-bit sub-selector to obtain the higher 128-bit first vector, which is also the higher 128-bit target vector. The target processor concatenates the lower 128-bit target vector with the higher 128-bit target vector to obtain a 256-bit target vector. Finally, the target processor executes the target program within its own memory based on this 256-bit target vector.

[0173] As shown in Tables 15 and 16 above, the vector shuffling operation in the compiler front-end and the vector shuffling instruction in the target processor in this step differ significantly in their parameter processing methods and behaviors. Since the selector content in this example conforms to the definition of fixed feature information, a new selector content is generated for this feature. According to the behavior of the vector shuffling instruction in the combination of temporary vectors and target vectors, the transformed selector content elements are shown in Table 17 below:

[0174] Table 17

[0175] index 0 1 2 3 4 5 6 7 Element value w1[0] w1[0] w1[0] w1[0] w2[0] w2[0] w2[0] w2[0]

[0176] The transformed selector, combined with the original vectors v1 and v2 to be processed, is used in the vector shuffling instruction to achieve an effect in the instruction output that matches the definition of the vector shuffling operation in the compiler front-end. It should be noted that this invention does not limit the length or number of elements of any vector, whether the element values ​​are signed numbers, or the way instruction parameters are split or combined.

[0177] In this embodiment, at least two vectors to be processed are obtained, and a preset vector in a selector is also obtained. Each vector includes multiple element values ​​and an index corresponding to each element value. The selector represents the position information of each element value in the preset vector. The order information of the multiple element values ​​in the preset vector is determined. Based on the order information of the multiple element values, a matching relationship between the preset vector and preset fixed feature information is determined. The order rule information represented by the fixed feature information includes first order rule information and second order rule information. The first order rule information indicates grouping according to preset grouping rules, and the second order rule information indicates that the element values ​​in the preset vector cover any vector to be processed. The matching relationship includes a first matching relationship corresponding to the first order rule information and a second matching relationship corresponding to the second order rule information. Based on the at least two vectors to be processed and the matching relationship, the preset vector is transformed to obtain a transformed selector. If the first position information of the element values ​​in the preset vector in the selector is different from the second position information of the element values ​​in the preset vector in the first vector, a shuffling auxiliary instruction is generated. Based on the transformed selector and at least two vectors to be processed, vector shuffling instructions are generated and sent to the target processor. These instructions are used by the target processor to execute the target program. Therefore, without altering the hardware design, based on the fixed characteristic information of the selector provided by the compiler front-end, the preset vectors in the selector are judged, and selectors conforming to the fixed characteristic information are transformed to obtain the transformed selector. Then, based on the transformed selector and the vectors to be processed, vector shuffling instructions and shuffling auxiliary instructions are generated, enabling the compiler to successfully complete vectorization optimization. This allows the compiler to generate vector shuffling instruction code that is more efficient than scalar instruction code with the same behavior, and ensures that the behavior of the generated program in vector shuffling operations is consistent with the compiler front-end. Thus, without compromising program correctness, the program's execution efficiency is improved, solving the technical problem of low program execution efficiency.

[0178] Figure 4 This is a schematic diagram of the structure of a vector data processing device provided in an embodiment of this application, as shown below. Figure 4 As shown, the device is applied to an electronic device and includes:

[0179] The acquisition unit 31 is used to acquire at least two vectors to be processed and to acquire a preset vector in the selector; wherein, the vector includes multiple element values ​​and an index corresponding to each element value, and the selector represents the position information of each element value in the preset vector.

[0180] The determining unit 32 is used to determine the matching relationship between the preset vector and the preset fixed feature information; wherein, the fixed feature information represents the order rule information of multiple element values.

[0181] Transformation unit 33 is used to transform a preset vector based on at least two vectors to be processed and a matching relationship to obtain a transformed selector; wherein the transformed selector includes a transformed vector corresponding to the preset vector.

[0182] The first generation unit 34 is used to generate a vector shuffling instruction based on the transformed selector and at least two vectors to be processed, and send the vector shuffling instruction to the target processor; wherein the vector shuffling instruction is used by the target processor to execute the target program within the target processor.

[0183] The apparatus in this embodiment can execute the technical solutions in the above method. Its specific implementation process and technical principles are the same, and will not be repeated here.

[0184] Figure 5 This is a schematic diagram of another vector data processing device provided in an embodiment of this application. Figure 4 Based on the illustrated embodiments, as Figure 5 As shown, the vector shuffling instruction includes operation instructions for the transformed selector and at least two vectors to be processed. The vector shuffling instruction is used by the target processor to split the at least two vectors to be processed to obtain two sub-vectors corresponding to each vector to be processed, and to split the transformed vector in the transformed selector corresponding to the preset vector to obtain two sub-selectors; to concatenate the two sub-vectors corresponding to each vector to be processed to obtain multiple first temporary vectors; wherein each first temporary vector corresponds to a sub-selector; to shuffle the first temporary vectors corresponding to the sub-selectors through each sub-selector to obtain multiple first vectors; to concatenate the multiple first vectors to obtain the target vector; and to execute the target program in the target processor according to the target vector.

[0185] In one example, unit 32 is defined as including:

[0186] The first determining module 321 is used to determine the order information of multiple element values ​​in a preset vector.

[0187] The second determining module 322 is used to determine the matching relationship between a preset vector and preset fixed feature information based on the order information of multiple element values; wherein, the order rule information represented by the fixed feature information includes first order rule information and second order rule information, the first order rule information indicates that the vector is grouped according to a preset grouping rule, and the second order rule information indicates that the element values ​​in the preset vector cover any vector to be processed; the matching relationship includes a first matching relationship corresponding to the first order rule information and a second matching relationship corresponding to the second order rule information.

[0188] In one example, transformation unit 33 includes:

[0189] The third determining module 331 is used to determine the first transformation strategy information corresponding to either the first matching relationship or the second matching relationship if the determined matching relationship is either the first matching relationship or the second matching relationship.

[0190] The first transformation module 332 is used to transform a preset vector based on at least two vectors to be processed and the first transformation strategy information to obtain a transformed selector.

[0191] In one example, the first transformation module 332 includes:

[0192] The first generation submodule 3321 is used to concatenate at least two vectors to be processed to generate a second temporary vector.

[0193] The determination submodule 3322 is used to determine the first element value corresponding to each first index in the second temporary vector by using each element value in the preset vector as the first index.

[0194] The first transformation submodule 3323 is used to replace each element value in the preset vector with the first element value corresponding to each first index, so as to obtain the transformation vector in the transformed selector that corresponds to the preset vector.

[0195] In one example, transformation unit 33 includes:

[0196] The fourth determining module 333 is used to determine the second transformation strategy information corresponding to the other matching relationship if the determined matching relationship is other than the first matching relationship and the second matching relationship.

[0197] The second transformation module 334 is used to transform a preset vector based on at least two vectors to be processed and the second transformation strategy information to obtain a transformed selector.

[0198] In one example, the second transformation module 334 includes:

[0199] The reading submodule 3341 is used to read and process multiple element values ​​in a preset vector sequentially according to the second transformation strategy information.

[0200] The skip submodule 3342 is used to skip element values ​​within the first preset interval if it is determined that the element value being read is within the first interval, and then perform interval judgment on the next element value to be read.

[0201] The second transformation submodule 3343 is used to generate an offset value based on the number of element values ​​in the preset vector and the number of element values ​​in at least two vectors to be processed if it is determined that the next element value to be read is located in the preset second interval, and then transform the element value located in the second interval according to the offset value to obtain the transformed second element value.

[0202] The second generation submodule 3344 is used to obtain a transformed selector based on the skipped element values ​​located in the first interval and the second element value; wherein the transformed selector includes a second transformation vector corresponding to a preset vector, and the second transformation vector includes the skipped element values ​​located in the first interval and the second element value.

[0203] In one example, the device also includes:

[0204] The third generation submodule 3325 is used to generate a transformation failure signal and stop reading the preset vector if it is determined that any element value read is within a preset third interval.

[0205] In one example, the device also includes:

[0206] The second generation unit 41 is used to generate a shuffling auxiliary instruction if it is determined that the first position information of the element value in the preset vector in the selector is different from the second position information of the element value in the preset vector in the first vector. The device of this embodiment can execute the technical solution in the above method, and its specific implementation process and technical principle are the same, which will not be repeated here.

[0207] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, such as... Figure 6 As shown, the electronic device includes: a memory 51 and a processor 52.

[0208] The memory 51 stores a computer program that can run on the processor 52.

[0209] Processor 52 is configured to perform the methods provided in the embodiments described above.

[0210] The electronic device also includes a receiver 53 and a transmitter 54. The receiver 53 is used to receive instructions and data sent by an external device, and the transmitter 54 is used to send instructions and data to an external device.

[0211] Figure 7 This is a block diagram of an electronic device provided in an embodiment of this application. The electronic device may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0212] The device 600 may include one or more of the following components: a processing component 602, a memory 604, a power supply component 606, a multimedia component 608, an audio component 610, an input / output (I / O) interface 612, a sensor component 614, and a communication component 616.

[0213] Processing component 602 typically controls the overall operation of device 600, such as operations associated with display, telephone calls, data communication, camera operation, and recording. Processing component 602 may include one or more processors 620 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 602 may include one or more modules to facilitate interaction between processing component 602 and other components. For example, processing component 602 may include a multimedia module to facilitate interaction between multimedia component 608 and processing component 602.

[0214] Memory 604 is configured to store various types of data to support the operation of device 600. Examples of such data include instructions for any application or method operating on device 600, contact data, phonebook data, messages, pictures, videos, etc. Memory 604 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0215] Power supply component 606 provides power to the various components of device 600. Power supply component 606 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to device 600.

[0216] Multimedia component 608 includes a screen that provides an output interface between device 600 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 608 includes a front-facing camera and / or a rear-facing camera. When device 600 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0217] Audio component 610 is configured to output and / or input audio signals. For example, audio component 610 includes a microphone (MIC) configured to receive external audio signals when device 600 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 604 or transmitted via communication component 616. In some embodiments, audio component 610 also includes a speaker for outputting audio signals.

[0218] I / O interface 612 provides an interface between processing component 602 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0219] Sensor assembly 614 includes one or more sensors for providing state assessments of various aspects of device 600. For example, sensor assembly 614 may detect the on / off state of device 600, the relative positioning of components such as the display and keypad of device 600, changes in the position of device 600 or a component of device 600, the presence or absence of user contact with device 600, the orientation or acceleration / deceleration of device 600, and temperature changes of device 600. Sensor assembly 614 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 614 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 614 may also include an accelerometer, a gyroscope, a magnetometer, a pressure sensor, or a temperature sensor.

[0220] Communication component 616 is configured to facilitate wired or wireless communication between device 600 and other devices. Device 600 can access wireless networks based on communication standards, such as WiFi, 2G, or 3G, or combinations thereof. In one exemplary embodiment, communication component 616 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 616 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0221] In an exemplary embodiment, the apparatus 600 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0222] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 604 including instructions, which can be executed by a processor 620 of the device 600 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0223] This application also provides a non-transitory computer-readable storage medium, which, when the instructions in the storage medium are executed by the processor of an electronic device, enables the electronic device to perform the methods provided in the above embodiments.

[0224] This application also provides a computer program product, which includes: a computer program stored in a readable storage medium, at least one processor of an electronic device can read the computer program from the readable storage medium, and the at least one processor executes the computer program to cause the electronic device to perform the solution provided in any of the above embodiments.

[0225] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0226] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A vector data processing method, characterized in that, Applied to electronic devices; the method includes: Obtain at least two vectors to be processed and obtain a preset vector in the selector; wherein, both the vector to be processed and the preset vector include multiple element values ​​and an index corresponding to each element value, each element value corresponds to an element, and the selector is used to indicate the position information of the element pointed to by each element value in the preset vector; Determine the matching relationship between the preset vector and preset fixed feature information; wherein, the fixed feature information represents the order rule information of multiple element values, the order rule information includes first order rule information and second order rule information, the first order rule information indicates that grouping is performed according to preset grouping rules, and the second order rule information indicates that the element values ​​in the preset vector cover any vector to be processed; Based on at least two vectors to be processed and the matching relationship, the preset vector is transformed to obtain a transformed selector; wherein, the transformed selector includes a transformed vector corresponding to the preset vector; Based on the transformed selector and at least two vectors to be processed, a vector shuffling instruction is generated and sent to the target processor; wherein, the vector shuffling instruction is used by the target processor to execute the target program within the target processor.

2. The method according to claim 1, characterized in that, The vector shuffling instruction includes operation instructions for the transformed selector and at least two vectors to be processed. The vector shuffling instruction is used to cause the target processor to split the at least two vectors to be processed to obtain two sub-vectors corresponding to each vector to be processed. The two sub-vectors include a low-order sub-vector and a high-order sub-vector. The transformed vector in the transformed selector corresponding to the preset vector is split to obtain two sub-selectors. The low-order sub-vectors corresponding to each vector to be processed are concatenated, and the high-order sub-vectors corresponding to each vector to be processed are concatenated to obtain multiple first temporary vectors; each first temporary vector corresponds to a sub-selector; the first temporary vectors corresponding to each sub-selector are shuffled through each sub-selector to obtain multiple first vectors; the multiple first vectors are concatenated to obtain the target vector; the target program in the target processor is executed according to the target vector.

3. The method according to claim 1, characterized in that, Determining the matching relationship between the preset vector and preset fixed feature information includes: Determine the order information of multiple element values ​​in the preset vector; Based on the order information of multiple element values, a matching relationship is determined between the preset vector and preset fixed feature information; the matching relationship includes a first matching relationship corresponding to the first order rule information and a second matching relationship corresponding to the second order rule information.

4. The method according to claim 3, characterized in that, Based on at least two vectors to be processed and the matching relationship, the preset vector is transformed to obtain a transformed selector, including: If the matching relationship is determined to be a first matching relationship or a second matching relationship, then the first transformation strategy information corresponding to both the first matching relationship and the second matching relationship is determined; Based on at least two vectors to be processed and the first transformation strategy information, the preset vector is transformed to obtain the transformed selector.

5. The method according to claim 4, characterized in that, Based on at least two vectors to be processed and the first transformation strategy information, a preset vector is transformed to obtain a transformed selector, including: At least two vectors to be processed are concatenated to generate a second temporary vector; Each element value in the preset vector is used as the first index in the second temporary vector, and the first element value corresponding to each first index is determined sequentially in the second temporary vector; Replace each element value in the preset vector with the first element value corresponding to each first index to obtain the transformed vector in the transformed selector that corresponds to the preset vector.

6. The method according to claim 3, characterized in that, Based on at least two vectors to be processed and the matching relationship, the preset vector is transformed to obtain a transformed selector, including: If the matching relationship is determined to be a matching relationship other than the first matching relationship and the second matching relationship, then the other matching relationship is determined to correspond to the second transformation strategy information; Based on at least two vectors to be processed and the second transformation strategy information, the preset vector is transformed to obtain the transformed selector.

7. The method according to claim 6, characterized in that, Based on at least two vectors to be processed and the second transformation strategy information, a preset vector is transformed to obtain a transformed selector, including: Based on the second transformation strategy information, multiple element values ​​within the preset vector are read and processed sequentially; If it is determined that the element value being read is within the preset first interval, then skip the element values ​​within the first interval and perform interval judgment on the next element value to be read. If it is determined that the next element value to be read is located within the preset second interval, an offset value is generated based on the number of element values ​​in the preset vector and the number of element values ​​in at least two vectors to be processed. The element value located within the second interval is then transformed based on the offset value to obtain the transformed second element value. Based on the skipped element values ​​located in the first interval and the second element value, a transformed selector is obtained; wherein, the transformed selector includes a second transformation vector corresponding to the preset vector, and the second transformation vector includes the skipped element values ​​located in the first interval and the second element value.

8. The method according to claim 7, characterized in that, The method further includes: If any element value read is determined to be within the preset third interval, a transformation failure signal is generated, and the reading process of the preset vector is stopped.

9. The method according to any one of claims 1-8, characterized in that, The method further includes: If the first position information of the element value in the preset vector in the selector is different from the second position information of the element value in the vector to be processed, a shuffling auxiliary instruction is generated. The first position information and the second position information represent the high or low bit information of the vector.

10. A vector data processing apparatus, characterized in that, Applied to electronic devices; the device includes: An acquisition unit is used to acquire at least two vectors to be processed and to acquire a preset vector in a selector; wherein, both the vectors to be processed and the preset vector include multiple element values ​​and an index corresponding to each element value, each element value corresponds to an element, and the selector is used to indicate the position information of the element pointed to by each element value in the preset vector; A determining unit is used to determine the matching relationship between the preset vector and preset fixed feature information; wherein, the fixed feature information represents the order rule information of multiple element values, the order rule information includes first order rule information and second order rule information, the first order rule information indicates that grouping is performed according to preset grouping rules, and the second order rule information indicates that the element values ​​in the preset vector cover any vector to be processed; A transformation unit is configured to transform the preset vector based on at least two vectors to be processed and the matching relationship to obtain a transformed selector; wherein the transformed selector includes a transformation vector corresponding to the preset vector; The first generation unit is configured to generate a vector shuffling instruction based on the transformed selector and at least two vectors to be processed, and send the vector shuffling instruction to the target processor; wherein the vector shuffling instruction is used by the target processor to execute the target program within the target processor.

11. The apparatus according to claim 10, characterized in that, The vector shuffling instruction includes operation instructions for the transformed selector and at least two vectors to be processed. The vector shuffling instruction is used by the target processor to split the at least two vectors to be processed to obtain two sub-vectors corresponding to each vector to be processed. The two sub-vectors include a low-order sub-vector and a high-order sub-vector. The transformed vector in the transformed selector corresponding to the preset vector is split to obtain two sub-selectors. The low-order sub-vectors corresponding to each vector to be processed are concatenated, and the high-order sub-vectors corresponding to each vector to be processed are concatenated to obtain multiple first temporary vectors; each first temporary vector corresponds to a sub-selector; the first temporary vectors corresponding to each sub-selector are shuffled through each sub-selector to obtain multiple first vectors; the multiple first vectors are concatenated to obtain the target vector; the target program in the target processor is executed according to the target vector.

12. The apparatus according to claim 10, characterized in that, The determining unit includes: The first determining module is used to determine the order information of multiple element values ​​in the preset vector; The second determining module is used to determine the matching relationship between the preset vector and the preset fixed feature information based on the order information of multiple element values; wherein the matching relationship includes a first matching relationship corresponding to the first order rule information and a second matching relationship corresponding to the second order rule information.

13. The apparatus according to claim 12, characterized in that, The transformation unit includes: The third determining module is used to determine the first transformation strategy information corresponding to either the first matching relationship or the second matching relationship if the matching relationship is determined to be a first matching relationship or a second matching relationship. The first transformation module is used to transform a preset vector based on at least two vectors to be processed and the first transformation strategy information to obtain a transformed selector.

14. The apparatus according to claim 13, characterized in that, The first transformation module includes: The first generation submodule is used to concatenate at least two vectors to be processed to generate a second temporary vector; The determination submodule is used to determine the first element value corresponding to each first index in the second temporary vector, using each element value in the preset vector as the first index; The first transformation submodule is used to replace each element value in the preset vector with the first element value corresponding to each first index, so as to obtain the transformation vector in the transformed selector that corresponds to the preset vector.

15. The apparatus according to claim 12, characterized in that, The transformation unit includes: The fourth determining module is used to determine the second transformation strategy information corresponding to the other matching relationship if the matching relationship is determined to be a matching relationship other than the first matching relationship and the second matching relationship. The second transformation module is used to transform the preset vector according to at least two vectors to be processed and the second transformation strategy information to obtain the transformed selector.

16. The apparatus according to claim 15, characterized in that, The second transformation module includes: The reading submodule is used to read and process multiple element values ​​in the preset vector sequentially according to the second transformation strategy information; The skip submodule is used to skip element values ​​within the first preset interval if the element value being read is determined to be within the first interval, and then perform interval judgment on the next element value to be read. The second transformation submodule is used to generate an offset value based on the number of element values ​​in the preset vector and the number of element values ​​in at least two vectors to be processed if it is determined that the next element value to be read is located in the preset second interval, and then transform the element value located in the second interval according to the offset value to obtain the transformed second element value. The second generation submodule is used to obtain a transformed selector based on the skipped element values ​​located in the first interval and the second element value; wherein the transformed selector includes a second transformation vector corresponding to the preset vector, and the second transformation vector includes the skipped element values ​​located in the first interval and the second element value.

17. The apparatus according to claim 16, characterized in that, The device further includes: The third generation submodule is used to generate a transformation failure signal and stop reading the preset vector if it is determined that any element value read is within the preset third interval.

18. The apparatus according to any one of claims 10-17, characterized in that, The device further includes: The second generation unit is used to generate a shuffling auxiliary instruction if it is determined that the first position information of the element value in the preset vector in the selector is different from the second position information of the element value in the preset vector in the vector to be processed. The first position information and the second position information represent the high or low bit information of the vector.

19. An electronic device, characterized in that, The method includes a memory and a processor, wherein the memory stores a computer program that can run on the processor, and the processor executes the computer program to implement the method of any one of claims 1-9.

20. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-9.

21. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method of any one of claims 1-9.

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