A method and apparatus for identifying sequential logic

Abstract

The application provides a timing logic identification method, comprising: obtaining a process block event corresponding to a design under test; when the process block event does not match a template successfully, splitting the process block event into a plurality of process block sub-events, wherein the number of selection control structure layers of the process block sub-events is less than the number of selection control structure layers of the process block event, and the template is a description code of timing logic that can be optimized; matching the process block sub-events with the template, and determining the process block sub-events that match the template successfully as the description code of timing logic that can be optimized. The application splits the process block event into a plurality of process block sub-events with a smaller number of selection control structure layers, and then matches the split process block sub-events with a template to identify, so that the chip design developer is not limited to some fixed timing logic writing methods, the development threshold is reduced, the development efficiency is improved, and the identification accuracy of the timing logic that can be optimized and the simulation efficiency are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of EDA function simulation, in particular to a timing logic identification method and device. BACKGROUND

[0002] In the chip design process, a digital simulator needs to be used to simulate the circuit design of a chip. According to statistics, simulation covers more than 80% of the chip development cycle, and pre-simulation (also known as functional simulation) accounts for 90% of the simulation resource input, can expose more than 90% of the problems, and has the lowest cost. Therefore, the efficiency of pre-simulation to a great extent determines the length of the chip design project. If the pre-simulation period can be shortened, the effect on shortening the entire chip development cycle will be obvious.

[0003] Pre-simulation includes a simulation compilation phase and a simulation running phase. The simulation compilation phase needs to optimize and compile the hardware description language of the timing logic circuit, so as to improve the simulation efficiency of the simulation running phase, and thus shorten the simulation time. The hardware description language is used to describe a circuit. Theoretically, the same circuit can be described in multiple ways, but limited by the optimization of the simulation tool, many optimizations are based on pattern matching, and only specific writing methods can be suitable for these optimizations. If the programmer's code writing method is slightly changed, the simulation performance will not be ideal. For programmers, it is necessary to develop efficient code based on experience, which has a high threshold, poor experience for new programmers, and low development efficiency. SUMMARY

[0004] Embodiments of the present application provide a timing logic identification method and device. The process block event is split into multiple process block sub-events with fewer selection control structure layers, and then the split process block sub-events are matched and identified, so that chip design developers do not need to be limited to certain fixed timing logic writing methods, the development threshold is reduced, the development efficiency is improved, and the identification accuracy of the optimizable timing logic is improved.

[0005] In a first aspect, the present application provides a timing logic identification method, including obtaining a process block event corresponding to a design under test (DUT); when the process block event and a code template do not match successfully, splitting the process block event into multiple process block sub-events, wherein the number of selection control structure layers of the process block sub-events is less than the number of selection control structure layers of the process block event, and the code template indicates the description code of the timing logic that can be optimized; matching the process block sub-events with the code template, and determining the process block event sub-event that matches successfully as the description code of the target timing logic, which can be optimized.

[0006] The embodiment of the present application splits the process block event into a plurality of process block sub-events with less layers of selection control structure, and then performs template matching on the split process block sub-events, and identifies the process block sub-event matched successfully as the timing logic that can be optimized, so that the chip design developer does not need to be limited to some fixed timing logic writing method, and no matter what writing method is used, the timing logic optimization pass can be used to reduce the development threshold and improve the development efficiency, and the identification false positive rate of the timing logic suitable for optimization is greatly reduced to improve the identification accuracy, thereby maximizing the use of the timing logic optimization pass and improving the simulation efficiency.

[0007] In one possible implementation, when the process block event does not match the code template, splitting the process block event into a plurality of process block sub-events is implemented as follows: according to the logical relationship of the selection control structure of the process block event, the process block event is split into a plurality of process block sub-events with the number of layers of selection control structure less than or equal to a preset number of layers, and the preset number of layers is related to the number of layers of selection control structure of the template.

[0008] For example, the process block event has a plurality of layers of nested selection control structure, according to the logical relationship of the plurality of layers of nested selection control structure, the process block event is split into a plurality of single-layer selection control structures, and a plurality of process block sub-events are obtained based on the plurality of single-layer selection control structures.

[0009] In this possible implementation, the number of layers of selection control structure of the split process block sub-event is related to the number of layers of selection control structure of the code template, for example, the number of layers of selection control structure of the split process block sub-event is the same as the number of layers of selection control structure of the code template, when the template provided by the developer is relatively simple, for example, the number of layers of selection control structure supported is less, the granularity of the process block event splitting needs to be finer, and if the template provided by the developer is relatively powerful, for example, the number of layers of selection control structure supported is more, the granularity of the process block event splitting can be coarser.

[0010] In one possible implementation, the process block sub-event is a single-layer selection control structure event, that is, the process block event is directly split into a process block event with the simplest logic, and matched with the basic template, without the need for the developer to prepare a more complex template.

[0011] In another possible implementation, before splitting the process block event into a plurality of process block sub-events, the following further includes: determining that the number of layers of selection control structure of the process block event is greater than a preset number of layers, and the preset number of layers is related to the number of layers of selection control structure of the code template.

[0012] In this possible implementation, before the process block event is split, a judgment step is added to determine whether the process block event needs to be split, if the number of layers of selection control structure of the process block event meets the requirement of the template, the process block event does not need to be split, and can be directly matched with the template.

[0013] In another possible implementation, the number of write signals in the process block sub-event is less than or equal to a preset threshold (e.g., 100).

[0014] Optionally, the preset threshold is related to the number of write signals in the code template, for example, the preset threshold is the same as the number of writes in the code template.

[0015] Optionally, the preset threshold can also be customized by a user.

[0016] If the process block event contains a large number (e.g., 1000) of signal assignments, there can be a large number of invalid assignments in the simulation process, for example, the values before and after the assignment are the same. In order to avoid this situation, the process block event can be split into multiple process block sub-events with a small number of signal assignments, thereby reducing the number of assignments in the process block sub-event and reducing invalid assignments.

[0017] In a second aspect, an embodiment of the present application provides a timing logic identification device, comprising an acquisition module, a splitting module and a matching module, wherein the acquisition module is configured to acquire a process block event corresponding to a design under test (DUT), the splitting module is configured to split the process block event into multiple process block sub-events when the process block event fails to match a code template, wherein the number of selection control structure layers of the process block sub-event is less than the number of selection control structure layers of the process block event, the code template indicates a description code of timing logic that can be optimized, and the matching module is configured to match the process block sub-event with the code template, and determine a description code of target timing logic as the process block sub-event that matches successfully, wherein the description code of target timing logic can be optimized.

[0018] In one possible implementation, the splitting module is specifically configured to split the process block event into multiple process block sub-events according to the logical relationship of the selection control structure of the process block event, wherein the number of selection control structure layers of the process block sub-event is less than or equal to a preset number of layers, and the preset number of layers is related to the number of selection control structure layers of the code template.

[0019] In another possible implementation, the process block sub-event is a single-layer selection control structure event.

[0020] In another possible implementation, the splitting module is further configured to determine that the number of selection control structure layers of the process block event is greater than a preset number of layers before splitting the process block event into multiple process block sub-events, wherein the preset number of layers is related to the number of selection control structure layers of the preset code template.

[0021] In another possible implementation, the number of write signals in the process block sub-event is less than or equal to a preset threshold, and the preset threshold is related to the number of write signals in the code template.

[0022] In a third aspect, an embodiment of the present application provides a computing device, comprising a memory and a processor, the memory storing executable code, and the processor executing the executable code to implement the method provided in the first aspect of the present application.

[0023] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, storing a computer program, which, when executed in a computer, causes the computer to perform the method provided in the first aspect of the present application.

[0024] In a fifth aspect, an embodiment of the present application provides a computer program or computer program product, comprising instructions which, when executed, implement the method provided in the first aspect of the present application.

[0025] In a sixth aspect, an embodiment of the present application provides a chip, comprising at least one processor and an interface, the at least one processor determining program instructions or data through the interface; the at least one processor is configured to execute the program instructions to implement the method provided in the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 A description code schematic diagram of a sequential logic circuit;

[0027] Figure 2 A description code schematic diagram of a sequential logic circuit with more assignment signals;

[0028] Figure 3 A design flow schematic diagram of a digital chip;

[0029] Figure 4 A signaling interaction schematic diagram in a working process of a simulator;

[0030] Figure 5 An implementation flow diagram of a simulator in a simulation compilation phase;

[0031] Figure 6 A flow diagram of a sequential logic identification method provided in an embodiment of the present application;

[0032] Figure 7 A template example schematic diagram;

[0033] Figure 8 An always event schematic diagram;

[0034] Figure 9 Another always event schematic diagram;

[0035] Figure 10 Another always event schematic diagram;

[0036] Figure 11 is another schematic diagram of an always event;

[0037] Figure 12 is a schematic diagram of the always event shown in Figure 11 split to form a plurality of always sub-events;

[0038] Figure 13 is a schematic diagram of the always event shown in Figure 2 split to form a plurality of always sub-events;

[0039] Figure 14 is a schematic diagram of the implementation flow of the timing logic optimization Pass after the timing logic recognition method of the embodiments of the present application is applied;

[0040] Figure 15 is a structural schematic diagram of a timing logic recognition device provided by the embodiments of the present application;

[0041] Figure 16 is a structural schematic diagram of a computing device. DETAILED DESCRIPTION

[0042] The technical solutions of the present application will be described in further detail below with reference to the accompanying drawings and embodiments.

[0043] In order to facilitate understanding of the timing logic recognition method and device provided by the embodiments of the present application, part of the technical terms related to the embodiments of the present application will be briefly described below.

[0044] Hardware description language (HDL): a language for describing the behavior, structure and data flow of an electronic system. Using this language, the design of a digital circuit system can describe its own design idea from top to bottom (from abstract to concrete) layer by layer, and use a series of hierarchical modules to represent an extremely complex digital system. Then, using electronic design automation (EDA) tools, the design is simulated and verified layer by layer, and the modules that need to be converted into actual circuits are combined, and then converted to gate-level circuit netlist through automatic synthesis tools. Next, using automatic layout and routing tools for application-specific integrated circuits (ASIC) or field programmable gate arrays (FPGA), the netlist is converted to the specific circuit layout structure to be implemented.

[0045] Verilog: a widely used hardware description language.

[0046] VHDL (very high speed integrated circuit hardware description language): a hardware description language.

[0047] DUT (design under test): usually a hardware design written in Verilog or VHDL.

[0048] TB (testbench): usually written in SystemVerilog, a test module used to test the correctness of DUT.

[0049] Sequential logic circuit: refers to the steady-state output of the circuit at any time not only depends on the current input, but also related to the state formed by the previous input, for example, latch and flip-flop are two typical sequential logic circuits.

[0050] EDA digital simulator: a software tool for digital circuit simulation, used to verify the correctness of circuit design.

[0051] Pattern matching: the behavior of checking whether there is a certain pattern of components in a given sequence of symbols. In the field of simulation, pattern matching is often used as the basic idea of some optimization algorithms.

[0052] Signal: the abstract representation of input and output ports and wires in hardware language description, for example, variables in Verilog, wires in VHDL, etc.

[0053] Always event: (System) Verilog has a class of syntax always process, used to represent the trigger relationship between signals, we call the code block corresponding to this syntax as always event.

[0054] Digital circuits are divided into sequential logic circuits and combinational logic circuits. Sequential logic circuit refers to the steady-state output of the circuit at any time not only depends on the current input, but also related to the state formed by the previous input, typical sequential logic circuits such as latch and flip-flop. Combinational logic circuit refers to the steady-state output of the circuit at any time, only related to the value of the input variable at that time, and has nothing to do with the value of the input variable before that time.

[0055] A typical hardware description language code of a sequential logic circuit is shown in the following Figure 1 For the convenience of description, the hardware description language code is referred to as the description code hereinafter.

[0056] Figure 1The sensitive signal of the timing logic circuit corresponding to the description code in the above is clock (clk), and all the read signals in the timing logic circuit are called data (for example Figure 1 The meaning of this code segment is: whenever the rising edge of clk comes, if the value of ctrl is 1, the value of D is assigned to Q.

[0057] In the embodiments of the present application, the meaning of the description code of the timing logic circuit can be understood as a description of the timing logic of the timing logic circuit by VHDL, and therefore, the code description of the timing logic circuit can also be expressed as the code description of the timing logic.

[0058] Many optimizations in the simulator are performed on the description code of the timing logic circuit, and generally, the description code of the timing logic circuit that can be optimized is identified first, and then the optimization is performed. Therefore, the optimization effect is greatly dependent on the identification accuracy. There are generally two schemes for how to identify the description code of the timing logic circuit that can be optimized.

[0059] The first scheme is that the simulator provides a plurality of templates, if the code structure of the description code of the circuit can match the code structure of the template, the description code of the circuit is identified as the description code of the timing logic circuit that can be optimized, and the optimization can be applied, if the code structure of the description code of the circuit does not match the code structure of the template, the optimization is skipped.

[0060] Since the templates are provided by programmers, and are limited by the number and typicality of the templates, this scheme cannot identify all the user's writing methods (for example, the programmers may only provide a template of a single selection control structure, resulting in that the code of the nested selection control structure written by the user cannot be identified), that is, the false negative rate is high; in addition, the timing logic circuit with the same function can have a plurality of code writing methods, some of which can be matched with the template and are identified as the timing logic that can be optimized and is optimized, and some of which can not be matched with the template and are identified as the timing logic that cannot be optimized and is not optimized, and the timing logic that is optimized and the timing logic that is not optimized can have a large simulation performance difference, therefore, some programmers can only choose one writing method in order to obtain better simulation performance, which limits the convenience of the programmers when writing codes.

[0061] The second scheme is that no identification of the description code of the timing logic circuit is performed, and if the event is sensitive to the rising edge of the clock, it is considered as the description code of the timing logic circuit that is applicable to the optimization.

[0062] The identification of the description code of the timing logic circuit has a cost, if a very complex always event (see Figure 2)identify the timing logic circuit that can be optimized, and the cost brought by the optimization will exceed the performance benefit brought by the optimization. That is, the description code of the timing logic circuit that is not suitable for optimization is mistakenly identified as the description code of the timing logic circuit that can be optimized, and the false positive rate of the optimization identification is high.

[0063] To solve the above problems, an embodiment of the present application provides a timing logic identification method and device. Before optimization of the description code of the timing logic circuit, the description code of the timing logic circuit with multiple layers of nested selection control structures is split into the description code of the timing logic circuit with less levels of nested selection control structures or single-layer selection control structures by judging the conditions in the selection control structure of the description code of the circuit, and the split timing logic circuit description code is matched with a template, the description code matched with the template is optimized, and otherwise, it is not optimized. In this way, accurate identification of the description code of the timing logic circuit that can be optimized is realized, and the false negative rate is reduced. At the same time, the chip design developer does not need to be limited to some fixed timing logic writing method, and the timing logic circuit with the same function can be optimized by the timing logic optimization regardless of the writing method, thereby reducing the development threshold and improving the development efficiency.

[0064] Figure 3 A design flow diagram of a digital chip is shown. As shown in Figure 3 , the main flow of the digital chip design includes steps of (1) chip architecture, (2) RTL design, (3) functional simulation, (4) synthesis, (5) static timing analysis, (6) DFT design, (7) formal verification / equivalence checking, (8) layout and routing, (9) design rule checking, (10) GDS II file, and finally, the GDS II file is delivered to the manufacturer for production. The timing logic identification method and device provided by the embodiment of the present application can be applied to the functional simulation link of the digital chip design flow to improve the simulation efficiency. Since simulation occupies most of the time of the chip design flow, improving the efficiency of simulation (including the compilation efficiency and running efficiency of the simulator and the work efficiency of the developer) can effectively shorten the development cycle of the entire chip.

[0065] It should be explained that Figure 3 The design flow diagram of the digital chip shown is only an example that can be implemented, and does not constitute a limitation on the embodiment of the present application. In practice, the design flow of the digital chip can include more steps or fewer steps than Figure 3 .

[0066] Figure 3The functional simulation steps can be implemented using a simulator. The simulator performs functional simulation through a simulation compilation phase (also known as compilation period) and a simulation runtime phase (also known as runtime period). In the simulation compilation phase, the input source files (including the DUT and TB) are compiled into simulation files. In the simulation runtime phase, simulation results are obtained by running simulation software that uses the simulation files as the primary carrier. For the signaling interaction during simulator operation, please refer to [link to relevant documentation]. Figure 4 .

[0067] Figure 5 This illustrates one implementation flow of the simulation compilation stage. The simulator reads source files, which are then converted into intermediate representation (IR) by the frontend. For example, the frontend performs preprocessing, lexical analysis, and code generation on the source files to generate the corresponding IR. After generating the IR, the simulator calls N timing logic optimization passes to optimize the description code of the timing logic circuits, ultimately converting the IR into a simulation file. A timing logic optimization pass can be understood as a module in the simulator that performs analysis, optimization, and conversion on the IR. The quality of the timing logic optimization pass determines the quality of the simulation file, and thus its runtime performance. Multiple timing logic optimization passes (e.g.) Figure 5 The Pass1 to PassN in the table are used to perform different optimization tasks. The implementation methods and the scope of the Pass are also different depending on the task.

[0068] Figure 5 The Pass step in the process generally includes a step of identifying the optimizable timing logic of events in the IR, and a step of optimizing the identified timing logic.

[0069] This application provides a method for identifying timing logic, which can be applied to... Figure 5 The Pass step in the algorithm enables accurate identification of optimizable timing logic to ensure the optimization effect of Pass.

[0070] This application provides a method for identifying sequential logic, including obtaining process block events corresponding to the design under test; when a process block event does not match a template, splitting the process block event into process block sub-events with fewer control structure layers or fewer written signals; matching the process block events with the template; and determining the successfully matched process block events as description codes for optimizable sequential logic circuits.

[0071] It needs to be explained that the meaning of the process block event mentioned in the embodiments of the present application is a hardware language description of a hardware circuit, which includes the input and output of the circuit and the trigger mode, which is usually edge trigger or level trigger.

[0072] For example, the process block event is always event in Verilog hardware description language, and is process event in VHDL hardware description language. The embodiments of the present application do not specifically limit the hardware description language used, and a suitable hardware description language can be selected as needed.

[0073] The specific implementation of the timing logic recognition method provided by the embodiments of the present application is described below in the Verilog hardware description language. The implementation of the timing logic recognition method of other hardware description languages is similar, and will not be described again in the embodiments of the present application.

[0074] Figure 6 A flowchart of the timing logic recognition method provided by the embodiments of the present application. The method can be executed by any computing device, device, platform or device cluster with computing ability. The embodiments of the present application do not specifically limit the specific computing device for executing the method, and a suitable computing device can be selected for execution as needed. As shown in the figure, the timing logic recognition method comprises at least steps S601-S603. Figure 6

[0075] In step S601, the always event corresponding to the design under test is obtained.

[0076] In one example, the DUT can be directly analyzed and optimized, and the implementation of obtaining the always event corresponding to the DUT is to directly identify the always event from the hardware description language corresponding to the DUT, and obtain a plurality of always events in the hardware description language corresponding to the DUT, which are the process block events corresponding to the DUT.

[0077] In another example, the IR corresponding to the DUT can also be optimized, and the implementation of obtaining the always event corresponding to the DUT is to input the source file including the DUT into the simulator, and the source file is processed by the front end of the simulator (including preprocessing, lexical analysis and code generation, etc.), to obtain the IR corresponding to the DUT, and then the always event is identified for each segment of the IR code, and a plurality of always events in the IR are obtained, which are the always events corresponding to the DUT.

[0078] In step S602, when the always event and the code template are not matched successfully, the always event is split into a plurality of always sub-events.​

[0079] The always event is matched with a code template (for the convenience of description, it is referred to as a template hereinafter), and when the matching fails, the always event is split into multiple always sub-events with fewer layers of selection control structures.

[0080] The template is an example of the description code of a sequential logic circuit that can be optimized by a sequential logic optimization Pass in a simulator, and when the always event can be matched with the template, it indicates that the always event can be optimized by the sequential logic optimization Pass in the simulator, so as to achieve the purpose of identifying the description code of the sequential logic circuit that can be optimized.

[0081] However, due to the different writing habits of each programmer, the number of layers of the selection control structure of the written always event can be different. For example, some programmers are used to writing with multiple layers of nesting, and the written always event can have multiple layers of nested selection control structures. Therefore, the always event with multiple layers of nested selection control structures can fail to be matched with the template, and cannot be optimized by the Pass, thereby affecting the subsequent simulation effect.

[0082] In the embodiment of the application, the successful matching of the always event with the template does not mean that the code of the always event and the template are completely one-to-one corresponding, but the code structure of the always event meets the constraint of the code structure of the template. If the code structure of the always event meets the constraint of the code structure of the template, it is determined that the always event is successfully matched with the template. The constraint of the code structure means that the sensitive signal of the always event and the selection control structure are the same as or within the constraint range of the template.

[0083] For example, Figure 7 The template is an example, in which the trigger conditions represent the sensitive signal of the always event; each of the condition 1 to condition N represents a judgment condition, such as an if-else judgment condition; each of the stmts1 to stmtsN represents a code set in each branch that does not change the control flow, which means that the code is executed from top to bottom in sequence, and does not need to jump to other places for execution at some places, that is, the stmts is a sequential control structure; the code set refers to a set of 0 or multiple lines of code, and N is an integer greater than or equal to 1.

[0084] Figures 8-10 The three always events are Figure 8The shown always event is a special case of the template when N = 1, trigger conditions =posedge clk, which meets the constraints of the code structure of the template. Figure 9 The shown always event is a special case of the template when N = 2, trigger conditions =posedge clk, which also meets the constraints of the code structure of the template. Figure 10 The shown always event is composed of two layers of nested if-else, which changes the control flow, and the number of selection control structures is 2, while stmts1 to stmtsN in the template are all sequential control structures. Figure 10 The shown always event does not meet the constraints of the code structure of the template; therefore, Figure 8 The shown always event and Figure 9 The shown always event can match the template, while Figure 10 The shown always event does not match the template.

[0085] When the always event does not match the template, the always event is split into multiple always sub-events with simpler logic and fewer layers of selection control structures, and the always sub-events are matched with the template to reduce the false negative rate and improve the optimization effect of the timing logic optimization Pass.

[0086] In an example, the always event can be recursively split until the number of layers of selection control structures of the always sub-event is the same as that of the template, so as to avoid the influence of different writing habits on the matching result.

[0087] For example, when the number of layers of selection control structures of the template is 2, the always event is split into multiple always sub-events with the number of layers of selection control structures being 2; when the template is a single-layer selection control structure, the always event is split into multiple always sub-events with a single-layer selection control structure.

[0088] That is, the splitting granularity of the always event is related to the number of layers of selection control structures of the template. For example, if the template provided by the developer is relatively simple and supports fewer layers of selection control structures, the granularity of the always event splitting needs to be finer; if the template provided by the developer is relatively powerful and supports more layers of selection control structures, the granularity of the always event splitting can be coarser.

[0089] Specifically, the always event can be split according to the logical relationship in the multi-layer nested selection control structure of the always event until the logic of the split always sub-event is the simplest, that is, the number of layers of the selection control structure meets the template requirement.

[0090] Exemplarily, Figure 11 For the always event to be matched, Figure 12 For the split always sub-event (including Figure 12 A1 event, A2 event, A3 event and A4 event in FIG. 1). Figure 11 The if (cond2) of the always event in the fourth row is inside the if (cond1) in the second row, indicating that the execution of stmts2 needs to satisfy both cond1 and cond2, so in the process of splitting to A2, the judgment condition needs to be changed to cond1 && cond2. Similarly, the else in the seventh row is inside the if (cond1) in the second row, indicating that the execution of stmts3 needs to satisfy both cond1 and!cond2, so in the process of splitting to A3, the judgment condition needs to be changed to cond1 &&!cond2. In summary, when splitting the inner-layer nested if-else, the outer if-else needs to be combined, and the AND operation (&&) and the NOT operation (!) are used to complete the splitting of the inner if-else.

[0091] The split always sub-event (including Figure 12 A1 event, A2 event, A3 event and A4 event in FIG. 1). Figure 7 The template shown in FIG. 1 can be more easily recognized by the timing logic optimization Pass in the simulator, and the optimization of the timing logic optimization Pass can be maximized.

[0092] In another example, the always event can be directly split into always sub-events with the simplest logic selection control structure without considering the number of layers of the selection control structure of the template, that is, the always event is split into always sub-events with single-layer selection control structure.

[0093] When there are more (e.g., greater than 100) signal assignments (also referred to as write signals) in the description code of the sequential logic circuit, many invalid assignments may be generated in the simulation process, for example, the value before and after the assignment is the same. In order to avoid this situation, the code structure of the template further includes a constraint on the number of signal assignments, that is, the matching of the always event and the template should also consider the number of signal assignments. For example, the template includes the number constraint information M of signal assignments, indicating that the number of signal assignments in the always event cannot exceed M, otherwise it cannot be matched. In order to meet the constraint of the template on the number of signal assignments, the always sub-events after the splitting of the always event should also meet the constraint of the template on the number of signal assignments. For example, when M in the template is 100, the number of signal assignments in the always event should be split into always sub-events with a number of signal assignments less than or equal to 100.

[0094] For example, Figure 2 An example of an always event is shown, which includes 1000 signal assignments. The always event can be split into multiple always sub-events with a number of signal assignments not exceeding 100 (see the example of the always sub-event after splitting in Figure 13 The number of invalid signal assignments is reduced, and the simulation efficiency is improved.

[0095] It should be explained that Figure 7 This is only an example of the template, and does not constitute a limitation on the embodiments of the application. The chip design developer can set a suitable template according to the actual situation. The number of templates can also be multiple. When the number of templates is multiple, if the always event matches any one of the multiple templates, it is determined that the always event matches the template successfully.

[0096] It should be pointed out that in the embodiments of the application, the meaning of selecting the number of layers of the control structure is: indicating the maximum depth of a selection control structure. If a selection control structure only includes a sequential control structure, the selection control structure is single-layer. If a selection control structure includes one or more single-layer selection control structures, the selection control structure is two-layer. If a selection control structure includes one or more two-layer selection control structures, the selection control structure is three-layer. And so on.

[0097] In step S603, the always sub-event is matched with the code template, and the always sub-event matched successfully is determined as the description code of the target sequential logic circuit.

[0098] The split always sub-event is matched with the template, the always sub-event matched successfully is identified as the description code of the timing logic circuit which can be optimized by the timing logic optimization Pass, and then the timing logic optimization Pass performs optimization on the always sub-event matched successfully. If the split always sub-event still does not match the template, it is proved that the always sub-event is not suitable for optimization of the timing logic optimization Pass, and then the next always sub-event is analyzed, and if the always event is obtained after the analysis of the always sub-event is finished, the always event is identified according to the similar method.

[0099] It should be noted that the timing logic optimization Pass specifically how to optimize the timing logic of the always sub-event matched successfully is not limited in the embodiment of the application, and the chip design developer can select a suitable timing logic optimization method to optimize the identified timing logic according to the needs.

[0100] The identification method of the timing logic provided in the embodiment of the application splits the always event into a plurality of always sub-events with fewer layers of selection control structures, and then matches the split always sub-event with the template, and identifies the always sub-event matched successfully as the timing logic which can be optimized, so that the chip design developer does not need to be limited to some fixed timing logic writing method, the development threshold is reduced, the development efficiency is improved, the identification false positive rate of the timing logic circuit suitable for optimization is greatly reduced, the identification accuracy is improved, and the optimization of the timing logic Pass is maximized, and the simulation efficiency is improved.

[0101] Figure 14 The implementation flowchart of the timing logic optimization Pass after the timing logic identification method of the embodiment of the application is applied. As shown in FIG. 8, the implementation flowchart of the timing logic optimization Pass includes the following steps: Figure 14

[0102] S1, for the IR corresponding to the DUT, setting N as 1, indicating that the Nth event is about to be analyzed, and setting M as the total number of events in the IR;

[0103] S2, judging whether N is less than or equal to M, if yes, indicating that there are still events to be analyzed, executing step S3, otherwise, indicating that all events have been analyzed, executing step S10;

[0104] S3, obtaining the Nth event;

[0105] S4, judging whether the event is an always event, if yes, executing step S5, otherwise, executing step S9;

[0106] ​S5, judging whether the always event is the timing logic meeting the optimization condition through template matching, if yes, executing step S6, otherwise executing step S7;

[0107] S6, executing the timing logic optimization Pass, and executing step S9 after the optimization is completed;

[0108] S7, judging whether the event has been split into the simplest logic, where the definition of the simplest logic has no uniform standard, and is defined differently according to the implementation of different digital simulators. For example, it can be defined as the simplest selection control structure (for example Figure 2 as shown in the single-layer selection control structure with only if, or for example Figure 9 as shown in the single-layer selection control structure with if-else) and the like.

[0109] S8, splitting, and returning to step S5;

[0110] S9, N=N+1, indicating that the next event will be analyzed, and returning to step 2;

[0111] S10, executing other timing logic optimization Pass.

[0112] The embodiment of the timing logic recognition method described above is based on the same concept, and the embodiment of the present application further provides a timing logic recognition device 1500, which comprises units or modules for implementing Figure 6 each step in the timing logic recognition method shown in

[0113] Figure 15 The structure diagram of the timing logic recognition device provided by the embodiment of the present application. The device can be deployed in any device, equipment, platform or equipment cluster with computing capability, for example, can be a computer or a server, to realize accurate recognition of the timing logic that can be optimized by the timing logic optimization Pass.

[0114] As Figure 15As shown in the figure, the identification apparatus 1500 of the sequential logic at least includes: an acquisition module 1501, a splitting module 1502, and a matching module 1503; the acquisition module 1501 is configured to acquire an always event corresponding to a design under test; the splitting module 1502 is configured to split the always event into a plurality of always sub-events when the always event fails to match a code template, wherein the always sub-events have a selection control structure with a layer number less than that of the always event, and the code template indicates a description code of a sequential logic circuit that can be optimized; and the matching module 1503 is configured to match the always sub-events with the code template, and determine a description code of a target sequential logic circuit from the always sub-events that match the code template, wherein the description code of the target sequential logic circuit can be optimized.

[0115] In one possible implementation, the splitting module 1502 is specifically configured to split the always event into a plurality of always sub-events with a selection control structure having a layer number less than or equal to a preset layer number according to a logical relationship of the selection control structure of the always event, and the preset layer number is related to a layer number of a selection control structure of the code template.

[0116] In another possible implementation, the always sub-event is an event with a single-layer selection control structure.

[0117] In another possible implementation, the splitting module 1502 is further configured to determine that the always event has a selection control structure with a layer number greater than a preset layer number before splitting the always event into a plurality of always sub-events, and the preset layer number is related to a layer number of a selection control structure of the code template.

[0118] In another possible implementation, the always sub-event has a write signal number in a same layer selection control structure less than or equal to a preset threshold, and the preset threshold is related to a write signal number in a same layer selection control structure of the code template.

[0119] The identification apparatus 1500 of the sequential logic according to the embodiments of the present application can correspond to performing the methods described in the embodiments of the present application, and the above and other operations and / or functions of each module in the identification apparatus 1500 of the sequential logic are respectively to realize the corresponding procedures of each method in Figure 6 For brevity, they will not be described here.

[0120] Based on the same idea as the foregoing method embodiments, the embodiments of the present application further provide a computing device, which at least includes a processor and a memory, and the memory has stored a program, and the processor can implement Figures 4-14 The units or modules of each step in the method shown.

[0121] Figure 16 A structural schematic diagram of a computing device provided in an embodiment of the present application.

[0122] As shown in Figure 16 the computing device 1600 includes at least one processor 1601, a memory 1602 and a communication interface 1603. Among them, the processor 1601, the memory 1602 and the communication interface 1603 are communicatively connected, which can be realized by wired (such as bus) or wireless communication. The communication interface 1603 is used to receive data (such as the IR corresponding to the DUT) sent by other devices; the memory 1602 stores computer instructions, and the processor 1601 executes the computer instructions to execute the method in the foregoing method embodiments.

[0123] It should be understood that in the embodiments of the present application, the processor 1601 can be a central processing unit CPU, and the processor 1601 can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc.

[0124] The memory 1602 can include read-only memory and random access memory, and provide instructions and data for the processor 1601. The memory 1602 can also include non-volatile random access memory.

[0125] The memory 1602 can be a volatile memory or a nonvolatile memory, or can include both volatile and nonvolatile memory. Where the nonvolatile memory is a read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), or flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example, and not limitation, many forms of RAM are available, for example, static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0126] It should be understood that the computing device 1600 according to the embodiments of the present application can perform the method shown in the embodiments of the present application, and the detailed description of the method implemented by the method is described above. For brevity, it will not be repeated here. Figures 4-14 It should be understood that the computing device 1600 according to the embodiments of the present application can perform the method shown in the embodiments of the present application, and the detailed description of the method implemented by the method is described above. For brevity, it will not be repeated here.

[0127] The embodiments of the present application provide a computer readable storage medium, which stores a computer program, when the computer program is executed by a processor, the above-mentioned method is implemented.

[0128] The embodiments of the present application provide a chip, which includes at least one processor and an interface, the at least one processor determines program instructions or data through the interface; the at least one processor is used to execute the program instructions to implement the above-mentioned method.

[0129] The embodiments of the present application provide a computer program or computer program product, which includes instructions, when the instructions are executed, the computer executes the above-mentioned method.

[0130] Those skilled in the art should further understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been described in the above description in a general manner. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0131] The steps of the method or algorithm described in combination with the embodiments disclosed herein can be implemented in hardware, software executed by a processor, or a combination of both. The software module can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0132] The above specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A method of identifying sequential logic, characterized by, The method comprises the following steps: acquiring a process block event corresponding to a design under test (DUT); when the process block event fails to match a code template, splitting the process block event into a plurality of process block sub-events, wherein the number of layers of selection control structures of the process block sub-events is less than the number of layers of selection control structures of the process block event, and / or the number of write signals of the process block sub-events is less than or equal to the number of write signals of the process block event; the code template indicates a description code of timing logic that can be optimized; matching the process block sub-events with the code template to obtain a description code of target timing logic, the description code of target timing logic being a process block sub-event that matches successfully.

2. The method of claim 1, wherein, The splitting of the process block event into a plurality of process block sub-events comprises the following steps: according to a logical relationship of selection control structures of the process block event, splitting the process block event into a plurality of process block sub-events with a number of layers of selection control structures less than or equal to a preset number of layers, the preset number of layers being related to the number of layers of selection control structures of the code template.

3. The method of claim 1, wherein, The process block sub-event is an event with a single-layer selection control structure.

4. The method of claim 1, wherein, Before the splitting of the process block event into a plurality of process block sub-events, the following step is further included: determining that the number of layers of selection control structures of the process block event is greater than a preset number of layers, the preset number of layers being related to the number of layers of selection control structures of the code template.

5. The method according to any one of claims 1 to 4, characterized in that, The number of write signals in the process block sub-event is less than or equal to a preset threshold.

6. An apparatus for identifying sequential logic, characterized by The method comprises the following steps: an acquiring module is configured to acquire a process block event corresponding to a design under test (DUT); a splitting module is configured to, when the process block event fails to match a code template, split the process block event into a plurality of process block sub-events, wherein the number of layers of selection control structures of the process block sub-events is less than the number of layers of selection control structures of the process block event, and / or the number of write signals of the process block sub-events is less than or equal to the number of write signals of the process block event; the code template indicates a description code of timing logic that can be optimized; a matching module is configured to match the process block sub-events with the code template to obtain a description code of target timing logic, the description code of target timing logic being a process block sub-event that matches successfully.

7. The apparatus of claim 6, wherein, The splitting module is specifically configured to, according to a logical relationship of selection control structures of the process block event, split the process block event into a plurality of process block sub-events with a number of layers of selection control structures less than or equal to a preset number of layers, the preset number of layers being related to the number of layers of selection control structures of the code template.

8. The apparatus of claim 6, wherein, The process block sub-event is an event with a single-layer selection control structure.

9. The apparatus of claim 6, wherein, The splitting module is further configured to, before the splitting of the process block event into a plurality of process block sub-events, determine that the number of layers of selection control structures of the process block event is greater than a preset number of layers, the preset number of layers being related to the number of layers of selection control structures of the code template.

10. The device according to any of claims 6-9, characterized in that The number of write signals in the process block sub-event is less than or equal to a preset threshold.

11. A computing device comprising a memory and a processor, wherein: The memory stores executable codes, and the processor executes the executable codes to implement the method in any one of claims 1-5.

12. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is configured to cause a computer to perform the method of any one of claims 1-5 when the computer program is executed in the computer.

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