Bidirectional signal acquisition circuit and integrated circuit suitable for a silicon via
By using a bidirectional signal acquisition circuit and latch to record signals within the through-silicon via (TSV), the problems of chip position identification and signal timing asynchrony are solved, thereby improving signal transmission efficiency and reducing the number of TSVs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHEJIANG LIJI ELECTRONICS CO LTD
- Filing Date
- 2022-09-28
- Publication Date
- 2026-05-12
AI Technical Summary
In multi-chip stacking, existing technologies cannot automatically identify the position of chips in the stack, resulting in asynchronous signal timing and requiring multiple through-silicon vias (TSVs) to transmit signals, which increases the number of TSVs.
By using first and second components connected in parallel, bidirectional signal transmission is achieved within a through-silicon via (TSV) through a bidirectional signal acquisition circuit, and a latch is used to record the signal to determine the chip position, thereby reducing the number of TSVs.
The location of each chip is effectively determined, reducing the number of through-silicon vias (TSVs) and simplifying subsequent timing adjustments, thereby improving signal transmission efficiency.
Smart Images
Figure CN115497536B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more particularly to a bidirectional signal acquisition circuit and integrated circuit suitable for a single silicon path. Background Technology
[0002] Traditional DRAM, or Dynamic Random Access Memory, can no longer meet the higher demands for storage capacity and speed in applications such as artificial intelligence and data servers. Through-Silicon Vias (TSV) interconnect technology, which completely penetrates the silicon wafer or chip, forming thousands of vertical interconnect circuits between the chip's surface and back side, offers the advantage of shorter interconnect lengths in its three-dimensional packaged integrated circuits compared to traditional stacking solutions such as wire bonding and flip-chip bonding. Therefore, this characteristic of TSV interconnect technology in expanding storage device capacity and bandwidth has made it a crucial means of improving DRAM performance and density, and it is already widely used in existing DRAMs.
[0003] Take a single read / write operation of the controller and chip as an example. Figure 1 The diagram illustrates the read / write process of stacked chips in the prior art. The controller sends a read command to the chip. Upon receiving the read command, the chip sends out its stored data. Simultaneously, the chip sends a return read command back to the controller.
[0004] In multi-chip stacking, for a command sent by the controller at a certain moment, the top-level chip receives the signal much later than the bottom-level chip because the intrinsic distance between the top-level chip and the controller is greater than that between the bottom-level chips. This means that the signal timing differs when requesting data from different layers of chips. Therefore, when using through-silicon vias (TSVs) to implement multi-chip stacking, the signal timing between chips in different layers is an unavoidable problem in chip design. In existing technologies, the timing of each chip is typically configured after stacking, based on the number of chips and their positions within the stack. However, since the internal logic of each chip is pre-defined, although the number of chips in the current stack and the position of a particular chip can be obtained after chip stacking is complete, post-stack timing adjustments are extremely cumbersome.
[0005] The technical challenge of adjusting after chip stacking lies in the fact that the chip cannot automatically identify its position relative to other chips in the stack (mainly the top and bottom chips), nor can it automatically identify whether it is the top or bottom chip. As a result, the chip cannot configure the corresponding timing according to its position relative to the top and / or bottom chips.
[0006] To address the aforementioned issues, existing technologies provide a timing-based chip location identification method. This method determines the positional relationship between different chips by analyzing the transmission timing of a first signal and a second signal at each chip layer. However, when determining the chip positional relationship using the first and second signals, each chip requires at least two through-silicon vias (TSVs). One TSV is used to transmit the first signal between chips, and the other TSV is used to transmit the second signal between chips. Figure 2 As shown, this method requires each of the first and second signals to occupy a through-silicon via (TSV), resulting in a large number of TSVs. Summary of the Invention
[0007] This invention provides a bidirectional signal acquisition circuit and integrated circuit suitable for a single silicon via, which enables bidirectional signal transmission within a single through-silicon via (TSV). This reduces the number of TSVs while ensuring that the position of each chip can be effectively determined.
[0008] A first aspect of the present invention provides a bidirectional signal acquisition circuit suitable for a single silicon path, characterized in that it comprises:
[0009] A first component and a second component are connected in parallel at each chip. The first component is used to transmit the signal in a first direction, and the second component is used to transmit the signal in a second manner.
[0010] The first component and the second component are respectively connected to the connecting line, and the first component and the second component are connected to the silicon path of the adjacent chip through the connecting line;
[0011] A first latch and / or a second latch are respectively connected to the first component and / or the second component, and are used to record the signals acquired by the first component and / or the second component at each time.
[0012] Optionally, in one possible implementation of the first aspect, the first component is a first tri-state gate, and the input and output arrangements of the first tri-state gates of all chips are the same;
[0013] The first tri-state gate has a first signal output line, which is connected to the first latch. The first latch is used to store the first signal flowing through the first tri-state gate.
[0014] Optionally, in one possible implementation of the first aspect, the second component is a second tri-state gate, and the input and output arrangements of the second tri-state gates of all chips are the same;
[0015] The second tri-state gate has a signal output line, which is connected to the second latch. The second latch is used to store the second signal flowing through the second tri-state gate.
[0016] Optionally, in one possible implementation of the first aspect, it also includes:
[0017] A signal generator is used to create a clock signal for the latch. When the RSTB global signal is low, the first tri-state gate is opened, and the first signal is transmitted from the chip at the substrate to the chip at the top layer through the silicon path and the first component. The rising edge of the global signal RSTB creates a clock signal, which is transmitted to the first latch to store the first signal.
[0018] Optionally, in one possible implementation of the first aspect, when the RSTB global signal is high, the second tri-state gate is opened, and the second signal is transmitted from the top-layer chip to the substrate chip through the silicon path and the second component. The rising edge of the RSTB delay creates a clock signal, which is transmitted to the second latch to store the second signal.
[0019] Optionally, in one possible implementation of the first aspect, it also includes:
[0020] A signal generator is used to create a clock signal for the latch. When the RSTB global signal is low, the first tri-state gate is open, and the first signal is transmitted from the chip at the substrate to the chip at the top layer through the silicon path and the first component. The rising edge of the READY signal of the internal power system of the chip creates a clock signal, which is transmitted to the first latch to store the first signal.
[0021] Optionally, in one possible implementation of the first aspect, when the RSTB global signal is high, the second tri-state gate is opened, and the second signal is transmitted from the top-layer chip to the substrate chip through the silicon path and the second component; the rising edge of the RSTB delay creates a clock signal, which is transmitted to the second latch to store the second signal.
[0022] A second aspect of the present invention provides an integrated circuit comprising the above-described bidirectional signal acquisition circuit suitable for a single silicon path, comprising:
[0023] Multilayer silicon wafers, in which multiple chips are set in each layer of silicon wafers;
[0024] Each chip is equipped with the bidirectional signal acquisition circuit;
[0025] Any two adjacent silicon substrates are electrically connected through silicon pathways, and the bidirectional signal acquisition circuit is connected to the vertically adjacent chips based on the silicon pathways.
[0026] The present invention provides a bidirectional signal acquisition circuit and integrated circuit suitable for a single silicon via, which enables bidirectional signal transmission within a single through-silicon via (TSV), reducing the number of TSVs while ensuring that the position of each chip can be effectively determined.
[0027] Two latches can be used to latch signals transmitted in different directions, which facilitates subsequent timing comparison and allows us to determine the position of each chip in the integrated circuit. Attached Figure Description
[0028] Figure 1 This describes the read / write process of stacked chips in existing technology.
[0029] Figure 2 This is a schematic diagram of a silicon channel and signal acquisition circuit in the prior art;
[0030] Figure 3 This is a schematic diagram of the silicon channel and signal acquisition circuit in this application;
[0031] Figure 4 This is a schematic diagram of the transmission of the first signal in the silicon channel and signal acquisition circuit in this application;
[0032] Figure 5 This is a schematic diagram of the transmission of the second signal in the silicon channel and signal acquisition circuit in this application. Detailed Implementation
[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0034] The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in sequences other than those illustrated or described herein.
[0035] It should be understood that in the various embodiments of the present invention, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.
[0036] It should be understood that in this invention, "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or device.
[0037] It should be understood that in this invention, "multiple" refers to two or more. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, "and / or B" can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "Contains A, B, and C", "Contains A, B, and C" means that all three A, B, and C are contained; "Contains A, B, or C" means that one of A, B, and C is contained; "Contains A, B, and / or C" means that any one, two, or three of A, B, and C are contained.
[0038] It should be understood that in this invention, "B corresponding to A", "B corresponding to A", and "A and B" are used interchangeably.
[0039] "Corresponding" or "B corresponds to A" means that B is associated with A, and B can be determined based on A. Determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information. A match between A and B is defined as a similarity between A and B that is greater than or equal to a preset threshold.
[0040] Depending on the context, "if" as used here can be interpreted as "when," "when," "in response to determination," or "in response to detection."
[0041] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.
[0042] like Figure 3 As shown, the present invention provides a bidirectional signal acquisition circuit suitable for a single silicon path, the bidirectional signal acquisition circuit specifically comprising:
[0043] A first component and a second component are connected in parallel at each chip. The first component is used to transmit the signal in a first direction, and the second component is used to transmit the signal in a second manner.
[0044] The bidirectional signal acquisition circuit in this invention can be a hybrid circuit, which includes multiple series-connected sub-modules. Each sub-module includes a first component and a second component connected in parallel. The first components in all sub-modules have the same signal transmission direction, and the second components in all sub-modules have the same signal transmission direction. The number of sub-modules can be the same as the number of chip layers, that is, each chip in each layer will have a corresponding sub-module.
[0045] The first and second components are respectively connected to connecting lines, and the first and second components are connected to the silicon pathways of adjacent chips through the connecting lines. The connecting lines can be considered as connecting lines between any two adjacent sub-modules, and signals are transmitted between different sub-modules based on these connecting lines.
[0046] A first latch and / or a second latch are respectively connected to the first component and / or the second component, and are used to record the signals acquired by the first component and / or the second component at each time.
[0047] The present invention records the signals flowing through the first component and / or the second component using a first latch and / or a second latch.
[0048] In existing chip position detection methods, the position of each chip in the integrated circuit is obtained by retrieving the corresponding signals passed through each chip as recorded by a first latch and / or a second latch. The first latch and / or the second latch in this invention can record the corresponding first and second signals. S in the figure represents a latch.
[0049] In one possible implementation, the first component is a first tri-state gate, and the input and output arrangements of the first tri-state gates on all chips are identical. To ensure a fixed current transmission direction in chips on different vertical layers, this invention adopts a uniform arrangement for all first tri-state gates, allowing current signals to be transmitted simultaneously within the first tri-state gates. The first signal transmitted within the first tri-state gate can be transmitted from the bottom-layer chip towards the top-layer chip.
[0050] The first tri-state gate has a first signal output line, which is connected to the first latch. The first latch is used to store the first signal flowing through the first tri-state gate.
[0051] In one possible implementation, the second component is a second tri-state gate, and the input and output arrangements of the second tri-state gates on all chips are identical. To ensure a fixed current transmission direction in chips on different vertical layers, this invention adopts a uniform arrangement for all second tri-state gates, allowing current signals to be transmitted simultaneously within the second tri-state gates. The second signal transmitted within the second tri-state gate can be transmitted from the top-level chip towards the bottom-level chip.
[0052] The second tri-state gate has a second signal output line, which is connected to the second latch. The second latch is used to store the second signal flowing through the second tri-state gate.
[0053] In an embodiment of the present invention, preferably, the first component and the second component are tri-state gates. Tri-state gates require an enable signal to open, so that the corresponding current signal can only be transmitted in a fixed direction according to its setting.
[0054] In one possible implementation, it also includes:
[0055] A signal generator is used to create a clock signal for the latch. When the RSTB global signal is low, the first tri-state gate is opened, and the first signal is transmitted from the chip at the substrate to the chip at the top layer through the silicon path and the first component. The rising edge of the global signal RSTB creates a clock signal, which is transmitted to the first latch to store the first signal.
[0056] When the RSTB global signal is high, the second tri-state gate is opened, and the second signal is transmitted from the top-layer chip to the base chip through the silicon path and the second component. The rising edge of the RSTB delay creates a clock signal, which is transmitted to the second latch to store the second signal.
[0057] Through the above technical solutions, the present invention can generate the first and second signals using only global signals, enabling the latch to perform statistics on the first and second signals flowing through each chip.
[0058] In one possible implementation, it also includes:
[0059] A signal generator is used to create a clock signal for the latch. When the RSTB global signal is low, the first tri-state gate is open, and the first signal is transmitted from the chip at the substrate to the chip at the top layer through the silicon path and the first component. The rising edge of the READY signal of the internal power system of the chip creates a clock signal, which is transmitted to the first latch to store the first signal.
[0060] When the RSTB global signal is high, the second tri-state gate is opened, and the second signal is transmitted from the top-layer chip to the base chip through the silicon path and the second component; the rising edge of the RSTB delay creates a clock signal, which is transmitted to the second latch to store the second signal.
[0061] Through the above technical solutions, the present invention generates the first signal and the second signal by using a combination of global signals and internal signals, so that the latch can perform statistics on the first signal and the second signal flowing through each chip.
[0062] Embodiments of the present invention also provide an integrated circuit, including the above-described bidirectional signal acquisition circuit suitable for a single silicon path, wherein the integrated circuit specifically includes:
[0063] A multilayer silicon substrate, wherein multiple chips are disposed in each silicon substrate layer. In this invention, there is no limitation on the number of silicon substrate layers in the integrated circuit, nor on the number of chips in each silicon substrate layer.
[0064] Each chip is equipped with the bidirectional signal acquisition circuit. The inclusion of a bidirectional signal acquisition circuit in each chip enables bidirectional signal acquisition, modifying and integrating the existing technology where each circuit can only acquire one signal at a time, thus halving the number of silicon paths required for bidirectional signal acquisition.
[0065] Any two adjacent silicon substrates are electrically connected through silicon paths. A bidirectional signal acquisition circuit connects to vertically adjacent chips based on these silicon paths. Since any two vertically adjacent silicon substrates need to be electrically connected through silicon paths, the bidirectional signal acquisition circuit allows a single silicon path to acquire bidirectional signals, effectively reducing the number of silicon paths required.
[0066] like Figure 4 As shown, this is a schematic diagram of the signal flow from the bottom chip to the top in the technical solution of this application.
[0067] like Figure 5 As shown, this is a schematic diagram of the signal flow from the top chip to the bottom in the technical solution of this application.
[0068] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A bidirectional signal acquisition circuit suitable for a single silicon path, characterized in that, include: A first component and a second component are connected in parallel at each chip. The first component is used to transmit the signal in a first direction, and the second component is used to transmit the signal in a second direction. The first direction is the top-to-bottom direction of the chip, and the second direction is the bottom-to-top direction of the chip. The first component and the second component are respectively connected to the connecting line, and the first component and the second component are connected to the silicon path of the adjacent chip through the connecting line; The first latch and / or the second latch are respectively connected to the first component and / or the second component, and are used to record the signals collected by the first component and / or the second component at each time. The first component is a first tri-state gate, and the input and output arrangements of the first tri-state gates of all chips are the same; The first tri-state gate has a first signal output line, which is connected to the first latch. The first latch is used to store the first signal flowing through the first tri-state gate. The second component is a second tri-state gate, and the input and output arrangements of the second tri-state gates of all chips are the same; The second tri-state gate has a second signal output line, which is connected to the second latch. The second latch is used to store the second signal flowing through the second tri-state gate.
2. The bidirectional signal acquisition circuit suitable for a single silicon path according to claim 1, characterized in that, Also includes: A signal generator is used to create a clock signal for the latch. When the RSTB global signal is low, the first tri-state gate is opened, and the first signal is transmitted from the chip at the substrate to the chip at the top layer through the silicon path and the first component. The rising edge of the global signal RSTB creates a clock signal, which is transmitted to the first latch to store the first signal.
3. The bidirectional signal acquisition circuit suitable for a single silicon path according to claim 2, characterized in that, When the RSTB global signal is high, the second tri-state gate is opened, and the second signal is transmitted from the top-layer chip to the base chip through the silicon path and the second component. The rising edge of the RSTB delay creates a clock signal, which is transmitted to the second latch to store the second signal.
4. The bidirectional signal acquisition circuit suitable for a single silicon path according to claim 1, characterized in that, Also includes: A signal generator is used to create a clock signal for the latch. When the RSTB global signal is low, the first tri-state gate is opened, and the first signal is transmitted from the chip at the substrate to the chip at the top layer through the silicon path and the first component. The rising edge of the READY signal of the internal power system of the chip creates a clock signal, which is transmitted to the first latch to store the first signal.
5. The bidirectional signal acquisition circuit suitable for a single silicon path according to claim 4, characterized in that, When the RSTB global signal is high, the second tri-state gate is opened, and the second signal is transmitted from the top-layer chip to the base chip through the silicon path and the second component; the rising edge of the RSTB delay creates a clock signal, which is transmitted to the second latch to store the second signal.
6. An integrated circuit comprising the bidirectional signal acquisition circuit suitable for a single silicon path as described in any one of claims 1 to 5, characterized in that, include: Multilayer silicon wafers, in which multiple chips are set in each layer of silicon wafers; Each chip is equipped with the bidirectional signal acquisition circuit; Any two adjacent silicon substrates are electrically connected through silicon pathways, and the bidirectional signal acquisition circuit is connected to the vertically adjacent chips based on the silicon pathways.