Trench field effect transistor and method for manufacturing trench field effect transistor
By introducing a dielectric region into the trench-type field effect transistor, the problem of increasing gate-drain capacitance is solved, and the operation speed and efficiency of the device are improved.
Patent Information
- Application Number
- CN202211188475.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-09-27
- Publication Date
- 2025-08-12
- Estimated Expiration
- 2042-09-27
AI Technical Summary
The parasitic capacitance of existing MOSFETs, especially gate-drain capacitance, affects their operating speed and performance, and increases as the device size shrinks.
In the trench type field effect transistor, by forming a dielectric region between the shielding conductor and the gate conductor, the value of the gate-drain capacitance is reduced using a low dielectric constant material.
It effectively reduces the gate-drain capacitance and improves the operating performance of the trench-type field effect transistor.
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Figure CN115497828B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a trench field effect transistor and a method for manufacturing the trench field effect transistor. Background Art
[0002] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has many parasitic capacitors that affect the MOSFET's operating speed. As MOSFET size decreases, the distance between the gate and source, as well as the distance between the gate and drain, also decreases, which in turn increases the capacitance of the parasitic capacitors. Parasitic capacitors include gate-drain capacitance, gate-source capacitance, and drain-source capacitance. Gate-drain capacitance slows down the charge and discharge speed, affecting the performance of the MOSFET. Summary of the Invention
[0003] Based on the foregoing, the present application provides a trench field effect transistor and a method for manufacturing the trench field effect transistor, which can reduce the value of the gate-drain capacitance and improve the operation of the trench field effect transistor.
[0004] Based on the above objectives, the present application provides a method for manufacturing a trench field-effect transistor, comprising: forming an epitaxial layer on a substrate; forming a trench in the epitaxial layer; forming a first insulating layer and a shielding conductor in the trench, wherein the first insulating layer surrounds the shielding conductor; forming a dielectric layer on the epitaxial layer, on the first insulating layer, and on the sidewalls of the trench; etching a portion of the dielectric layer to form a dielectric region, wherein the dielectric region is located on the first insulating layer and on the sidewalls of the trench; and forming a second insulating layer and a gate conductor in the trench, wherein the second insulating layer surrounds the gate conductor and fills the trench.
[0005] Based on the above objectives, the present application provides a trench field-effect transistor, comprising a substrate, an epitaxial layer, a trench, an insulating layer, a shielding conductor, a gate conductor, and a dielectric region. The epitaxial layer is disposed on the substrate. The trench is disposed in the epitaxial layer, wherein the trench extends from the surface of the epitaxial layer to the interior of the epitaxial layer. The insulating layer is disposed in the trench. The shielding conductor is disposed in the trench, wherein the shielding conductor is surrounded by the insulating layer and is insulated from the epitaxial layer by the insulating layer. The gate conductor is disposed in the trench, wherein the gate conductor is located on the shielding conductor and surrounded by the insulating layer, and is insulated from the shielding conductor and the epitaxial layer by the insulating layer. The dielectric region is disposed between the shielding conductor and the gate conductor and is located on the sidewalls of the trench.
[0006] In summary, the trench field effect transistor and the method for manufacturing the trench field effect transistor of the present application can reduce the gate-drain capacitance and improve the operation of the trench field effect transistor by forming a dielectric region between the shield conductor and the gate conductor, and the dielectric region is located on the sidewall of the trench near the gate conductor. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 FIG1 is a cross-sectional view of a trench field effect transistor according to an embodiment of the present application.
[0008] Figure 2 The present invention is a flowchart illustrating a method for manufacturing a trench field effect transistor according to an embodiment of the present application.
[0009] Figures 3A to 3G The present invention illustrates cross-sectional views of various stages of a method for manufacturing a trench field effect transistor according to an embodiment of the present application.
[0010] Figures 4A to 4C FIG. 1 is a flow chart illustrating a method for forming a dielectric region according to another embodiment of the present application.
[0011] Figure 5 FIG1 is a cross-sectional view of a trench field effect transistor according to another embodiment of the present application.
[0012] Figure 6 The flowchart of the method for manufacturing a trench field effect transistor according to another embodiment of the present application is shown.
[0013] 7A to 7F The present invention is a cross-sectional view illustrating various stages of a method for manufacturing a trench field effect transistor according to another embodiment of the present application.
[0014] Description of reference numerals:
[0015] 10: substrate
[0016] 20: Epitaxial layer
[0017] 30: Insulation layer
[0018] 31: First insulation layer
[0019] 32: Second insulation layer
[0020] 33: The third insulation layer
[0021] 40: Shielded conductor
[0022] 50: Dielectric layer
[0023] 51: Medium area
[0024] 60: Gate conductor
[0025] 70: Well region
[0026] 80: Source area
[0027] 90: Interlayer dielectric layer
[0028] 100: Body contact area
[0029] 110: Metal District
[0030] 111: Source metal layer
[0031] 112: Conductive channel
[0032] 120: Drain metal layer
[0033] F1: First surface
[0034] F2: Second surface
[0035] T1: Groove
[0036] 1A, 1B: Trench field-effect transistors
[0037] S11~S16, S21~S33: Steps DETAILED DESCRIPTION
[0038] The terms "first," "second," and the like in the specification, claims, and drawings of this application are used to distinguish similar objects, not to describe a particular order or sequential sequence. In addition, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or elements is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to the process, method, product, or apparatus.
[0039] See also Figure 1 , which is a cross-sectional view of a trench field effect transistor according to an embodiment of the present application. Figure 1 As shown, the trench field effect transistor includes a substrate 10 , an epitaxial layer 20 , a trench T1 , an insulating layer 30 , a shield conductor 40 , a gate conductor 60 and a dielectric region 51 .
[0040] Epitaxial layer 20 is disposed on substrate 10. Trench T1 is disposed in epitaxial layer 20 and extends from the surface to the interior of epitaxial layer 20. Insulating layer 30 is disposed in trench T1. Shield conductor 40 is disposed in trench T1 and surrounded by insulating layer 30. Shield conductor 40 is insulated from epitaxial layer 20 by insulating layer 30. Gate conductor 60 is disposed in trench T1. Specifically, gate conductor 60 is located above shield conductor 40 and surrounded by insulating layer 30. Gate conductor 60 is insulated from shield conductor 40 and epitaxial layer 20 by insulating layer 30. Dielectric region 51 is disposed between shield conductor 40 and gate conductor 60 and located on the sidewalls of trench T1. It may be close to the sidewalls of gate conductor 60. In other words, the distance between dielectric region 51 and gate conductor 60 is less than the distance between dielectric region 51 and shield conductor 40. Shield conductor 40, gate conductor 60, and dielectric region 51 are enclosed by insulating layer 30.
[0041] The thickness of the insulating layer 30 between the trench T1 and the sidewalls of the gate conductor 60 is less than the thickness of the insulating layer 30 between the sidewalls of the trench T1 and the sidewalls of the shield conductor 40. The width of the gate conductor 60 as projected on the substrate 10 is greater than the width of the shield conductor 40 as projected on the substrate 10. The width of the dielectric region 51 as projected on the substrate 10 is less than the width of the gate conductor 60 as projected on the substrate 10.
[0042] The substrate 10 and the epitaxial layer 20 are of a first doping type, and the material of the substrate 10 and the epitaxial layer 20 includes silicon. The first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type. In order to form an N-type semiconductor layer or region, an N-type dopant may be implanted into the substrate 10 and the epitaxial layer 20. The N-type dopant may be, for example, phosphorus (P) or arsenic (As). In order to form a P-type semiconductor layer or region, a P-type dopant may be doped into the substrate 10 and the epitaxial layer 20. For example, the P-type dopant may be boron (B). In one embodiment, the substrate 10 and the epitaxial layer 20 are of N-type.
[0043] The material of the insulating layer 30 can be silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), aluminum oxide (AlO x), hafnium dioxide (HfO2), or a combination thereof; the material of the dielectric region 51 may be a low-k material having a dielectric constant less than 3.9, and the low-k material may include polyimide (PI), hydrogen silsesquioxane (HSQ), or methylsilsesquioxane (MSQ). The materials of the shield conductor 40 and the gate conductor 60 may include a metal material, doped polysilicon, or a combination thereof, and the metal material may include indium (In), tin (Sn), aluminum (Al), gold (Au), platinum (Pt), indium (In), zinc (Zn), germanium (Ge), silver (Ag), lead (Pb), palladium (Pd), copper (Cu), gold beryllium (AuBe), germanium beryllium (BeGe), nickel (Ni), lead tin (PbSn), chromium (Cr), gold zinc (AuZn), titanium (Ti), tungsten (W), or titanium tungsten (TiW).
[0044] In this embodiment, the number of dielectric regions 51 can be two or more. When multiple dielectric regions 51 are provided, they can be located on the trench sidewalls on opposite sides of the gate conductor 60, based on the centerline of the gate conductor 60. In one embodiment, when an even number of dielectric regions are provided, they can be symmetrical with each other, based on the centerline of the gate conductor 60 as the axis of symmetry. Because the dielectric region 51 is located between the shield conductor 40 and the gate conductor 60 and is composed of a low-k dielectric constant material, the gate-drain capacitance can be reduced by increasing the dielectric thickness at the bottom of the gate conductor 60 (i.e., the thickness of the insulating layer 30 and the dielectric region 51) and reducing the dielectric constant.
[0045] See also Figure 2 , which is a flow chart of a method for manufacturing a trench field effect transistor according to an embodiment of the present application. Figure 2 As shown, the method for manufacturing a trench field effect transistor includes steps S11 to S16.
[0046] Step S11: forming an epitaxial layer 20 on the substrate 10. Figure 3A As shown, substrate 10 includes a first surface F1 and a second surface F2. Epitaxial layer 20 is formed on first surface F1 of substrate 10. The doping concentration of epitaxial layer 20 is lower than that of substrate 10. Epitaxial layer 20 may be formed by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or atomic layer deposition (ALD). Other methods of forming film layers may also be used, and the present application is not limited thereto.
[0047] Step S12: forming a trench T1 in the epitaxial layer 20. Figure 3B As shown, the trench T1 extends from the surface of the epitaxial layer 20 toward the substrate 10 and terminates in the epitaxial layer 20 .
[0048] In one embodiment, laser etching can be used to etch through the patterned photoresist layer from the surface of the epitaxial layer 20 to the interior of the epitaxial layer 20 to form a trench T1 in the epitaxial layer 20. For example, the depth and opening width of the trench T1 can be controlled by adjusting the laser energy, spot size, and etching time.
[0049] In one embodiment, an oxide layer is formed on the epitaxial layer 20, and then a patterned photoresist layer is formed on the oxide layer. Etching is performed from the opening in the photoresist layer to the oxide layer, stopping at the surface of the epitaxial layer 20, thereby forming an opening through the oxide layer. The oxide layer with the opening serves as a hard mask, and etching is performed from the surface of the epitaxial layer 20 to the interior of the epitaxial layer 20 to form a trench T1 in the epitaxial layer 20. The etching can be inductively coupled plasma reactive-ion etching (ICP-RIE) or wet etching, and the depth and opening width of the trench T1 can be controlled by adjusting the concentration of the etching solution and the etching time.
[0050] Step S13 : forming a first insulating layer 31 and a shield conductor 40 in the trench T1 , wherein the first insulating layer 31 surrounds the shield conductor 40 .
[0051] like Figure 3C As shown, a first insulating layer 31 is formed on the bottom and part of the sidewall of the trench T1 , but the first insulating layer 31 does not fill the entire trench T1 . A shielding conductor 40 is formed on the first insulating layer 31 at the bottom of the trench T1 . The first insulating layer 31 shields the conductor 40 .
[0052] A first insulating layer 31 is formed on the bottom and sidewalls of the trench T1 and on the surface of the epitaxial layer 20 by chemical vapor deposition or thermal oxidation. The material of the first insulating layer 31 may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), aluminum oxide (AlOx), hafnium dioxide (HfO2), or a combination thereof. A conductive layer is formed inside the trench T1 and on the surface of the epitaxial layer 20 by chemical vapor deposition to fill the trench T1. The conductive layer located on the surface of the epitaxial layer 20 and in the trench T1 is partially etched, leaving a conductive layer such as Figure 3C The portion of the conductor layer shown serves as the shield conductor 40. The aforementioned portion of the conductor layer can be partially etched by isotropic or anisotropic plasma etching.
[0053] A photoresist layer is formed on the shield conductor 40 so that the photoresist layer fills the trench T1, and then the first insulating layer 31 on the epitaxial layer 20 and the first insulating layer 31 on the opposite side walls of the trench T1 are partially etched, leaving the following: Figure 3C The portion of the first insulating layer 31 located on the sidewalls of the trench T1 is removed to expose the epitaxial layer 20 and a portion of the sidewalls of the trench T1. The photoresist layer is then removed. The first insulating layer 31 is then formed again so that the first insulating layer 31 covers the shield conductor 40. In other words, the first insulating layer 31 surrounds the shield conductor 40.
[0054] Step S14 : forming a dielectric layer 50 on the epitaxial layer 20 , the first insulating layer 31 and the sidewalls of the trench T1 .
[0055] like Figure 3D As shown, a dielectric layer 50 is formed on the epitaxial layer 20, the first insulating layer 31, and the sidewalls of the trench T1 without the first insulating layer 31. The dielectric layer 50 can be formed by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), or sputtering.
[0056] Step S15 : Partially etching the dielectric layer 50 to form a dielectric region 51 , wherein the dielectric region 51 is located on the first insulating layer 31 and on the sidewalls of the trench T1 .
[0057] like Figure 3E As shown, the dielectric layer 50 on the epitaxial layer 20, the first insulating layer 31 and the sidewalls of the trench T1 is partially etched by reactive ion etching, leaving the dielectric layer 50 on both sidewalls of the trench T1. The dielectric layers 50 on the two sidewalls are not connected to each other. At this time, the thickness of the dielectric layer 50 on the sidewalls of the trench T1 is less than Figure 3D The thickness of the dielectric layer 50 on the sidewalls of the trench T1 is shown.
[0058] like Figure 3F As shown, the gas flow rate and reaction time of the reactive ion gas are adjusted, and reactive ion etching is performed to partially etch the dielectric layer 50 located on both side walls of the trench T1 again, leaving the dielectric layer 50 located on the first insulating layer 31 and the side walls of the trench T1 as two dielectric regions 51. Each dielectric region 51 partially covers the first insulating layer 31 and a portion of the side wall of the trench T1, and a gap is formed between the two dielectric regions 51.
[0059] Step S16 : forming a second insulating layer 32 and a gate conductor 60 in the trench T1 , wherein the second insulating layer 32 surrounds the gate conductor 60 .
[0060] like Figure 3G As shown, a second insulating layer 32 is formed on a portion of the sidewall of the trench T1 and above the shield conductor 40 , a gate conductor 60 is formed in the trench T1 having the second insulating layer 32 , and a third insulating layer 33 is formed to cover the gate conductor 60 .
[0061] A second insulating layer 32 is formed on part of the sidewalls of the trench T1, on the second insulating layer 32 on the first insulating layer 31, and on the surface of the epitaxial layer 20 by chemical vapor deposition or thermal oxidation. The material of the second insulating layer 32 may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), aluminum oxide (AlOx), hafnium dioxide (HfO2), or a combination thereof. Then, a conductive layer is formed on the inside of the trench T1 and on the surface of the epitaxial layer 20 by chemical vapor deposition to fill the trench T1, and the conductive layer on the surface of the epitaxial layer 20 and in the trench T1 is partially etched, leaving a conductive layer such as Figure 3G The portion of the conductor layer shown serves as the gate conductor 60. The portion of the conductor layer may be etched by reactive ion etching.
[0062] Then, the third insulating layer 33 is formed again so that the third insulating layer 33 covers the gate conductor 60 , and the third insulating layer 33 is partially etched so that the surface of the third insulating layer 33 is flush with the surface of the epitaxial layer 20 .
[0063] The first insulating layer 31, the second insulating layer 32, and the third insulating layer 33 collectively form the insulating layer 30. The materials of the first insulating layer 31, the second insulating layer 32, and the third insulating layer 33 can be the same or different, and the composition and arrangement of the first insulating layer 31, the second insulating layer 32, and the third insulating layer 33 are not limited. The thickness of the first insulating layer 31 on the sidewalls of the trench T1 is greater than the thickness of the second insulating layer 32 on the sidewalls of the trench T1.
[0064] See also Figures 4A to 4C , is a flow chart illustrating forming a dielectric region according to another embodiment of the present application, wherein Figure 4A correspond Figure 2 As shown in step S14, Figure 4B and Figure 4C correspond Figure 2 Step S15 is shown.
[0065] like Figure 4A As shown, a dielectric layer 50 is formed in the trench T1 and on the epitaxial layer 20, and then planarized by chemical mechanical polishing. Figure 4B As shown in FIG. 1 , the dielectric layer 50 on the first insulating layer 31 in the trench T1 is partially etched by wet etching. Figure 4CAs shown, the concentration of the wet etching solution and the etching time are adjusted, and the dielectric layer 50 located in the trench T1 is partially etched again through wet etching, leaving the dielectric layer 50 located on the first insulating layer 31 and at the junction of the two side walls of the trench T1 as two dielectric regions 51. Each dielectric region 51 partially covers the first insulating layer 31 and a portion of the sidewall of the trench T1.
[0066] See also Figure 5 , which is a cross-sectional view of a trench field effect transistor according to another embodiment of the present application. As shown in FIG4 , the trench field effect transistor includes: a substrate 10, an epitaxial layer 20, a trench T1, an insulating layer 30, a shielding conductor 40, a gate conductor 60, a dielectric region 51, a well region 70, a source region 80, an interlayer dielectric layer 90, a body contact region 100, a conductive channel, a source metal layer 110, and a drain metal layer 120, wherein the configuration of the substrate 10, the epitaxial layer 20, the trench T1, the insulating layer 30, the shielding conductor 40, the gate conductor 60, and the dielectric region 51 is similar to that of FIG4 . Figure 1 The configurations of the illustrated embodiments are the same and will not be described again here.
[0067] A well region 70 is disposed in the epitaxial layer 20 and is adjacent to the trench T1; the well region 70 is of the second doping type. A source region 80 is disposed above the well region 70 and is adjacent to the trench T1; the source region 80 is of the first doping type. A body contact region 100 is disposed in the well region 70 and is adjacent to the source region 80; the body contact region 100 is of the second doping type.
[0068] Interlayer dielectric layer 90 is disposed on source region 80, located on gate conductor 60, and covering the opening of trench T1; in other words, interlayer dielectric layer 90 is located on epitaxial layer 20. Conductive vias penetrate interlayer dielectric layer 90 and source region 80 and extend to body contact region 100. Metal region 110 includes a source metal layer 111 and two conductive vias 112. Source metal layer 111 is disposed on interlayer dielectric layer 90, and two conductive vias 112 are located on opposite sides of interlayer dielectric layer 90. The source metal layer is electrically connected to body contact region 100 through the conductive vias. Drain metal layer 120 is disposed on second surface F2 of substrate 10.
[0069] See also Figure 6 , which is a flow chart illustrating a method for manufacturing a trench field effect transistor according to another embodiment of the present application. Figure 6 As shown, the manufacturing method of the trench field effect transistor includes steps S21 to S33; wherein steps S21 to S26 are Figure 2 Steps S11 to S16 are the same and will not be described again here. Figure 6 The manufacturing method of the trench field effect transistor shown in the figure can be used to manufacture the following Figure 5The trench field effect transistor 1B is shown, but not limited thereto. Figure 6 The manufacturing method of the trench field effect transistor shown in FIG. Figure 5 The trench field effect transistor 1B is shown.
[0070] Step S27: forming a well region 70 in the epitaxial layer 20 near the trench T1. Figure 7A As shown, with the trench T1 as a reference, two well regions 70 are formed in the epitaxial layer 20 through ion implantation technology. The two well regions 70 correspond to each other and are located in a region close to the trench T1 .
[0071] Step S28 : forming a source region 80 in a region above the well region 70 and close to the trench T1 .
[0072] like Figure 7B As shown, two source regions 80 are formed in the two well regions 70 by ion implantation technology, so that the two source regions 80 are located above the well regions 70 and close to the trench T1 .
[0073] Step S29 : forming an interlayer dielectric layer 90 on the source region 80 .
[0074] like Figure 7C As shown, an interlayer dielectric layer 90 is formed by chemical vapor deposition to cover the opening of the trench T1 and the two source regions 80, and the interlayer dielectric layer 90 is partially etched to expose a portion of the source region 80; wherein the material of the interlayer dielectric layer 90 may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), aluminum oxide (AlOx), hafnium dioxide (HfO2) or a combination thereof.
[0075] Step S30 : forming a body contact region 100 in the well region 70 .
[0076] like Figure 7D As shown, two body contact regions 100 are formed in the two well regions 70 by ion implantation technology, so that the well regions 70 , the source regions 80 and the body contact regions 100 are adjacent to each other.
[0077] Figure 7A 、 Figure 7B as well as Figure 7D The dimensions of the well region 70, source region 80, and body contact region 100 shown are for illustration only. By controlling ion implantation parameters, such as implantation energy and dose, desired depths and doping concentrations of the well region 70, source region 80, and body contact region 100 can be achieved. Furthermore, an additional photoresist mask can be used to control the lateral extensions of the body region 111 and source region 113.
[0078] Step S31: Forming a conductive channel 112, wherein the conductive channel 112 penetrates the interlayer dielectric layer 90 and the source region 80 and extends to the body contact region 100. The interlayer dielectric layer 90 and the source region 80 are partially etched to form the conductive channel 112 penetrating the interlayer dielectric layer 90 and the source region 80 to reach the body contact region 100.
[0079] Step S32: forming a source metal layer 111 on the interlayer dielectric layer 90, wherein the source metal layer 111 is electrically connected to the body contact region 100 through the conductive via 112. Figure 7E As shown, a source metal layer 111 is formed on the interlayer dielectric layer 90 by sputtering or evaporation to contact the conductive via 112 , so that the source metal layer is electrically connected to the body contact region 100 through the conductive via 112 .
[0080] Step S33 : forming a drain metal layer 120 on the second surface F2 .
[0081] like Figure 7F As shown, the drain metal layer 120 is formed on the second surface F2 of the substrate 10 by sputtering or evaporation.
[0082] In steps S32 to S33, the materials of the source metal layer 110 and the drain metal layer 120 include indium (In), tin (Sn), aluminum (Al), gold (Au), platinum (Pt), indium (In), zinc (Zn), germanium (Ge), silver (Ag), lead (Pb), palladium (Pd), copper (Cu), gold beryllium (AuBe), germanium beryllium (BeGe), nickel (Ni), lead tin (PbSn), chromium (Cr), gold zinc (AuZn), titanium (Ti), tungsten (W) or titanium tungsten (TiW).
[0083] In summary, the trench field effect transistor and the method for manufacturing the trench field effect transistor of the present application form a dielectric region between the shield conductor and the gate conductor, and the dielectric region is located on the sidewall of the trench close to the gate conductor, thereby reducing the value of the gate-drain capacitance and improving the operation of the trench field effect transistor.
Claims
1. A method for manufacturing a trench field effect transistor, characterized in that: include: forming an epitaxial layer on a substrate; forming a trench in the epitaxial layer; forming a first insulating layer and a shield conductor in the trench, wherein the first insulating layer surrounds the shield conductor; forming a dielectric layer on the epitaxial layer, the first insulating layer, and the sidewalls of the trench; Etching a portion of the dielectric layer to form a plurality of dielectric regions, wherein the dielectric regions are located on the first insulating layer and on the sidewalls of the trench, and a distance is provided between two adjacent dielectric regions; as well as A second insulating layer and a gate conductor are formed in the trench, wherein the second insulating layer surrounds the gate conductor and fills the trench.
2. The method for manufacturing a trench field effect transistor according to claim 1, wherein: The dielectric region is located between the shielding conductor and the gate conductor, and a distance between the dielectric region and the gate conductor is smaller than a distance between the dielectric region and the shielding conductor.
3. The method for manufacturing a trench field effect transistor according to claim 1, wherein: The method of partially etching the dielectric layer to form the dielectric region includes: Reactive ion etching is performed on a portion of the dielectric layer located on the epitaxial layer, the first insulating layer, and the sidewalls of the trench to form dielectric layers located on both sidewalls of the trench, wherein the dielectric layers on both sidewalls of the trench are not connected to each other; Adjusting the gas flow rate and reaction time of the reactive ion gas to again etch the portion of the dielectric layer located on both side walls of the trench through the reactive ions; and Two dielectric regions are formed and are respectively located on the first insulating layer and on two opposite side walls of the trench.
4. The method for manufacturing a trench field effect transistor according to claim 1, wherein: The method of partially etching the dielectric layer to form the dielectric region includes: etching the dielectric layer on the epitaxial layer and a portion of the dielectric layer in the trench by wet etching; Adjusting the concentration of the wet etching solution and the etching time, and etching the portion of the dielectric layer located in the trench again through the wet etching; Two dielectric regions are formed and are respectively located on the first insulating layer and on two opposite side walls of the trench.
5. A trench field effect transistor, characterized in that include: substrate; an epitaxial layer, disposed on the substrate; a trench provided in the epitaxial layer, wherein the trench extends from a surface of the epitaxial layer to an interior of the epitaxial layer; an insulating layer, disposed in the groove; a shielding conductor disposed in the trench, wherein the shielding conductor is surrounded by the insulating layer and insulated from the epitaxial layer by the insulating layer; a gate conductor disposed in the trench, wherein the gate conductor is located on the shield conductor and surrounded by the insulating layer, and is insulated from the shield conductor and the epitaxial layer by the insulating layer; and A plurality of dielectric regions are arranged between the shielding conductor and the gate conductor and located on the sidewall of the trench, and a distance is provided between two adjacent dielectric regions.
6. The trench field effect transistor according to claim 5, wherein A distance between the dielectric region and the gate conductor is smaller than a distance between the dielectric region and the shield conductor.
7. The trench field effect transistor according to claim 5, wherein The thickness of the insulating layer between the trench sidewall and the gate conductor sidewall is less than the thickness of the insulating layer between the trench sidewall and the shield conductor sidewall.
8. The trench field effect transistor according to claim 5, wherein There are multiple dielectric regions, and the material of the dielectric regions is a low dielectric constant material, and the dielectric constant of the low dielectric constant material is less than 3.
9.
9. The trench field effect transistor according to claim 5, wherein When the number of the dielectric regions is multiple and is an even number, the dielectric regions are symmetrical to each other with the center line of the gate conductor being the symmetry axis.
Citation Information
Patent Citations
Power MOS device with low gate charge and manufacturing method thereof
CN111524976A