Semiconductor device and method for manufacturing the same

Abstract

The present invention relates to a semiconductor device having improved reliability and a method of manufacturing the same. A method of manufacturing a semiconductor device according to an embodiment of the present invention may include: forming a plurality of bit line structures over a substrate; forming a line-shaped opening between the bit line structures; forming a stopper structure on an edge of the line-shaped opening; filling a line pattern in each of the line-shaped openings; forming a plurality of contact plugs and a plurality of isolation grooves by etching the line pattern; and filling a plug isolation layer in the isolation grooves.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Application No. 10 - 2021 - 0079260, filed on Jun. 18, 2021, which is incorporated herein by reference in its entirety. Technical field

[0003] Various embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device including a stopper structure and a method of manufacturing the semiconductor device. Background art

[0004] A dielectric material is formed between adjacent pattern structures in a semiconductor device. As semiconductor devices are highly integrated, the distance between pattern structures is decreasing. Accordingly, parasitic capacitance increases. The performance of the semiconductor device deteriorates as the parasitic capacitance increases. Therefore, an improved structure is needed to maintain and further improve the reliability of the semiconductor device. Summary of the invention

[0005] Various embodiments of the present invention provide a semiconductor device having improved reliability and a method of manufacturing the semiconductor device.

[0006] A semiconductor device according to an embodiment of the present invention may include: a substrate including a cell array region and a cell array edge region; a plurality of bit - line structures formed over the cell array region of the substrate; a stopper structure formed over the cell array edge region of the substrate; a plurality of storage - node contact plugs formed between the bit - line structures in the cell array region; and dummy plugs formed on the stopper structure.

[0007] A method of manufacturing a semiconductor device according to an embodiment of the present invention may include: forming a plurality of bit - line structures over a substrate; forming a line - shaped opening between the bit - line structures; forming a stopper structure on an edge of the line - shaped opening; filling a line pattern in each of the line - shaped openings; forming a plurality of contact plugs and a plurality of isolation grooves by etching the line pattern; and filling a plug isolation layer in the isolation grooves.

[0008] A semiconductor device according to an embodiment of the present invention may include: a plurality of bit line structures, each of the bit line structures including a bit line contact plug formed on a substrate, a bit line formed on the bit line contact plug, and a bit line hard mask formed on the bit line contact plug; a plurality of storage node contact plugs formed between the bit line structures above a cell array region of the substrate; a plurality of plug isolation layers, wherein each plug isolation layer is disposed between a pair of adjacent storage node contact plugs; a stopper structure formed above a cell array edge region of the substrate; and a plurality of dummy plugs formed above the cell array edge region of the substrate separated by another plurality of plug isolation layers, wherein the stopper structure is located at a level higher than a bottom surface of the plurality of storage node contact plugs.

[0009] The present invention can prevent etching defects of the storage node contact plugs by forming a stopper structure at the cell array edge region.

[0010] These and other features of the present invention will be better understood from the following drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A is a plan view of a semiconductor device illustrating an embodiment of the present invention.

[0012] Figure 1B is a cross-sectional view taken along line A-A' of Figure 1A FIG. 1.

[0013] Figures 2A to 2N is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0014] Various embodiments described herein will be described with reference to cross-sectional views, plan views, and block diagrams that are ideal schematic diagrams of the present invention. Accordingly, the structure of the drawings may be modified by manufacturing techniques and / or tolerances. The various embodiments of the present invention are not limited to the specific structures shown in the drawings, but include any variations of the structures that can be produced according to the manufacturing process. In addition, any regions and the shapes of the regions shown schematically in the drawings are intended to illustrate specific examples of the regional structures of various elements, and are not intended to limit the scope of the present invention.

[0015] Figure 1A is a plan view of a semiconductor device illustrating an embodiment of the present invention. Figure 1B is a cross-sectional view taken along line A-A' of FIG. 1.

[0016] Referring to Figures 1A to 1B FIG. 1, the semiconductor device 100 may include a plurality of memory cells. Each memory cell may include a cell transistor, and the cell transistor may include a buried word line 207 and a bit line 213.

[0017] The semiconductor device 100 will be described in detail below.

[0018] A device isolation layer 202 and active regions 203 may be formed in a substrate 201. The plurality of active regions 203 may be defined by the device isolation layer 202. The substrate 201 may be made of a material suitable for semiconductor processing. The substrate 201 may include a semiconductor substrate. The substrate 201 may be formed of a silicon-containing material. The substrate 201 may include silicon, single-crystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single-crystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, combinations thereof, or multiple layers thereof. The substrate 201 may include other semiconductor materials, such as germanium. The substrate 201 may include a group III / V semiconductor substrate, such as a compound semiconductor substrate, such as GaAs. The substrate 201 may include a silicon on insulator (SOI) substrate. The device isolation layer 202 may be formed by a Shallow Trench Isolation (STI) process.

[0019] A gate trench 205 may be formed in the substrate 201. A gate dielectric layer 206 may be conformally formed on the bottom surface and side surfaces of the gate trench 205. A buried word line 207 may be formed on the gate dielectric layer 206. The buried word line 207 may partially fill the lower portion of the gate trench 205 on the gate dielectric layer 206. A gate capping layer 208 may be formed on the buried word line 207. The upper surface of the buried word line 207 may be disposed at a level lower than the upper surface of the substrate 201. The buried word line 207 may be formed of a metal material having a low resistivity. The buried word line 207 may be formed by sequentially stacking titanium nitride (TiN) and tungsten (W). In another embodiment, the buried word line 207 may be formed only of titanium nitride. The buried word line 207 may also be referred to as a "buried gate electrode". The buried word line 207 may extend along its major axis in a first direction D1.

[0020] A first impurity region 209 and a second impurity region 210 may be formed in the substrate 201. The first impurity region 209 and the second impurity region 210 may be spaced apart from each other by the gate trench 205. The first impurity region 209 and the second impurity region 210 may also be referred to as "source / drain regions". The first impurity region 209 and the second impurity region 210 may include an N-type impurity such as arsenic (As) or phosphorus (P). The buried word line 207 and the first impurity region 209 and the second impurity region 210 may form a unit transistor. The short-channel effect of the unit transistor may be improved by the buried word line 207.

[0021] The bit line contact plug 212 can be formed on the substrate 201. The bit line contact plug 212 can be formed on the first impurity region 209. The bit line contact plug 212 can be disposed inside the bit line contact hole 211. The bit line contact hole 211 can penetrate through the hard mask layer 204 formed on the substrate 201 and extend into the substrate 201. The hard mask layer 204 can be formed on the substrate 201. The hard mask layer 204 can include a dielectric material. The bit line contact hole 211 can expose the first impurity region 209. The lower surface of the bit line contact plug 212 can be disposed at a level lower than the upper surfaces of the device isolation layer 202 and the active region 203. The bit line contact plug 212 can be formed of polysilicon or a metal material. A part of the bit line contact plug 212 can have a line width smaller than the diameter of the bit line contact hole 211. The bit line 213 can be formed on the bit line contact plug 212. The bit line hard mask 214 can be formed on the bit line 213. The stacked structure of the bit line contact plug 212, the bit line 213, and the bit line hard mask 214 can also be referred to as a "bit line structure". The bit line 213 can have a line shape extending in a second direction D2 intersecting the buried word line 207. A part of the bit line 213 can be connected to the bit line contact plug 212. The line widths of the bit line 213 and the bit line contact plug 212 can be the same in a first direction. Accordingly, the bit line 213 can cover the bit line contact plug 212 and extend in the second direction D2. The bit line hard mask 214 can include a dielectric material such as silicon nitride.

[0022] The spacer structure BLS can be formed on the sidewalls of the bit line structure. The spacer structure BLS can extend to be disposed on the sidewalls of the bit line contact plug 212. For example, the spacer structure BLS on two sidewalls of the bit line 213 can include a first spacer 215, a second spacer 217, and a third spacer 218. The spacer structure BLS of the bit line contact plug 212 can include a first spacer 215 and a gap-fill spacer 216. The spacer structure BLS can include silicon nitride, silicon oxide, a low-k material, or a combination thereof. The low-k material can include silicon boron nitride (SiBN), silicon carbon oxide (SiCO), silicon carbon nitride (SiCN), silicon boron carbon nitride (SiBCN), or a combination thereof. The first spacer 215 and the gap-fill spacer 216 can include silicon nitride, and the second spacer 217 can include silicon oxide or a low-k material. In another embodiment, the spacer structure BLS can include a multi-layer spacer including NKON, NKNAN, NKOK, NKOKN, NKAKN, KOK, or KAK, where N refers to silicon nitride, K refers to a low-k material, O refers to silicon oxide, and A indicates an air gap. In another embodiment, the outermost spacer of the spacer structure BLS can include a low-k material.

[0023] The storage node contact plug 221 may be formed between adjacent bit line structures. The storage node contact plug 221 may be connected to the second impurity region 210. The storage node contact plug 221 may include polysilicon, metal nitride, metal material, metal silicide, or a combination thereof. In some embodiments, the storage node contact plug 221 may be formed by sequentially stacking polysilicon, cobalt silicide, and tungsten.

[0024] When viewed from a direction parallel to the bit line structure, the plug isolation layer 222 may be formed between adjacent storage node contact plugs 221. The plug isolation layer 222 may be formed between adjacent bit line structures. The storage node contact plugs 221 adjacent to each other along the second direction D2 may be spaced apart by the storage node contact plugs 221. The plurality of plug isolation layers 222 and the plurality of storage node contact plugs 221 may be alternately disposed between adjacent bit line structures along the second direction D2. The storage node contact plug 221 may directly contact the third spacer 218 of the spacer structure BLS, and the third spacer 218 may include a low-k material.

[0025] A storage element (not shown) may be formed on the storage node contact plug 221. The storage element may include a capacitor having a storage node. The storage node may include a columnar storage node. The storage node may also include a cylindrical storage node, or a combination of a cylindrical and a columnar storage node.

[0026] Although not shown, a dielectric layer and a plate node may be formed on the storage node.

[0027] The plug isolation layer 222 may include silicon nitride or a low-k material. In the case where the plug isolation layer 222 includes a low-k material, the parasitic capacitance between adjacent storage node contact plugs 221 with the plug isolation layer 222 interposed therebetween may be reduced. The plug isolation layer 222 may include SiCO, SiCN, SiOCN, SiBN, or SiBCN.

[0028] According to Figure 1A and Figure 1B , the semiconductor device 100 may include a cell array region CA and a cell array edge region ME. A plurality of storage node contact plugs 221 may be formed in the cell array region CA, and a plurality of dummy plugs 221D may be formed in the cell array edge region ME. A stopper structure 230 may be disposed under the dummy plug 221D. The cell array edge region ME may refer to the edge of the cell array region CA. In addition, the cell array edge region ME may refer to the boundary region between the cell array region CA and a peripheral circuit region (not shown). The cell array region CA may be a cell pad region, and the cell array edge region ME may be a cell pad edge region.

[0029] The bottom surface of the storage node contact plug 221 may be disposed at a level lower than the bottom surface of the dummy plug 221D. A planarization structure may be formed by forming a stopper structure 230 under the dummy plug 221D. As will be described below, the storage node contact plug 221 and the dummy plug 221D may be formed simultaneously. For example, the storage node contact plug 221 and the dummy plug 221D may be formed simultaneously by forming and etching a line-shaped polysilicon layer in the cell array region CA and the cell array edge region ME.

[0030] As described above, the stopper structure 230 may be formed in the cell array edge region ME to reduce the etching difficulty for forming the storage node contact plug 221 and the dummy plug 221D and may prevent etching defects.

[0031] The stopper structure 230 may be formed of the same material as a part of the spacer structure BLS. For example, the stopper structure 230 may include silicon nitride, silicon oxide, or a combination thereof. After forming the spacer structure BLS having a multilayer structure of silicon nitride and silicon oxide, the silicon nitride or silicon oxide may be partially retained without being etched by using a mask layer, and may be used to form the stopper structure 230. In the present embodiment, the stopper structure 230 may include a stack of a first stopper 231 and a second stopper 232. The first stopper 231 and the second stopper 232 may include silicon nitride. The first stopper 231 and the first spacer 215 may be formed of the same material (e.g., silicon nitride). The second stopper 232 and the gap spacer 216 may be formed of the same material (e.g., silicon nitride).

[0032] Figures 2A to 2N is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. Figures 2A to 2N is illustrated based on a cross-sectional view taken along Figure 1A the line A-A' of.

[0033] As Figure 2AAs shown, a device isolation layer 12 may be formed in a substrate 11. The substrate 11 may include a cell array region CA and a cell array edge region ME. A plurality of active regions 13 may be defined by the device isolation layer 12. The device isolation layer 12 may be formed through a Shallow Trench Isolation (STI) process. The STI process may be as follows. An isolation trench (reference numeral omitted) is formed by etching the substrate 11. The isolation trench is filled with a dielectric material to form the device isolation layer 12. The device isolation layer 12 may include silicon oxide, silicon nitride, or a combination thereof. Chemical vapor deposition or other deposition processes may be used to fill the isolation trench with the dielectric material. At least one planarization process, such as chemical-mechanical polishing (CMP), may be utilized.

[0034] Next, a buried word line structure may be formed in the substrate 11. The buried word line structure may include: a gate trench 15, a gate dielectric layer 16 conformally covering the bottom surface and sidewalls of the gate trench 15, a buried word line 17 partially filling the lower part of the gate trench 15 on the gate dielectric layer 16, and a gate capping layer 18 formed on the buried word line 17.

[0035] The method for forming the buried word line structure may be as follows.

[0036] First, a gate trench 15 may be formed in the substrate 11. The gate trench 15 may have a line shape intersecting the active region 13 and the device isolation layer 12. The gate trench 15 may be formed through an etching process that includes forming a mask pattern (not shown) on the substrate 11 and using the mask pattern as an etching mask. To form the gate trench 15, a hard mask layer 14 may be used as an etching stop layer. The hard mask layer 14 may have a shape patterned through the mask pattern. The hard mask layer 14 may include silicon oxide. The hard mask layer 14 may include tetra ethyl ortho silicate (TEOS). The bottom of the gate trench 15 may be at a level higher than the bottom of the device isolation layer 12.

[0037] Although not shown, a part of the isolation layer 12 may be recessed to expose the active region 13 disposed under the gate trench 15. For example, the device isolation layer 12 disposed under the gate trench 15 may be selectively recessed along the length direction of the gate trench 15. Thus, a fin region (reference numeral omitted) may be formed under the gate trench 15. The fin region may be a part of the channel region.

[0038] Next, a gate dielectric layer 16 can be formed on the bottom surface and sidewalls of the gate trench 15. Before forming the gate dielectric layer 16, the etching damage on the surface of the gate trench 15 can be cured. For example, a sacrificial oxide can be formed and removed by thermal oxidation treatment.

[0039] The gate dielectric layer 16 can be formed by a thermal oxidation process. For example, the gate dielectric layer 16 can be formed by oxidizing the bottom surface and sidewalls of the gate trench 15.

[0040] In another embodiment, the gate dielectric layer 16 can be formed by a deposition method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The gate dielectric layer 16 can include a high-k material, an oxide, a nitride, a oxynitride, or a combination thereof. The high-k material can include a hafnium-containing material. The hafnium-containing material can include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In another embodiment, the high-k material can include lanthanum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, and combinations thereof.

[0041] In another embodiment, the gate dielectric layer 16 can be formed by depositing a liner polysilicon layer and then thoroughly oxidizing the liner polysilicon layer.

[0042] In yet another embodiment, the gate dielectric layer 16 can be formed by forming a liner silicon nitride layer and then thoroughly oxidizing the liner silicon nitride layer thereafter.

[0043] Next, a buried word line 17 can be formed on the gate dielectric layer 16. To form the buried word line 17, a recess process can be performed after forming a conductive layer (not shown) to fill the gate trench 15. The recess process can be performed by an etch-back process or a chemical mechanical polishing (CMP) process followed by an etch-back process. The buried word line 17 can have a recessed shape that partially fills the gate trench 15. That is, the upper surface of the buried word line 17 can be at a level lower than the upper surface of the active region 13. The buried word line 17 can include a metal, a metal nitride, or a combination thereof. For example, the buried word line 17 can be formed of titanium nitride (TiN), tungsten (W), or a titanium nitride / tungsten (TiN / W) stack. The titanium nitride / tungsten (TiN / W) stack can have a structure in which titanium nitride is conformally formed and then tungsten is used to partially fill the gate trench 15. Titanium nitride can be used alone as the buried word line 17, which can also be referred to as a buried word line 17 with a "TiN-only structure". A dual-gate structure of a titanium nitride / tungsten (TiN / W) stack and a polysilicon layer can be used as the buried word line 17.

[0044] Next, a gate capping layer 18 can be formed on the buried word line 17. The gate capping layer 18 can include a dielectric material. The gate capping layer 18 is used to fill the remaining part of the gate trench 15 on the buried word line 17. The gate capping layer 18 can include silicon nitride. In another embodiment, the gate capping layer 18 can include silicon oxide. In yet another embodiment, the gate capping layer 18 can have a Nitride-Oxide-Nitride (NON) structure. The upper surface of the gate capping layer 18 can be at the same level as the upper surface of the hard mask layer 14. To this end, a chemical mechanical polishing (CMP) process can be performed when forming the gate capping layer 18.

[0045] After forming the gate capping layer 18, impurity regions 19 and 20 can be formed. The impurity regions 19 and 20 can be formed by a doping process such as ion implantation. The impurity regions 19 and 20 can include a first impurity region 19 and a second impurity region 20. The first impurity region 19 and the second impurity region 20 can be doped with impurities of the same conduction type. The first impurity region 19 and the second impurity region 20 can have the same depth. In another embodiment, the first impurity region 19 can be deeper than the second impurity region 20. The first impurity region 19 and the second impurity region 20 can also be referred to as source / drain regions. The first impurity region 19 can be the region to which the bit line contact plug is to be connected, and the second impurity region 20 can be the region to which the storage node contact plug is to be connected. The first impurity region 19 and the second impurity region 20 can be disposed in different active regions 13. In addition, the first impurity region 19 and the second impurity region 20 can be disposed in their respective active regions 13 while being spaced apart from each other by the gate trench 15.

[0046] The cell transistor of the memory cell can be formed by the buried word line 17 and the first impurity region 19 and the second impurity region 20.

[0047] As Figure 2BAs shown, bit line contact holes 21 can be formed. A hard mask layer 14 can be etched using a contact mask (not shown) to form the bit line contact holes 21. When observed in a plan view, the bit line contact holes 21 can have a circular shape or an elliptical shape. A portion of the substrate 11 can be exposed through the bit line contact holes 21. The bit line contact holes 21 can have a diameter controlled by a predetermined line width. The bit line contact holes 21 can have a shape that exposes a portion of the active region 13. For example, the first impurity region 19 can be exposed through the bit line contact holes 21. The bit line contact holes 21 can have a diameter greater than the width of the minor axis of the active region 13. Accordingly, during the etching process for forming the bit line contact holes 21, the first impurity region 19, the device isolation layer 12, and the gate capping layer 18 can be partially etched. That is, the gate capping layer 18, the first impurity region 19, and the device isolation layer 12 under the bit line contact holes 21 can be recessed to a predetermined depth. Accordingly, the bottom of the bit line contact holes 21 can extend into the substrate 11. As the bit line contact holes 21 expand, the surface of the first impurity region 19 can be recessed, and the upper surface of the first impurity region 19 can be located at a level lower than the upper surface of the active region 13.

[0048] As Figure 2C shown, a pre-plug 22A can be formed. The pre-plug 22A can be formed by selective epitaxial growth (SEG). For example, the pre-plug 22A can include an epitaxial layer doped with phosphorus, such as SEG SiP. In this way, a void-free pre-plug 22A can be formed by selective epitaxial growth. In another embodiment, the pre-plug 22A can be formed by depositing a polysilicon layer and performing a CMP process on the polysilicon layer. The pre-plug 22A can fill the bit line contact holes 21. The upper surface of the pre-plug 22A can be at the same level as the upper surface of the hard mask layer 14.

[0049] As Figure 2D shown, a bit line conductive layer 23A and a bit line hard mask layer 24A can be stacked. The bit line conductive layer 23A and the bit line hard mask layer 24A can be sequentially stacked on the pre-plug 22A and the hard mask layer 14. The bit line conductive layer 23A can include a metal-containing material. The bit line conductive layer 23A can include a metal, a metal nitride, a metal silicide, or a combination thereof. In the present embodiment, the bit line conductive layer 23A can include tungsten (W). In another embodiment, the bit line conductive layer 23A can include a stack of titanium nitride and tungsten (TiN / W). In this case, titanium nitride can be used as a barrier layer. The bit line hard mask layer 24A can be formed of an insulating material having an etching selectivity with respect to the bit line conductive layer 23A and the pre-plug 22A. The bit line hard mask layer 24A can include silicon oxide or silicon nitride. In the present embodiment, the bit line hard mask layer 24A can be formed of silicon nitride.

[0050] As Figure 2E shown, a bit line structure can be formed. The bit line structure may include a stack of a bit line contact plug 22, a bit line 23, and a bit line hard mask 24. The bit line contact plug 22, the bit line 23, and the bit line hard mask 24 can be formed by an etching process using a bit line mask layer (not shown).

[0051] The bit line hard mask layer 24A and the bit line conductive layer 23A are etched using the bit line mask layer as an etching stopper layer. Thus, the bit line 23 and the bit line hard mask 24 can be formed. The bit line 23 can be formed by etching the bit line conductive layer 23A. The bit line hard mask 24 can be formed by etching the bit line hard mask layer 24A.

[0052] Subsequently, the pre-plug 22A can be etched to have the same line width as the bit line 23. Thus, the bit line contact plug 22 can be formed. The bit line contact plug 22 can be formed over the first impurity region 19. The bit line contact plug 22 can interconnect the first impurity region 19 and the bit line 23. The bit line contact plug 22 can be formed in the bit line contact hole 21. The line width of the bit line contact plug 22 is smaller than the diameter of the bit line contact hole 21. Thus, a gap 25 can be defined on both sides of the bit line contact plug 22.

[0053] As described above, when the bit line contact plug 22 is formed, the gap 25 is formed in the bit line contact hole 21. This is because the bit line contact plug 22 is formed to be smaller than the diameter of the bit line contact hole 21. The gap 25 is not formed to surround the bit line contact plug 22, but is independently formed on two sidewalls of the bit line contact plug 22. As a result, one bit line contact plug 22 and a pair of gaps 25 are located in the bit line contact hole 21, and the pair of gaps 25 are separated from each other by the bit line contact plug 22. The bottom surface of the gap 25 can extend into the device isolation layer 12. The bottom surface of the gap 25 can be at a level lower than the recessed upper surface of the first impurity region 19.

[0054] The structure in which the bit line contact plug 22, the bit line 23, and the bit line hard mask 24 are sequentially stacked can also be referred to as a bit line structure. When viewed from above, the bit line structure can be a line-shaped pattern structure extending in any direction.

[0055] A line-shaped opening LO can be defined between adjacent bit line structures. The line-shaped opening LO can be parallel to the bit line structure. The hard mask layer 14 can be exposed through the line-shaped opening LO. The line-shaped opening LO can extend from the cell array region CA to the cell array edge region ME. The hard mask layer 14 in the cell array edge region ME can also be exposed through the line-shaped opening LO.

[0056] As Figure 2FAs shown, a first spacer layer 26A may be formed on the bit line structure. The first spacer layer 26A may cover both the sidewalls of the bit line contact plug 22 and the sidewalls of the bit line 23. The first spacer layer 26A may cover both the sidewalls and the upper surface of the bit line hard mask 24. The first spacer layer 26A may include an insulating material. In this embodiment, the first spacer layer 26A may include silicon nitride.

[0057] A second spacer layer 27A may be formed on the first spacer layer 26A. The second spacer layer 27A and the first spacer layer 26A may be formed of the same material. The second spacer layer 27A may include silicon nitride. The second spacer layer 27A may be conformally formed on the first spacer layer 26A disposed on the upper surface and the side surfaces of the bit line structure. The second spacer layer 27A may fill the gap 25 on both sides of the bit line contact plug 22.

[0058] The first spacer layer 26A and the second spacer layer 27A may be formed in the cell array edge region ME. For example, the first spacer layer 26A and the second spacer layer 27A may extend from the cell array region CA to the cell array edge region ME.

[0059] As Figure 2G shown, a mask layer 28 may be formed. The mask layer 28 may shield the cell array edge region ME. The mask layer 28 may include a photoresist pattern. The second spacer layer 27A in the cell array region CA may be selectively exposed by the mask layer 28.

[0060] Next, the second spacer layer 27A may be selectively etched. For example, the second spacer layer 27A may be trimmed to fill the gap 25 on both sides of the bit line contact plug 22. Thus, the second spacer layer 27A may be retained in the gap 25 on both sides of the bit line contact plug 22, and the second spacer layer 27A may not be retained on the first spacer layer 26A on both sides of the bit line 23. The second spacer layer 27A may be retained in the cell array edge region ME.

[0061] The second spacer layer filling the gap 25 is simply referred to as the "gap-fill spacer 27", and the second spacer layer retained in the cell array edge region is simply referred to as the "stop liner 27L". The first spacer layer 26A may be retained under the stop liner 27L. Hereinafter, the first spacer layer retained in the cell array edge region ME is denoted by the reference numeral "26L", and the stack of the first spacer layer 26L and the stop liner 27L retained in the cell array edge region ME is referred to as the "stop structure ESL".

[0062] As Figure 2HAs shown, after removing the mask layer 28, a third spacer layer 29A can be formed on the stop liner 27L. The third spacer layer 29A can include silicon oxide. The third spacer layer 29A can be formed in the cell array region CA and the cell array edge region ME. In the cell array region CA, the third spacer layer 29A can be formed on the first spacer layer 26A. In the cell array edge region ME, the third spacer layer 29A can be formed on the stop liner 27L.

[0063] As Figure 2I shown, the third spacer layer 29A can be etched to form the third spacer 29. An etch-back process of the third spacer layer 29A can be performed to form the third spacer 29. The third spacer 29 can cover the upper portion of the gap-fill spacer 27. The third spacer 29 can be located on two sidewalls of the bit line 23, with the first spacer layer 26A interposed therebetween. In the cell array edge region ME, the third spacer layer 29A can remain on the stop liner 27L.

[0064] As Figure 2J shown, the third spacer 29 can be formed. A fourth spacer layer 30A can be formed on the third spacer layer 29A and the third spacer 29. The fourth spacer layer 30A can include silicon nitride.

[0065] As Figure 2K shown, the fourth spacer layer 30A can be selectively etched to form the fourth spacer 30 on the sidewalls of the line-shaped opening LO.

[0066] The lower material can be etched to be self-aligned to the fourth spacer 30. Thus, a plurality of recessed regions 31 exposing a part of the active region 13 can be formed between the bit line structures. The recessed regions 31 can be formed using anisotropic etching or a combination of anisotropic etching and isotropic etching. For example, the fourth spacer layer 30A and the first spacer layer 26A disposed between the bit line structures can be sequentially etched anisotropically, and then the exposed portion of the active region 13 can be etched isotropically. In another embodiment, the hard mask layer 14 can also be etched isotropically. The active region 13 and a part of the gap-fill spacer 27 can be exposed through the recessed regions 31.

[0067] The recessed regions 31 can extend into the substrate 11. During the formation of the recessed regions 31, the device isolation layer 12, the gate capping layer 18, and the second impurity region 20 can be recessed to a predetermined depth. The bottom surface of the recessed regions 31 can be at a level lower than the upper surface of the bit line contact plug 22. The bottom surface of the recessed regions 31 can be at a level higher than the bottom surface of the bit line contact plug 22. The line-shaped opening LO and the recessed regions 31 can be interconnected. The vertical structure of the line-shaped opening LO and the recessed regions 31 can also be referred to as a "storage node contact hole".

[0068] The spacer structure BLS can be formed on the sidewalls of the bit line structure by etching the fourth spacer layer 30A and the first spacer layer 26A while forming the recessed region 31. The spacer structure BLS can include materials having different dielectric constants.

[0069] The spacer structure BLS can include a first spacer 26, a third spacer 29, and a fourth spacer 30. The first spacer 26 can directly contact the sidewalls of the bit line contact plug 22 and the bit line 23. The third spacer 29 can cover the first spacer 26, and the fourth spacer 30 can cover the third spacer 29. The first spacer 26 can be located between the gap-fill spacer 27 and the bit line contact plug 22. The third spacer 29 can be located between the fourth spacer 30 and the first spacer 26.

[0070] The first spacer 26, the third spacer 29, and the fourth spacer 30 can be sequentially stacked on the sidewall of the bit line 23. The first spacer 26 and the gap-fill spacer 27 can be stacked on the sidewall of the bit line contact plug 22.

[0071] As Figure 2L shown, a line pattern 32 can be formed to fill each line-shaped opening LO. The line pattern 32 can fill the line-shaped opening LO and the recessed region 31. The line pattern 32 can contact the second impurity region 20. The line pattern 32 can be disposed adjacent to the bit line structure. When viewed from above, a plurality of line patterns 32 can be located between a plurality of bit line structures.

[0072] The line pattern 32 can extend to the cell array edge region ME while being formed in the cell array region CA. In the line pattern 32, a planarization structure can be formed in the cell array region CA and the cell array edge region ME by a stopper structure ESL. The planarization structure means that the bottom surface of the line pattern 32 formed in the cell array region CA is lower than the bottom surface of the line pattern 32 formed in the cell array edge region ME. Due to this planarization structure, subsequent etching processes may become easier.

[0073] As Figure 2MAs shown, the line pattern 32 can be etched by using a mask layer extending in a direction intersecting the line pattern 32. Accordingly, a plurality of contact plugs 32P and a plurality of isolation grooves 32C can be formed. When viewed from above, a plurality of contact plugs 32P can be disposed between adjacent bit line structures, and isolation grooves 32C can be disposed between the contact plugs 32P. During the etching process for forming the isolation grooves 32C, a planarized structure can be formed by the lower stopper structure ESL. The contact plugs formed in the cell array edge region ME can be simply referred to as dummy plugs 32D. The bottom surfaces of the dummy plugs 32D and the bottom surfaces of the contact plugs 32P can be at different heights. For example, the bottom surface of the dummy plug 32D can be at a level higher than the bottom surface of the contact plug 32P.

[0074] According to the present embodiment, the etching difficulty for forming the storage node contact plug 221 and the dummy plug 221D can be reduced, and etching defects can be prevented by forming the stopper structure ESL. When forming the stopper structure ESL, etching can be sufficiently performed to separate adjacent dummy plugs 221D. Accordingly, bridging between the dummy plug 221D and the storage node contact plug 221 due to unetched dummy plugs 221D can be prevented. For example, the etching process for forming the dummy plug 221D can be completed before the etching process for forming the storage node contact plug 221 is completed, and thus adjacent dummy plugs 221D can be completely spaced apart. The lower structure disposed under the dummy plug 221D can be prevented from being etched by the stopper structure ESL until the etching process for forming the storage node contact plug 221 is completed.

[0075] As Figure 2N shown, a plug isolation layer 33 filling the isolation grooves 32C can be formed. To form the plug isolation layer 33, silicon nitride deposition and chemical mechanical polishing (CMP) can be sequentially performed.

[0076] Although not shown, a storage node of a capacitor can be subsequently formed on the storage node contact plug 221. In another embodiment, a metal silicide and a metal material can be sequentially formed on the etched-back storage node contact plug 221 before forming the storage node of the capacitor and after etching back the storage node contact plug 221.

[0077] The present invention described above is not limited to the above embodiments and the drawings, and it is apparent to those skilled in the art that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: A substrate including a cell array region and a cell array edge region; A plurality of bit line structures formed over the cell array region of the substrate; A stopper structure formed over the cell array edge region of the substrate; A plurality of storage node contact plugs formed between the bit line structures in the cell array region; And A plurality of dummy plugs formed on the stopper structure; Wherein the bit line structures extend from the cell array region to the cell array edge region; Wherein the plurality of dummy plugs are located between the bit line structures in the cell array edge region; Wherein the stopper structure is formed between the substrate and the dummy plugs.

2. The semiconductor device according to claim 1, wherein, The bottom surface of the dummy plug is disposed at a level higher than the bottom surface of the storage node contact plug.

3. The semiconductor device according to claim 1, wherein, The stopper structure includes silicon nitride, silicon oxide, or a combination thereof.

4. The semiconductor device according to claim 1, further comprising a multilayer spacer formed on two sidewalls of the bit line structure.

5. The semiconductor device according to claim 4, wherein, The multilayer spacer and the stopper structure include the same material.

6. The semiconductor device according to claim 1, wherein, The bit line structure includes a stack structure of a bit line contact plug, a bit line formed on the bit line contact plug, and a bit line hard mask formed on the bit line.

7. The semiconductor device according to claim 6, further comprising: A first spacer covering sidewalls of the bit line contact plug and the bit line; A gap-fill spacer disposed on the first spacer above two sidewalls of the bit line contact plug; And A second spacer disposed on the first spacer and covering two sidewalls of the bit line, Wherein the stopper structure and the gap spacer include the same material.

8. The semiconductor device according to claim 7, wherein, The gap-fill spacer and the stopper structure include silicon nitride.

9. The semiconductor device according to claim 1, wherein, The storage node contact plug and the dummy plug include polysilicon.

10. The semiconductor device according to claim 1, further comprising a plug isolation layer located between the bit line structures, Among them, The storage node contact plug and the dummy plug are disposed between the plug isolation layers.

11. The semiconductor device according to claim 10, wherein, The plug isolation layer includes silicon nitride.

12. A method for manufacturing a semiconductor device, comprising: Forming a plurality of bit line structures over a substrate; Forming a line-shaped opening between the bit line structures; Forming a stopper structure on an edge of the line-shaped opening; Filling each of the line-shaped openings above the stopper structure with a line pattern; Forming a plurality of contact plugs and a plurality of isolation grooves by etching the line pattern; Filling the isolation grooves with a plug isolation layer; Wherein the substrate includes a cell array region and a cell array edge region; and Wherein the contact plugs include a plurality of storage node contact plugs formed over the cell array region and a plurality of dummy plugs formed over the cell array edge region; Wherein the bit line structures extend from the cell array region to the cell array edge region; Wherein the plurality of dummy plugs are located between the bit line structures in the cell array edge region; Wherein the stopper structure is formed between the substrate and the dummy plugs.

13. The method according to claim 12, wherein The forming of the stopper structure includes: Form a spacer layer on the bit line structure; Form a mask layer on the spacer layer to cover the edges of the line-shaped openings; and Etch the spacer layer by using the mask layer to form the stopper structure remaining on the edges of the line-shaped openings.

14. The method according to claim 12, wherein The stopper structure includes silicon nitride, silicon oxide, or a combination thereof.

15. The method according to claim 12, wherein, Forming the line-shaped openings between the bit line structures includes: Form a multi-layer spacer layer on the bit line structure, wherein the stopper structure retains a portion of the multi-layer spacer layer.

16. The method according to claim 15, wherein, The multi-layer spacer layer and the stopper structure are made of the same material.

17. The method according to claim 12, wherein, Forming the plurality of contact plugs and the plurality of isolation grooves by etching the line pattern includes: Form a mask layer extending in a direction intersecting the line pattern; and Etch the line pattern by using the mask layer.

18. The method according to claim 12, wherein, The stopper structure is formed above the cell array edge region, and the dummy plug is formed above the stopper structure.

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