Semiconductor structure and preparation method thereof, three-dimensional memory, and storage system

Abstract

The present disclosure provides a semiconductor structure and a preparation method thereof, a three-dimensional memory, and a storage system, which relate to the field of semiconductor chip technology to improve the storage density of the semiconductor structure. The semiconductor structure includes a first stacking structure, a storage structure, and a conductive layer. The first stacking structure includes a first dielectric layer, a first insulating layer, a second insulating layer, a first channel layer, a gate line layer, and a plate line layer; the first channel layer penetrates the gate line layer, and one end of the first channel layer contacts the plate line layer, and at least a portion of the second insulating layer is located between the first channel layer and the gate line layer, and between the gate line layer and the plate line layer. The storage structure includes multiple ferromagnetic free layers, a tunneling layer, and a ferromagnetic pinning layer. Each ferromagnetic free layer contacts the other end of the first channel layer, and the tunneling layer is arranged between the multiple ferromagnetic free layers and the ferromagnetic pinning layers. The conductive layer is located on the side of the ferromagnetic pinning layer away from the tunneling layer. The semiconductor structure is applied to a three-dimensional memory to implement data reading and writing operations.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and a preparation method thereof, a three-dimensional memory, and a storage system. Background Art

[0002] Magnetic Random Access Memory (MRAM) is a non-volatile magnetic random access memory (RAM) that combines the high-speed read and write capabilities of static random access memory (SRAM) with the high integration density of dynamic random access memory (DRAM), and can be rewritten virtually unlimited times. However, increasing the storage density of MRAM structures is a challenge currently under development. Summary of the Invention

[0003] Embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, a three-dimensional memory, and a storage system to improve the storage density of the semiconductor structure.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] In one aspect, a semiconductor structure is provided. The semiconductor structure includes a first stacked structure, a storage structure, and a conductive layer. The first stacked structure includes a plurality of stacked sub-stacked structures. Along the stacking direction of the plurality of sub-stacked structures, the sub-stacked structures include a first dielectric layer, a first insulating layer, a second insulating layer, a first channel layer, a gate line layer, and a plate line layer. The first channel layer extends through the gate line layer, and one end of the first channel layer contacts the plate line layer. At least a portion of the second insulating layer is located between the first channel layer and the gate line layer, and between the gate line layer and the plate line layer. The storage structure extends through the first stacked structure. The storage structure includes a plurality of ferromagnetic free layers, a tunneling layer, and a ferromagnetic pinning layer. Each ferromagnetic free layer contacts the other end of the first channel layer of a sub-stacked structure, and the tunneling layer is disposed between the plurality of ferromagnetic free layers and the ferromagnetic pinning layer. The conductive layer extends through the first stacked structure; the conductive layer is located on a side of the ferromagnetic pinning layer away from the tunneling layer and is coupled to a bit line.

[0006] In some embodiments, the first insulating layer is close to the boundary of the storage structure and is farther away from the central axis of the storage structure than the first dielectric layer and the first channel layer are close to the boundary of the storage structure to form a first groove; the ferromagnetic free layer is disposed in the first groove.

[0007] In some embodiments, the tunneling layer, the ferromagnetic pinning layer, and the conductive layer are at least partially located within the first recess.

[0008] In some embodiments, the plate line layer is close to the boundary of the storage structure and exceeds the second insulating layer close to the boundary of the storage structure. The first channel layer and the portion of the plate line layer exceeding the second insulating layer are the first portion, and the first channel layer and the first portion are in contact with the surface close to the gate line layer.

[0009] In some embodiments, the first insulating layer is close to the boundary of the storage structure and is inward compared to the second insulating layer close to the boundary of the storage structure; the second insulating layer is also arranged between the gate line layer and the first insulating layer, and the second insulating layer includes a first sub-portion in contact with the upper surface of the gate line layer and a second sub-portion in contact with the lower surface of the gate line layer.

[0010] The sub-stack structure further includes a second dielectric layer disposed between the first insulating layer and the second sub-section, and / or the sub-stack structure further includes a third dielectric layer disposed between the first sub-section and the plate line layer.

[0011] In some embodiments, the plurality of ferromagnetic free layers are separated from each other along a first direction. Furthermore, the tunneling layer and the ferromagnetic pinned layer are both continuous film layers along the first direction. The first direction is perpendicular to a reference plane, which is the plane where the lower surface of the first stacked structure lies.

[0012] In some embodiments, the sub-stack structure further includes a third insulating layer, and the third insulating layer is disposed between the plate line layer and the storage structure.

[0013] In some embodiments, the storage structure further includes an antiferromagnetic layer, wherein the antiferromagnetic layer is disposed between the conductive layer and the ferromagnetic pinned layer.

[0014] In some embodiments, the semiconductor structure further includes a first connecting column, the first connecting column passing through the first stack structure, contacting the plate line layer of the first stack structure, and configured to connect to the source layer.

[0015] In some embodiments, the semiconductor structure further includes a second stacked structure and a channel structure. The second stacked structure is disposed on the first stacked structure. The second stacked structure includes at least one select gate line layer and at least one fourth dielectric layer. The channel structure extends through the second stacked structure. The channel structure includes a second channel layer, the second channel layer being electrically connected to the conductive layer and configured to connect to the bit line.

[0016] The semiconductor structure provided by the present disclosure is a random access memory based on spin-transfer torque magnetism, which has the advantages of high speed, low power consumption, and unlimited erasing and rewriting. In addition, the storage structure can be arranged in an array in the direction of the reference plane, and each storage structure includes a plurality of storage cells arranged at intervals in a direction perpendicular to the reference plane. In other words, the plurality of storage cells are arranged in an array in the direction of the reference plane and at intervals in a direction perpendicular to the reference plane, thereby realizing three-dimensional storage and improving the storage density of the semiconductor structure.

[0017] In addition, the gate line of the gate line layer can also individually control whether a corresponding memory cell can be written or read by controlling the conduction and disconnection of the first channel layer, thereby achieving random reading and writing of any memory cell.

[0018] In another aspect, a method for fabricating a semiconductor structure is provided. The method comprises: forming an initial stacking structure; the initial stacking structure comprises a plurality of stacked sub-initial stacking structures. Each sub-initial stacking structure comprises a first dielectric layer, a first insulating layer, a sacrificial layer, and a plate line layer stacked in the direction in which the plurality of sub-initial stacking structures are stacked. A first channel hole is formed through the initial stacking structure. A first channel layer is formed within the first channel hole; the first channel layer is disposed at an end of the sacrificial layer proximal to the first channel hole, and one end of the first channel layer contacts the plate line layer.

[0019] A storage structure and a conductive layer are formed in the first channel hole; the storage structure includes multiple ferromagnetic free layers, a tunneling layer, and a ferromagnetic pinning layer; the ferromagnetic free layer contacts the other end of the first channel layer, and the tunneling layer is arranged between the multiple ferromagnetic free layers and the ferromagnetic pinning layer; the conductive layer is located on the side of the ferromagnetic pinning layer away from the tunneling layer. A gate line gap is formed through the initial stacking structure. The sacrificial layer is removed through the gate line gap to form a second cavity. A second insulating layer and a gate line layer are sequentially formed in the second cavity; at least a portion of the second insulating layer is located between the first channel layer and the gate line layer, and between the gate line layer and the plate line layer.

[0020] In some embodiments, forming the first channel layer in the first channel hole includes: removing an edge portion of the sacrificial layer near the first channel hole through the first channel hole to form a second groove, and forming the first sub-channel layer in the second groove.

[0021] In some embodiments, during the process of forming the initial stacked structure, a second dielectric layer and a third dielectric layer are further formed, wherein the second dielectric layer is disposed between the sacrificial layer and the first insulating layer, and the third dielectric layer is disposed between the sacrificial layer and the plate line layer.

[0022] After forming the first sub-channel layer in the second groove, forming the first channel layer in the first channel hole also includes: removing edge portions of the second dielectric layer and the third dielectric layer near the first channel hole through the first channel hole to form a third groove and a fourth groove, respectively. Forming a second sub-channel layer and a third sub-channel layer in the third groove and the fourth groove, respectively; the second sub-channel layer is disposed at an end portion of the second dielectric layer near the first channel hole and contacts the first insulating layer and the first sub-channel layer; the third sub-channel layer is disposed at an end portion of the third dielectric layer near the first channel hole and contacts the first sub-channel layer and the plate line layer.

[0023] In some embodiments, forming the second sub-channel layer and the third sub-channel layer in the third groove and the fourth groove, respectively, includes: forming a second channel film; the second channel film fills the third groove and the fourth groove and covers the inner wall of the first channel hole and the upper side of the initial stacked structure; and removing the portion of the second channel film covering the inner wall of the first channel hole and the upper side of the initial stacked structure.

[0024] In some embodiments, during the process of removing the edge portions of the second and third dielectric layers near the first channel hole, the edge portion of the first dielectric layer near the first channel hole is also removed to form a fifth groove. During the process of forming the second channel film, the second channel film also covers the inner wall of the fifth groove. During the process of removing the portion of the second channel film covering the inner wall of the first channel hole and the upper side of the initial stacked structure, the portion of the second channel film covering the inner wall of the fifth groove is also removed.

[0025] In some embodiments, after forming the second sub-channel layer and the third sub-channel layer in the third groove and the fourth groove respectively, forming the first channel layer in the first channel hole further includes: forming a first sub-dielectric layer in the fifth groove.

[0026] In some embodiments, between forming the first channel layer in the first channel hole and forming the storage structure and the conductive layer in the first channel hole, the method for fabricating the semiconductor structure further includes: removing an edge portion of the plate line layer near the first channel hole through the first channel hole to form a sixth groove, and forming a third insulating layer in the sixth groove.

[0027] In some embodiments, forming a storage structure and a conductive layer within the first channel hole includes: removing a portion of the first insulating layer near an edge of the first channel hole through the first channel hole to form a first groove. Forming a ferromagnetic free layer within the first groove. Sequentially forming a tunneling film, a ferromagnetic pinning film, and a first conductive film. The tunneling film, the ferromagnetic pinning film, and the first conductive film fill the first groove and cover the inner wall of the first channel hole, the inner wall of the first groove, and the upper side of the initial stacked structure. Removing portions of the tunneling film, the ferromagnetic pinning film, and the first conductive film that cover the upper side of the initial stacked structure.

[0028] In some embodiments, forming a ferromagnetic free layer in the first groove includes forming a ferromagnetic free film; the ferromagnetic free film covers the inner wall of the first groove, the inner wall of the first channel hole, and the upper side of the initial stacked structure; forming a second filling layer in the first groove; removing the portion of the ferromagnetic free film covering the inner wall of the first channel hole and the upper side of the initial stacked structure; and removing the second filling layer.

[0029] In some embodiments, after sequentially forming the tunneling film, the ferromagnetic pinning film, and the first conductive film, forming the memory structure and the conductive layer within the first channel hole further includes: forming a first filling layer within the first channel hole; forming a second conductive film; the second conductive film covering the first filling layer and the portion of the first conductive film located above the initial stacked structure; and removing the portions of the tunneling film, the ferromagnetic pinning film, and the first conductive film that cover the upper side of the initial stacked structure. The portion of the second conductive film that covers the upper side of the initial stacked structure is also removed during the process of removing the portions of the tunneling film, the ferromagnetic pinning film, and the first conductive film that cover the upper side of the initial stacked structure.

[0030] In some embodiments, sequentially forming a second insulating layer and a gate line layer in the second cavity includes: forming a second insulating layer in the second cavity via the gate line gap; forming a gate line thin film; the gate line thin film filling the second cavity and covering an inner wall of the gate line gap and an upper side of the initial stacked structure; and removing a portion of the gate line thin film covering the inner wall of the gate line gap and an upper side of the initial stacked structure.

[0031] In another aspect, a three-dimensional memory is provided, comprising the semiconductor structure described above and a peripheral device, wherein the peripheral device is electrically connected to the semiconductor structure.

[0032] In another aspect, a storage system is provided, comprising the three-dimensional memory as described above and a controller, wherein the controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

[0033] In another aspect, an electronic device is provided, comprising the storage system described above.

[0034] It can be understood that the beneficial effects achieved by the semiconductor structure preparation method, three-dimensional memory, storage system and electronic device provided by the above embodiments of the present disclosure can be referred to the beneficial effects of the semiconductor structure above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0036] Figure 1 is a cross-sectional view of a three-dimensional memory according to some embodiments;

[0037] Figure 2 for Figure 1 A cross-sectional view of a memory cell string of a three-dimensional memory;

[0038] Figure 3 for Figure 2 Equivalent circuit diagram of the storage cell string in FIG;

[0039] Figure 4 is a partial enlarged view of a magnetic tunnel junction of a semiconductor structure according to some embodiments;

[0040] Figure 5 is a partial enlarged view of a magnetic tunnel junction of another semiconductor structure according to some embodiments;

[0041] Figures 6 to 32 is a diagram of preparation steps of a method for preparing a semiconductor structure according to some embodiments;

[0042] Figures 33 to 41 is a flow chart of a method for preparing a semiconductor structure according to some embodiments;

[0043] Figure 42 is a block diagram of a storage system according to some embodiments;

[0044] Figure 43 is a block diagram of a storage system according to some other embodiments. DETAILED DESCRIPTION

[0045] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0046] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0047] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0048] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0049] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0050] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0051] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0052] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0053] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0054] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0055] In the context of this disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes “on something” with intervening features or layers, and “over” or “over” means not only “over” or “above” something, but also includes “over” or “above” something with no intervening features or layers (i.e., directly on something).

[0056] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0057] As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0058] As used herein, the term "vertical / vertically" means nominally perpendicular to a major surface (ie, a lateral surface) of a substrate or source layer.

[0059] See also Figure 1 Some embodiments of the present disclosure provide a three-dimensional memory 10 . The three-dimensional memory 10 may include a semiconductor structure 100 .

[0060] For example, see Figure 1 The three-dimensional memory 10 may further include a source layer SL coupled to the semiconductor structure 100, and a peripheral device 200 coupled to the semiconductor structure 100. The peripheral device 200 may be disposed on a side of the semiconductor structure 100 away from the source layer SL.

[0061] The source layer SL may be made of a semiconductor material, such as single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other suitable semiconductor materials. The source layer SL may be partially or fully doped. For example, the source layer SL may include a doped region doped with a p-type dopant. The source layer SL may also include an undoped region.

[0062] Here, the peripheral device 200 may be disposed on a side of the memory array structure 20 away from the substrate 11 .

[0063] Among them, the peripheral device 200 may include a peripheral circuit. The peripheral circuit is configured to control and sense the array device. The peripheral circuit can be any suitable digital, analog, and / or mixed signal control and sensing circuit for supporting the operation (or work) of the array device, including but not limited to a page buffer, a decoder (such as a row decoder and a column decoder), a sense amplifier, a driver (such as a gate driver), a charge pump, a current or voltage reference, or any active or passive component of the circuit (such as a transistor, a diode, a resistor or a capacitor). The peripheral circuit may also include any other circuit compatible with an advanced logic process, including a logic circuit (such as a processor and a programmable logic device (PLD)) or a memory circuit (such as a static random-access memory (SRAM)).

[0064] In some embodiments, as Figure 1 As shown, the peripheral device 200 may include a substrate 201, a transistor 202 disposed on the substrate 201, and a peripheral interconnect layer 203 disposed on the substrate 201. The peripheral circuit may include the transistor 202.

[0065] The substrate 201 may be made of single crystal silicon, or other suitable materials, such as silicon germanium, germanium, or silicon-on-insulator thin film.

[0066] The peripheral interconnect layer 203 is coupled to the transistor 202 to enable transmission of electrical signals between the transistor 202 and the peripheral interconnect layer 203. The peripheral interconnect layer 203 may include one or more second interlayer insulating layers 204 and one or more second interconnect conductor layers 205. Different second interconnect conductor layers 205 may be coupled via contacts.

[0067] The second interconnect conductor layer 205 and the contacts may be made of a conductive material, such as tungsten, cobalt, copper, aluminum, or a combination of one or more metal silicides, or other suitable materials.

[0068] The second interlayer insulating layer 204 is made of an insulating material, such as silicon oxide, silicon nitride, and a combination of one or more high-k insulating materials, or other suitable materials.

[0069] In some embodiments, as Figure 1 As shown, the peripheral interconnect layer 203 may be coupled to the array interconnect layer 300 , so that the semiconductor structure 100 and the peripheral device 200 may be coupled.

[0070] Here, since the peripheral interconnect layer 203 is coupled to the array interconnect layer 300 , the peripheral circuit in the peripheral device 200 can be coupled to the memory cell string 400 in the semiconductor structure 100 to achieve transmission of electrical signals between the peripheral circuit and the memory cell string 400 .

[0071] In some possible implementations, see Figure 1 A bonding interface 500 may be provided between the peripheral interconnection layer 203 and the array interconnection layer 300 , and the peripheral interconnection layer 203 and the array interconnection layer 300 may be bonded and coupled to each other through the bonding interface 500 .

[0072] In some embodiments, as Figure 1 As shown, the semiconductor structure 100 may include a substrate 11 providing a supporting function and a memory array structure 20 disposed on the substrate 11 .

[0073] There are various types of substrates 11, which can be selected according to actual needs.

[0074] For example, the substrate 11 is made of glass and / or polymethylmethacrylate (PMMA).

[0075] For another example, the material of the substrate 11 includes at least one of single crystal silicon (Si), polycrystalline silicon, single crystal germanium (Ge), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0076] For another example, the material of the substrate 11 may also include at least one of polyethylene terephthalate (PET), polyethylene naphthalate two formic acid glycol ester (PEN), or polyimide (PI).

[0077] It should be noted that, when the material of the substrate 11 includes single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials or at least one of other semiconductor materials known in the art, the above-mentioned source layer SL can serve as the substrate 11.

[0078] See also Figure 1 and Figure 2 , the memory array structure 20 can be a random memory of spin transfer torque magnetism.

[0079] For example, Figure 1 and Figure 2 As shown, the memory array structure 20 includes a first stack structure 210 and a memory structure 220 and a conductive layer 230 penetrating the first stack structure 210 .

[0080] See also Figure 2 and Figure 4 The first stack structure 210 may include a plurality of stacked sub-stack structures 21, along the stacking direction of the plurality of sub-stack structures 21 (eg Figure 2 In the first direction Z), each sub-stack structure 21 includes a first dielectric layer 211, a first insulating layer 212, a second insulating layer 213, a first channel layer 214, a gate line layer 215 and a plate line layer 216.

[0081] Among them, the first dielectric layer 211, the first insulating layer 212, the gate line layer 215 and the plate line layer 216 can be stacked in sequence, for example, the first channel layer 214 passes through the gate line layer 215, and one end of the first channel layer 214 is in contact with the plate line layer 216, and at least a portion of the second insulating layer 213 is located between the first channel layer 214 and the gate line layer 215, and between the gate line layer 215 and the plate line layer 216, so that the first channel layer 214 and the gate line layer 215 are electrically insulated, and the gate line layer 215 and the plate line layer 216 are electrically insulated.

[0082] It should be noted that the gate line layer 215 can be configured to control the conduction or disconnection of the first channel layer 214, and the plate line layer 216 can be connected to the source layer SL (see Figure 1 )connect.

[0083] Here, as Figure 1 and Figure 2 As shown, the gate line layer 215 is divided into a plurality of gate lines WL by the gate line isolation structure 250, and the gate lines WL can be electrically connected to corresponding gate line connection lines WL-CL through the second connection pillars 12. In addition, the plate line layer 216 can be divided into a plurality of source lines by the gate line isolation structure 250, and the source lines can be electrically connected to the source layer SL through the first connection pillars 13.

[0084] For example, the above-mentioned semiconductor structure 100 also includes a first connecting column 13 and a second connecting column 12 that pass through the first stacking structure 210. The first connecting column 13 contacts the plate line layer 216 of the first stacking structure 210 and is connected to the source layer SL; the second connecting column 12 contacts the gate line layer 215 of the first stacking structure 210 and is connected to the corresponding gate line connection line WL-CL.

[0085] The materials of the above-mentioned first dielectric layer 211, first insulating layer 212 and second insulating layer 213 may include insulating materials, and the insulating materials may include, for example, silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organic silicate glass, dielectric metal oxides (such as aluminum oxide, hafnium dioxide, etc.) and their silicates, and at least one of organic insulating materials.

[0086] The material of the first channel layer 214 may include a semiconductor material, which may include, for example, single crystal silicon (Si), polycrystalline silicon, single crystal germanium (Ge), III-V compound semiconductor materials, II-VI compound semiconductor materials or at least one of other semiconductor materials known in the art.

[0087] The gate line layer 215 and the plate line layer 216 may be made of a conductive material. The conductive material may be made of at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, and silicide.

[0088] See also Figure 2 and Figure 4 The storage structure 220 includes a plurality of ferromagnetic free layers 221 , a tunneling layer 222 and a ferromagnetic pinned layer 223 .

[0089] Among them, such as Figure 4 As shown, the ferromagnetic free layer 221 contacts the first channel layer 214 of a sub-stack structure 21 , the tunneling layer 222 is disposed between the ferromagnetic free layer 221 and the ferromagnetic pinned layer 223 , and the ferromagnetic pinned layer 223 is disposed on a side of the tunneling layer 222 away from the ferromagnetic free layer 221 .

[0090] It should be noted that the ferromagnetic free layer 221 , the tunneling layer 222 and the ferromagnetic pinned layer 223 are in contact with each other in sequence to form a magnetic tunnel junction.

[0091] In some embodiments, see Figure 2 and Figure 4 The above-mentioned storage structure 220 also includes an antiferromagnetic layer (not shown in the figure), which is arranged between the conductive layer 230 and the ferromagnetic pinning layer 223 to increase the magnetic coercivity of the ferromagnetic pinning layer 223 and reduce the risk of other magnetic tunnel junctions on the same bit line BL (or gate line WL) being erroneously written.

[0092] At this time, the ferromagnetic free layer 221 , the tunneling layer 222 , the ferromagnetic pinned layer 223 and the antiferromagnetic layer are in contact with each other in sequence to form a magnetic tunnel junction.

[0093] The material of the ferromagnetic free layer 221 includes a ferromagnetic material. For example, the ferromagnetic material may include at least one of a cobalt-iron alloy, a cobalt-iron-boron alloy, a boron-iron alloy, and a cobalt-nickel alloy.

[0094] The tunneling layer 222 may be made of an insulating material that is non-magnetic or weakly magnetic. For example, the insulating material may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxides (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials.

[0095] The material of the ferromagnetic pinning layer 223 includes ferromagnetic material, and the ferromagnetic material may include at least one of cobalt-iron alloy, cobalt-iron-boron alloy, boron-iron alloy and cobalt-nickel alloy.

[0096] The magnetization direction of the ferromagnetic free layer 221 can be switched under certain external influences, while the magnetization direction of the ferromagnetic pinned layer 223 is fixed. For example, under the influence of a current flowing along the plate line layer 216, the magnetization direction of the ferromagnetic free layer 221 can be switched between a third direction and a fourth direction, which are opposite to each other. The magnetization direction of the ferromagnetic pinned layer 223 is in the third direction or the fourth direction.

[0097] It is understood that when the magnetization directions of the ferromagnetic free layer 221 and the ferromagnetic pinned layer 223 are the same, the resistance of the magnetic tunnel junction is relatively low. When the magnetization directions of the ferromagnetic free layer 221 and the ferromagnetic pinned layer 223 are opposite, the resistance of the magnetic tunnel junction is relatively high.

[0098] Based on this, the resistance of the magnetic tunnel junction can be changed by changing the magnetization direction of the ferromagnetic free layer 221, that is, the resistance of the magnetic tunnel junction can be used to read the stored information. Figure 2 and Figure 3 , a magnetic tunnel junction can form a memory cell C. For example, when the resistance of the magnetic tunnel junction is relatively high, it represents data "0"; when the resistance of the magnetic tunnel junction is relatively low, it represents data "1".

[0099] At this time, if Figure 2 and Figure 3 As shown, the multiple magnetic tunnel junctions included in a memory structure 220 can form a memory portion of a memory cell string 400 .

[0100] See also Figure 2 and Figure 4 The conductive layer 230 is disposed on a side of the ferromagnetic pinning layer 223 away from the tunneling layer 222 , and the conductive layer 230 is coupled to the bit line BL.

[0101] In some embodiments, see Figure 2 , the conductive layer 230 includes a first conductive portion 231 and a second conductive portion 232 .

[0102] The first conductive portion 231 contacts the ferromagnetic pinning layer 223. The first conductive portion 231 is a tubular structure, with the opening of the tubular structure facing away from the reference plane, which is the plane of the lower surface of the first stacked structure 210. Furthermore, the second conductive portion 232 covers the opening of the tubular structure and, together with the first conductive portion 231, forms a first cavity, thereby increasing the surface area of ​​the conductive layer 230 away from the reference plane, facilitating electrical connection of the conductive layer 230 to the bit line BL via other conductive structures (e.g., the second channel layer 271).

[0103] It should be noted that the reference surface may be, for example, the lower surface of the first stacked structure 210 ( Figure 1 The plane where the surface of the lower middle side is located.

[0104] The material of the first conductive portion 231 and the second conductive portion 232 includes a conductive material, and the conductive material may include at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, and silicide.

[0105] It should be noted that the materials of the first conductive portion 231 and the second conductive portion 232 can be the same or different. For example, the materials of the first conductive portion 231 and the second conductive portion 232 are the same to reduce the types of materials and reduce costs.

[0106] On this basis, see Figure 1 and Figure 2 The semiconductor structure 100 may further include a first filling layer 240 . The first filling layer 240 is disposed in the first cavity to provide mechanical support and reduce the risk of collapse of the semiconductor structure 100 .

[0107] The material of the first filling layer 240 includes an insulating material, which may be non-magnetic or weakly magnetic. The insulating material may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organic silicate glass, dielectric metal oxides (such as aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials.

[0108] At this time, see Figure 2 、 Figure 3 and Figure 4 A memory cell C (magnetic tunnel junction) can be controlled by a conductive layer 230 and a plate line layer 216 electrically connected to the memory cell C, thereby achieving a write or read operation.

[0109] Furthermore, the gate line WL can also individually control whether a corresponding memory cell C can be written or read by controlling the conduction and disconnection of the first channel layer 214 , thereby achieving random reading and writing of any memory cell C.

[0110] The following uses the example of a magnetic tunnel junction representing data “0” when the resistance is relatively high and representing data “1” when the resistance is relatively low as an example to exemplify the write and read operations of the embodiment of the present disclosure.

[0111] Assume that the magnetization direction reversal voltage of the ferromagnetic free layer 221 in the magnetic tunnel junction is V1, and the read voltage is V2; and assume that the threshold voltage of the first channel layer 214 is V3, and the turn-on voltage V4 is provided to the first channel layer 214 through the gate line WL, V4 ≥ V3, so that the first channel layer 214 is turned on.

[0112] It should be noted that V2 is much smaller than V1 to avoid a large V2 during the reading process that may cause the magnetization direction of the ferromagnetic free layer 221 to change, thereby causing deviation or error in the read data.

[0113] For example, in a write operation, a turn-on voltage V4 is first provided to the first channel layer 214 through the gate line WL, so that the first channel layer 214 is turned on.

[0114] Then, a switching voltage V1 is applied to the ferromagnetic pinned layer 223 through the conductive layer 230 (bit line BL), and the plate line layer 216 (source layer SL) is grounded, that is, the voltage of the plate line layer 216 (source layer SL) is 0, so that the magnetization direction of the ferromagnetic free layer 221 is the same as the magnetization direction of the ferromagnetic pinned layer 223, thereby writing data "1". Alternatively, a switching voltage V1 is applied to the ferromagnetic free layer 221 through the plate line layer 216 (source layer SL), and the conductive layer 230 (bit line BL) is grounded, that is, the voltage of the conductive layer 230 (bit line BL) is 0, so that the magnetization direction of the ferromagnetic free layer 221 is opposite to the magnetization direction of the ferromagnetic pinned layer 223, thereby writing data "0".

[0115] For example, in a read operation, a turn-on voltage V4 is first provided to the first channel layer 214 through the gate line WL, so that the first channel layer 214 is turned on.

[0116] Then, a read voltage V2 is provided to the ferromagnetic pinned layer 223 through the conductive layer 230 (bit line BL), and the plate line layer 216 (source layer SL) is grounded, that is, the voltage of the plate line layer 216 (source layer SL) is 0, so as to read the resistance of the magnetic tunnel junction and thus read the written data.

[0117] As can be seen from the above, the semiconductor structure 100 is a random access memory based on spin transfer torque magnetism, which has the advantages of high speed, low power consumption and unlimited erasing and writing. In addition, the storage structure 220 can be arranged in an array in the reference plane direction, and each storage structure 220 includes a plurality of storage cells C arranged at intervals in a direction perpendicular to the reference plane. In other words, the plurality of storage cells C are arranged in an array in the reference plane direction, and in a direction perpendicular to the reference plane (for example, Figure 1 The semiconductor devices 100 are arranged at intervals in the first direction Z), thereby realizing three-dimensional storage and improving the storage density of the semiconductor structure 100.

[0118] In some embodiments, see Figure 2 and Figure 4 The plurality of ferromagnetic free layers 221 are separated from each other along a first direction Z. The first direction Z is perpendicular to the reference plane.

[0119] For example, Figure 2 and Figure 4 As shown, the first insulating layer 212 is close to the boundary of the storage structure 220 and is inward compared to the boundary of the first dielectric layer 211 and the first channel layer 214 close to the storage structure 220. That is, the first insulating layer 212 is close to the boundary of the storage structure 220 and is farther away from the central axis of the storage structure 220 than the boundary of the first dielectric layer 211 and the first channel layer 214 close to the storage structure 220, thereby forming a first groove C1 (see Figure 19 At this time, the ferromagnetic free layer 221 is disposed in the first groove C1 (see Figure 19) and in contact with the first channel layer 214. In this way, the preparation process of the multiple ferromagnetic free layers 221 is simple and the cost is low.

[0120] On this basis, the tunneling layer 222, the ferromagnetic pinning layer 223 and the conductive layer 230 are at least partially located in the first groove C1 (see Figure 19 ). In this way, any adjacent surfaces of any two adjacent layers in the ferromagnetic free layer 221, the tunneling layer 222, and the ferromagnetic pinned layer 223 are all flat. In this case, the magnetic tunnel junction can have more stable magnetic properties, thereby improving the stability of data writing and reading.

[0121] Here, both the tunneling layer 222 and the ferromagnetic pinning layer 223 can be continuous film layers along a first direction Z, which is perpendicular to the reference plane. In this case, the tunneling layer 222 can position the plateline layer 216 near the end of the storage structure 220, electrically insulating it from the ferromagnetic pinning layer 223 and the conductive layer 230. Furthermore, the fabrication process for the continuous tunneling layer 222 and ferromagnetic pinning layer 223 is simple and low-cost.

[0122] In some embodiments, as Figure 4 As shown, the second insulating layer 213 is disposed between the gate line layer 215 and the plate line layer 216 , between the gate line layer 215 and the first insulating layer 212 , and between the gate line layer 215 and the first channel layer 214 .

[0123] That is, the second insulating layer 213 includes a first sub-portion 2131, a second sub-portion 2132, and a third sub-portion 2133. The first sub-portion 2131 contacts the upper surface of the gate line layer 215 and is located between the gate line layer 215 and the plate line layer 216; the second sub-portion 2132 contacts the lower surface of the gate line layer 215 and is located between the gate line layer 215 and the first insulating layer 212; and the third sub-portion 2133 contacts the side surface of the gate line layer 215 and is located between the gate line layer 215 and the first channel layer 214.

[0124] In this case, the second insulating layer 213 and the gate line layer 215 can be formed by replacing the sacrificial layer after the storage structure 220 is formed, and the process flow is simple.

[0125] On this basis, the plate line layer 216 close to the boundary of the storage structure 220 may extend beyond the boundary of the second insulating layer 213 close to the storage structure 220 .

[0126] At this time, the portion of the plate line layer 216 extending beyond the second insulating layer 213 is the first portion, and the first channel layer 214 contacts the surface of the first portion close to the gate line layer 215 , resulting in a simple structure and easy preparation.

[0127] In some embodiments, see Figure 2 and Figure 5 The first insulating layer 212 is close to the boundary of the storage structure 220 and is also inward compared to the boundary of the second insulating layer 213 close to the storage structure 220. That is, the first insulating layer 212 is close to the boundary of the storage structure 220 and is further away from the central axis of the storage structure 220 than the boundary of the second insulating layer 213 close to the storage structure 220. That is, the first groove C1 (see Figure 19 ) extends to the lower side of the second sub-portion 2132.

[0128] At this time, see Figure 4 and Figure 5 In order to reduce the electromagnetic interference generated by the gate line layer 215 on the ferromagnetic free layer 221, the above-mentioned sub-stack structure 21 also includes a second dielectric layer 217, and the second dielectric layer 217 is arranged between the first insulating layer 212 and the second sub-portion 2132 to reduce the electromagnetic interference generated between the gate line layer 215 and the ferromagnetic free layer 221, and reduce the risk of short circuit between the gate line layer 215 and the ferromagnetic free layer 221.

[0129] The material of the second dielectric layer 217 includes an insulating material, which may be non-magnetic or weakly magnetic. The insulating material may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxides (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials.

[0130] In addition, see Figure 4 and Figure 5 The above-mentioned sub-stack structure 21 also includes a third dielectric layer 218, which is arranged between the first sub-portion 2131 and the plate line layer 216 to reduce the electromagnetic interference generated between the gate line layer 215 and the plate line layer 216, and reduce the risk of short circuit between the gate line layer 215 and the plate line layer 216.

[0131] The material of the third dielectric layer 218 includes an insulating material, which may be non-magnetic or weakly magnetic. The insulating material may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxides (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials.

[0132] It should be noted that the material of the second dielectric layer 217 can be the same as that of the third dielectric layer 218 , so as to simplify the process and reduce costs.

[0133] At this time, the first channel layer 214 includes a first sub-channel layer 2141, a second sub-channel layer 2142, and a third sub-channel layer 2143. The first sub-channel layer 2141 is disposed between the third sub-portion 2133 and the storage structure 220; the second sub-channel layer 2142 is disposed between the second dielectric layer 217 and the storage structure 220, and is in contact with the ferromagnetic free layer 221 and the first sub-channel layer 2141; and the third sub-channel layer 2143 is disposed between the third dielectric layer 218 and the storage structure 220, and is in contact with the first sub-channel layer 2141 and the plate line layer 216.

[0134] In some embodiments, see Figure 2 、 Figure 4 and Figure 5 The above-mentioned sub-stack structure 21 also includes a third insulating layer 219, which is arranged between the plate line layer 216 and the storage structure 220 to reduce the electromagnetic interference generated between the plate line layer 216 and the ferromagnetic pinning layer 223 and / or the conductive layer 230, and reduce the risk of short circuit between the plate line layer 216 and the ferromagnetic pinning layer 223 and / or the conductive layer 230.

[0135] It should be noted that the material of the third insulating layer 219 can be the same as that of the first dielectric layer 211 , so as to reduce the types of materials and lower the manufacturing cost.

[0136] In some embodiments, see Figure 1 The semiconductor structure 100 further includes a gate line isolation structure 250, which penetrates the first stacked structure 210. Here, the gate line isolation structure 250 extends along the second direction X to divide the gate line layer 215 into a plurality of gate lines WL and the plate line layer 216 into a plurality of source lines.

[0137] It should be noted that the second direction X is parallel to the reference plane. For example, the second direction X may be a row direction or a column direction of the array arrangement of the storage structures 220 .

[0138] It should be noted that the material of the gate line isolation structure 250 includes an insulating material, and the insulating material may include, for example, silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organic silicate glass, dielectric metal oxides (such as aluminum oxide, hafnium dioxide, etc.) and their silicates, and at least one of organic insulating materials.

[0139] In some embodiments, see Figure 1 and Figure 2 The memory array structure 20 further includes a second stacked structure 260 and a channel structure 270 .

[0140] like Figure 1 and Figure 2As shown, the second stack structure 260 is disposed on the first stack structure 210. For example, the second stack structure 260 is disposed on a side of the first stack structure 210 away from the substrate 11.

[0141] The second stacked structure 260 includes at least one select gate line layer 261 and at least one fourth dielectric layer 262. For example, the second stacked structure 260 includes one select gate line layer 261 and one fourth dielectric layer 262.

[0142] The material of the select gate line layer 261 may include a conductive material, such as at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, and silicide. The material of the select gate line layer 261 may be the same as or different from the material of the gate line layer 215, and the present disclosure does not specifically limit this.

[0143] The material of the fourth dielectric layer 262 may include an insulating material, which may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organic silicate glass, dielectric metal oxides (such as aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials.

[0144] Here, the material of the fourth dielectric layer 262 may be the same as or different from the material of the first dielectric layer 211 , which is not specifically limited in the embodiment of the present disclosure.

[0145] like Figure 1 and Figure 2 As shown, the channel structure 270 penetrates the second stacked structure 260. The channel structure 270 includes a second channel layer 271. The second channel layer 271 is electrically connected to the conductive layer 230 and the second channel layer 271 is electrically connected to the bit line BL.

[0146] Here, the second channel layer 271 and the selection gate line layer 261 can be constructed as simple metal-oxide-semiconductor (MOS) transistors as switch transistors, thereby simplifying the process and reducing the manufacturing cost.

[0147] For example, Figure 1 and Figure 2 As shown, the channel structure 270 further includes a fifth dielectric layer 272, which is disposed between the second channel layer 271 and the select gate line layer 261. At this time, the second channel layer 271, the fifth dielectric layer 272 and the select gate line layer 261 form a select transistor T (see Figure 3 ).

[0148] At this time, the memory cell string 400 further includes a selection transistor T. In this case, the selection transistor T (see Figure 3 ) controls the reading and writing of the memory cell C. That is, the transistor T (see Figure 3 ) controls the conduction state of a source end channel (bit line BL) in the memory cell string 400, and by writing the voltage on the bit line BL and the source layer SL, the data writing and reading of each memory cell C in the memory cell string 400 can be completed.

[0149] In some embodiments, as Figure 2 As shown, the channel structure 270 further includes a channel filling layer 273. A cavity is left inside the second channel layer 271, and the channel filling layer 273 fills the cavity to provide mechanical support.

[0150] It should be noted that the material of the channel filling layer 273 includes an insulating material, and the insulating material may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organic silicate glass, dielectric metal oxides (such as aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials, but the present disclosure is not limited to this.

[0151] Some embodiments of the present disclosure also provide a method for preparing a semiconductor structure, see Figure 33 , the preparation method includes steps S100 to S700.

[0152] S100: See Figure 6 , forming an initial stacking structure 210 ′.

[0153] In the above steps, the initial stacking structure 210' includes a plurality of stacked sub-initial stacking structures 21', and the stacking direction of the plurality of sub-initial stacking structures 210' is (for example) Figure 6 In the first direction Z), each sub-initial stacking structure 21' includes a first dielectric layer 211, a first insulating layer 212, a sacrificial layer 213' and a plate line layer 216 that are stacked. The first dielectric layer 211, the first insulating layer 212, the sacrificial layer 213' and the plate line layer 216 can be stacked in sequence, for example.

[0154] The initial stacked structure 210 ′ may be formed on the substrate 11 by using any thin film deposition process including chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0155] It should be noted that the materials of the substrate 11 , the first dielectric layer 211 , the first insulating layer 212 , the sacrificial layer 213 ′ and the plate line layer 216 can all be referred to above, and are not described in detail in this disclosure.

[0156] In some embodiments, as Figure 6 As shown, in the process S100 , a second dielectric layer 217 and a third dielectric layer 218 are also formed. The second dielectric layer 217 is disposed between the sacrificial layer 213 ′ and the first insulating layer 212 , and the third dielectric layer 218 is disposed between the sacrificial layer 213 ′ and the plate line layer 216 .

[0157] S200: See Figure 7 , forming a first channel hole CH1 penetrating the initial stacked structure 210 ′.

[0158] In the above steps, the shape of the orthographic projection of the first channel hole CH1 on the reference surface is not unique. Exemplarily, the shape of the orthographic projection of the first channel hole CH1 on the reference surface is a rectangle or a circle.

[0159] The first channel hole CH1 penetrating the initial stacked structure 210' can be formed by dry / wet etching. For example, the first channel hole CH1 is formed by anisotropic etching (any dry etching method such as ion milling, plasma etching, reactive ion etching, laser ablation, etc.).

[0160] S300: See Figure 13 , a first channel layer 214 is formed in the first channel hole CH1 .

[0161] In the above steps, the first channel layer 214 is disposed at the end of the sacrificial layer 213 ′ close to the first channel hole CH1 , and one end of the first channel layer 214 is in contact with the plate line layer 216 .

[0162] In the case where the initial stacked structure 210' does not include the second dielectric layer 217 and the third dielectric layer 218, as shown in FIG. Figure 34 As shown, S300 includes S310 to S320.

[0163] S310: See Figure 8 , an edge portion of the sacrificial layer 213 ′ close to the first channel hole CH1 is removed through the first channel hole CH1 .

[0164] In the above steps, the edge portion of the sacrificial layer 213 ′ near the first channel hole CH1 is removed through the first channel hole CH1 , so that the sacrificial layer 213 ′ near the boundary of the first channel hole CH1 is retracted inward compared to the boundary between the plate line layer 216 and the first insulating layer 212 , thereby forming a second groove C2 .

[0165] The first channel hole CH1 may be used as an etchant channel to etch the end portion of the sacrificial layer 213 ′ exposed at the first channel hole CH1 , and the etchant is used to etch the sacrificial layer 213 ′.

[0166] S320: See Figure 10 , a first sub-channel layer 2141 is formed in the second groove C2.

[0167] In the above steps, the first sub-channel layer 2141 fills the second groove C2 and is disposed at the end of the sacrificial layer 213 ′ close to the first channel hole CH1 .

[0168] In some embodiments, as Figure 35 As shown, S320 may include S321 to S322.

[0169] S321: See Figure 9 , forming a first channel film 2141'.

[0170] In the above steps, the first channel film 2141 ′ fills the second groove C2 and covers the inner wall of the first channel hole CH1 and the upper side of the initial stacked structure 210 ′. The first channel film 2141 ′ can be formed by any thin film deposition process including CVD, PVD, and ALD.

[0171] S322: See Figure 9 and Figure 10 , a portion of the first channel film 2141 ′ covering the inner wall of the first channel hole CH1 and the upper side of the initial stack structure 210 ′ is removed.

[0172] In the above steps, a dry / wet etching process may be used to remove the portion of the first channel film 2141 ′ covering the inner wall of the first channel hole CH1 and the upper side of the initial stacked structure 210 ′, and retain the portion of the first channel film 2141 ′ filling the second groove C2 to form a first sub-channel layer 2141 .

[0173] At this time, when the initial stacked structure 210 ′ does not include the second dielectric layer 217 and the third dielectric layer 218 , the first sub-channel layer 2141 is the first channel layer 214 , and the first sub-channel layer 2141 is in contact with the plate line layer 216 and the first insulating layer 212 .

[0174] In the case where the initial stacked structure 210' further includes a second dielectric layer 217 and a third dielectric layer 218, after S320, see Figure 36 , S300 also includes S330 and S340.

[0175] S330: See Figure 11, through the first channel hole CH1 , the edge portions of the second dielectric layer 217 and the third dielectric layer 218 close to the first channel hole CH1 are removed.

[0176] In the above steps, the edge portions of the second dielectric layer 217 and the third dielectric layer 218 near the first channel hole CH1 are removed through the first channel hole CH1, so that the second dielectric layer 217 near the boundary of the first channel hole CH1 is retracted compared to the boundary of the first insulating layer 212 and the first sub-channel layer 2141 near the first channel hole CH1, thereby forming a third groove C3; and the third dielectric layer 218 near the boundary of the first channel hole CH1 is retracted compared to the boundary of the first sub-channel layer 2141 and the plate line layer 216 near the first channel hole CH1, thereby forming a fourth groove C4.

[0177] S340: See Figure 11 and Figure 13 A second sub-channel layer 2142 and a third sub-channel layer 2143 are formed in the third groove C3 and the fourth groove C4, respectively.

[0178] In the above steps, the second sub-channel layer 2142 is disposed at an end of the second dielectric layer 217 near the first channel hole CH1 and is in contact with the first insulating layer 212 and the first sub-channel layer 2141. The third sub-channel layer 2143 is disposed at an end of the third dielectric layer 218 near the first channel hole CH1 and is in contact with the first sub-channel layer 2141 and the plate line layer 216.

[0179] In some embodiments, as Figure 37 As shown, S340 includes S341 to S342.

[0180] S341: See Figure 12 , forming a second channel film 2142'.

[0181] In the above steps, see Figure 11 and Figure 12 The second channel film 2142' fills the third groove C3 and the fourth groove C4 and covers the inner wall of the first channel hole CH1 and the upper side of the initial stacked structure 210'. The second channel film 2142' can be formed by any thin film deposition process including CVD, PVD, and ALD.

[0182] S342: See Figure 12 and Figure 13 , a portion of the second channel film 2142 ′ covering the inner wall of the first channel hole CH1 and the upper side of the initial stack structure 210 ′ is removed.

[0183] In the above steps, a dry / wet etching process can be used to remove the portion of the second channel film 2142' covering the inner wall of the first channel hole CH1 and the upper side of the initial stacked structure 210', and the second channel film 2142' is retained to fill the third groove C3 (see Figure 11 ) and the fourth groove C4 (see Figure 11 ) portion to form a second sub-channel layer 2142 and a third sub-channel layer 2143.

[0184] At this time, when the initial stacked structure 210 ′ includes the second dielectric layer 217 and the third dielectric layer 218 , the first sub-channel layer 2141 , the second sub-channel layer 2142 and the third sub-channel layer 2143 together constitute the first channel layer 214 , which contacts the plate line layer 216 and the first insulating layer 212 .

[0185] In some embodiments, the materials of the first dielectric layer 211 , the second dielectric layer 217 , and the third dielectric layer 218 are all the same.

[0186] At this time, see Figure 11 In step S330 , the edge portion of the first dielectric layer 211 near the first channel hole CH1 is also removed, so that the first dielectric layer 211 near the boundary of the first channel hole CH1 is retracted relative to the boundary of the plate line layer 216 and the first insulating layer 212 near the first channel hole CH1, thereby forming a fifth groove C5. The remaining portion of the first dielectric layer 211 forms the second sub-dielectric layer 2112.

[0187] In the process of S341, see Figure 12 and Figure 13 The second channel film 2142' also covers the inner wall of the fifth groove C5. In the process of S342, the portion of the second channel film 2142' covering the inner wall of the fifth groove C5 is further removed.

[0188] On this basis, after S340, such as Figure 36 As shown, S300 also includes S350.

[0189] S350: See Figure 15 , a first sub-dielectric layer 2111 is formed in the fifth groove C5.

[0190] In the above steps, the first sub-dielectric layer 2111 contacts the second sub-dielectric layer 2112 to form the first dielectric layer 211. Figure 14 and Figure 15A first dielectric film 2111' may be formed by any thin film deposition process including CVD, PVD, and ALD. The portion of the first dielectric film 2111' covering the inner wall of the first channel hole CH1 and the upper side of the initial stacked structure 210' is then removed, and the portion of the first dielectric film 2111' filling the fifth groove C5 is retained to form a first sub-dielectric layer 2111.

[0191] S400: See Figure 29 , a storage structure 220 and a conductive layer 230 are formed in the first channel hole CH1.

[0192] In the above steps, the storage structure 220 includes multiple ferromagnetic free layers 221, a tunneling layer 222, and a ferromagnetic pinned layer 223. The ferromagnetic free layer 223 contacts the other end of the first channel layer 214, and the tunneling layer 222 is disposed between the multiple ferromagnetic free layers 221 and the ferromagnetic pinned layer 223. The conductive layer 230 is located on the side of the ferromagnetic pinned layer 223 away from the tunneling layer 222.

[0193] In some embodiments, see Figure 38 , S400 includes S410 to S440.

[0194] S410: See Figure 19 , an edge portion of the first insulating layer 212 close to the first channel hole CH1 is removed through the first channel hole CH1 .

[0195] In the above steps, the edge portion of the first insulating layer 212 near the first channel hole CH1 is removed through the first channel hole CH1, so that the first insulating layer 212 near the boundary of the first channel hole CH1 is retracted compared to the first dielectric layer 211 and the first channel layer 214 near the boundary of the first channel hole CH1, thereby forming a first groove C1.

[0196] The first channel hole CH1 may be used as an etchant channel to etch the end portion of the first insulating layer 212 exposed at the first channel hole CH1 , thereby removing the edge portion of the first insulating layer 212 near the first channel hole CH1 .

[0197] S420: See Figure 24 A ferromagnetic free layer 221 is formed in the first groove C1.

[0198] In the above steps, the ferromagnetic free layer 221 covers the inner wall of the first groove and contacts the first channel layer 214 .

[0199] In some embodiments, see Figure 39 , S420 includes S421 to S424.

[0200] S421: See Figure 20 , forming a ferromagnetic free film 221'.

[0201] In the above steps, the ferromagnetic free film 221' covers the inner wall of the first groove C1, the inner wall of the first channel hole CH1 and the upper side of the initial stacked structure 210'. The ferromagnetic free film 221' can be formed by any thin film deposition process such as CVD, PVD and ALD.

[0202] S422: See Figure 20 and Figure 22 , a second filling layer 225 is formed in the first groove C1.

[0203] In the above steps, the second filling layer 225 fills the first groove C1 to protect the portion of the ferromagnetic free film 221' located in the first groove C1. Figure 21 and Figure 22 , any thin film deposition process among CVD, PVD, and ALD can be used to first form a second filling film 225', and then remove the portion of the second filling film 225' covering the inner wall of the first channel hole CH1 and the upper side of the initial stacking structure 210', retaining the portion of the second filling film 225' filling the first groove C1 to form a second filling layer 225.

[0204] S423: See Figure 22 and Figure 23 , a portion of the ferromagnetic free film 221 ′ covering the inner wall of the first channel hole CH1 and the upper side of the initial stacked structure 210 ′ is removed.

[0205] In the above steps, a dry / wet etching process can be used to remove the portion of the ferromagnetic free film 221' covering the inner wall of the first channel hole CH1 and the upper side of the initial stacked structure 210'. Here, the ferromagnetic free film 221' covers the first groove C1 (see Figure 20 ) will not be etched away due to the protection and blocking of the second filling layer 225, thereby forming a ferromagnetic free layer 221.

[0206] S424: See Figure 23 and Figure 24 , remove the second filling layer 225.

[0207] In the above steps, a dry / wet etching process may be used to remove the second filling layer 225 , so as to dispose at least one of the tunneling layer 222 , the ferromagnetic pinning layer 223 and the conductive layer 230 in the first groove C1 .

[0208] S430: See Figure 25 、 Figure 26 and Figure 27 , a tunneling film 222 ′, a ferromagnetic pinning film 223 ′ and a first conductive film 231 ′ are formed in sequence.

[0209] In the above steps, the tunneling film 222', the ferromagnetic pinning film 223', and the first conductive film 231' fill the first groove C1 and cover the inner wall of the first channel hole CH1 and the upper side of the initial stacked structure 210'. The tunneling film 222', the ferromagnetic pinning film 223', and the first conductive film 231' can be sequentially formed using any of the following thin film deposition processes: CVD, PVD, or ALD.

[0210] S440: See Figure 27 and Figure 29 , portions of the tunneling film 222 ′, the ferromagnetic pinning film 223 ′, and the first conductive film 231 ′ covering the upper side of the initial stacked structure 210 ′ are removed.

[0211] In the above steps, either chemical mechanical planarization (CMP) or dry / wet etching process can be used to remove the portion of the tunneling film 222', the ferromagnetic pinning film 223' and the first conductive film 231' covering the upper side of the initial stacked structure 210', and retain the tunneling film 222', the ferromagnetic pinning film 223' and the first conductive film 231' to fill the first groove C1 (see Figure 20 ) and a portion covering the inner wall of the first channel hole CH1 to form the storage structure 220 and the first conductive portion 231 of the conductive layer 230.

[0212] In some embodiments, after S430, see Figure 40 , S400 also includes S450~S460.

[0213] S450: See Figure 27 and Figure 28 , a first filling layer 240 is formed in the first channel hole CH1 .

[0214] In the above steps, the channel layer CH is filled with the first filling layer 240. The first filling layer 240 can be formed by any thin film deposition process including CVD, PVD, and ALD.

[0215] S460: See Figure 28 and Figure 29 , forming a second conductive film.

[0216] In the above steps, the second conductive film covers the first filling layer 240 and the portion of the first conductive film 231' located on the upper side of the initial stacked structure 210'. The second conductive film can be formed by any thin film deposition process such as CVD, PVD, or ALD.

[0217] On this basis, in step S440, the portion of the second conductive film covering the upper side of the initial stacked structure 210' is removed, while the portion of the second conductive film covering the first filling layer 240 is retained, thereby forming the second conductive portion 232 of the conductive layer 230. At this point, the first conductive portion 231 and the second conductive portion 232 form the conductive layer 230.

[0218] S500 : forming a gate line gap penetrating the initial stacked structure 210 ′.

[0219] In the above steps, gate line gaps penetrating the initial stacked layer 210' can be formed by dry or wet etching. For example, the gate line gaps are formed by anisotropic etching (any dry etching method such as ion milling, plasma etching, reactive ion etching, laser ablation, etc.).

[0220] S600: See Figure 29 and Figure 30 , the sacrificial layer 213 ′ is removed through the gate line gap to form a second cavity.

[0221] In the above steps, the gate line gap GLS may be used as an etchant channel, and the sacrificial layer 213 ′ may be removed by isotropic etching to form a second cavity.

[0222] S700: See Figure 30 and Figure 32 , a second insulating layer 213 and a gate line layer 215 are sequentially formed in the second cavity.

[0223] In the above steps, if Figure 4 and Figure 5 As shown, the second insulating layer 213 includes a first sub-portion 2131, a second sub-portion 2132 and a third sub-portion 2133. The first sub-portion 2131 contacts the upper surface of the gate line layer 215 and is located between the gate line layer 215 and the plate line layer 216; the second sub-portion 2132 contacts the lower surface of the gate line layer 215 and is located between the gate line layer 215 and the first insulating layer 212; the third sub-portion 2133 contacts the side surface of the gate line layer 215 and is located between the gate line layer 215 and the first channel layer 214. At this time, the first stacked structure 210 is formed (see Figure 2 ).

[0224] The second insulating layer 213 may be directly formed by any thin film deposition process such as CVD, PVD, or ALD. At this time, the second insulating layer 213 also covers the sidewalls of the gate line slit GLS and the upper side of the initial stacked structure 210'.

[0225] It should be noted that, since the second insulating layer 213 is made of insulating material, the portion of the second insulating layer 213 covering the sidewalls of the gate line slit GLS and the upper side of the initial stacked structure 210 ′ can be retained to simplify the process steps and reduce the manufacturing cost.

[0226] In addition, see Figure 31 and Figure 32 , any thin film deposition process among CVD, PVD, and ALD can be used to first form a gate line film 215', and then remove the portion of the gate line film 215' covering the sidewalls of the gate line gap and the upper side of the initial stacking structure 210', retaining the portion of the gate line film 215' filling the second cavity to form a gate line layer 215.

[0227] In some embodiments, between S300 and S400, see Figure 33 The method for preparing the semiconductor structure further includes S800 to S810.

[0228] S800: See Figure 16 , an edge portion of the plate line layer 216 close to the first channel hole CH1 is removed through the first channel hole CH1 .

[0229] In the above steps, the edge portion of the plate line layer 216 near the first channel hole CH1 is removed through the first channel hole CH1, so that the plate line layer 216 near the boundary of the first channel hole CH1 is retracted compared to the first dielectric layer 211 and the first channel layer 214 near the boundary of the first channel hole CH1, thereby forming a sixth groove C6.

[0230] S810: See Figure 16 and Figure 18 , a third insulating layer 219 is formed in the sixth groove C6.

[0231] In the above steps, the third insulating layer 219 is disposed at the end of the plate line layer 216 near the first channel hole CH1. The material of the third insulating layer 219 can be the same as that of the first dielectric layer 211 to reduce the number of materials and lower the manufacturing cost.

[0232] Among them, see Figure 17 and Figure 18 , any one of CVD, PVD, and ALD thin film deposition processes can be used to first form a third insulating film 219 ′, and then the portion of the third insulating film 219 ′ covering the inner wall of the first channel hole CH1 and the upper side of the initial stacked structure 210 ′ is removed, and the portion of the third insulating film 219 ′ filling the sixth groove C6 is retained to form a third insulating layer 219.

[0233] In some embodiments, after S700, refer to Figure 41 The method for preparing the semiconductor structure further includes S900.

[0234] S900: See Figure 1 , a gate line isolation structure 250 is formed in the gate line gap.

[0235] In the above steps, any thin film deposition process such as CVD, PVD, and ALD can be used to form the gate line isolation structure 250 in the gate line gap GLS. The structure and material of the gate line isolation structure 250 can be referred to above and will not be described in detail in this disclosure.

[0236] In some embodiments, see Figure 41 The method for preparing the semiconductor structure further includes S910 and S920.

[0237] S910: See Figure 1 and Figure 2 , forming a second stacking structure 260.

[0238] In the above steps, the second stacked structure 260 is located on the first stacked structure 210. The second stacked structure 260 includes multiple select gate line layers 261 and multiple fourth dielectric layers 262. For example, the multiple select gate line layers 261 and the multiple fourth dielectric layers 262 are alternately stacked. The second stacked structure 260 can be formed on the first stacked structure 210 using any of the following thin film deposition processes: CVD, PVD, and ALD.

[0239] S920: See Figure 1 and Figure 2 , forming a channel structure 270 penetrating the second stacked structure 260 .

[0240] In the above steps, a dry / wet etching process may be used to form the second channel hole CH2 penetrating the second stacked structure 260 . Then, a channel structure 270 is formed in the second channel hole CH2 , and the channel structure 270 is electrically connected to the conductive layer 230 .

[0241] The channel structure 270 includes a second channel layer 271 . The second channel layer 271 is electrically connected to the conductive layer 230 , and the channel layer 271 is electrically connected to the bit line BL.

[0242] It should be noted that the structure and material of the channel structure 270 can be referred to above, and will not be elaborated in detail in the embodiment of the present disclosure.

[0243] Figure 42 is a block diagram of a storage system according to some embodiments. Figure 43 is a block diagram of a storage system according to some other embodiments.

[0244] See Figure 42 and Figure 43Some embodiments of the present disclosure further provide a storage system 1000. The storage system 1000 includes a controller 30 and a three-dimensional memory 10 according to some embodiments above. The controller 30 is coupled to the three-dimensional memory 10 to control the three-dimensional memory 10 to store data.

[0245] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0246] In some embodiments, see Figure 42 The storage system 1000 includes a controller 30 and a three-dimensional memory 10. The storage system 1000 can be integrated into a three-dimensional memory card.

[0247] Among them, the three-dimensional memory card includes any one of a PC card (PCMCIA, Personal Computer 3D Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a three-dimensional memory, a Multimedia Card (MMC), a Secure Digital (SD) card, and a UFS.

[0248] In other embodiments, see Figure 43 The storage system 1000 includes a controller 30 and a plurality of three-dimensional memories 10. The storage system 1000 is integrated into a solid state drive (SSD).

[0249] In the storage system 1000, in some embodiments, the controller 30 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0250] In other embodiments, the controller 30 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0251] In some embodiments, the controller 30 may be configured to manage data stored in the semiconductor structure 100 and communicate with an external device (e.g., a host). In some embodiments, the controller 30 may also be configured to control operations of the semiconductor structure 100, such as read, erase, and program operations. In some embodiments, the controller 30 may also be configured to manage various functions related to data stored or to be stored in the semiconductor structure 100, including at least one of bad block management, garbage collection, logical to physical address translation, and wear leveling. In some embodiments, the controller 30 may also be configured to process error correction codes for data read from or written to the semiconductor structure 100.

[0252] Of course, the controller 30 may also perform any other suitable functions, such as formatting the semiconductor structure 100 ; for example, the controller 30 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0253] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Mini Interface (SCSI) protocol, Enhanced Minidisk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and Firewire protocol.

[0254] Some embodiments of the present disclosure further provide an electronic device. The electronic device can be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, an in-vehicle device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0255] The electronic device may include the storage system 1000 described above, and may further include at least one of a central processing unit (CPU) and a cache.

[0256] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope of protection of the claims.

Claims

1. A semiconductor structure, characterized in that include: A first stack structure includes a plurality of stacked sub-stack structures, wherein along the stacking direction of the plurality of sub-stack structures, the sub-stack structures include a first dielectric layer, a first insulating layer, a second insulating layer, a first channel layer, a gate line layer, and a plate line layer stacked in layers; the first channel layer penetrates the gate line layer, and one end of the first channel layer contacts the plate line layer; at least a portion of the second insulating layer is located between the first channel layer and the gate line layer, and between the gate line layer and the plate line layer; a storage structure extending through the first stacked structure; the storage structure comprising a plurality of ferromagnetic free layers, a tunneling layer, and a ferromagnetic pinned layer; each ferromagnetic free layer contacts the other end of the first channel layer of one of the sub-stacked structures, and the tunneling layer is disposed between the plurality of ferromagnetic free layers and the ferromagnetic pinned layer; A conductive layer runs through the first stack structure; the conductive layer is located on a side of the ferromagnetic pinning layer away from the tunneling layer and is coupled to a bit line.

2. The semiconductor structure according to claim 1, wherein: The first insulating layer is close to the boundary of the storage structure and is farther away from the central axis of the storage structure than the first dielectric layer and the first channel layer are close to the boundary of the storage structure to form a first groove; the ferromagnetic free layer is arranged in the first groove.

3. The semiconductor structure according to claim 2, wherein: The tunneling layer, the ferromagnetic pinning layer, and the conductive layer are at least partially located in the first groove.

4. The semiconductor structure according to claim 2, wherein: The plate line layer is close to the boundary of the storage structure and extends beyond the second insulating layer close to the boundary of the storage structure; A portion of the plate line layer extending beyond the second insulating layer is a first portion, and the first channel layer is in contact with a surface of the first portion close to the gate line layer.

5. The semiconductor structure according to claim 2, wherein: The first insulating layer is close to the boundary of the storage structure and is indented compared to the second insulating layer close to the boundary of the storage structure; the second insulating layer is further arranged between the gate line layer and the first insulating layer, and the second insulating layer includes a first sub-portion in contact with the upper surface of the gate line layer and a second sub-portion in contact with the lower surface of the gate line layer; The sub-stack structure further includes: a second dielectric layer, disposed between the first insulating layer and the second sub-section; and / or, The sub-stack structure further includes: The third dielectric layer is arranged between the first sub-section and the plate line layer. The semiconductor structure according to claim 1 , wherein: The multiple ferromagnetic free layers are separated from each other along a first direction; and / or, The tunneling layer and the ferromagnetic pinning layer are both film layers continuous along a first direction; The first direction is perpendicular to a reference plane, and the reference plane is a plane where the lower surface of the first stacking structure is located.

7. The semiconductor structure according to claim 1, wherein: The sub-stack structure further includes: A third insulating layer is provided between the plate line layer and the storage structure.

8. The semiconductor structure according to claim 1, wherein: The storage structure further includes an antiferromagnetic layer, which is disposed between the conductive layer and the ferromagnetic pinning layer.

9. The semiconductor structure according to any one of claims 1 to 8, wherein: Also includes: The first connecting column passes through the first stack structure; the first connecting column contacts the plate line layer of the first stack structure and is configured to connect to the source layer.

10. The semiconductor structure according to any one of claims 1 to 8, wherein: Also includes: a second stacking structure, disposed on the first stacking structure; The second stacked structure includes at least one selection gate line layer and at least one fourth dielectric layer; A channel structure penetrates the second stack structure; the channel structure includes a second channel layer, the second channel layer is electrically connected to the conductive layer, and the second channel layer is configured to connect the bit line.

11. A method for preparing a semiconductor structure, characterized in that: include: forming an initial stacking structure; The initial stacking structure includes a plurality of stacked sub-initial stacking structures; Along the stacking direction of the plurality of sub-initial stacking structures, each sub-initial stacking structure includes a first dielectric layer, a first insulating layer, a sacrificial layer and a plate line layer which are stacked; forming a first channel hole penetrating the initial stacked structure; forming a first channel layer in the first channel hole; the first channel layer is disposed at an end portion of the sacrificial layer close to the first channel hole, and one end of the first channel layer is in contact with the plate line layer; A storage structure and a conductive layer are formed in the first channel hole; the storage structure includes a plurality of ferromagnetic free layers, a tunneling layer, and a ferromagnetic pinning layer; the ferromagnetic free layer contacts the other end of the first channel layer, and the tunneling layer is disposed between the plurality of ferromagnetic free layers and the ferromagnetic pinning layer; The conductive layer is located on a side of the ferromagnetic pinning layer away from the tunneling layer; forming a gate line gap penetrating the initial stacked structure; Removing the sacrificial layer through the gate line gap to form a second cavity; A second insulating layer and a gate line layer are sequentially formed in the second cavity; at least a portion of the second insulating layer is located between the first channel layer and the gate line layer, and between the gate line layer and the plate line layer.

12. The method for preparing a semiconductor structure according to claim 11, wherein: The forming of the first channel layer in the first channel hole includes: removing an edge portion of the sacrificial layer close to the first channel hole through the first channel hole to form a second groove; A first sub-channel layer is formed in the second groove.

13. The method for preparing a semiconductor structure according to claim 12, wherein: In the process of forming the initial stacking structure, a second dielectric layer and a third dielectric layer are also formed; the second dielectric layer is arranged between the sacrificial layer and the first insulating layer, and the third dielectric layer is arranged between the sacrificial layer and the plate line layer; After forming the first sub-channel layer in the second groove, forming a first channel layer in the first channel hole, further comprising: removing edge portions of the second dielectric layer and the third dielectric layer close to the first dielectric layer through the first channel hole to form a third groove and a fourth groove respectively; A second sub-channel layer and a third sub-channel layer are formed in the third groove and the fourth groove, respectively; the second sub-channel layer is arranged at an end portion of the second dielectric layer close to the first channel hole, and is in contact with the first insulating layer and the first sub-channel layer; the third sub-channel layer is arranged at an end portion of the third dielectric layer close to the first channel hole, and is in contact with the first sub-channel layer and the plate line layer.

14. The method for preparing a semiconductor structure according to claim 13, wherein: The forming of the second sub-channel layer and the third sub-channel layer in the third groove and the fourth groove respectively includes: forming a second channel film; the second channel film fills the third groove and the fourth groove and covers the inner wall of the first channel hole and the upper side of the initial stacked structure; A portion of the second channel film covering the inner wall of the first channel hole and the upper side of the initial stacked structure is removed.

15. The method for preparing a semiconductor structure according to claim 14, wherein: In the process of removing the edge portions of the second dielectric layer and the third dielectric layer close to the first channel hole, the edge portion of the first dielectric layer close to the first channel hole is also removed to form a fifth groove; During the process of forming the second channel film, the second channel film also covers the inner wall of the fifth groove; In the process of removing the portion of the second channel film covering the inner wall of the first channel hole and the upper side of the initial stacked structure, the portion of the second channel film covering the inner wall of the fifth groove is also removed.

16. The method for preparing a semiconductor structure according to claim 15, wherein: After forming the second sub-channel layer and the third sub-channel layer in the third groove and the fourth groove respectively, forming the first channel layer in the first channel hole further includes: A first sub-dielectric layer is formed in the fifth groove.

17. The method for preparing a semiconductor structure according to claim 11, wherein: Between forming the first channel layer in the first channel hole and forming the storage structure and the conductive layer in the first channel hole, the method further includes: Removing an edge portion of the board line layer near the first channel hole through the first channel hole to form a sixth groove; A third insulating layer is formed in the sixth groove.

18. The method for preparing a semiconductor structure according to any one of claims 11 to 17, wherein: The forming of a storage structure and a conductive layer in the first channel hole includes: removing an edge portion of the first insulating layer close to the first channel hole through the first channel hole to form a first groove; forming a ferromagnetic free layer in the first groove; forming a tunneling film, a ferromagnetic pinning film, and a first conductive film in sequence; wherein the tunneling film, the ferromagnetic pinning film, and the first conductive film fill the first groove and cover the inner wall of the first channel hole and the upper side of the initial stacked structure; Portions of the tunneling film, the ferromagnetic pinning film, and the first conductive film that cover an upper side of the initial stacked structure are removed.

19. The method for preparing a semiconductor structure according to claim 18, wherein: The forming of a ferromagnetic free layer in the first groove includes: forming a ferromagnetic free film; the ferromagnetic free film covers the inner wall of the first groove, the inner wall of the first channel hole and the upper side of the initial stacking structure; forming a second filling layer in the first groove; removing a portion of the ferromagnetic free film covering an inner wall of the first channel hole and an upper side of the initial stacked structure; The second filling layer is removed.

20. The method for preparing a semiconductor structure according to claim 19, wherein: After sequentially forming the tunneling film, the ferromagnetic pinning film, and the first conductive film, forming a storage structure and a conductive layer in the first channel hole further includes: forming a first filling layer in the first channel hole; forming a second conductive film; wherein the second conductive film covers the first filling layer and a portion of the first conductive film located on an upper side of the initial stacked structure; In the process of removing the tunneling film, the ferromagnetic pinning film, and the portion of the first conductive film covering the upper side of the initial stacked structure, the portion of the second conductive film covering the upper side of the initial stacked structure is also removed.

21. The method for preparing a semiconductor structure according to claim 11, wherein: The sequentially forming a second insulating layer and a gate line layer in the second cavity includes: forming a second insulating layer in the second cavity via the gate line gap; forming a gate line thin film; the gate line thin film fills the second cavity and covers the inner wall of the gate line gap and the upper side of the initial stacked structure; The portion of the gate line film covering the inner wall of the gate line gap and the upper side of the initial stacking structure is removed.

22. A three-dimensional memory, characterized in that: include: A semiconductor structure, wherein the semiconductor structure is the semiconductor structure according to any one of claims 1 to 10; The peripheral device is electrically connected to the semiconductor structure.

23. A storage system, characterized in that: The device comprises a controller and the three-dimensional memory according to claim 22, wherein the controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

24. An electronic device, characterized in that: Comprising the storage system of claim 23.

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