Array substrate and display panel

Abstract

This application discloses an array substrate and a display panel. The array substrate includes a substrate, a data routing layer, an intermediate layer, and an anode layer. The data routing layer is disposed on the substrate and includes data signal lines. The intermediate layer is disposed on the data routing layer. The anode layer is disposed on the side of the intermediate layer away from the substrate and includes a shielding portion. The orthographic projection of the shielding portion on the substrate at least partially overlaps with the orthographic projection of the data signal lines on the substrate. This array substrate can reduce the coupling capacitance between the data routing layer and the cathode, thereby improving horizontal crosstalk and enhancing the display effect.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to an array substrate and a display panel. Background Technology

[0002] Currently, Active Matrix Organic Light Emitting Display (AMOLED) displays are widely used in various fields due to their advantages such as high brightness, low power consumption, fast response, high definition, good flexibility, and high luminous efficiency. As the application scope of AMOLED display products becomes increasingly widespread, the requirements for their display quality are also becoming more stringent.

[0003] Existing OLED display panels contain numerous metal traces, cathodes, and other metal materials. These metal materials overlap directly, especially the data lines and cathodes, which overlap over a large area. This results in a large coupling capacitance inside the panel, which can easily cause horizontal crosstalk and affect the display effect.

[0004] Therefore, how to reduce the coupling capacitance between the data line and the cathode to improve crosstalk and enhance display performance is an urgent problem to be solved. Summary of the Invention

[0005] This application provides an array substrate and a display panel that can reduce the coupling capacitance between the data trace layer and the cathode, thereby improving horizontal crosstalk and enhancing the display effect.

[0006] In a first aspect, embodiments of this application provide an array substrate, comprising: a substrate, a data trace layer, an intermediate layer, and an anode layer. The data trace layer is disposed on the substrate and includes data signal lines. The intermediate layer is disposed on the data trace layer. The anode layer is disposed on the side of the intermediate layer away from the substrate and includes a shielding portion. The orthographic projection of the shielding portion on the substrate at least partially overlaps with the orthographic projection of the data signal lines on the substrate.

[0007] Optionally, in some embodiments of this application, the anode layer further includes an anode, the orthographic projection of the anode on the substrate at least partially overlaps with the orthographic projection of the data signal line on the substrate, and the shielding portion is disposed adjacent to the anode.

[0008] Optionally, in some embodiments of this application, the anode layer includes a plurality of shielding portions spaced apart and a plurality of anodes spaced apart, the plurality of shielding portions and the plurality of anodes being arranged correspondingly along the extension direction of the data signal line.

[0009] Optionally, in some embodiments of this application, the cross-sectional length of the shield is less than the distance between two adjacent anodes.

[0010] Optionally, in some embodiments of this application, the shielding part is electrically connected to the anode in a one-to-one correspondence, or the shielding part and the anode are spaced apart in a one-to-one correspondence.

[0011] Optionally, in some embodiments of this application, at least some of the anodes are electrically connected to at least two of the shielding portions.

[0012] Optionally, in some embodiments of this application, at least two shielding portions are provided between two adjacent anodes.

[0013] Optionally, in some embodiments of this application, the cross-sectional width of the shield is greater than or equal to the cross-sectional width of the data signal line.

[0014] Optionally, in some embodiments of this application, the intermediate layer includes a buffer layer, a semiconductor layer, an interlayer dielectric layer, a passivation layer, a pixel definition layer, a light-emitting layer, and a cathode. The buffer layer covers the data trace layer. The semiconductor layer is disposed on the side of the buffer layer away from the substrate. The interlayer dielectric layer covers the semiconductor layer. The passivation layer is disposed on the side of the interlayer dielectric layer away from the substrate. The pixel definition layer covers the shielding portion and partially covers the anode. The light-emitting layer is disposed on the side of the anode away from the substrate. The cathode is disposed on the side of the pixel definition layer away from the substrate. The orthogonal projection of the cathode on the substrate covers the shielding portion and the orthogonal projection of the anode on the substrate.

[0015] On the other hand, this application provides a display panel including the array substrate described above.

[0016] This application provides an array substrate and a display panel. The array substrate includes a substrate, a data routing layer, an intermediate layer, and an anode layer. The data routing layer is disposed on the substrate and includes data signal lines. The intermediate layer is disposed on the data routing layer. The anode layer is disposed on the side of the intermediate layer away from the substrate and includes a shielding portion. The orthographic projection of the shielding portion on the substrate at least partially overlaps with the orthographic projection of the data signal lines on the substrate. This array substrate can reduce the coupling capacitance between the data routing layer and the cathode, thereby improving horizontal crosstalk and enhancing display performance. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. The accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a top view of the array substrate provided in the first embodiment of this application;

[0019] Figure 2 This is a schematic diagram of the sub-pixel driving circuit in the array substrate provided in the embodiments of this application;

[0020] Figure 3 yes Figure 1 A schematic diagram of the cross-sectional structure of the array substrate along the AA' direction provided in the diagram;

[0021] Figure 4 This is one of the top view structural schematic diagrams of the array substrate provided in the second embodiment of this application;

[0022] Figure 5 This is a second top view of the array substrate provided in the second embodiment of this application;

[0023] Figure 6 This is a top view of the array substrate provided in the third embodiment of this application;

[0024] Figure 7 This is a top view of the array substrate provided in the fourth embodiment of this application; Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0026] This application provides an array substrate and a display panel that can reduce the coupling capacitance between the data trace layer and the cathode, thereby improving horizontal crosstalk and enhancing display performance. Detailed descriptions are provided below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments. Furthermore, in the description of this application, the term "comprising" means "including but not limited to". The terms "first", "second", "third", etc., are used merely as identifiers to distinguish different objects, and are not used to describe a specific order.

[0027] Please see Figures 1 to 3 , Figure 1 This is a top view of the array substrate provided in the first embodiment of this application; Figure 2 This is a schematic diagram of the sub-pixel driving circuit in the array substrate provided in the embodiments of this application;

[0028] Figure 3 yes Figure 1 The diagram provided shows a cross-sectional view of the array substrate along the AA' direction. Figures 1 to 3 As shown, this application embodiment provides an array substrate 100, including: a substrate 10, a data trace layer 20, an intermediate layer 30, and an anode layer 40. The data trace layer 20 is disposed on the substrate 10 and includes data signal lines. The intermediate layer 30 is disposed on the data trace layer 20. The anode layer 40 is disposed on the side of the intermediate layer 30 away from the substrate 10. The anode layer 40 includes a shielding portion 41. The orthographic projection of the shielding portion 41 on the substrate 10 at least partially overlaps with the orthographic projection of the data signal lines on the substrate 10.

[0029] The array substrate provided in this application can cover and shield a portion of the data trace layer 20 by providing a shielding part 41 on the anode layer 40, thereby improving horizontal crosstalk and enhancing the display effect.

[0030] In this embodiment, the array substrate further includes a light-emitting layer 50 and a cathode 60. The light-emitting layer 50 is disposed on the side of the anode layer 40 away from the substrate 10, and the cathode 60 is disposed on the side of the light-emitting layer 50 away from the substrate 10.

[0031] In this embodiment, the anode layer 40 further includes an anode 42, which includes a first sub-conductive portion 421 and a second sub-conductive portion 422 disposed around the first sub-conductive portion 421. The orthographic projection of the first sub-conductive portion 421 on the substrate 10 covers the orthographic projection of the light-emitting layer 50 on the substrate 10. The orthographic projection of the second sub-conductive portion 422 on the substrate 10 at least partially overlaps with the orthographic projection of the data signal line on the substrate 10. The shielding portion is disposed adjacent to the anode. The orthographic projection of the cathode 60 on the substrate 10 covers the shielding portion 41 and the orthographic projection of the anode 42 on the substrate 10. It should be noted that the cross-sectional shape of the anode 42 can be a centrally symmetrical shape, and the specific shape can be adjusted as needed. This application does not impose a specific limitation here. The anode 42 and the light-emitting layer 50 are stacked and are both centrally symmetrical shapes. This structure is more conducive to improving the flatness of the light-emitting layer 50 and the uniformity of light emission, thereby improving the display effect.

[0032] In this embodiment, the intermediate layer 30 includes a buffer layer 31, a semiconductor layer 32, an interlayer dielectric layer 33, a passivation layer 34, and a pixel definition layer 35. The buffer layer 31 covers the data routing layer 20. The semiconductor layer 32 is disposed on the side of the buffer layer 31 away from the substrate 10. The interlayer dielectric layer 33 covers the semiconductor layer 32. The passivation layer 34 is disposed on the side of the interlayer dielectric layer 33 away from the substrate 10. The pixel definition layer 35 covers the shielding portion 41 and partially covers the anode 42. The buffer layer 31, interlayer dielectric layer 33, passivation layer 34, and pixel definition layer 35 all include insulating materials, such as silicon oxide or silicon nitride. The semiconductor layer 32 includes indium gallium zinc oxide. Specifically, the intermediate layer 30 may also include other film layers. Since the specific film layers can be the same as the film layer structure of pixel units in existing displays, they are not listed here.

[0033] In the embodiments of this application, such as Figure 1 and Figure 2 As shown, the array substrate 100 also includes a plurality of sub-pixel regions 11 arranged in an array. Each sub-pixel region 11 is provided with a sub-pixel driving circuit and a plurality of light-emitting elements disposed on the side of the sub-pixel driving circuit away from the substrate 10. Each light-emitting element corresponds to a sub-pixel driving circuit. Each light-emitting element includes an anode 42, a light-emitting layer 50, and a cathode 60 sequentially stacked along the direction away from the substrate 10. The sub-pixel driving circuit is used to drive the corresponding light-emitting element to emit light, thereby realizing the display function. For example, in this application, each sub-pixel driving circuit includes three thin-film transistors, one capacitor, and one light-emitting element. The array substrate also includes a scan data signal line WR and a scan data signal line RD, a sensing data signal line SENSE, a data signal line DATA, a first power data signal line VDD, and a second power data signal line VSS.

[0034] In the embodiments of this application, such as Figure 2 As shown, the source of the first transistor T1 is electrically connected to the first power data signal line VDD, the gate of the first transistor is electrically connected to the first node G, and the drain of the first transistor is electrically connected to the second node S; the source of the second transistor T2 is electrically connected to the data signal line DATA, the gate of the second transistor is electrically connected to the scan data signal line WR, and the drain of the second transistor is electrically connected to the first node G; the source of the third transistor T3 is electrically connected to the sensing data signal line SENSE, the gate of the third transistor is electrically connected to the scan data signal line RD, and the drain of the third transistor is electrically connected to the second node S; the anode 42 of the light-emitting element is electrically connected to the second node S, and the cathode 60 of the light-emitting element is electrically connected to the second power data signal line VSS; one end of the capacitor C1 is electrically connected to the first node G, and the other end of the capacitor C1 is electrically connected to the second node S. It should be noted that the source and drain of the thin-film transistor are symmetrical, so their sources and drains are interchangeable.

[0035] In the embodiments of this application, such as Figure 1 As shown, the projection of the anode 42 onto the substrate 10 overlaps with the corresponding first power data signal line VDD, second power data signal line VSS, data signal line DATA, and sensing data signal line SENSE. Outside the overlap area between the anode 42 and the data signal line DATA, there is an overlap area between the data signal line DATA and the cathode 60. Consequently, there is a large coupling capacitance between the data signal line DATA and the cathode 60, and a large lateral coupling capacitance between the data signal line DATA and the second power data signal line VSS. Crosstalk also exists between the data signal line DATA and the cathode 60, the second power data signal line VDD, the second power data signal line VSS, and the third power data signal line VSS. The coupling capacitance between the power and data signal lines VSS is strongly correlated. Therefore, there is a direct overlap area between the data signal line DATA and the cathode 60, which can easily cause horizontal crosstalk and affect the display effect. The array substrate provided in this application covers and shields the part of the data signal line DATA that directly overlaps with the second power and data signal line VSS by setting a shielding part 41. That is, it directly reduces the direct overlap area between the data signal line DATA and the second power and data signal line VSS, so that the coupling capacitance between the data signal line DATA and the cathode 60 and the second power and data signal line VSS is significantly reduced, thereby improving horizontal crosstalk and enhancing the display effect.

[0036] In the embodiments of this application, such as Figure 1 As shown, the anode layer 40 includes multiple spaced shielding portions 41 and multiple spaced anodes 42, which are arranged correspondingly along the extension direction of the data signal lines. Specifically, the anodes 42 are also the anodes 42 in the light-emitting elements, corresponding one-to-one with the sub-pixel areas 11. The data signal lines are also the data signal lines DATA. The multiple anodes 42 are arranged spaced along the extension direction of the data signal lines DATA. One or more shielding portions 41 may be provided between each pair of adjacent anodes 42, or no shielding portions 41 may be provided between some adjacent anodes 42. The coverage area of ​​the shielding portions 41 on the data signal lines DATA between the spaced anodes 42 is greater than 70% of the cross-sectional area of ​​the data signal lines DATA located in the spaced areas. Figure 1 As exemplarily shown, a shielding part 41 is provided between anodes 42 that are spaced apart along the extension direction of the data signal line DATA, or there are two shielding parts 41, or there is no shielding part 41 provided, and the shielding part 41 can be electrically connected to the anodes 42 or can be spaced apart.

[0037] In this embodiment, preferably, the shielding portion 41 and the anode 42 have the same thickness and are made of the same material. Both the shielding portion 41 and the anode 42 can be made of indium zinc oxide. This design results in a higher film flatness of the anode layer 40, facilitates process operation, and improves both product quality and production efficiency.

[0038] In this embodiment, the cross-sectional width of the shielding portion 41 is greater than or equal to the cross-sectional width of the data signal line. This design improves the shielding effect of the shielding portion 41 on the data signal line, and the coupling capacitance between the data signal line and the cathode 60 is significantly reduced by adding the shielding portion 41 between the data signal line and the cathode 60.

[0039] In this embodiment, the cross-sectional length of the shielding portion 41 is less than the distance between two adjacent anodes 42. This design prevents adjacent anodes 42 from being electrically connected through the shielding portion 41, thus avoiding impact on the display effect. It should be noted that the cross-sectional length of the shielding portion 41, within the range of being less than the distance between two adjacent anodes 42, can be adjusted according to actual needs, and this application does not impose a specific limitation here. On the other hand, preferably, the cross-sectional shape of the shielding portion 41 is square, elliptical, etc., and the cross-sectional shape of the shielding portion 41 can also be adjusted according to actual needs, and this application does not impose a specific limitation here.

[0040] Please see Figure 4 and Figure 5 , Figure 4 This is one of the top view structural schematic diagrams of the array substrate provided in the second embodiment of this application; Figure 5 This is a second top view schematic diagram of the array substrate provided in the second embodiment of this application. Figure 4 and Figure 5 As shown, this application embodiment provides an array substrate 200. The difference between array substrate 200 and array substrate 100 is that: in array substrate 200, shielding portion 41 and anode 42 are electrically connected in a one-to-one correspondence, or shielding portion 41 and anode 42 are spaced apart in a one-to-one correspondence.

[0041] In this embodiment, the array substrate 200 includes a plurality of sub-pixel regions 11 arranged in an array. Each sub-pixel region 11 is provided with a sub-pixel driving circuit and a plurality of light-emitting elements disposed on the side of the sub-pixel driving circuit away from the substrate 10. Each light-emitting element corresponds one-to-one with a sub-pixel driving circuit. Each light-emitting element includes an anode 42, a light-emitting layer 50, and a cathode (not shown in the figure) sequentially stacked along the direction away from the substrate 10. The sub-pixel driving circuit is used to drive the corresponding light-emitting element to emit light, thereby realizing the display function. The array substrate also includes a scan data signal line WR and a scan data signal line RD, a sensing data signal line SENSE, a data signal line DATA, a first power data signal line VDD, and a second power data signal line VSS, which are electrically connected to the sub-pixel driving circuit.

[0042] like Figure 4 As shown, the shielding part 41 and the anode 42 are electrically connected in a one-to-one correspondence. This design is equivalent to the shielding part 41 being an extension of the anode 42 along the DATA direction of the data signal line. It is easy to manufacture and can be completed in the same process as the anode 42, which improves production efficiency and saves production costs.

[0043] like Figure 5 As shown, the shielding part 41 and the anode 42 are arranged in a one-to-one correspondence. This design can reduce the coupling capacitance between the data signal line DATA and the cathode 60, while also reducing signal interference between the anode 42 and the data signal line DATA, and controlling the capacitance between the anode 42 and the data signal line DATA within a suitable range, thereby improving the display effect.

[0044] The array substrate 200 provided in this application can cover and shield most of the area where the data signal line DATA and the cathode 60 directly overlap by setting a shielding part 41 that corresponds one-to-one with the anode 42, thereby reducing the coupling capacitance between the data signal line DATA and the cathode 60, improving horizontal crosstalk, and enhancing the display effect.

[0045] Please see Figure 6 , Figure 6 This is a top view of the array substrate provided in the third embodiment of this application. Figure 6 As shown, this application embodiment provides an array substrate 300. The difference between array substrate 300 and array substrate 100 is that at least a portion of the anodes 42 in array substrate 300 are electrically connected to at least two shielding portions 41. For example, Figure 6 The diagram only shows that the anode 42 is electrically connected to two shields 41 extending along the same data signal line DATA. Specifically, the anode 42 can also be electrically connected to two or more shields 41 that cover different data signal lines DATA respectively. Those skilled in the art can make adjustments according to actual needs, and this application does not make specific limitations here.

[0046] In this embodiment, the array substrate 300 includes a plurality of sub-pixel regions 11 arranged in an array. Each sub-pixel region 11 is provided with a sub-pixel driving circuit and a plurality of light-emitting elements disposed on the side of the sub-pixel driving circuit away from the substrate 10. Each light-emitting element corresponds one-to-one with a sub-pixel driving circuit. Each light-emitting element includes an anode 42, a light-emitting layer 50, and a cathode (not shown in the figure) stacked sequentially along the direction away from the substrate 10. The sub-pixel driving circuit is used to drive the corresponding light-emitting element to emit light, thereby realizing the display function. The array substrate also includes a scan data signal line WR and a scan data signal line RD, a sensing data signal line SENSE, a data signal line DATA, a first power data signal line VDD, and a second power data signal line VSS, which are electrically connected to the sub-pixel driving circuit.

[0047] The array substrate 300 provided in this application provides two shielding parts 41, which are electrically connected to two anodes 42 respectively, between multiple anodes 42 along the extension direction of the data signal line DATA. This enables the shielding of most of the area where the data signal line DATA and the cathode 60 directly overlap, thereby reducing the coupling capacitance between the data signal line DATA and the cathode 60, improving horizontal crosstalk, and enhancing the display effect.

[0048] Please see Figure 7 , Figure 7 This is a top view of the array substrate provided in the fourth embodiment of this application. Figure 7 As shown, this application embodiment provides an array substrate 400. The difference between the array substrate 400 and the array substrate 100 is that at least two shielding portions 41 are provided between two adjacent anodes 42 in the array substrate 400. For example, Figure 7 The image only shows three shielding portions 41 spaced apart between multiple anodes 42 spaced along the extension direction of the data signal line DATA. Specifically, the number of shielding portions 41 spaced apart can be two, three, four or more, and can be adjusted according to actual needs; this application does not impose a specific limitation here.

[0049] In this embodiment, the array substrate 400 includes a plurality of sub-pixel regions 11 arranged in an array. Each sub-pixel region 11 is provided with a sub-pixel driving circuit and a plurality of light-emitting elements disposed on the side of the sub-pixel driving circuit away from the substrate 10. Each light-emitting element corresponds one-to-one with a sub-pixel driving circuit. Each light-emitting element includes an anode 42, a light-emitting layer 50, and a cathode (not shown in the figure) stacked sequentially along the direction away from the substrate 10. The sub-pixel driving circuit is used to drive the corresponding light-emitting element to emit light, thereby realizing the display function. The array substrate also includes a scan data signal line WR and a scan data signal line RD, a sensing data signal line SENSE, a data signal line DATA, a first power data signal line VDD, and a second power data signal line VSS, which are electrically connected to the sub-pixel driving circuit.

[0050] The array substrate 400 provided in this application has multiple spaced shielding portions 41 between multiple anodes 42 spaced apart along the extension direction of the data signal line DATA. This can cover and shield most of the area where the data signal line DATA and the cathode 60 directly overlap, thereby reducing the coupling capacitance between the data signal line DATA and the cathode 60, improving horizontal crosstalk, and enhancing the display effect.

[0051] On the other hand, this application provides a display panel including the aforementioned array substrate. It should be noted that this display panel can be applied to any product or component with display functionality, such as televisions, monitors, digital photo frames, mobile phones, and tablet computers.

[0052] This application provides an array substrate and a display panel. The array substrate includes a substrate 10, a data routing layer 20, an intermediate layer 30, and an anode layer 40. The data routing layer 20 is disposed on the substrate 10, and a first conductive layer includes data signal lines. The intermediate layer 30 is disposed on the data routing layer 20. The anode layer 40 is disposed on the side of the intermediate layer 30 away from the substrate 10, and the anode layer 40 includes a shielding portion 41. The orthographic projection of the shielding portion 41 on the substrate 10 at least partially overlaps with the orthographic projection of the data signal lines on the substrate 10. This array substrate can reduce the coupling capacitance between the data routing layer 20 and the cathode 60, thereby improving horizontal crosstalk and enhancing the display effect.

[0053] The above provides a detailed description of an array substrate and display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An array substrate, characterized by, include: Substrate; A data routing layer is disposed on the substrate, and the data routing layer includes data signal lines; An intermediate layer is disposed on the data routing layer; as well as An anode layer is disposed on the side of the intermediate layer away from the substrate. The anode layer includes a shielding portion, the orthographic projection of the shielding portion on the substrate at least partially overlapping the orthographic projection of the data signal line on the substrate. The anode layer includes a plurality of anodes, which are spaced apart along the extension direction of the data signal line. At least two shielding portions are provided between two adjacent anodes spaced apart along the extension direction of the data signal line. One shielding portion is electrically connected to one of the two adjacent anodes, and another shielding portion is electrically connected to the other of the two adjacent anodes. The shielding portions are disconnected from the two shielding portions that are electrically connected to the two adjacent anodes spaced apart along the extension direction of the data signal line.

2. The array substrate of claim 1, wherein, The anode layer further includes an anode, the orthographic projection of the anode on the substrate at least partially overlaps with the orthographic projection of the data signal line on the substrate, and the shielding portion is disposed adjacent to the anode.

3. The array substrate of claim 2, wherein, The anode layer includes a plurality of spaced-apart shielding portions and a plurality of spaced-apart anodes, which are arranged correspondingly along the extension direction of the data signal line.

4. The array substrate of claim 3, wherein, The cross-sectional length of the shield is less than the distance between two adjacent anodes.

5. The array substrate of claim 1, wherein, The cross-sectional width of the shield is greater than or equal to the cross-sectional width of the data signal line.

6. The array substrate of claim 2, wherein, The intermediate layer includes a buffer layer, a semiconductor layer, an interlayer dielectric layer, a passivation layer, a pixel definition layer, a light-emitting layer, and a cathode. The buffer layer covers the data trace layer. The semiconductor layer is disposed on the side of the buffer layer away from the substrate. The interlayer dielectric layer covers the semiconductor layer. The passivation layer is disposed on the side of the interlayer dielectric layer away from the substrate. The pixel definition layer covers the shielding portion and partially covers the anode. The light-emitting layer is disposed on the side of the anode away from the substrate. The cathode is disposed on the side of the pixel definition layer away from the substrate. The orthographic projection of the cathode on the substrate covers the shielding portion and the orthographic projection of the anode on the substrate.

7. A display panel, characterized by Includes the array substrate as described in any one of claims 1-6.

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